JP2007214191A - Radiation detector and radiographic examination equipment - Google Patents

Radiation detector and radiographic examination equipment Download PDF

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JP2007214191A
JP2007214191A JP2006029832A JP2006029832A JP2007214191A JP 2007214191 A JP2007214191 A JP 2007214191A JP 2006029832 A JP2006029832 A JP 2006029832A JP 2006029832 A JP2006029832 A JP 2006029832A JP 2007214191 A JP2007214191 A JP 2007214191A
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semiconductor
wiring board
semiconductor crystal
radiation detector
radiation
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Daizo Amano
大三 天野
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Sumitomo Heavy Industries Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a radiation detector capable of controlling deterioration of the detection characteristics of a semiconductor crystal object, even in the case of a wiring board having a thermal expansion coefficient different substantially from that of the semiconductor crystal object, and to provide radiographic examination equipment using the detector. <P>SOLUTION: In the radiation detector, a semiconductor detector 20 comprises: a wiring board 21 having a thermal expansion coefficient of 8.0×10<SP>-6</SP>[1/°C] or more, for example, a board consisting of a glass epoxy board or a flexible printed wiring board; and a semiconductor detection element 22 and the like arranged on the wiring board 21. The semiconductor detection element 22 is extended to an almost plated-shape semiconductor crystal object 23 and to the whole Y-axis direction of the semiconductor crystal object 23 in its undersurface. Eight element electrodes 24<SB>1</SB>-24<SB>8</SB>consisting of Au, for example, by a predetermined width are arranged in the direction of the X-axis. The element electrodes 24<SB>1</SB>-24<SB>8</SB>and pad electrodes 26<SB>1</SB>-26<SB>8</SB>arranged in the wiring board 21 are secured by bumps 28 composed of conductive adhesives of shearing modulus smaller than Young's modulus of the semiconductor crystal object 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、放射線検出器および放射線検査装置に関し、特に、被検体内にある放射性同位元素から放出されたガンマ線を検出する放射線検出器および放射線検査装置に関する。   The present invention relates to a radiation detector and a radiation inspection apparatus, and more particularly to a radiation detector and a radiation inspection apparatus that detect gamma rays emitted from a radioisotope in a subject.

近年、生体(被検体)の内部の情報を得るために断層撮影装置が広く用いられるようになってきた。断層撮影装置としては、X線コンピュータ断層撮影(X線CT)装置、磁気共鳴映像装置、SPECT(single photon emission CT)装置、ポジトロン断層撮影(PET)装置が挙げられる。X線CT装置は、生体のある断面に多方向から幅の狭いX線ビームを曝射し、透過したX線を検出してその断面内でのX線の吸収の度合いの空間分布をコンピュータで計算し画像化している。このようにして、生体内部の形態的な異常、例えば出血巣を把握できる。   In recent years, tomographic apparatuses have been widely used to obtain information inside a living body (subject). Examples of the tomography apparatus include an X-ray computed tomography (X-ray CT) apparatus, a magnetic resonance imaging apparatus, a SPECT (single photon emission CT) apparatus, and a positron tomography (PET) apparatus. An X-ray CT apparatus irradiates a cross section of a living body with a narrow X-ray beam from multiple directions, detects transmitted X-rays, and calculates the spatial distribution of the degree of X-ray absorption in the cross section by a computer. Calculated and imaged. In this way, morphological abnormalities inside the living body, such as bleeding spots, can be grasped.

また、PET装置は被検体内の機能情報の精密情報が得られるため、近年、盛んに開発が進められている。PET装置を用いた診断方法は、まず、ポジトロン核種で標識された検査用薬剤を、注射や吸入等により被検体の内部に導入する。被検体内に導入された検査用薬剤は、検査用薬剤に応じた機能を有する特定の部位に蓄積される。例えば、糖類の検査用薬剤を用いた場合、ガン細胞等の新陳代謝の盛んな部位に選択的に蓄積される。このとき、検査用薬剤のポジトロン核種から陽電子が放出され、放出された陽電子と周囲の電子とが結合して消滅する際に2つのガンマ線(いわゆる消滅ガンマ線)が互いに約180度の方向に放出される。そこで、この2つのガンマ線を被検体の周りに配置した放射線検出器により同時検出し、コンピュータ等で画像を再生成することにより被検体における放射性同位元素の分布画像データを取得する。このようにPET装置では被検体の体内の機能情報が得られるため、様々な難病の病理解明が可能である。   In addition, since the PET apparatus can obtain precise information on the function information in the subject, development has been actively promoted in recent years. In a diagnostic method using a PET apparatus, first, a test drug labeled with a positron nuclide is introduced into a subject by injection or inhalation. The test drug introduced into the subject is accumulated in a specific part having a function corresponding to the test drug. For example, when a saccharide test drug is used, it is selectively accumulated at sites with high metabolism such as cancer cells. At this time, positrons are emitted from the positron nuclide of the test agent, and when the emitted positrons and surrounding electrons are combined and annihilated, two gamma rays (so-called annihilation gamma rays) are emitted in a direction of about 180 degrees from each other. The Therefore, the two gamma rays are simultaneously detected by a radiation detector arranged around the subject, and the image of the radioisotope in the subject is acquired by regenerating an image with a computer or the like. As described above, since the function information in the body of the subject can be obtained with the PET apparatus, the pathology of various intractable diseases can be elucidated.

PET装置では、ガンマ線を検出するために半導体検出素子を用いることが提案されている(例えば、特許文献1参照。)。図1に示すように、半導体結晶素子100は、CdTe等の半導体結晶体104に電極103,105を設けた構造を有する。半導体検出素子100は半導体結晶体104に入射したガンマ線が電子正孔対を生成する性質を利用してガンマ線を電気信号として検出する。半導体検出素子100は構造が単純なため小型化が容易であり、小型化によりガンマ線の入射位置を高精度に検出できる。その結果、ガンマ線の発生源である被検体のポジトロン核種の位置を高精度に取得でき、PET装置の空間分解能を向上できる。
特開平4−196180号公報
In the PET apparatus, it has been proposed to use a semiconductor detection element to detect gamma rays (see, for example, Patent Document 1). As shown in FIG. 1, the semiconductor crystal element 100 has a structure in which electrodes 103 and 105 are provided on a semiconductor crystal body 104 such as CdTe. The semiconductor detection element 100 detects gamma rays as electrical signals by utilizing the property that gamma rays incident on the semiconductor crystal body 104 generate electron-hole pairs. Since the semiconductor detection element 100 has a simple structure, the semiconductor detection element 100 can be easily reduced in size and can detect the incident position of gamma rays with high accuracy. As a result, the position of the positron nuclide of the subject that is the source of gamma rays can be acquired with high accuracy, and the spatial resolution of the PET apparatus can be improved.
Japanese Patent Laid-Open No. 4-196180

ところで、半導体結晶体、特にCdTe結晶体は脆いため壊れ易く、外部からの応力の印加により結晶中に欠陥が生じ易い。CdTe結晶体に欠陥が生じると、CdTe結晶体中でガンマ線の入射により生成された電子および正孔が電極に到達し難くなり、ガンマ線の検出特性が劣化する。   By the way, a semiconductor crystal body, particularly a CdTe crystal body, is fragile and easily broken, and defects are easily generated in the crystal by applying external stress. When a defect occurs in the CdTe crystal, electrons and holes generated by the incidence of gamma rays in the CdTe crystal are difficult to reach the electrodes, and the gamma ray detection characteristics deteriorate.

特に、CdTe結晶体を配線基板に接合する際あるいは接合した後にCdTe結晶体に応力が印加され易い。特に、加熱によりCdTe結晶体と配線基板とを接合した後に冷却によって、配線基板とCdTe結晶体との熱膨張係数の差異により、CdTe結晶体に応力が印加される。CdTe結晶体の熱膨張係数(線膨張係数)は、4.9×10-6[1/℃]である。配線基板にアルミナ基板(熱膨張係数6.9×10-6[1/℃])やガラス基板(7.7×10-6[1/℃])を用いた場合は、CdTe結晶体との熱膨張係数差が少なく、検出特性の劣化はほとんど生じない。 In particular, stress is easily applied to the CdTe crystal when or after the CdTe crystal is bonded to the wiring board. In particular, stress is applied to the CdTe crystal due to the difference in thermal expansion coefficient between the wiring substrate and the CdTe crystal due to cooling after joining the CdTe crystal and the wiring substrate by heating. The thermal expansion coefficient (linear expansion coefficient) of the CdTe crystal is 4.9 × 10 −6 [1 / ° C.]. When an alumina substrate (coefficient of thermal expansion: 6.9 × 10 −6 [1 / ° C.]) or a glass substrate (7.7 × 10 −6 [1 / ° C.]) is used as the wiring substrate, the CdTe crystal The difference in thermal expansion coefficient is small, and the detection characteristics hardly deteriorate.

しかし、配線基板にガラスエポキシ基板(熱膨張係数30×10-6[1/℃])を用いた場合は、CdTe結晶体との熱膨張係数差が大きく検出特性が劣化する。図1に示すように、ガラスエポキシ基板101とCdTe結晶体104を導電性接着剤102により接合した場合、冷却時にガラスエポキシ基板101が収縮すると、その圧縮応力が導電性接着剤102を介してCdTe結晶体104に印加される。導電性接着剤102は、ガラスエポキシ基板101とCdTe結晶体104との接合面全体に設けられているので、ガラスエポキシ基板101の収縮をそのままCdTe結晶体104に伝え、CdTe結晶体104全体に圧縮応力が印加されてしまう。その結果、CdTe結晶体104の検出特性の劣化が生じ実用に耐えなくなるという問題を生じる。 However, when a glass epoxy substrate (thermal expansion coefficient 30 × 10 −6 [1 / ° C.]) is used as the wiring board, the difference in thermal expansion coefficient from the CdTe crystal is large and the detection characteristics are deteriorated. As shown in FIG. 1, when the glass epoxy substrate 101 and the CdTe crystal body 104 are joined by the conductive adhesive 102, when the glass epoxy substrate 101 contracts during cooling, the compressive stress is transferred to the CdTe via the conductive adhesive 102. Applied to the crystal 104. Since the conductive adhesive 102 is provided on the entire bonding surface between the glass epoxy substrate 101 and the CdTe crystal 104, the shrinkage of the glass epoxy substrate 101 is directly transmitted to the CdTe crystal 104 and compressed to the entire CdTe crystal 104. Stress is applied. As a result, there is a problem that the detection characteristics of the CdTe crystal 104 are deteriorated and cannot be practically used.

そこで、本発明は上記問題点に鑑みてなされたもので、本発明の目的は、半導体結晶体と熱膨張係数差が大きな配線基板でも半導体結晶体の検出特性の劣化を抑制可能な放射線検出器、およびこれを用いた放射線検査装置を提供することである。   Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a radiation detector capable of suppressing deterioration of detection characteristics of a semiconductor crystal even on a wiring substrate having a large difference in thermal expansion coefficient from that of the semiconductor crystal. And a radiation inspection apparatus using the same.

本発明の一観点によれば、配線基板と、該配線基板上に放射線の入射により電子正孔対を生成する半導体検出素子を備える放射線検出器であって、前記半導体検出素子は、略板状の半導体結晶体と、該半導体結晶体の厚さ方向に直交し、配線基板側の第1の主面に、略等間隔で互いに離隔して配列された複数の素子電極からなる第1の電極部と、その反対側の第2の主面に、該第2の主面を略覆う金属膜からなる第2の電極部とを有し、前記配線基板は、その表面に前記第1の電極部の素子電極に対応するパッド電極が設けられると共に、その熱膨張係数が8.0×10-6[1/℃]以上であり、前記半導体検出素子は、前記素子電極の各々とパッド電極の各々とが、半導体結晶体のヤング率よりも小さいずれ弾性を有する導電性接着剤からなるバンプ状接着部により固着されてなり、該バンプ状接着部が素子電極とパッド電極とが互いに対向する領域の一部に配設されてなることを特徴とする放射線検出器が提供される。 According to one aspect of the present invention, there is provided a radiation detector including a wiring board and a semiconductor detection element that generates electron-hole pairs upon incidence of radiation on the wiring board, the semiconductor detection element having a substantially plate shape. And a first electrode composed of a plurality of element electrodes arranged perpendicularly to the thickness direction of the semiconductor crystal body and spaced apart from each other on the first main surface on the wiring board side at substantially equal intervals And a second electrode portion made of a metal film substantially covering the second main surface on the second main surface on the opposite side, and the wiring board has the first electrode on the surface thereof And a thermal expansion coefficient of 8.0 × 10 −6 [1 / ° C.] or more, and the semiconductor detection element includes each of the element electrodes and the pad electrode. Each of them is made of a conductive adhesive having elasticity that is smaller than the Young's modulus of the semiconductor crystal. That is secured by a bump like bonding portion becomes, the radiation detector in which the bump-like adhesive portion is characterized by comprising disposed in a part of the region where the device electrode and the pad electrode facing each other are provided.

本発明によれば、配線基板に従来よりも熱膨張係数が大きい基板を用いている。半導体検出素子と配線基板とを導電性接着剤からなるバンプ状接着部を用いている。バンプ状接着部は、そのずれ弾性が固化後の状態で半導体結晶体のヤング率よりも小さい材料が用いられるので、配線基板と半導体結晶体との熱膨張係数差により生じる応力を吸収して半導体結晶体に印加される応力を抑制する。したがって、半導体結晶体と熱膨張係数差が大きな配線基板を用いても半導体結晶体の検出特性の劣化を抑制できる。さらに、製造コストの安価な配線基板を使用できるので、アルミナ基板やガラス基板よりも製造コストの低減を図れる。   According to the present invention, a substrate having a larger thermal expansion coefficient than the conventional one is used for the wiring substrate. A bump-like adhesive portion made of a conductive adhesive is used between the semiconductor detection element and the wiring board. The bump-like adhesive part is made of a material whose misalignment elasticity is less than the Young's modulus of the semiconductor crystal in the solidified state. Therefore, it absorbs the stress caused by the difference in thermal expansion coefficient between the wiring board and the semiconductor crystal, and thus the semiconductor. The stress applied to the crystal body is suppressed. Therefore, even if a wiring substrate having a large difference in thermal expansion coefficient from that of the semiconductor crystal is used, deterioration of the detection characteristics of the semiconductor crystal can be suppressed. Furthermore, since a wiring board with a low manufacturing cost can be used, the manufacturing cost can be reduced as compared with an alumina substrate or a glass substrate.

なお、熱膨張係数は、対象物の長さをLとすると、温度変化ΔTにおける長さの変化ΔLを用いて(ΔL/L)/ΔT[1/℃]で表され、いわゆる線膨張係数である。本願明細書および特許請求の範囲において熱膨張係数は線膨張係数で示している。   The thermal expansion coefficient is represented by (ΔL / L) / ΔT [1 / ° C.] using a change in length ΔL in the temperature change ΔT, where L is the length of the object, and is a so-called linear expansion coefficient. is there. In the present specification and claims, the thermal expansion coefficient is indicated by a linear expansion coefficient.

また、前記半導体結晶体の第1の主面は、隣接する素子電極間に、配線基板の熱膨張に起因する応力を抑制するための溝部が形成されてなる構成としてもよい。半導体結晶体の第1の電極部側に、隣接する素子電極間に溝部を設けることで、配線基板と半導体結晶体との熱膨張係数差により生じる応力を溝部が形成された領域に集中させる。その結果、素子電極が接する半導体結晶体の領域への応力印加を回避でき、検出特性の劣化をいっそう抑制できる。   In addition, the first main surface of the semiconductor crystal body may be configured such that a groove portion for suppressing stress caused by thermal expansion of the wiring board is formed between adjacent element electrodes. By providing a groove portion between adjacent element electrodes on the first electrode portion side of the semiconductor crystal body, stress caused by a difference in thermal expansion coefficient between the wiring substrate and the semiconductor crystal body is concentrated on the region where the groove portion is formed. As a result, the application of stress to the region of the semiconductor crystal that is in contact with the device electrode can be avoided, and deterioration of detection characteristics can be further suppressed.

本発明の他の観点によれば、放射性同位元素を含む被検体から発生する放射線を検出する上記いずれかの放射線検出器と、前記放射線検出器から取得した放射線の入射時刻および入射位置を含む検出情報に基づいて前記放射性同位元素の被検体内における分布情報を取得する情報処理手段と、を備える放射線検査装置が提供される。   According to another aspect of the present invention, any one of the above radiation detectors that detects radiation generated from a subject containing a radioisotope, and detection including an incident time and an incident position of radiation acquired from the radiation detector Information processing means for acquiring distribution information of the radioisotope in the subject based on the information is provided.

本発明によれば、放射線検出器に検出特性の劣化を抑制し、かつ安価な放射線検出器を備えることにより、性能を維持しつつ放射線検査装置の製造コストを低減を低減できる。   According to the present invention, it is possible to reduce the manufacturing cost of the radiation inspection apparatus while maintaining the performance by suppressing the deterioration of the detection characteristics in the radiation detector and providing an inexpensive radiation detector.

本発明によれば、半導体結晶体と熱膨張係数差が大きな配線基板でも半導体結晶体の検出特性の劣化を抑制可能な放射線検出器、およびこれを用いた放射線検査装置を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the radiation detector which can suppress deterioration of the detection characteristic of a semiconductor crystal body, and a radiation inspection apparatus using the same can be provided even if it is a wiring board with a large thermal expansion coefficient difference with a semiconductor crystal body.

以下図面を参照しつつ実施の形態を説明する。   Embodiments will be described below with reference to the drawings.

(第1の実施の形態)
図2は、本発明の第1の実施の形態に係るPET装置の構成を示すブロック図である。図2を参照するに、PET装置10は、被検体Sの周囲に配置され、ガンマ線を検出する検出器11と、検出器11からの検出データを処理し、得られた被検体Sの体内のポジトロン核種RIの位置の画像データを再生成する情報処理部12と、画像データを表示等する表示部13と、被検体Sや検出器11の移動等の制御を行う制御部14と、情報処理部12や制御部14に指示を送る端末や画像データを出力するプリンタ等からなる入出力部15等から構成される。
(First embodiment)
FIG. 2 is a block diagram showing the configuration of the PET apparatus according to the first embodiment of the present invention. Referring to FIG. 2, the PET apparatus 10 is disposed around the subject S, detects a gamma ray, and processes detection data from the detector 11. An information processing unit 12 that regenerates image data at the position of the positron nuclide RI, a display unit 13 that displays image data, a control unit 14 that controls movement of the subject S and the detector 11, and the information processing The input / output unit 15 includes a terminal that sends instructions to the unit 12 and the control unit 14, a printer that outputs image data, and the like.

検出器11は半導体検出部20と検出回路16からなる。半導体検出部20は、ガンマ線γa,γbの入射面が被検体Sに面するように配置されている。なお、予め被検体Sにはポジトロン核種RIで標識化された検査用薬剤が導入されている。   The detector 11 includes a semiconductor detection unit 20 and a detection circuit 16. The semiconductor detector 20 is arranged so that the incident surfaces of the gamma rays γa and γb face the subject S. Note that a test drug labeled with a positron nuclide RI is introduced into the subject S in advance.

ポジトロン核種RIからの陽電子の消滅の際に、同時に発生する2つのガンマ線γa、γbを検出する。2つのガンマ線γa、γbは、互いに略180度をなして放出されるので、被検体Sを挟んで対向する検出器11の半導体検出部20に入射する。ガンマ線γa、γbが入射した2つの半導体検出部20の各々は、ガンマ線γa、γbの入射により生じる電気信号(検出信号)を検出回路16に送出する。 When the positron from the positron nuclide RI disappears, two gamma rays γ a and γ b generated simultaneously are detected. Since the two gamma rays γ a and γ b are emitted at an angle of about 180 degrees, they enter the semiconductor detection unit 20 of the detector 11 facing each other with the subject S interposed therebetween. Each of the two semiconductor detector 20 the gamma ray gamma a, is gamma b the incident gamma gamma a, and sends an electric signal (detection signal) the detection circuit 16 caused by the incidence of the gamma b.

検出回路16は、検出信号から、ガンマ線γa、γbが検出素子に入射した時刻(入射時刻)と入射位置を決定し、これらの情報(検出データ)を情報処理部12に送出する。検出回路16は、例えば、アナログ信号である検出信号から入射時刻を算出するためのアナログASICと、入射時刻および入射位置をデジタルデータとして情報処理部に送出するデジタルASIC等から構成される。 The detection circuit 16 determines the time (incident time) and the incident position where the gamma rays γ a and γ b are incident on the detection element from the detection signal, and sends the information (detection data) to the information processing unit 12. The detection circuit 16 includes, for example, an analog ASIC for calculating an incident time from a detection signal that is an analog signal, a digital ASIC that transmits the incident time and the incident position to the information processing unit as digital data, and the like.

情報処理部12では、検出データに基づいてコインシデンス検出および画像再生成アルゴリズムによる画像データの再生成を行う。コインシデンス検出は、入射時刻が略一致する2つ以上の検出データがある場合、それらの検出データを有効と判定し、コインシデンス情報とする。また、コインシデンス検出は、ガンマ線入射時刻が一致しない検出データを無効と判定し破棄する。そして、コインシデンス情報と、コインシデンス情報に含まれる検出素子番号等と、これに対応する検出素子の位置情報等から所定の画像再生成アルゴリズム(例えば、期待値最大化(Expectation Maximization)法)に基づいて画像データを再生成する。表示部13は、入出力部15の要求に応じて再生成された画像データを表示する。   The information processing unit 12 performs coincidence detection and image data regeneration using an image regeneration algorithm based on the detection data. In the coincidence detection, when there are two or more pieces of detection data whose incident times substantially coincide with each other, it is determined that these pieces of detection data are valid and used as coincidence information. In the coincidence detection, detection data whose gamma ray incident times do not match is determined to be invalid and discarded. Then, based on the coincidence information, the detection element number included in the coincidence information, the position information of the detection element corresponding to the coincidence information, and the like, based on a predetermined image regeneration algorithm (for example, expectation maximization (Expectation Maximization method)) Regenerate the image data. The display unit 13 displays the image data regenerated in response to a request from the input / output unit 15.

以上の構成および動作により、PET装置10は、被検体Sの体内に選択的に位置するポジトロン核種RIからのガンマ線を検出し、ポジトロン核種RIの分布状態の画像データを再生成する。   With the above configuration and operation, the PET apparatus 10 detects gamma rays from the positron nuclide RI selectively located in the body of the subject S, and regenerates image data of the distribution state of the positron nuclide RI.

検出器111〜118は、被検体Sの周囲に360度に亘って配置される。各々の検出器111〜118には、被検体S側に半導体検出部20が設けられている。ここで、被検体Sの体軸方向をZ軸方向(Zおよび−Z方向)とする。検出器11は、被検体Sに対して相対的にZ軸方向に移動可能としてもよい。なお、図2において8個の検出器111〜118が示されているがこれらの数は一例過ぎず、検出器111〜118の数は適宜選択される。 The detectors 11 1 to 11 8 are arranged around the subject S over 360 degrees. Each of the detectors 11 1 to 11 8 is provided with a semiconductor detector 20 on the subject S side. Here, the body axis direction of the subject S is defined as the Z-axis direction (Z and −Z directions). The detector 11 may be movable relative to the subject S in the Z-axis direction. Although eight detectors 11 1 to 11 8 in FIG. 2 is shown the number of these are only examples, the number of detectors 11 1 to 11 8 is appropriately selected.

図3は、第1の実施の形態の半導体検出部の構成を示す分解斜視図、図4は、第1の実施の形態の半導体検出部の概略平面図である。図3は、おおよそガンマ線の略入射側から半導体検出部を見た図であり、説明の便宜上、配線基板上に配置される構成要素を上方に分離して示している。また、図4は、半導体検出素子22を透視して示している。   FIG. 3 is an exploded perspective view showing the configuration of the semiconductor detection unit of the first embodiment, and FIG. 4 is a schematic plan view of the semiconductor detection unit of the first embodiment. FIG. 3 is a diagram of the semiconductor detection unit viewed from the substantially incident side of the gamma rays. For convenience of explanation, components arranged on the wiring board are shown separated upward. FIG. 4 is a perspective view of the semiconductor detection element 22.

図3および図4を参照するに、半導体検出部20は、配線基板21と、配線基板21上に配置された半導体検出素子22と、半導体検出素子22に電気的に接続されるパッド電極261〜268(特に断らない限り符号26で示す。)と、配線基板21に形成された配線パターン30と、半導体検出素子22の検出信号を検出回路(図3に示す検出回路16)に送出するためのコネクタ29a等からなる。 Referring to FIGS. 3 and 4, the semiconductor detection unit 20 includes a wiring board 21, a semiconductor detection element 22 disposed on the wiring board 21, and a pad electrode 26 1 electrically connected to the semiconductor detection element 22. ˜26 8 (indicated by reference numeral 26 unless otherwise specified), the wiring pattern 30 formed on the wiring substrate 21, and the detection signal of the semiconductor detection element 22 are sent to the detection circuit (detection circuit 16 shown in FIG. 3). Connector 29a and the like.

半導体検出素子22は、略平板状の半導体結晶体23と、半導体結晶体23の下面に形成された第1電極部24と上面に形成された第2電極部25からなる。   The semiconductor detection element 22 includes a substantially flat semiconductor crystal 23, a first electrode portion 24 formed on the lower surface of the semiconductor crystal 23, and a second electrode portion 25 formed on the upper surface.

半導体結晶体23は、その材料としては、例えば、エネルギーが511keVのガンマ線に有感なテルル化カドミウム(CdTe)、Cd1-xZnxTe(CZT)、臭化タリウム(TlBr)、シリコンなどが挙げられる。また、これらの材料には導電性等を制御するためのドーパントが含まれていてもよい。CdTeは、単位長さ当たりの光電吸収確率がシリコンの100倍程度ある点で好ましい。シリコンはCdTeよりも機械的強度が高いので加工中に結晶欠陥が生じにくい点で好ましい。半導体結晶体23は、半導体の結晶成長法であるブリッジマン法や、移動加熱法を用いて半導体結晶を形成し、所定の結晶方位に平板状に切出して得られる。また、半導体結晶体23がCdTeからなる場合は、半導体結晶体23はその第1電極部24との界面にInが拡散されている。これにより半導体結晶体23と第1電極部24との間にショットキー接合が形成される。 The material of the semiconductor crystal 23 is, for example, cadmium telluride (CdTe), Cd 1-x Zn x Te (CZT), thallium bromide (TlBr), silicon or the like sensitive to gamma rays having an energy of 511 keV. Can be mentioned. Moreover, the dopant for controlling electroconductivity etc. may be contained in these materials. CdTe is preferable in that the photoelectric absorption probability per unit length is about 100 times that of silicon. Silicon is preferable because it has a higher mechanical strength than CdTe, and thus crystal defects are less likely to occur during processing. The semiconductor crystal body 23 is obtained by forming a semiconductor crystal using a Bridgeman method, which is a semiconductor crystal growth method, or a moving heating method, and cutting it into a flat plate shape with a predetermined crystal orientation. When the semiconductor crystal 23 is made of CdTe, In is diffused in the interface between the semiconductor crystal 23 and the first electrode portion 24. As a result, a Schottky junction is formed between the semiconductor crystal body 23 and the first electrode portion 24.

第2電極部25は、半導体結晶体23の上面を略覆う導電膜からなる。第2電極部25には負のバイアス電圧Vbが印加され、カソードとなっている。半導体結晶体23がCdTeからなる場合は第2電極部25にはPtが用いられる。バイアス電圧Vbは、直流電圧で例えば−60V〜−1000Vに設定される。なお、バイアス電圧は、配線基板21の外部から、コネクタ29b、配線パターン30a、パッド31およびワイヤー32を介して第2電極部25に形成される。   The second electrode portion 25 is made of a conductive film that substantially covers the upper surface of the semiconductor crystal body 23. A negative bias voltage Vb is applied to the second electrode portion 25 to serve as a cathode. When the semiconductor crystal 23 is made of CdTe, Pt is used for the second electrode portion 25. The bias voltage Vb is a DC voltage and is set to, for example, −60V to −1000V. The bias voltage is formed on the second electrode portion 25 from the outside of the wiring substrate 21 through the connector 29b, the wiring pattern 30a, the pad 31, and the wire 32.

第1電極部24は、半導体結晶体23の下面に、そのY軸方向全体に延在し、X軸方向には所定の幅で形成された8個の素子電極241〜248(特に断らない限り符号24で示す。また、図中一部の符号を省略している。)からなる。素子電極24の各々は、X軸方向に隣接する素子電極24と互いに離隔され、電気的に絶縁されている。素子電極24は例えばAu膜からなり、例えば、幅(X軸方向の長さ)が0.5mm、X軸方向の間隔が0.1mm、奥行き(Y軸方向の長さ)が5mmに設定される。素子電極24の各々は抵抗を介して接地されアノードとして機能する。なお、ここでは素子電極24の数を8個としているが、2個以上であればその数に特に制限はない。 The first electrode portion 24 extends to the entire lower surface of the semiconductor crystal body 23 in the Y-axis direction, and is formed with eight element electrodes 24 1 to 24 8 (particularly refused) formed with a predetermined width in the X-axis direction. Unless otherwise indicated, reference numeral 24 is also provided. Each of the element electrodes 24 is separated from and electrically insulated from the element electrodes 24 adjacent in the X-axis direction. The element electrode 24 is made of, for example, an Au film, and has a width (length in the X-axis direction) of 0.5 mm, an interval in the X-axis direction of 0.1 mm, and a depth (length in the Y-axis direction) of 5 mm. The Each of the element electrodes 24 is grounded via a resistor and functions as an anode. Although the number of element electrodes 24 is eight here, the number is not particularly limited as long as it is two or more.

次に半導体検出素子22の動作を説明する。半導体検出素子22は、ガンマ線が半導体結晶体23に入射すると、半導体結晶体23中で電子正孔対が生成される。半導体結晶体23には、素子電極24から第2電極部25に向かって電界が印加されているので、正孔は第2電極部25に引きつけられ、電子は素子電極24に引きつけられる。この際、電子は最も近い素子電極24に引きつけられ、素子電極24毎に接続される検出回路にガンマ線が入射したことを示す検出信号が形成される。   Next, the operation of the semiconductor detection element 22 will be described. In the semiconductor detection element 22, when gamma rays are incident on the semiconductor crystal body 23, electron-hole pairs are generated in the semiconductor crystal body 23. Since an electric field is applied to the semiconductor crystal body 23 from the device electrode 24 toward the second electrode portion 25, holes are attracted to the second electrode portion 25 and electrons are attracted to the device electrode 24. At this time, electrons are attracted to the nearest element electrode 24, and a detection signal indicating that gamma rays are incident on a detection circuit connected to each element electrode 24 is formed.

配線基板21は、熱膨張係数が8.0×10-6[1/℃]以上の基板を用いる。このような基板としては、ガラスエポキシ基板またはフレキシブルプリント基板等の樹脂を含有するプリント基板が挙げられる。樹脂を含有するプリント基板は、従来用いられているアルミナ基板やガラス基板よりも設計および製造が容易であり安価である。PET装置は大型化するほどより多くの検出器を必要とし、それに対応する数の配線基板21を必要とするので、配線基板21のコスト低減は、PET装置10のコスト低減の寄与が極めて大きい。但し、配線基板21の熱膨張係数は20×10-6[1/℃]以下に設定すべきである。配線基板21の熱膨張係数が20×10-6[1/℃]を超えるとバンプ28により後ほど詳述する応力を十分に吸収し難くなる。 As the wiring board 21, a board having a thermal expansion coefficient of 8.0 × 10 −6 [1 / ° C.] or more is used. Examples of such a substrate include a printed board containing a resin such as a glass epoxy board or a flexible printed board. A printed circuit board containing a resin is easier and cheaper to design and manufacture than conventionally used alumina and glass substrates. As the PET apparatus increases in size, more detectors are required and a corresponding number of wiring boards 21 are required. Therefore, the cost reduction of the wiring board 21 greatly contributes to the cost reduction of the PET apparatus 10. However, the thermal expansion coefficient of the wiring board 21 should be set to 20 × 10 −6 [1 / ° C.] or less. If the thermal expansion coefficient of the wiring board 21 exceeds 20 × 10 −6 [1 / ° C.], it will be difficult to sufficiently absorb the stress described in detail later by the bumps 28.

ガラスエポキシ基板は、ガラスクロスに変性エポキシ基板を含浸して熱硬化させたものであり、例えば、いわゆるFR−4やFR−5のグレードのプリント配線基板である。ガラスエポキシ基板の熱膨張係数は面内方向(図3中のX−Y面の面内方向)で10×10-6〜16×10-6[1/℃]である。 The glass epoxy board is obtained by impregnating a glass cloth with a modified epoxy board and thermosetting, for example, a so-called FR-4 or FR-5 grade printed wiring board. The thermal expansion coefficient of the glass epoxy substrate is 10 × 10 −6 to 16 × 10 −6 [1 / ° C.] in the in-plane direction (in-plane direction of the XY plane in FIG. 3).

また、フレキシブルプリント基板は、ポリエステル樹脂やポリイミド樹脂のフィルムに銅箔あるいは銅メッキ等で配線パターンを形成したものである。フレキシブルプリント基板の熱膨張係数は面内方向で12×10-6〜20×10-6[1/℃]である。なお、ガラスエポキシ基板およびフレキシブルプリント基板は、単層基板および多層積層基板のいずれでもよい。 Further, the flexible printed circuit board is obtained by forming a wiring pattern on a film of polyester resin or polyimide resin with copper foil or copper plating. The thermal expansion coefficient of the flexible printed circuit board is 12 × 10 −6 to 20 × 10 −6 [1 / ° C.] in the in-plane direction. Note that the glass epoxy substrate and the flexible printed circuit board may be either a single layer substrate or a multilayer laminated substrate.

半導体検出素子22は、その第1電極部24と、配線基板21に設けられたパッド電極261〜268とが導電性接着剤からなるバンプ28により互いに固着されている。具体的には、第1電極部24の素子電極241〜248の各々と配線基板21の表面に設けられたパッド電極261〜268の各々とが導電性接着剤からなる2つのバンプ28により固着されている。これにより、従来のべた付けによる接合方法よりも配線基板21の熱膨張により生じる応力が半導体結晶体23に伝わりにくくなり、検出特性の劣化を抑制できる(後ほど詳述する)。 In the semiconductor detection element 22, the first electrode portion 24 and the pad electrodes 26 1 to 26 8 provided on the wiring substrate 21 are fixed to each other by a bump 28 made of a conductive adhesive. Specifically, each of the element electrodes 24 1 to 24 8 of the first electrode section 24 and each of the pad electrodes 26 1 to 26 8 provided on the surface of the wiring board 21 are two bumps made of a conductive adhesive. 28 is fixed. As a result, the stress caused by the thermal expansion of the wiring board 21 is less likely to be transmitted to the semiconductor crystal body 23 than in the conventional bonding method by sticking, and deterioration of detection characteristics can be suppressed (detailed later).

バンプ28を形成する導電性接着剤は、Au、Ag、Cu、およびこれらの合金から選択される金属粉やカーボンフィラーと樹脂からなる、いわゆる導電性ペーストや異方性接着剤を用いることができる。導電性接着剤は、接合した後の固化した状態でずれ弾性が半導体結晶体23のヤング率よりも小さい材料が用いられる。半導体結晶体23のヤング率は、CdTeが54×109Pa、シリコンが167×109Paである。一方、導電性接着剤には、例えば、固化後のずれ弾性が1.0×109Paの市販品を用いるとよい。 As the conductive adhesive forming the bumps 28, a so-called conductive paste or anisotropic adhesive made of metal powder selected from Au, Ag, Cu, and alloys thereof, a carbon filler, and a resin can be used. . As the conductive adhesive, a material having a deviation elasticity smaller than the Young's modulus of the semiconductor crystal 23 in a solidified state after bonding is used. The Young's modulus of the semiconductor crystal body 23 is 54 × 10 9 Pa for CdTe and 167 × 10 9 Pa for silicon. On the other hand, as the conductive adhesive, for example, a commercially available product having a deviation elasticity after solidification of 1.0 × 10 9 Pa may be used.

また、バンプ28の厚さは、例えば100μmに設定される。バンプの厚さは厚いほど後ほど説明する応力吸収の効果は高いが、例えば10μm〜200μmの範囲に設定することが好ましい。   Further, the thickness of the bump 28 is set to 100 μm, for example. The thicker the bump is, the higher the effect of absorbing stress, which will be described later, but it is preferable to set the bump in the range of 10 μm to 200 μm, for example.

半導体検出素子22と配線基板21との接合工程を図3を参照しつつ説明する。最初に配線基板21のパッド電極26の各々に、導電性ペーストをグラビア印刷法等の塗布法により2個のバンプ28を形成する。次いで、図示されないステージに載置された配線基板21に対して半導体検出素子22を位置決めする。次いで半導体検出素子22を配線基板21上に配置し仮接合する。   A bonding process between the semiconductor detection element 22 and the wiring substrate 21 will be described with reference to FIG. First, two bumps 28 are formed on each pad electrode 26 of the wiring board 21 by applying a conductive paste such as a gravure printing method. Next, the semiconductor detection element 22 is positioned with respect to the wiring substrate 21 placed on a stage (not shown). Next, the semiconductor detection element 22 is disposed on the wiring board 21 and temporarily joined.

次いで、半導体検出素子22を上方から抑え治具で圧接しながら、ホットプレートやオーブンにより配線基板21と半導体検出素子22とを例えば温度120℃で加熱時間60分、あるいは温度150℃で加熱時間2分〜4分の条件で加熱して本接合する。次いで、冷却する際に、導電性ペーストが固化開始後に上記の抑え治具を半導体検出素子22から離し、さらに室温まで冷却する。以上により、半導体検出素子22と配線基板21とが接合される。   Next, while holding the semiconductor detection element 22 from above and pressing it with a jig, the wiring board 21 and the semiconductor detection element 22 are heated, for example, at a temperature of 120 ° C. for 60 minutes, or at a temperature of 150 ° C. for a heating time of 2 The main bonding is performed by heating under the conditions of min to 4 min. Next, when cooling, after the conductive paste starts to solidify, the holding jig is separated from the semiconductor detection element 22 and further cooled to room temperature. As described above, the semiconductor detection element 22 and the wiring substrate 21 are joined.

図5および図6は、第1の実施の形態の作用を説明するための図である。図5(A)および図6(A)は、配線基板と半導体検出素子とを本接合工程におけるバンプの固化開始時点での状態を示す図であり、図5(B)および図6(B)は固化後の状態を示す図である。なお、図5は図3に示すX軸方向の断面図の一部(一例として素子電極241と242を含む部分)、図6は図3に示すY軸方向の断面図の一部(一例として素子電極241を含む部分)を示している。 5 and 6 are diagrams for explaining the operation of the first embodiment. FIGS. 5A and 6A are views showing a state of the wiring board and the semiconductor detection element at the start of solidification of the bumps in the main joining step, and FIGS. 5B and 6B. FIG. 3 is a diagram showing a state after solidification. 5 is a part of the cross-sectional view in the X-axis direction shown in FIG. 3 (part including the device electrodes 24 1 and 24 2 as an example), and FIG. 6 is a part of the cross-sectional view in the Y-axis direction shown in FIG. As an example, a portion including the device electrode 24 1 is shown.

図5(A)を参照するに、上述した接合工程の本接合の温度から室温に戻る際に、バンプ28の固化開始時点では、配線基板21および半導体結晶体23はそれぞれ矢印21a,23a方向に収縮しようとする。配線基板21の熱膨張係数が半導体結晶体23の熱膨張係数よりも大きいため、この時点では配線基板21は半導体結晶体23よりも膨張しているため、バンプ28は、素子電極241と242との間隔よりもパッド電極261と262との間隔の方が広く、パッド電極261,262側でX軸方向の外側にしなっている。 Referring to FIG. 5A, when returning from the temperature of the main bonding in the bonding process described above to room temperature, the wiring board 21 and the semiconductor crystal body 23 are in the directions of arrows 21a and 23a, respectively, at the start of the solidification of the bumps 28. Try to shrink. Since the thermal expansion coefficient of the wiring board 21 is larger than the thermal expansion coefficient of the semiconductor crystal 23, the wiring substrate 21 at this point because it expands more than the semiconductor crystal 23, the bumps 28, device electrodes 24 1 and 24 wider towards the gap between the pad electrode 26 1 and 26 2 than the distance between 2, which is on the outside of the X-axis direction in the pad electrode 26 1, 26 2 side.

図5(B)を参照するに、バンプ28の固化後は、図5(A)のバンプの固化開始時点から固化するまでに配線基板21が収縮した量が、半導体結晶体23が収縮した量よりも大きい。仮にバンプ28が理想的な剛体の場合は、配線基板21が収縮により生じる圧縮応力がバンプを介して半導体結晶体23に印加される。しかし、バンプ28が半導体結晶体23のヤング率よりも低いずれ弾性を有するため、配線基板21からの応力を吸収する。すなわち、図5(A)に示すバンプがしなった状態と図5(B)に示すバンプが略直立した状態とのしなり量の差をバンプ自体が略吸収するので、半導体結晶体23に印加される応力を抑制する。これにより、半導体結晶体23の検出特性の劣化を抑制できる。この作用は、図6(A)および(B)に示すY軸方向の断面においても同様であり、バンプ28がそのしなりを吸収することで、Y軸方向の熱膨張係数差により生じる半導体結晶体23に印加される応力を抑制する。   Referring to FIG. 5B, after the bumps 28 are solidified, the amount of shrinkage of the wiring substrate 21 from the solidification start time of the bumps of FIG. Bigger than. If the bump 28 is an ideal rigid body, a compressive stress generated by contraction of the wiring board 21 is applied to the semiconductor crystal body 23 via the bump. However, since the bump 28 has elasticity that is lower than the Young's modulus of the semiconductor crystal body 23, the stress from the wiring substrate 21 is absorbed. That is, since the bump itself substantially absorbs the difference in bending amount between the state where the bump shown in FIG. 5A is bent and the state where the bump shown in FIG. Suppresses applied stress. Thereby, deterioration of the detection characteristics of the semiconductor crystal body 23 can be suppressed. This effect is the same in the cross section in the Y-axis direction shown in FIGS. 6A and 6B, and the semiconductor crystal produced by the difference in the thermal expansion coefficient in the Y-axis direction by the bump 28 absorbing the deformation. The stress applied to the body 23 is suppressed.

また、バンプ28と半導体結晶体23(素子電極241,242を介する。)との接触領域では、バンプ28自体の収縮による圧縮応力が半導体結晶体23に印加されるが、バンプと半導体結晶体23とが接触する面積はベタ付けよりも極めて小さいためこの点でも半導体結晶体23に印加される応力を抑制できる。 In the contact region between the bump 28 and the semiconductor crystal 23 (via the device electrodes 24 1 and 24 2 ), compressive stress due to contraction of the bump 28 itself is applied to the semiconductor crystal 23. Since the area in contact with the body 23 is extremely smaller than the sticking, the stress applied to the semiconductor crystal body 23 can also be suppressed in this respect.

第1の実施の形態によれば、配線基板21に従来よりも熱膨張係数が大きい基板を用いている。半導体検出素子22と配線基板21とを導電性接着剤からなるバンプ28を用いている。バンプは、そのずれ弾性が固化後の状態で半導体結晶体23のヤング率よりも小さい材料が用いられるので、配線基板21と半導体結晶体23との熱膨張係数差により生じる応力を吸収して半導体結晶体23に印加される応力を抑制する。したがって、半導体結晶体23と熱膨張係数差が大きな配線基板21を用いても半導体結晶体23の検出特性の劣化を抑制できる。さらに、製造コストの安価なガラスエポキシ基板やフレキシブルプリント基板を使用できるので、アルミナ基板やガラス基板よりも製造コストの低減を図れる。   According to the first embodiment, a substrate having a larger thermal expansion coefficient than the conventional one is used for the wiring substrate 21. A bump 28 made of a conductive adhesive is used for the semiconductor detection element 22 and the wiring substrate 21. The bump is made of a material whose elasticity is less than the Young's modulus of the semiconductor crystal 23 in a state after solidification. Therefore, the bump absorbs the stress caused by the difference in thermal expansion coefficient between the wiring substrate 21 and the semiconductor crystal 23 and thus the semiconductor. The stress applied to the crystal body 23 is suppressed. Therefore, even if the wiring substrate 21 having a large difference in thermal expansion coefficient from that of the semiconductor crystal 23 is used, it is possible to suppress the deterioration of the detection characteristics of the semiconductor crystal 23. Furthermore, since a glass epoxy substrate or a flexible printed circuit board with a low manufacturing cost can be used, the manufacturing cost can be reduced as compared with an alumina substrate or a glass substrate.

さらに、保存環境下、例えば0℃〜50℃の温度範囲における温度変化によって、配線基板21の熱膨張による寸法変化が生じるが、上述した作用と同様にしてバンプ28により配線基板21の寸法変化により生じる応力が半導体結晶体23に印加されることを抑制できる。したがって、製造時のみならず製造後においても半導体結晶体23の検出特性の劣化を抑制でき、放射線検出器およびPET装置10の長期信頼性が向上する。   Furthermore, a dimensional change due to thermal expansion of the wiring board 21 occurs due to a temperature change in a temperature range of 0 ° C. to 50 ° C., for example, in a storage environment. Application of the generated stress to the semiconductor crystal body 23 can be suppressed. Therefore, deterioration of the detection characteristics of the semiconductor crystal body 23 can be suppressed not only during the manufacturing but also after the manufacturing, and the long-term reliability of the radiation detector and the PET apparatus 10 is improved.

(第2の実施の形態)
次に本発明の第2の実施の形態に係るPET装置を説明する。第2の実施の形態に係るPET装置は、第1の実施の形態に係るPET装置の変形例であり、図3で示した半導体検出部20の半導体検出素子22が異なる以外は同様の構成を有する。
(Second Embodiment)
Next, a PET apparatus according to the second embodiment of the present invention will be described. The PET apparatus according to the second embodiment is a modification of the PET apparatus according to the first embodiment, and has the same configuration except that the semiconductor detection element 22 of the semiconductor detection unit 20 shown in FIG. 3 is different. Have.

図7は、本発明の第2の実施の形態に係るPET装置の半導体検出部の構成を示す斜視図である。図中、先に説明した部分に対応する部分には同一の参照符号付し、説明を省略する。   FIG. 7 is a perspective view showing the configuration of the semiconductor detection unit of the PET apparatus according to the second embodiment of the present invention. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

図7を参照するに、半導体検出素子42は、半導体結晶体43の第1電極部44側にX軸方向に所定の間隔でかつY軸方向に延在する溝部43aが形成されている。半導体検出素子42は、さらに、互いに隣接する溝部43aと溝部43aとの間の凸部43bの表面に素子電極241〜248が形成されている。半導体結晶体43の材料等は図3の半導体結晶体23と同様である。溝部43aの幅は、例えば0.1mm、深さは0.3mmに設定される。なお、この場合の素子電極24の幅および間隔は第1の実施の形態に示したものと同様である。 Referring to FIG. 7, in the semiconductor detection element 42, a groove 43 a extending in the X axis direction at a predetermined interval and extending in the Y axis direction is formed on the first electrode portion 44 side of the semiconductor crystal body 43. In the semiconductor detection element 42, element electrodes 24 1 to 24 8 are further formed on the surface of the convex portion 43b between the adjacent groove portions 43a and 43a. The material of the semiconductor crystal 43 is the same as that of the semiconductor crystal 23 in FIG. The width of the groove 43a is set to 0.1 mm, for example, and the depth is set to 0.3 mm. In this case, the width and interval of the element electrodes 24 are the same as those shown in the first embodiment.

このように第1電極部44側に溝部43aを設けることで、半導体結晶体43にガンマ線が入射して電子正孔対が生成された際に、電子を最も近い素子電極241〜248に集中させることができる。その結果、検出信号の波高値が高くなり、ガンマ線の位置検出分解能が向上する。さらに、溝部43aを設けることで、次の効果が生じる。 Thus, by providing the groove 43a on the first electrode portion 44 side, when gamma rays are incident on the semiconductor crystal body 43 and an electron-hole pair is generated, electrons are transferred to the closest device electrodes 24 1 to 24 8 . Can concentrate. As a result, the peak value of the detection signal is increased, and the position detection resolution of the gamma ray is improved. Furthermore, the following effects are produced by providing the groove 43a.

図8は、第2の実施の形態の作用を説明するための図であり、配線基板と半導体検出素子とを本接合工程におけるバンプの固化後の状態を示す図である。なお、図8は図7に示すX軸方向の断面図の一部(一例として素子電極241と242を含む部分)を示している。 FIG. 8 is a diagram for explaining the operation of the second embodiment, and is a diagram showing a state after the bumps are solidified in the main bonding step between the wiring board and the semiconductor detection element. 8 shows a part of the cross-sectional view in the X-axis direction shown in FIG. 7 (a part including element electrodes 24 1 and 24 2 as an example).

図8を参照するに、半導体結晶体43の溝部43aの上方の領域43cは、素子電極241,242が接する領域43dよりも溝部43aが形成されているため薄くなっており、機械的強度が領域43dよりも劣る。バンプ28の固化後の状態において、バンプ28により配線基板21と半導体結晶体43との熱膨張係数差により生じる応力が抑制されている。しかし、半導体結晶体43にはバンプ28により完全に吸収できない応力が残るおそれがある。この応力は、素子電極241と242との間隔を狭める方向に印加され、これにより領域43cに矢印43eで示すように引張り応力が印加される。領域43cは、素子電極241と素子電極242との間の領域なので、この位置でガンマ線の入射により生成された電子正孔対は領域43dで生成された電子正孔対よりも位置検出を目的とする必要性は低い。したがって、領域43cに応力を集中させ、領域43dへの応力印加を回避でき、その結果、検出特性の劣化をいっそう抑制できる。 Referring to FIG. 8, the region 43c above the groove 43a of the semiconductor crystal body 43 is thinner than the region 43d where the device electrodes 24 1 and 24 2 are in contact with each other, so that the mechanical strength is reduced. Is inferior to the region 43d. In the state after the bumps 28 are solidified, the stress caused by the difference in thermal expansion coefficient between the wiring substrate 21 and the semiconductor crystal body 43 is suppressed by the bumps 28. However, there is a possibility that stress that cannot be completely absorbed by the bumps 28 remains in the semiconductor crystal body 43. This stress is applied in a direction that narrows the distance between the device electrodes 24 1 and 24 2, and thereby a tensile stress is applied to the region 43 c as indicated by an arrow 43 e. Since the region 43c is a region between the device electrode 24 1 and the device electrode 24 2 , the electron-hole pair generated by the incidence of gamma rays at this position is detected more than the electron-hole pair generated in the region 43d. The need for purpose is low. Therefore, stress can be concentrated on the region 43c and stress application to the region 43d can be avoided, and as a result, deterioration of detection characteristics can be further suppressed.

なお、溝部43aは、上述したように半導体結晶体43のY軸方向に全体に亘って形成することが好ましいが、Y軸方向の一部に溝部を設けてもよい。この場合、上述した効果と同様の効果が生じる。但し、その効果の程度は低下するが配線基板21の熱膨張係数と半導体結晶体43の熱膨張係数との差の程度に応じて適宜適用すればよい。   In addition, although it is preferable to form the groove part 43a over the whole Y-axis direction of the semiconductor crystal body 43 as mentioned above, you may provide a groove part in a part of Y-axis direction. In this case, the same effect as described above is produced. However, although the degree of the effect is reduced, it may be appropriately applied depending on the degree of difference between the thermal expansion coefficient of the wiring substrate 21 and the thermal expansion coefficient of the semiconductor crystal body 43.

第2の実施の形態によれば、半導体結晶体43の第1電極部44側に溝部43aを設けることで、配線基板21と半導体結晶体43との熱膨張係数差により生じる応力を領域43cに集中させることで、素子電極24が接する領域43dへの応力印加を回避できる。その結果、検出特性の劣化をいっそう抑制できる。   According to the second embodiment, by providing the groove 43a on the first electrode portion 44 side of the semiconductor crystal 43, the stress caused by the difference in thermal expansion coefficient between the wiring substrate 21 and the semiconductor crystal 43 is applied to the region 43c. By concentrating, application of stress to the region 43d with which the element electrode 24 is in contact can be avoided. As a result, the deterioration of detection characteristics can be further suppressed.

なお、上記の第1および第2の実施の形態では、図3および図7に示したように、素子電極24およびパッド電極26の1組当たりのバンプの数を2個としたが、3個以上でもよい。但し、各々のバッド間は離隔されていることが必要である。さらに、次に示すように素子電極およびパッド電極の1組当たりのバンプの数を1個としてもよい。   In the first and second embodiments described above, as shown in FIGS. 3 and 7, the number of bumps per set of the element electrode 24 and the pad electrode 26 is two, but three That's all. However, each pad needs to be separated. Furthermore, as shown below, the number of bumps per set of element electrodes and pad electrodes may be one.

図9は半導体検出部の変形例を示す概略平面図である。図中、先に説明した部分に対応する部分には同一の参照符号付し、説明を省略する。   FIG. 9 is a schematic plan view showing a modification of the semiconductor detection unit. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

図9を参照するに、半導体検出部50は、図3に示す第1の実施の形態の半導体検出部20の変形例である。半導体検出部50は、半導体検出素子22と配線基板21とが、素子電極241〜248およびパッド電極261〜268の1組当たり1個のバンプ28により接合されている。バンプ28が1個の場合は、Y軸方向の熱膨張により生じた圧縮応力がバンプ28および半導体結晶体23に印加されないので、よりいっそう半導体結晶体23への応力印加による検出特性の劣化を抑制できる。なお、図7に示す半導体検出部40においても上記のように1組の素子電極44およびパッド電極26を1個のバンプで接合してもよい。 Referring to FIG. 9, a semiconductor detection unit 50 is a modification of the semiconductor detection unit 20 of the first embodiment shown in FIG. In the semiconductor detection unit 50, the semiconductor detection element 22 and the wiring substrate 21 are joined by one bump 28 per set of element electrodes 24 1 to 24 8 and pad electrodes 26 1 to 26 8 . In the case of a single bump 28, the compressive stress generated by the thermal expansion in the Y-axis direction is not applied to the bump 28 and the semiconductor crystal 23, thereby further suppressing the deterioration of detection characteristics due to the stress applied to the semiconductor crystal 23. it can. In the semiconductor detection unit 40 shown in FIG. 7 as well, one set of element electrode 44 and pad electrode 26 may be joined by one bump as described above.

次に半導体検出部の他の変形例を説明する。   Next, another modification of the semiconductor detection unit will be described.

図10は、半導体検出部の他の変形例を示す概略平面図、図11は、図10に示すA−A線断面図である。図中、先に説明した部分に対応する部分には同一の参照符号付し、説明を省略する。   FIG. 10 is a schematic plan view showing another modification of the semiconductor detection unit, and FIG. 11 is a cross-sectional view taken along line AA shown in FIG. In the figure, portions corresponding to the portions described above are denoted by the same reference numerals, and description thereof is omitted.

図10および図11を参照するに、半導体検出部60は、配線基板21が隣接するパッド電極261〜268間にスリット状の開口部21aが設けられている。開口部21aは、配線基板21の厚さ方向に貫通している。開口部21aの幅(X軸方向の長さ)は、パッド電極261〜268間の間隙よりも小さく設定される。但し、配線基板21の平坦性が損なわれない程度の幅に設定される。このような開口部21aを設けることにより配線基板21の熱膨張による寸法変化を抑制できる。したがって、配線基板21と半導体結晶体23との熱膨張係数差により生じる数法変化量を低減できる。その結果、配線基板21と半導体結晶体23との熱膨張係数差により生じる応力を低減することにより、半導体結晶体23に印加される応力をいっそう抑制できる。その結果、半導体結晶体23の検出特性の劣化をいっそう抑制できる。なお、本変形例は、図7に示す半導体検出部40に適用することでさらに効果が高まる。 Referring to FIGS. 10 and 11, the semiconductor detection unit 60, a slit-shaped opening 21a is provided between the pad electrode 26 1-26 8 wiring board 21 is adjacent. The opening 21 a penetrates in the thickness direction of the wiring board 21. The width of the opening 21a (X-axis direction length) is set smaller than the gap between the pad electrodes 26 1 to 26 8. However, the width is set such that the flatness of the wiring board 21 is not impaired. By providing such an opening 21a, a dimensional change due to thermal expansion of the wiring board 21 can be suppressed. Therefore, it is possible to reduce the numerical change caused by the difference in thermal expansion coefficient between the wiring substrate 21 and the semiconductor crystal body 23. As a result, the stress applied to the semiconductor crystal body 23 can be further suppressed by reducing the stress caused by the difference in thermal expansion coefficient between the wiring substrate 21 and the semiconductor crystal body 23. As a result, the deterioration of the detection characteristics of the semiconductor crystal body 23 can be further suppressed. In addition, the effect is further enhanced by applying this modification to the semiconductor detection unit 40 shown in FIG.

以上本発明の好ましい実施の形態について詳述したが、本発明は係る特定の実施の形態に限定されるものではなく、特許請求の範囲に記載された本発明の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It can be changed.

例えば、上述した第1の実施の形態では、PET装置を例に説明したが、本発明は、SPECT(単一光子放射形コンピュータ断層撮影)装置に適用できる。また、上記では半導体検出部がガンマ線を検出する場合を例に説明したが、X線や他の放射線の半導体検出部にも適用できることはいうまでもない。   For example, in the above-described first embodiment, the PET apparatus has been described as an example, but the present invention can be applied to a SPECT (Single Photon Emission Computed Tomography) apparatus. In the above description, the case where the semiconductor detection unit detects gamma rays has been described as an example. However, it goes without saying that the present invention can also be applied to a semiconductor detection unit for X-rays or other radiation.

従来の半導体検出器の問題点を説明するための図である。It is a figure for demonstrating the problem of the conventional semiconductor detector. 本発明の第1の実施の形態に係るPET装置の構成を示すブロック図である。It is a block diagram which shows the structure of the PET apparatus which concerns on the 1st Embodiment of this invention. 第1の実施の形態の半導体検出部の構成を示す分解斜視図である。It is a disassembled perspective view which shows the structure of the semiconductor detection part of 1st Embodiment. 第1の実施の形態の半導体検出部の概略平面図である。It is a schematic plan view of the semiconductor detection part of 1st Embodiment. 第1の実施の形態の作用を説明するための図(その1)である。It is FIG. (1) for demonstrating the effect | action of 1st Embodiment. 第1の実施の形態の作用を説明するための図(その2)である。It is FIG. (2) for demonstrating the effect | action of 1st Embodiment. 本発明の第2の実施の形態に係るPET装置の半導体検出部の構成を示す斜視図である。It is a perspective view which shows the structure of the semiconductor detection part of the PET apparatus which concerns on the 2nd Embodiment of this invention. 第2の実施の形態の作用を説明するための図である。It is a figure for demonstrating the effect | action of 2nd Embodiment. 半導体検出部の変形例を示す概略平面図である。It is a schematic plan view which shows the modification of a semiconductor detection part. 半導体検出部の他の変形例を示す概略平面図である。It is a schematic plan view which shows the other modification of a semiconductor detection part. 図10に示すA−A線断面図である。It is the sectional view on the AA line shown in FIG.

符号の説明Explanation of symbols

10 PET装置
11,111〜118 検出器
12 情報処理部
13 表示部
14 制御部
15 入出力部
16 検出回路
20,40,50,60 半導体検出部
21 配線基板
22,42 半導体検出素子
23,43 半導体結晶体
24,44 第1電極部
241〜248 素子電極
25 第2電極部
26,261〜268 パッド電極
28 バンプ
29a,29b コネクタ
30,30a 配線パターン
43a 溝部
43b 凸部
10 PET device 11, 11 1 to 11 8 detector 12 information processing unit 13 display unit 14 control unit 15 input unit 16 detecting circuit 20,40,50,60 semiconductor detector 21 wiring board 22, 42 semiconductor detection device 23, 43 semiconductor crystal 24, 44 first electrode portion 24 1-24 8 element electrode 25 second electrode 26, 26 1 to 26 8 pad electrode 28 bumps 29a, 29b connector 30,30a wiring patterns 43a groove 43b protrusions

Claims (8)

配線基板と、該配線基板上に放射線の入射により電子正孔対を生成する半導体検出素子を備える放射線検出器であって、
前記半導体検出素子は、略板状の半導体結晶体と、該半導体結晶体の厚さ方向に直交し、配線基板側の第1の主面に、略等間隔で互いに離隔して配列された複数の素子電極からなる第1の電極部と、その反対側の第2の主面に、該第2の主面を略覆う金属膜からなる第2の電極部とを有し、
前記配線基板は、その表面に前記第1の電極部の素子電極に対応するパッド電極が設けられると共に、その熱膨張係数が8.0×10-6[1/℃]以上であり、
前記半導体検出素子は、前記素子電極の各々とパッド電極の各々とが、半導体結晶体のヤング率よりも小さいずれ弾性を有する導電性接着剤からなるバンプ状接着部により固着されてなり、該バンプ状接着部が素子電極とパッド電極とが互いに対向する領域の一部に配設されてなることを特徴とする放射線検出器。
A radiation detector comprising a wiring board and a semiconductor detection element that generates electron-hole pairs by incidence of radiation on the wiring board,
The semiconductor detection element includes a substantially plate-like semiconductor crystal body and a plurality of semiconductor crystal bodies that are orthogonal to the thickness direction of the semiconductor crystal body and arranged on the first main surface on the wiring board side so as to be spaced apart from each other at substantially equal intervals. A first electrode portion made of the element electrode and a second electrode portion made of a metal film substantially covering the second main surface on the second main surface on the opposite side,
The wiring board is provided with a pad electrode corresponding to the element electrode of the first electrode portion on the surface, and has a thermal expansion coefficient of 8.0 × 10 −6 [1 / ° C.] or more,
In the semiconductor detection element, each of the element electrodes and each of the pad electrodes are fixed by a bump-like adhesive portion made of a conductive adhesive having elasticity that is smaller than the Young's modulus of the semiconductor crystal. A radiation detector, characterized in that the adhesive portion is disposed in a part of a region where the element electrode and the pad electrode face each other.
前記半導体結晶体の第1の主面は、略平坦であることを特徴とする請求項1記載の放射線検出器。   The radiation detector according to claim 1, wherein the first main surface of the semiconductor crystal body is substantially flat. 前記半導体結晶体の第1の主面は、隣接する素子電極間に、配線基板の熱膨張に起因する応力を抑制するための溝部が形成されてなることを特徴とする請求項1記載の放射線検出器。   2. The radiation according to claim 1, wherein the first main surface of the semiconductor crystal is formed with a groove for suppressing stress caused by thermal expansion of the wiring board between adjacent element electrodes. Detector. 前記バンプ状接着部は、前記領域に互いに離隔して配設された複数のバンプからなることを特徴とする請求項1〜3のうち、いずれか一項記載の放射線検出器。   The radiation detector according to any one of claims 1 to 3, wherein the bump-shaped adhesive portion includes a plurality of bumps disposed in the region so as to be separated from each other. 前記バンプ状接着部は、前記領域に配設された一つのバンプからなることを特徴とする請求項1〜4のうち、いずれか一項記載の放射線検出器。   The radiation detector according to any one of claims 1 to 4, wherein the bump-shaped adhesive portion is formed of a single bump disposed in the region. 前記配線基板はガラスエポキシ基板またはフレキシブルプリント基板であることを特徴とする請求項1〜5のうち、いずれか一項記載の放射線検出器。   The radiation detector according to claim 1, wherein the wiring board is a glass epoxy board or a flexible printed board. 前記配線基板は、隣接するパッド電極間に、当該配線基板の厚さ方向に貫通する開口部を有することを特徴とする請求項1〜6のうち、いずれか一項記載の放射線検出器。   The radiation detector according to claim 1, wherein the wiring board has an opening penetrating in the thickness direction of the wiring board between adjacent pad electrodes. 放射性同位元素を含む被検体から発生する放射線を検出する請求項1〜7のうちいずれか一項記載の放射線検出器と、
前記放射線検出器から取得した放射線の入射時刻および入射位置を含む検出情報に基づいて前記放射性同位元素の被検体内における分布情報を取得する情報処理手段と、を備える放射線検査装置。
A radiation detector according to any one of claims 1 to 7, which detects radiation generated from a subject containing a radioisotope,
A radiation examination apparatus comprising: information processing means for acquiring distribution information of the radioisotope in a subject based on detection information including an incident time and an incident position of radiation acquired from the radiation detector.
JP2006029832A 2006-02-07 2006-02-07 Radiation detector and radiographic examination equipment Pending JP2007214191A (en)

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