JP2007213654A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can easily impart an identification signal to each semiconductor chip. <P>SOLUTION: The semiconductor device 1 includes several semiconductor chips 11 to 14. A generation circuit 20 is formed in each of the semiconductor chips 11 to 14. The generation circuit 20 generates an identification signal unique to each of the semiconductor chips 11 to 14. Concerning two semiconductor chips among the semiconductor chips 11 to 14, the generation circuit 20 arranged in one semiconductor chip receives the identification signal generated by the generation circuit arranged in the other semiconductor chip, and generates the identification signal for the above one semiconductor chip based on the received identification signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  As a conventional semiconductor device, for example, there is one described in Patent Document 1. In the semiconductor device described in this document, in order to distinguish between a plurality of memory chips stacked on each other, each memory chip is provided with a shift register that stores an identification code unique to the memory chip. In addition to the memory chip, an identification code generation circuit and an oscillator are provided.

In addition to Patent Document 1, Patent Documents 2 and 3 are cited as prior art documents related to the present invention.
Japanese Patent Laid-Open No. 10-97463 Japanese Patent Laid-Open No. 11-135711 JP 2000-137645 A

  In the semiconductor device, the identification code from the identification code generation circuit is sent to the shift register in accordance with the clock signal output from the oscillator. Thereby, the identification code is stored in the shift register of each memory chip. This takes time and effort to assign the identification code to each memory chip. Thus, the conventional semiconductor device has room for improvement in terms of simplifying the provision of the identification code.

  A semiconductor device according to the present invention includes a plurality of semiconductor chips, and a generation circuit that is provided in each of the semiconductor chips and generates an identification signal unique to each of the semiconductor chips. For one semiconductor chip, the generation circuit provided in one semiconductor chip inputs the identification signal generated by the generation circuit provided in the other semiconductor chip, and based on the input identification signal The identification signal is generated.

  In this semiconductor device, a generation circuit is provided in each of a plurality of semiconductor chips. A generation circuit in a semiconductor chip receives an identification signal of another semiconductor chip, and generates an identification signal of the semiconductor chip provided with the generation circuit based on the identification signal. Therefore, by connecting the generation circuits, identification signals are generated one after another in each semiconductor chip. For this reason, according to this semiconductor device, an identification signal can be easily given to each semiconductor chip.

  According to the present invention, a semiconductor device in which an identification signal can be easily given to each semiconductor chip is realized.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

  FIG. 1 is a perspective view schematically showing one embodiment of a semiconductor device according to the present invention. The semiconductor device 1 includes a plurality (four in this example) of semiconductor chips 11 to 14. The semiconductor chips 11 to 14 are memory chips, for example, and have the same circuit configuration. These semiconductor chips 11 to 14 are stacked on each other via an interposer 90. In the interposer 90, wirings for electrically connecting the semiconductor chips 11 to 14 are formed. As a material of the interposer 90, for example, resin or silicon can be used.

  As shown in FIG. 2, a generation circuit 20 and a selection circuit 30 are formed in each of the semiconductor chips 11 to 14. The generation circuit 20 is a circuit that generates an identification signal unique to each of the semiconductor chips 11 to 14. The generation circuit 20 inputs an input signal (Y0, Y1) of n (n is an integer of 2 or more, in this example, n = 2) bit, and generates an output signal (P0, P1) of n bit. 20 is output as an identification signal of the semiconductor chip provided.

  As shown in FIG. 3, the generation circuit 20 provided in each of the semiconductor chips 11 to 14 is connected in series. In the drawing, the generation circuits 20 provided in the semiconductor chips 11 to 14 are respectively represented as generation circuits 21 to 24 for convenience. These generation circuits 21 to 24 have the same circuit configuration. Further, the identification signals of the semiconductor chips 11 to 14 are represented as (p10, p11), (p20, p21), (p30, p31) and (p40, p41), respectively.

  As can be seen from the figure, for two of the semiconductor chips 11 to 14, the generation circuit 20 provided in one semiconductor chip is generated by the generation circuit 20 provided in the other semiconductor chip. The identification signal of the one semiconductor chip is generated based on the input identification signal. For example, regarding the semiconductor chip 11 and the semiconductor chip 12, the generation circuit 22 provided in the semiconductor chip 12 inputs the identification signals (p10, p11) generated by the generation circuit 21 provided in the semiconductor chip 11. Based on the identification signals (p10, p11), the identification signals (p20, p21) of the semiconductor chip 12 are generated. Note that a predetermined signal (in this example, (1, 1)) is given to the generation circuit 21 as an input signal. This signal is given from, for example, a power supply terminal or a ground terminal.

  The generation circuit 20 includes n half adders 201 and 202 (denoted as “HA” in the drawing). Each bit value of the input signal is input to the X terminal (first input terminal) of each half adder 201, 202, and the output signal is output from the S terminal (sum output terminal) of each half adder 201, 202. Each bit value is output. For the two half adders 201 and 202, the output from the C terminal (carry output terminal) of one half adder 201 is the Y terminal (second input terminal) of the other half adder 202. ). A predetermined signal (“1” in this example) is given to the Y terminal of the half adder 201. This signal is given from, for example, a power supply terminal or a ground terminal.

FIG. 4 is a truth table showing the relationship between the input signals (Y0, Y1) and the output signals (P0, P1) in the generation circuit 20 of FIG. Y0 and Y1 are bit values input to the X terminals of the half adder 201 and the half adder 202, respectively. P0 and P1 are bit values output from the S terminals of the half adder 201 and the half adder 202, respectively. In this truth table, all of the following conditions (a) to (c) are satisfied.
(A) There is a one-to-one correspondence between the input signal and the output signal. (B) The input signal and the output signal are different. (C) The input signal and the output signal are irreversible.

  Note that the input signal and the output signal are irreversible means that all input signals (in this example, (0, 0), (0, 1), (1, 0), and (1, 1) 4). Type) means that the input signal and the output signal are not exchanged in the truth table. For example, when the input signal is (0, 0), the output signal is (1, 0). At this time, there is no relationship in which the input signal and the output signal are interchanged, that is, the relationship (1, 0) → (0, 0). The same applies to the other input signals (0, 1), (1, 0) and (1, 1). Therefore, in the truth table of FIG. 4, it can be said that the input signal and the output signal are irreversible.

  FIG. 5 is a circuit configuration diagram showing an example of the half adders 201 and 202. The half adder shown in the figure is composed of four NAND circuits and one inverter circuit.

  Returning to FIG. 2, the selection circuit 30 inputs the identification signal (P0, P1) generated by the generation circuit 20 and the address signal (A0, A1) for designating one of the semiconductor chips 11-14. . The address signal is given from, for example, a logic circuit (not shown) provided in the semiconductor device 1 separately from the semiconductor chips 11 to 14. The selection circuit 30 outputs a selection signal S having a first value when the address signal designates a semiconductor chip provided with the selection circuit 30, and the address signal is not provided with the selection circuit. When specifying a semiconductor chip, a selection signal S having a second value is output. Here, the first and second values are, for example, “1” and “0”, respectively. However, the first value may be “0” and the second value may be “1”.

  FIG. 6 is a circuit configuration diagram illustrating an example of the selection circuit 30. In the figure, the selection circuits 30 provided in the semiconductor chips 11 to 14 are respectively represented as selection circuits 31 to 34 for convenience. These selection circuits 31 to 34 have the same circuit configuration. In addition, identification signals ID1 to ID4 (that is, identification signals generated by the generation circuits 21 to 24) of the semiconductor chips 11 to 14 are conceptually illustrated.

  Each selection circuit 30 in the figure includes n EOR circuits. Each bit value of the identification signal is input to the first input terminal of each EOR circuit, and each bit value of the address signal is input to the second input terminal. The output from each EOR circuit is input to the AND circuit. The AND circuit outputs the selection signal S. Note that a NAND circuit may be used instead of the AND circuit. In the figure, the selection signals S output from the selection circuits 31 to 34 are respectively represented as selection signals S1 to S4 for convenience. Among these selection signals S1 to S4, one is configured to be the first value, and the remaining three are configured to be the second value.

  When the generation circuit 20 and the selection circuit 30 described in FIGS. 3 and 6 are used, a circuit configuration diagram corresponding to the block diagram of FIG. 2 is as shown in FIG.

  Returning to FIG. 1, electrode pads 71 to 74 are provided on the respective semiconductor chips 11 to 14. The electrode pad 71 is a pad for inputting an input signal to the generation circuit 20. The electrode pad 72 is a pad that outputs an output signal from the generation circuit 20. The electrode pad 73 is a pad for inputting an address signal to the selection circuit 30. The electrode pad 74 is a pad that outputs a selection signal from the selection circuit 30. Among these, the electrode pads 71 to 73 are provided for n bits, that is, n.

  Each interposer 90 is provided with electrode pads 81-83. There are also n electrode pads 81 to 83, which are connected to the electrode pads 71 to 73, respectively. For two adjacent interposers 90, the electrode pad 81 provided on one interposer 90 is connected to the electrode pad 82 provided on the other interposer 90. Further, the electrode pads 83 are connected to each other between two adjacent interposers 90.

  Then, the effect of this embodiment is demonstrated. In the semiconductor device 1, the generation circuit 20 is provided in each of the plurality of semiconductor chips 11 to 14. The generation circuit 20 in a certain semiconductor chip receives an identification signal of another semiconductor chip, and generates an identification signal of the semiconductor chip provided with the generation circuit 20 based on the identification signal. Therefore, by connecting the generating circuits 20 in series, identification signals are generated one after another in each of the semiconductor chips 11-14. For this reason, according to this semiconductor device 1, an identification signal can be easily given to each semiconductor chip 11-14.

  For example, in FIG. 3, when an input signal (1, 1) is given to the generation circuit 21, the generation circuits 21 to 24 have (0, 0), (1, 0), (0, 1), and ( 1, 1) is output. These output signals become identification signals for the semiconductor chips 11 to 14, respectively. Note that the initial value is not necessarily (1, 1), and may be any of (0, 0), (0, 1), and (1, 0).

  When the generation circuit 20 is configured as shown in FIG. 3, the generation circuit 20 can be realized with a simple circuit configuration.

In the truth table for the generation circuit 20, all of the above conditions (a) to (c) are satisfied. As a result, output signals from the 2 ⁿ generation circuits 20 connected in series do not overlap. Therefore, it is possible to generate an identification signal of 2 ⁿ as a theoretically maximum at n bits.

  Each semiconductor chip 11 to 14 is provided with a selection circuit 30. The selection circuit 30 outputs a selection signal having a first value when a semiconductor chip provided on the selection circuit 30 is specified by an address signal, and has a second value when another semiconductor chip is specified. Outputs a selection signal. Thereby, a desired semiconductor chip can be easily selected from the semiconductor chips 11 to 14.

  For example, in FIG. 6, when the address signal (A0, A1) is (1, 1), (0, 1), (1, 0) and (0, 0), the combination of the selection signals (S1, S2, S3, S4) become (1, 0, 0, 0), (0, 1, 0, 0), (0, 0, 1, 0) and (0, 0, 0, 1), respectively. That is, the semiconductor chip 11, the semiconductor chip 12, the semiconductor chip 13, and the semiconductor chip 14 are selected, respectively.

  When the selection circuit 30 is configured as shown in FIG. 6, the selection circuit 30 can be realized with a simple circuit configuration.

  The generation circuits 21 to 24 provided in different semiconductor chips 11 to 14 have the same circuit configuration. Thereby, the manufacturing of the semiconductor chips 11 to 14 can be simplified as compared with the case where the circuit configurations of the generation circuits 21 to 24 are different.

  Furthermore, in this embodiment, since the semiconductor chips 11 to 14 as a whole have the same circuit configuration, the manufacture of these semiconductor chips 11 to 14 is further simplified. On the other hand, when a plurality of semiconductor chips having the same circuit configuration are provided in one semiconductor device, it is necessary to give a unique identification signal to each semiconductor chip in order to distinguish the semiconductor chips. Therefore, in such a case, the semiconductor device 1 that can easily give an identification signal is particularly useful.

  Incidentally, Patent Document 2 also discloses a semiconductor device including a plurality of semiconductor chips stacked on each other. As shown in FIG. 15, in the semiconductor device 100 described in the same document, a plurality of semiconductor chips 101 to 104 having the same structure are stacked on each other via an interposer 190. The wiring in the interposer 190 is formed so that the position is shifted between the front and back sides. In addition, external terminals 111 to 114 are formed on the interposer 190 located at the lowest layer. These external terminals 111 to 114 are electrically connected to electrode pads 131 to 134, respectively. The electrode pads 131 to 134 are provided in the semiconductor chips 101 to 104, respectively, and are pads that output selection signals S1 to S4 to be output from the semiconductor chips 101 to 104, respectively.

  In the semiconductor device 100, selection signals S1 to S4 of the semiconductor chips 101 to 104 are generated by a decode circuit 122 provided in the logic circuit 121. These selection signals S1 to S4 are respectively applied to the external terminals 111 to 114 of the interposer 190 located in the lowest layer. Thus, desired selection signals S1 to S4 are output from the electrode pads 131 to 134.

  However, in the case of the semiconductor device 100, the area of the wiring area increases due to the structure. This is because the number of wiring areas is increased as the number of stages increases (the number of parallel connections increases). In addition, since each semiconductor chip 101-104 cannot have an identification signal, it is necessary to provide a decode circuit 122 that generates selection signals S1-S4. Furthermore, since the lengths of the selection signal lines are greatly different among the selection signals S1 to S4, a large difference occurs in the wiring capacitance value and the resistance value, thereby increasing the skew (shift in signal input timing). This leads to deterioration of the operating margin of the chip. Note that the selection signal line refers to a signal line extending from each of the external terminals 111 to 114 to the electrode pads 131 to 134.

On the other hand, in the semiconductor device 1, when the number of semiconductor chips is X, the required number N of signal lines is given by N = 2 · log ₂ X. For example, when X = 8, N = 6 (three for the address signal and three for the identification signal), which is two less than the semiconductor device 100 of FIG. Therefore, the area of the wiring area can be kept small. Further, since each of the semiconductor chips 11 to 14 itself includes the generation circuit 20 and the selection circuit 30, unlike the semiconductor device 100, it is not necessary to apply the selection signals S1 to S4 from the outside. Therefore, since it is not necessary to provide a decode circuit outside the semiconductor chips 11 to 14, the configuration of the entire semiconductor device can be simplified. Further, the skew between the selection signals S1 to S4 can be suppressed to be small.

  The semiconductor device according to the present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above-described embodiment, an example in which the generation circuit 20 is configured using a half adder has been described. However, as illustrated in FIG. 8, the generation circuit 20 may be configured using a half subtractor. The generation circuit 20 in the figure includes n half subtractors 206 and 207 (denoted as “HS” in the figure). Each bit value of the input signal is input to the X terminal (first input terminal) of each half subtractor 206, 207, and each bit of the output signal from the D terminal (difference output terminal) of each half subtractor 206, 207. The value is output. For the two half subtractors 206 and 207, the output from the B terminal (borrowed output terminal) of one half subtractor 206 is the Y terminal (second input terminal) of the other half subtractor 207. It is comprised so that it may be input. A predetermined signal (“1” in this example) is given to the Y terminal of the half subtractor 206.

  FIG. 9 is a truth table showing the relationship between the input signals (Y0, Y1) and the output signals (P0, P1) in the generation circuit 20 of FIG. Also in this truth table, all of the above conditions (a) to (c) are satisfied. FIG. 10 is a circuit configuration diagram showing an example of each of the half subtracters 206 and 207. The half subtracter shown in the figure is composed of three NAND circuits and three inverter circuits.

  Moreover, although the example in the case of n = 2 was shown in the said embodiment, as long as n is an integer greater than or equal to 2, any number may be sufficient. For example, if n = 3, the generation circuit 20 can be configured as shown in FIG. In the figure, eight generation circuits 20 are connected in series. Each generation circuit 20 includes three half adders 201, 202, and 203. The connection relationship between these half adders 201, 202, and 203 is the same as in FIG.

  FIG. 12 is a truth table showing the relationship between the input signals (Y0, Y1, Y2) and the output signals (P0, P1, P2) in the generation circuit 20 of FIG. Y2 is a bit value input to the X terminal of the half adder 203, and P2 is a bit value output from the S terminal of the half adder 203. Also in this truth table, all of the above conditions (a) to (c) are satisfied.

  Moreover, although the example which laminates | stacks several semiconductor chips via an interposer was shown in the said embodiment, as shown in FIG. 13, you may laminate | stack a semiconductor chip directly. In the figure, semiconductor chips 16 to 19 are stacked on each other without using an interposer. Adjacent semiconductor chips can be electrically connected by, for example, solder bumps. Although not shown, a generation circuit 20 and a selection circuit 30 are formed in each of the semiconductor chips 16-19.

  As shown in FIG. 14, each of the semiconductor chips 16 to 19 includes a semiconductor substrate 41 on which a predetermined circuit is formed, and a rewiring layer 42 provided on the circuit formation surface 41a. A through electrode 43 and a wiring 44 are formed in the semiconductor substrate 41. A rewiring 45 is formed in the rewiring layer 42. The wirings 44 of adjacent semiconductor chips are electrically connected to each other through the through electrode 43 and the rewiring 45.

  In the above embodiment, an example in which a plurality of semiconductor chips are stacked on each other has been described. However, it is not essential that a plurality of semiconductor chips be stacked. For example, a plurality of semiconductor chips may be arranged on the same plane.

  Moreover, although the example in which the input signal supplied to the generation circuit 21 is a fixed signal has been described in the above embodiment, the input signal may be a variable signal. In that case, by appropriately changing the input signal, a desired semiconductor chip can be selected even if the address signal is fixed.

  The semiconductor chip may be packaged. That is, in this specification, a so-called semiconductor package is also included in the concept of a semiconductor chip.

1 is a perspective view schematically showing an embodiment of a semiconductor device according to the present invention. It is a block diagram showing a generation circuit and a selection circuit. It is a block diagram which shows an example of a production | generation circuit. 4 is a truth table for the generation circuit of FIG. 3. It is a circuit block diagram which shows an example of a half adder. It is a circuit block diagram which shows an example of a selection circuit. It is a circuit block diagram which shows an example of a production | generation circuit and a selection circuit. It is a block diagram which shows the modification of a production | generation circuit. 9 is a truth table for the generation circuit of FIG. It is a circuit block diagram which shows an example of a half subtractor. It is a block diagram which shows the other modification of a production | generation circuit. 12 is a truth table for the generation circuit of FIG. It is a perspective view which shows one modification of a semiconductor chip. It is a figure for demonstrating the structure of the semiconductor chip of FIG. 10 is a diagram for explaining a semiconductor device described in Patent Document 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Semiconductor chip 12 Semiconductor chip 13 Semiconductor chip 14 Semiconductor chip 20 Generation circuit 21 Generation circuit 22 Generation circuit 23 Generation circuit 24 Generation circuit 30 Selection circuit 31 Selection circuit 32 Selection circuit 33 Selection circuit 34 Selection circuit 41 Semiconductor substrate 41a Circuit Formation surface 42 Rewiring layer 43 Through electrode 44 Wiring 45 Rewiring 71 Electrode pad 72 Electrode pad 73 Electrode pad 74 Electrode pad 81 Electrode pad 82 Electrode pad 83 Electrode pad 90 Interposer 201 Half adder 202 Half adder 203 Half adder 206 Half subtractor 207 Half subtractor

Claims (10)

A plurality of semiconductor chips;
A generation circuit that is provided in each semiconductor chip and generates an identification signal unique to each semiconductor chip;
For two semiconductor chips of the plurality of semiconductor chips, the generation circuit provided in one semiconductor chip inputs the identification signal generated by the generation circuit provided in the other semiconductor chip. The semiconductor device is configured to generate the identification signal based on the input identification signal. The semiconductor device according to claim 1,
The generation circuit provided in the plurality of semiconductor chips is a semiconductor device having the same circuit configuration. The semiconductor device according to claim 1 or 2,
The plurality of semiconductor chips are semiconductor devices having the same circuit configuration. The semiconductor device according to claim 1,
The generation circuit is configured to input an input signal of n (n is an integer of 2 or more) bits and output the output signal of n bits as the identification signal,
In the truth table representing the relationship between the input signal and the output signal, the conditions (a) to (c):
(A) The input signal and the output signal have a one-to-one correspondence.
(B) The input signal and the output signal are different.
(C) The input signal and the output signal are irreversible.
A semiconductor device that satisfies all of the above. The semiconductor device according to claim 4,
The generation circuit includes the n half adders,
Each bit value of the n-bit input signal is input to the first input terminal of each half adder,
Each bit value of the output signal of n bits is output from the sum output terminal of each half adder,
The two half adders of the n half adders are configured such that the output from the carry output terminal of one half adder is input to the second input terminal of the other half adder. Semiconductor device. The semiconductor device according to claim 4,
The generation circuit includes the n half subtractors,
Each bit value of the n-bit input signal is input to a first input terminal of each half subtractor,
Each bit value of the output signal of n bits is output from the difference output terminal of each half subtractor,
Two of the n half subtractors are configured such that an output from a borrow output terminal of one half subtractor is input to a second input terminal of the other half subtractor. Semiconductor device. The semiconductor device according to claim 1,
A selection circuit provided in each of the semiconductor chips,
The selection circuit receives the identification signal generated by the generation circuit and an address signal designating any one of the plurality of semiconductor chips, and the semiconductor chip in which the selection circuit is provided A selection signal having a first value is output when the address signal is to be specified, and a selection signal having a second value is selected when the address signal is to specify the semiconductor chip not provided with the selection circuit. A semiconductor device configured to output a signal. The semiconductor device according to claim 7,
The selection circuit includes a plurality of EOR circuits,
Each bit value of the identification signal is input to the first input terminal of each EOR circuit,
A semiconductor device configured such that each bit value of the address signal is input to a second input terminal of each EOR circuit. The semiconductor device according to claim 8,
The semiconductor device includes an AND circuit or a NAND circuit that receives an output from each EOR circuit and outputs the selection signal. The semiconductor device according to claim 1,
The semiconductor device in which the plurality of semiconductor chips are stacked on each other.

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