JP2007213179A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve parallel operation efficiency of a plurality of nonvolatile memory devices in a nonvolatile semiconductor storage device. <P>SOLUTION: During a period T7-T8 of data transfer T6-T9 between a memory controller Memo_Cnt and one nonvolatile memory device Memo_Dv0 via an internal common bus Int_Bus, data transfer is interrupted. In the interruption period T7-T8, an internal read action command Int_Rd_CMD is transferred from the Memo_Cnt to another nonvolatile memory device Memo_DvN via the Int_Bus. In parallel to an internal read action Int_Rd_Ope from a nonvolatile memory array Memo_Ary0 to an internal buffer memory Buffer0 in the Memo_DvN, data transfer Data_Tr_Pr_Data between the Memo_Cnt and the Memo_Dv0 can be carried out. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a technique useful for high-speed access to a nonvolatile memory.

  A non-volatile memory such as a flash memory employs wear leveling because the number of times of writing (write cycle) is a finite number of times (generally about 100,000 times). By this wear leveling, the fatigue level due to the writing of the sectors of the nonvolatile memory in the space in the file system and the fatigue level due to the erasing of the erase block are made uniform, and the life expectancy is shortened by local fatigue of the nonvolatile semiconductor memory device. Can be avoided. In order to implement this wear leveling, different physical addresses are generated by address conversion in the writing process using the same logical address from the host to the non-volatile memory, and the actual writing to the non-volatile memory is different. It is executed using the address. Not only is wear leveling realized by address mapping from the same logical address to a different physical address, but it is also possible to leave old data with an old physical address even when the power is cut off during write processing. For example, in a flash memory card that is inserted into a slot of the host device in a removable manner, an operation that the flash memory card is pulled out from the slot of the host device may be performed by the end user during a relatively slow write time. . This operation shuts off the power before data writing to the non-volatile memory at the same physical address is completed, so not only the latest data at the same physical address is lost, but also old data at the same physical address. There is also a danger of disappearing. In order to avoid this, even if the latest data of the same physical address is lost by using different physical addresses in the writing process using the same logical address from the host to the nonvolatile memory, the old data of the old physical address is lost. Can be securely stored. Address mapping from the same logical address to a different physical address is now an important technology in terms of measures to shut down the power supply during write processing and uniform fatigue of the nonvolatile memory in the file system space. ing. When new data is stored at the new physical address, the old data at the old physical address becomes unnecessary, and the old data becomes garbage in the file system. In order to secure the effective storage capacity of the file system, a process of making the memory area of the old physical address reusable for the next writing is performed by erasing old data called garbage collection.

  Further, in order to solve the problem that the nonvolatile memory such as a flash memory has a low writing speed, an interleaved writing technique for accessing a plurality of flash devices at a time has been proposed. In this interleave writing technique, in response to a write instruction from the host, the first write data is transferred from the memory controller to the internal buffer memory of one nonvolatile memory device via the internal common bus. Accordingly, an internal write operation from the internal buffer memory of one nonvolatile memory device to the internal nonvolatile memory array is started, and another nonvolatile memory is sent from the memory controller via the internal common bus using this internal write period. Next write data is transferred to the internal buffer memory of the memory device. In this way, the internal write operation of one non-volatile memory device and the data transfer of the write data to another non-volatile memory device via the internal common bus are executed in parallel, and data from the host In writing, the writing speed can be improved.

  Non-Patent Document 1 below introduces address mapping from the same logical address to a different physical address, garbage collection, and interleave writing technology. Further, the following Patent Literature 1, Patent Literature 2, and Patent Literature 3 disclose interleave writing techniques for accessing a plurality of flash devices at a time.

  Further, the following Patent Document 4 discloses an MS-DOS operating system including a boot record, a file allocation table (FAT), and a root directory in a system area when emulating a magnetic disk using a nonvolatile semiconductor memory having a large erase block. It is disclosed to build a system on a nonvolatile semiconductor memory. MS-DOS is an abbreviation for Microsoft Disk Operating System. For this purpose, a cluster mapping table for mapping the logical cluster of the magnetic disk to the physical sector of the file structure of the nonvolatile semiconductor memory is constructed. A logical cluster is the smallest storage unit that can be logically addressed by a magnetic disk. In the case of a 3.5 inch disk, the logical cluster corresponds to one physical sector of 512 bytes. In addition, the file allocation table (FAT) includes a chain-type record indicating how a plurality of clusters constituting one file are linked, and the root directory includes a file name, It includes the start cluster number of a plurality of clusters forming one file, the file size, and the like. A cluster mapping table that maps a logical cluster to a physical sector of a file structure links an external logical address and a physical sector of a file structure. In addition, the US patent corresponding to the following patent document 1, patent document 2, patent document 3, and patent document 4 is the US patent 6,145,050 specification, the US patent 5,519,847 specification, respectively. US Pat. Nos. 5,592,415 and 5,630,093.

JP-A-6-4399 JP-A-7-141247 JP-A-8-69698 JP-A-5-241741 Amir Friedman, “Disk Emulation Using Flash Memory”, 1993 Nonvolatile Memory Technology Review, 22-24 June 1993, PP. 61-65

  Prior to the present invention, the present inventors studied a flash memory card that incorporates a memory controller that supports interleave writing technology and a plurality of flash devices.

  The flash memory card includes a memory controller, a plurality of nonvolatile memory devices, and an internal shared bus connected to the memory controller and the plurality of nonvolatile memory devices. A memory controller embedded in a flash memory card and supporting interleaved writing technology includes a write command, a write physical address, and write data to one nonvolatile memory device of a plurality of nonvolatile memory devices via an internal shared bus. Perform data transfer. However, once this data transfer is started, the memory controller occupies the internal shared bus of the flash memory card until the transfer of the write data unit called a page is completed via the internal shared bus.

  On the other hand, in order to implement measures against power interruption during wear leveling or write processing, address mapping from the same logical address to different physical addresses is performed during write processing using the same logical address from the host to the nonvolatile memory. It is necessary to do. For this purpose, not only the update data from the host is written to the new physical address of one non-volatile memory device, but also the non-update data not updated by the host is transferred from the old physical address of the other non-volatile memory device to the new physical address. It is necessary to copy to. This copy requires reading the non-updated data from the old physical address of the other non-volatile memory device and writing the read non-updated data to the new physical address of the other non-volatile memory device. Become. However, since interleaved writing technology is adopted to improve the data writing speed from the host, the internal shared bus is occupied for transfer of write data units called pages to one non-volatile memory device. The controller cannot use the internal shared bus for other uses. Therefore, during this period, the memory controller may issue a non-update data read command for reading non-update data from the old physical address of the other nonvolatile memory device to the other nonvolatile memory device. Can not. As a result, after the transfer of update data to one non-volatile memory device is completed, a read command for non-update data must be issued to the other non-volatile memory device. As a result, the problem that the idle state continues in one other nonvolatile memory device until the transfer of update data to one nonvolatile memory device is completed, and the parallel operation rate of the plurality of nonvolatile memory devices decreases. This has been clarified by studies by the inventors. This problem can be solved by connecting a memory controller and a plurality of nonvolatile memory devices with a plurality of internal exclusive buses in the flash memory card. However, since it causes an increase in the number of external terminals of the memory controller and an increase in the board area of the flash memory card, a plurality of internal occupation buses is not a practical solution.

Therefore, the present invention has been made on the basis of the results of the study by the present inventors as described above. Accordingly, an object of the present invention is to improve the parallel operation rate of a plurality of nonvolatile memory devices in a nonvolatile semiconductor memory device in which a memory controller and a plurality of nonvolatile memory devices are connected by an internal shared bus. There is to do. In addition, a more specific object of the present invention is to provide one nonvolatile memory when performing address mapping from the same logical address to a different physical address in the writing process using the same logical address from the host to the nonvolatile memory. The object is to speed up the process of writing update data to a new physical address of a memory device and the process of reading non-update data from an old physical address of another non-volatile memory device.
Another object of the present invention is to avoid an increase in the number of external terminals of the memory controller and an increase in the substrate area of the nonvolatile semiconductor memory device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, the nonvolatile semiconductor memory device (Memo_Crd) according to one embodiment of the first aspect of the present invention includes a memory controller (Memo_Cnt) and a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). The nonvolatile semiconductor memory device (Memo_Crd) includes an internal shared bus (Int_Bus) connected between a memory controller (Memo_Cnt) and a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). Each of the plurality of nonvolatile memory devices (Memo_Dv0 ... Memo_DvN) stores internal write data to be written to the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN) and the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN), respectively. And internal buffer memory (Buffer 0... Buffer N) for storing internal read data read from the memory array (Memo_Ary 0... Memo_AryN) (see FIGS. 1 and 2).

  In response to the instruction from the host, the memory controller (Memo_Cnt) selects one nonvolatile memory device (Memo_Dv0) from the plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). The memory controller (Memo_Cnt) transfers the access data of the command and address corresponding to the instruction from the host to the selected one non-volatile memory device (Memo_Dv0) via the internal shared bus (Int_Bus) (FIG. 6). See T6-T7). Transfer of user data based on an instruction from a host via an internal shared bus (Int_Bus) between one nonvolatile memory device (Memo_Dv0) and a memory controller (Memo_Cnt) (Data_Tr_Pr_Data; see T8 to T9 in FIG. 6) Before completion of the above, the memory controller (Memo_Cnt) interrupts the selection of one nonvolatile memory device (Memo_Dv0), while selecting another nonvolatile memory device (Memo_DvN) (see T7 to T8 in FIG. 6). The memory controller (Memo_Cnt) is connected between the internal nonvolatile memory array (Memo_AryN) and the internal buffer memory (BufferN) to the other selected nonvolatile memory device (Memo_DvN) via the internal shared bus (Int_Bus). Access data (Data_Tr_Rd_CMD & Add) between the command and address for data transfer is transferred (see T7 to T8 in FIG. 6). In response to the access data (Data_Tr_Rd_CMD & Add) of the command and address for the internal data transfer, the selected other nonvolatile memory device (Memo_DvN) receives the internal nonvolatile memory array (Memo_AryN) and the internal buffer memory (BufferN). The internal data transfer (Int_Rd_Ope) is performed with respect to (see T8 to T9 in FIG. 6). During this internal data transfer (Int_Rd_Ope), the internal shared bus (Int_Bus) is not occupied by another selected nonvolatile memory device (Memo_DvN). Therefore, during this internal data transfer, the memory controller (Memo_Cnt) resumes the selection of one nonvolatile memory device (Memo_Dv0). By resuming this selection, transfer of user data (Data_Tr_Pr_Data) based on an instruction from the host via the internal shared bus (Int_Bus) between one nonvolatile memory device (Memo_Dv0) and the memory controller (Memo_Cnt) is executed. (See T8 to T9 in FIG. 6).

  According to the means of the first aspect of the first aspect of the present invention, internal data transfer (Int_Rd_Ope) in another nonvolatile memory device (Memo_DvN), one nonvolatile memory device (Memo_Dv0), and a memory controller (Memo_Cnt) And data transfer (Data_Tr_Pr_Data) based on an instruction from the host via the internal shared bus (Int_Bus) between the two (see T8 to T9 in FIG. 6). As a result, in the nonvolatile semiconductor memory device in which the memory controller and the plurality of nonvolatile memory devices are connected by the internal shared bus, the parallel operation rate of the plurality of nonvolatile memory devices can be improved (FIG. 1, (See FIG. 6).

  Further, in one specific form of the first aspect of the present invention, a plurality of selection signal lines (/ CE0, //) connected between a memory controller (Memo_Cnt) and a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). CEN). Through one selection signal line (/ CE0) of the plurality of selection signal lines (/ CE0, / CEN), the memory controller (Memo_Cnt) is transferred from the plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) to one nonvolatile memory device ( The memory controller (Memo_Cnt) is selected from the plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) via the other selection signal line (/ CEN) of the plurality of selection signal lines. A memory device (Memo_DvN) is selected (see FIG. 1).

  In one specific form of the first aspect of the present invention, a plurality of ready / busy signal lines (R / R) connected between a memory controller (Memo_Cnt) and a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). B0 ... R / BN). From the ready state and busy state of one ready / busy signal line (R / B0) of the plurality of ready / busy signal lines (R / B0... R / BN), the memory controller (Memo_Cnt) has one selection signal line (CE0). It is determined whether or not one nonvolatile memory device (Memo_Dv0) can be selected via the other, and another ready / busy signal of the plurality of ready / busy signal lines (R / B0... R / BN) is determined. Whether the memory controller (Memo_Cnt) can select another nonvolatile memory device (Memo_DvN) via another selection signal line (CEN) from the ready state and busy state of the line (R / BN) Is determined (see FIG. 1).

  In one specific form of the first aspect of the present invention, a plurality of ready / busy signal lines (R / B0... R / BN) from a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) are shared by one. Commonly connected to a ready / busy signal line (Wired_OR_R / B). The memory controller (Memo_Cnt) periodically checks the contents of the status registers of a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN), thereby allowing a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) via the internal common bus (Int_Bus). ) Which nonvolatile memory device is selectable (see FIG. 7).

  Further, in one specific form of the first aspect of the present invention, the memory controller transmits two consecutive new write user data (Data_PD00... Data_PD03, Data_PD04... Data_PD07) according to a write instruction from the host to a plurality of nonvolatile memory devices. It supports an interleave writing technique for writing to one non-volatile memory device (Memo_Dv0) selected from (Memo_Dv0... Memo_DvN) and another non-volatile memory device (Memo_DvN). In response to a write instruction from the host, two consecutive new write user data are transferred from the memory controller (Memo_Cnt) to the internal buffer memory (Buffer0) of one nonvolatile memory device (Memo_Dv0) via the internal common bus (Int_Bus). The first write user data (Data_PD00... Data_PD03) of (Data_PD00... Data_PD03, Data_PD04... Data_PD07) is transferred. In the internal write operation period of the first write user data (Data_PD00... Data_PD03) from the internal buffer memory (Buffer0) of the single nonvolatile memory device (Memo_Dv0) to the internal nonvolatile memory array (Memo_Ary0), Among the two new write user data (Data_PD00 ... Data_PD04, Data_PD04, Data_PD07) that are continuous from the memory controller (Memo_Cnt) to the internal buffer memory (BufferN) of another non-volatile memory device (Memo_DvN) via Int_Bus) Subsequent write user data (Data_PD04... Data_PD07) is transferred. As a result, internal write operation (Int_Wr_Ope) in one non-volatile memory device (Memo_Dv0) and subsequent write user data to another non-volatile memory device (Memo_DvN) via the internal common bus (Int_Bus) Data transfer (Data_Tr_Pr_Data) of (Data_PD04... Data_PD07) is executed in parallel (see FIGS. 2 and 3).

  In one specific form of the first aspect of the present invention, the memory controller (Memo_Cnt) generates different physical addresses (EB0, EBL) by address conversion during a plurality of write processes using the same logical address from the host. In addition, actual writing in the nonvolatile semiconductor memory device can be performed using different physical addresses (EB0, EBL) to enable at least one of wear leveling and storage of old data at the old physical address during writing processing. And When new data (Data_PD00 ′... Data_PD03 ′) of a new physical address (EBL) at the time of writing processing is saved, garbage collection for erasing old data (Data_PD00... Data_PD03) of an old physical address (EB0) is stored in the memory. The controller executes (see FIG. 1).

  In the nonvolatile semiconductor memory device (Memo_Crd) according to another specific form of the first aspect of the present invention, in response to an instruction from the host, the memory controller (Memo_Cnt) includes a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). ) To select one non-volatile memory device (Memo_Dv0). The memory controller (Memo_Cnt) starts transferring the write command (Pr_CMD) and the write physical address (Add_PDOO ′... Add_PD03 ′) to the selected one nonvolatile memory device (Memo_Dv0) (see T6 to T7 in FIG. 6). ). After starting the transfer of the write command (Pr_CMD) and the write physical address (Add_PDOO ′... Add_PD03 ′) to one nonvolatile memory device (Memo_Dv0), the internal buffer memory (Buffer0) of one nonvolatile memory device (Memo_Dv0) Prior to the completion of the transfer of data (Data_PD00 ′... Data_PD03 ′) (Data_Tr_Pr_Data; see T8 to T9 in FIG. 6) to the memory controller, the memory controller (Memo_Cnt) interrupts the selection of one nonvolatile memory device (Memo_Dv0). On the other hand, another non-volatile memory device (Memo_DvN) is selected. The memory controller (Memo_Cnt) starts transfer of the read command (Int_Rd_CMD) and the read physical address (Add_PDO4... Add_PD07) to the other selected nonvolatile memory device (Memo_DvN) via the internal shared bus (Int_Bus) ( (See T7 to T8 in FIG. 6). In the other selected nonvolatile memory device (Memo_DvN), the internal nonvolatile memory array (Memo_AryN) is transferred to the internal buffer memory (BufferN) in response to the read command (Int_Rd_CMD) and the read address (Add_PDO4... Add_PD07). An internal read operation is started (see T8 to T9 in FIG. 6). After the start of the internal read operation in the other nonvolatile memory device (Memo_DvN), the memory controller (Memo_Cnt) suspends the selection of the other nonvolatile memory device (Memo_DvN), while one nonvolatile memory device (Memo_Dv0) Resume selection. After restarting the selection of one nonvolatile memory device (Memo_Dv0), the memory controller (Memo_Cnt) writes to the internal buffer memory (Buffer0) of one nonvolatile memory device (Memo_Dv0) via the internal shared bus (Int_Bus). Transfer of data (Data_PD00 ′... Data_PD03 ′) is started (see T8 to T9 in FIG. 6). Transfer (Data_Tr_Pr_Data) of write data (Data_PD00 ′... Data_PD03 ′) from the memory controller (Memo_Cnt) to the internal buffer memory (Buffer0) of one nonvolatile memory device (Memo_Dv0) via the internal shared bus (Int_Bus); An internal read operation (Int_Rd_Ope) from the internal nonvolatile memory array (Memo_AryN) to the internal buffer memory (BufferN) in another nonvolatile memory device (Memo_DvN) is executed in parallel (FIGS. 1, 2, and 6). T8 to T9).

  According to the means of the one specific form of the first aspect of the present invention, the address mapping from the same logical address to a different physical address is performed in the writing process using the same logical address from the host to the nonvolatile memory. When performing, a data transfer process (Data_Tr_Pr_Data) for writing update data to a new physical address of one nonvolatile memory device, and non-update data from an old physical address of another nonvolatile memory device are internally read out The processing (Int_Rd_Ope) can be speeded up (see T8 to T9 in FIG. 6).

  Furthermore, a non-volatile semiconductor memory device (Memo_Crd) according to another embodiment of the first aspect of the present invention includes a memory controller (Memo_Cnt) and a plurality of non-volatile memory devices (Memo_Dv0... Memo_DvN). The nonvolatile semiconductor memory device (Memo_Crd) includes an internal shared bus (Int_Bus) connected between a memory controller (Memo_Cnt) and a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). Each of the plurality of nonvolatile memory devices (Memo_Dv0 ... Memo_DvN) stores internal write data to be written to the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN) and the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN), respectively. And internal buffer memory (Buffer 0... Buffer N) for storing internal read data read from the memory array (Memo_Ary 0... Memo_AryN) (see FIGS. 1 and 2).

  The logical address received together with the write instruction requested from the host does not match any of the past logical addresses corresponding to the physical addresses previously written in the plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). The memory controller (Memo_Cnt) responds. That is, the memory controller (Memo_Cnt) selects two consecutive new write user data (Data_PD00 ... Data_PD03, Data_PD04 ... Data_PD07) from a plurality of nonvolatile memory devices (Memo_Dv0 ... Memo_DvN) according to a write instruction from the host. The data is transferred to the nonvolatile memory device (Memo_Dv0) and the other selected nonvolatile memory device (Memo_DvN) in two time zones through the internal common bus (Int_Bus). Thereafter, the selected one nonvolatile memory device (Memo_Dv0) and the other selected nonvolatile memory device (Memo_DvN) from each internal buffer memory (Buffer0 ... BufferN) to each internal nonvolatile memory array (Memo_Ary0 ...). An internal write operation (Int_Wr_Ope) of each new write user data (Data_PD00... Data_PD03, Data_PD04... Data_PD07) to (Memo_AryN) is executed (see FIGS. 2 and 3).

  On the other hand, the logical address received together with the write instruction requested from the host matches one of the past logical addresses corresponding to the physical address written in the past in the plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). The memory controller (Memo_Cnt) responds. That is, the memory controller (Memo_Cnt) instructs the data written in the areas of the plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) having the old physical address (EB0) corresponding to the matched logical address to be requested from the host. Thus, the data (PD00... PD03) to be updated is distinguished from the non-updated data (PD04... PD07). Regarding the data to be updated (PD00... PD03), any one of a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) having a new physical address (EBL) corresponding to the matched logical address (Memo_Dv0... Memo_DvN). ), Update data (PD00 ′... PD03 ′) from the host is written to the internal nonvolatile memory array (Memo_Ary0... Memo_AryN) via the internal buffer memory (Buffer0... BufferN). Update data (PD00 '... PD03') from the host is non-updated data (PD04 ... PD07) in parallel with data transfer (Data_Tr_Pr_Data) to any nonvolatile memory device (Memo_Dv0 ... Memo_DvN) in time. Data written in the area of any one of the non-volatile memory devices (Memo_Dv0 ... Memo_DvN) of the plurality of non-volatile memory devices (Memo_Dv0 ... Memo_DvN) having the old physical address (EB0) corresponding to the matched logical address (PD04... PD07) is internally read into the internal buffer memory (Buffer0... BufferN). Thereafter, the non-updated data (PD04 ... PD07) internally read into the internal buffer memory (Buffer0 ... BufferN) is internally written to the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN) of this nonvolatile memory device (Memo_Dv0 ... Memo_DvN). (See FIGS. 4 and 6).

  Furthermore, a nonvolatile semiconductor memory device (Memo_Crd) according to another embodiment of the first aspect of the present invention includes a memory controller (Memo_Cnt), a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN), and an internal shared bus (Int_Bus). Including.

  Each of the plurality of nonvolatile memory devices (Memo_Dv0 ... Memo_DvN) stores internal write data to be written to the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN) and the internal nonvolatile memory array (Memo_Ary0 ... Memo_AryN), respectively. And an internal buffer memory (Buffer0 ... BufferN) for storing internal read data read from the memory array (Memo_Ary0 ... Memo_AryN).

  From the host (Host) that rewrites data (PD00 ... PD03) stored in the internal nonvolatile memory array (Memo_Ary0) of any one of the nonvolatile memory devices (Memo_Dv0 ... Memo_DvN). In response to the instruction, the memory controller (Memo_Cnt) transfers the command and address (Pr_CMD, Add_PD00 ′... Add_PD03 ′) for updating data to one nonvolatile memory device (Memo_Dv0) via the internal shared bus (Int_Bus). To do. Thereafter, the memory controller (Memo_Cnt) is connected to the other non-volatile memory device (Memo_DvN) of the other non-volatile memory device (Memo_DvN) with respect to the other non-volatile memory device (Memo_DvN). Commands and addresses (Int_Rd_CMD, Add_PD04) for reading data (PD04... PD07) stored in the memory array (Memo_AryN) and not to be updated into the internal buffer memory (BufferN) of another non-volatile memory device (Memo_DvN) ... (Add_PD07, Ini_Rd_CMD) are transferred.

  Thereafter, the memory controller (Memo_Cnt) transfers update data (PD00 ′... PD03 ′) for data update to the internal buffer memory (Buffer0) of one nonvolatile memory device (Memo_Dv0) via the internal shared bus (Int_Bus). In parallel with this, in the other nonvolatile memory device (Memo_DvN), an internal read operation (Int_Rd_Ope) for reading data (PD04... PD07) not subject to data update to the internal buffer memory (BufferN) is executed. (See T8 to T9 in FIGS. 1, 2, and 6).

  Further, in the nonvolatile semiconductor memory device (Memo_Crd) according to another specific form of the first aspect of the present invention, in one nonvolatile memory device (Memo_Dv0), the update data (Buffer0) transferred to the internal buffer memory (Buffer0) Internal write operation for writing PD00 '... PD03') to a new physical address (EBL) different from the physical address (EBO) storing pre-update data (PD00 ... PD03) already stored in the internal nonvolatile memory array (Memo_Ary0) (Int_Wr_Ope) is executed. In response to an internal write command (Int_Pr_CMD) and an address (Add_PD04 ... Add_PD07) transferred from the memory controller (MemO_Cnt) to another nonvolatile memory device (Memo_DvN) via the internal shared bus (Int_Bus) Another non-volatile memory device (Memo_DvN) reads data (PD04... PD07) that is not subject to data update to the internal buffer memory (BufferN), and data that is not subject to data update (Memo_AryN) (Memo_AryN). Data (PD04) from the internal buffer memory (Buffer N) to a new physical address (EBL) different from the old physical address (EB0) that stores PD04. Internal write operation (Int_Wr_Ope) is executed to say writing PD07).

  Further, in the non-volatile semiconductor memory device (Memo_Crd) according to another specific form of the first aspect of the present invention, the logic is accompanied by an instruction from the host (Host) to rewrite the stored data (PD00... PD03). The address is received by the memory controller (Memo_Cnt). This logical address is the physical address (EB0) that stores the data (PD00... PD03) stored before the data update in the internal nonvolatile memory array (Memo_Ary0) of one nonvolatile memory device (Memo_Dv0), and the other. A logical address from the host corresponding to a physical address (EB0) storing data (PD04... PD07) that is not a data update target in the internal nonvolatile memory array Memo_AryN) of one nonvolatile memory device (Memo_DvN) of Are the same.

  In response to the same logical address received with an instruction from the host to rewrite the data, the memory controller (Memo_Cnt) has a new physical address (EBL) of one non-volatile memory device (Memo_Dv0) and another non-volatile A new physical address (EBL) of the memory device (Memo_DvN) is generated by address conversion.

  Furthermore, in the nonvolatile semiconductor memory device (Memo_Crd) according to another specific form of the first aspect of the present invention, the old physical address of one nonvolatile memory device (Memo_Dv0) and one nonvolatile memory device (Memo_Dv0) These new physical addresses are arranged in different erase blocks (EB0, EBL) in the internal nonvolatile memory array (Memo_Ary0) of one nonvolatile memory device (Memo_Dv0). In addition, the old physical address of the other non-volatile memory device (Memo_DvN) and the new physical address of the other non-volatile memory device (Memo_DvN) are the internal non-volatile of the other non-volatile memory device (Memo_DvN). The memory arrays (Memo_AryN) are arranged in different erase blocks (EB0, EBL).

  Furthermore, the nonvolatile semiconductor memory device (Memo_Crd) according to one embodiment of the second aspect of the present invention includes a memory controller (Memo_Cnt) and a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN). The memory controller (Memo_Cnt) performs data transfer at a predetermined frequency to a plurality of nonvolatile memory devices (Memo_Dv0... Memo_DvN) via the internal shared bus (Int_Bus). The memory controller (Memo_Cnt) has at least two non-volatile memory devices (Memo_Dv0, Memo_DvN) selected from a plurality of non-volatile memory devices (Memo_Dv0 ... Memo_DvN) having a frequency lower than a predetermined frequency and different in phase. Access is alternately performed by two selection signals (/ CE0, / CEN) (see FIGS. 8 and 9).

  According to the means of the one aspect of the second aspect of the present invention, two nonvolatile memory devices (Memo_Dv0, Memo_DvN) are alternately accessed by at least two selection signals (/ CE0, / CEN) having different phases. Two nonvolatile memory devices (Memo_Dv0, Memo_DvN) operate in parallel at a low frequency. As a result, in the nonvolatile semiconductor memory device in which the memory controller and the plurality of nonvolatile memory devices are connected by the internal shared bus, the parallel operation rate of the plurality of nonvolatile memory devices can be improved.

  In the nonvolatile semiconductor memory device (Memo_Crd) according to one specific form of the second aspect of the present invention, the frequencies of the two selection signals (/ CE0, / CEN) are approximately half of the predetermined frequency. The phases of the two selection signals (/ CE0, / CEN) are substantially opposite phases.

  In the nonvolatile semiconductor memory device (Memo_Crd) according to another specific form of the second aspect of the present invention, L (L> 2) nonvolatiles selected from a plurality of nonvolatile memory devices (Memo_Dv0, Memo_DvN). The memory device is sequentially accessed by L selection signals (/ CE0... / CEL-1) having a frequency 1 / L lower than the predetermined frequency and having phases different by 2π / L.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, in a nonvolatile semiconductor memory device in which a memory controller and a plurality of nonvolatile memory devices are connected by an internal shared bus, the parallel operation rate of the plurality of nonvolatile memory devices can be improved. it can.

≪Flash memory card configuration≫
FIG. 1 is a diagram showing a configuration of a flash memory card Memo_Crd according to one embodiment of the first invention. The flash memory card Memo_Crd is removably inserted into the slot of the host device Host via the standard external bus Ext_Bus. The host device Host is an electronic device such as a personal computer, a personal digital assist (PDA), a digital still camera, a digital movie camera, or a mobile phone terminal. The flash memory card Memo_Crd includes a memory controller Memo_Cnt and a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. The nonvolatile semiconductor memory device Memo_Crd further includes an internal shared bus Int_Bus connected between the memory controller Memo_Cnt and the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. Each of the plurality of nonvolatile memory devices Memo_Dv0 ... Memo_DvN stores the write data to be written to the internal nonvolatile memory array Memo_Ary0 ... Memo_AryN and the internal nonvolatile memory array Memo_Ary0 ... Memo_AryN, while the internal nonvolatile memory array Including internal buffer memories Buffer0... BufferN for storing the read data that has been output.

  The memory controller Memo_Cnt includes a host interface Host_Int that is connected to a slot of the host device Host via a standard external bus Ext_Bus, and the host interface Host_Int performs various data write, data read, and data erase operations from the host device Host. Receive instructions. Based on the instruction received by the host interface Host_Int, the memory controller Memo_Cnt controls the data write, data read, and data erase operations of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. Write data from the host device Host is temporarily stored in the buffer memory BufferRAM of the memory controller Memo_Cnt before being written to the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. Read data read from the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN is temporarily stored in the buffer memory BufferRAM of the memory controller Memo_Cnt before being transferred to the host device Host. The write data temporarily stored in the buffer memory BufferRAM is read by the control unit Cnt_Unit via the buffer memory control unit Buffer_Cnt, and finally stored in a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. Read data read from the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN is transferred to the ECC control unit ECC via the control unit Cnt_Unit, and error detection and error correction of the read data are executed. The host interface Host_Int, the buffer memory BufferRAM, the buffer memory control unit Buffer_Cnt, the ECC control unit ECC, and the control unit Cnt_Unit inside the memory controller Memo_Cnt are controlled by the microcontroller unit MCU. The buffer memory BufferRAM is used to hold data when interleaved writing from the memory controller Memo_Cnt to a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN, and is used for error detection and error correction of read data by the ECC control unit ECC. Also used. Also, different physical addresses are generated by address conversion from the same logical address from the host in order to take measures against power interruption during wear leveling or writing processing. The history of the latest physical address from the old physical address corresponding to the same logical address is stored in the management data area of a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. When the system of the flash memory card Memo_Crd is activated by inserting the flash memory card Memo_Crd into the slot of the host device Host, an address conversion table indicating the relationship between the latest physical addresses corresponding to the same logical address is stored in the nonvolatile memory device Memo_Dv0. ... Copied from the management data area of Memo_DvN to the buffer memory BufferRAM. In order to access the latest data corresponding to the same logical address at high speed, the address conversion table copied to the buffer memory BufferRAM of the memory controller Memo_Cnt functions effectively. When the physical address is updated to the latest value during system operation after the system is started, the latest physical address value is stored in the management data area of the nonvolatile memory device Memo_Dv0... Memo_DvN and copied to the buffer memory BufferRAM. It is recommended to do. When a write instruction with a specific logical address LA1 is received from the host device Host by the host interface Host_Int of the memory controller Memo_Cnt, the control unit Cnt_Unit of the memory controller Memo_Cnt is, for example, a physical address corresponding to the specific logical address LA1 by random number generation. PA1 is generated. By using the generated physical address PA1, writing to a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN is tried. If the writing is successful, the address translation information between the specific logical address LA1 and physical address PA1 is stored in the management data area of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. If the writing fails, the write area of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN accessed by the physical address PA1 has written valid data or invalid data, but is in an unerased state. Yes, it is not writable. Therefore, a random number is generated again, and a physical address PA1 different from the previous value is generated. Writing to a plurality of non-volatile memory devices Memo_Dv0... Memo_DvN is tried using the regenerated different physical address PA1. Until the writing succeeds, the different physical address PA1 is regenerated, and finally the writing succeeds, and the address translation information between the specific logical address LA1 and the final physical address PA1 is a plurality of nonvolatile memory devices Memo_Dv0. ... stored in the management data area of Memo_DvN. When a write instruction by the same logical address LA2 (= LA1) as the specific logical address LA1 is received again by the host interface Host_Int of the memory controller Memo_Cnt, the control unit Cnt_Unit of the memory controller Memo_Cnt becomes a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN The value of the previous physical address PA1 corresponding to the specific logical address LA1 is read from the address conversion information stored in the management data area. A physical address PA2 having a value different from the value of the previous physical address PA1 is generated by address recalculation such as adding a newly generated random number to the value of the read physical address PA1. By using the generated physical address PA2, a write to a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN is tried. Until the writing succeeds, the physical address PA2 having a different value is regenerated. Finally, the writing succeeds, and a plurality of pieces of address conversion information between the same logical address LA2 (= LA1) and the final physical address PA2 are obtained. Are stored in the management data area of the non-volatile memory devices Memo_Dv0... Memo_DvN. With the above address calculation, writing with different physical addresses corresponding to the same logical address is possible, and at least one of wear leveling or storage of old data with an old physical address during writing processing is possible. Furthermore, when new data is stored in a new physical address corresponding to the same logical address by the address conversion from the logical address to the physical address as described above, the old data of the old physical address is deleted at an appropriate time. The memory controller Memo_Cnt is configured such that the collection processing is performed by a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN.

  As shown in FIG. 1, in the flash memory card Memo_Crd, an internal shared bus Int_Bus, chip selection signal lines CE0... CEN, and ready / Busy signal lines R / B0... R / BN are arranged. The internal shared bus Int_Bus, the chip selection signal lines CE0... CEN, and the ready / busy signal lines R / B0... R / BN are connected to the memory controller Memo_Cnt and the plurality of nonvolatile memory devices Memo_Dv0.

  The plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN store internal write data to be written to the internal nonvolatile memory array Memo_Ary0. Including internal buffer memories Buffer0... BufferN for storing the read internal read data. The nonvolatile memory device Memo_Dv0 as a representative of the N nonvolatile memory devices Memo_Dv0 ... Memo_DvN includes a nonvolatile memory array Memo_Ary0 and a peripheral circuit Per_Cir0. As is well known, the nonvolatile memory array Memo_Ary0 includes a plurality of nonvolatile memory cells arranged in a row direction and a column direction. The nonvolatile memory cell is, for example, a flash memory cell, and the flash memory cell has a control gate connected to a word line arranged in the row direction, a drain connected to a bit line arranged in the column direction, and a column direction. It is constituted by a MOS transistor having a source connected to the arranged ground line. Immediately below the control gate of the MOS transistor, a floating gate is formed as a nonvolatile storage node that is electrically insulated from the surroundings. Programming of MOS transistors as flash memory cells is performed by injecting electrons into the floating gate, and erasing is performed by neutralizing accumulated electrons in the floating gate. The peripheral circuit Per_Cir0 of the nonvolatile memory device Memo_Dv0 accesses the nonvolatile memory array Memo_Ary0 in the row direction and the column direction in response to a read command, a program command, and an erase command from the memory controller Memo_Cnt. The peripheral circuit Per_Cir0 includes a charge pump circuit, and the charge pump circuit generates a boosted voltage by boosting the power supply voltage supplied from the host device Host. The boosted voltage generated from the charge pump circuit is supplied to the read / program / erase circuit inside the peripheral circuit Per_Cir0 as a program high voltage and an erase high voltage. Other nonvolatile storage devices Memo_Dv1... Memo_DvN are configured in the same manner as the nonvolatile storage device Memo_Dv0.

  In order for the memory controller Memo_Cnt to access a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN via the internal shared bus Int_Bus, the chip enable signals / CE0... / CEN corresponding to the plurality of nonvolatile memory devices Memo_Dv0. For example, it is necessary to set to a low level. Before that, the memory controller Memo_Cnt confirms that the ready / busy signal lines R / B0... R / BN corresponding to the plurality of nonvolatile memory devices Memo_Dv0. Therefore, when it is confirmed that the nonvolatile memory device to be accessed through the internal shared bus Int_Bus is in the ready state, the chip enable signal corresponding to the nonvolatile memory device to be accessed is set to the low level enable state. Access to the nonvolatile memory device to be set and accessed via the internal shared bus Int_Bus is started. When the access via the internal shared bus Int_Bus is started, the ready / busy signal corresponding to the nonvolatile memory device being accessed becomes a busy state, for example, high level. When the access through the internal shared bus Int_Bus is completed, the ready / busy signal corresponding to the nonvolatile memory device for which the access has been completed returns to the ready state, for example, low level.

≪Flash memory card interleave writing operation≫
2 and 3 show that the memory controller Memo_Cnt of the flash memory card Memo_Crd shown in FIG. 1 supports a so-called interleave writing technique. With this interleaved writing that improves the writing speed from the host, it is possible to write two consecutive user data from the host to a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN in the following cases. That is, the logical address received together with the write instruction requested from the host device does not match any of the past logical addresses corresponding to the physical addresses previously written in the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. It is. When this mismatch is confirmed from the address conversion information stored in the management data area of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN, the memory controller Memo_Cnt starts the following interleave writing process. Note that the logical address received together with two consecutive user data from the host is a logical address that is common to the two consecutive user data, and two different logical addresses for the two consecutive user data. There is a case. In any case, when the common logical address or two different logical addresses do not match any of the past logical addresses corresponding to the physical addresses previously written in the plurality of nonvolatile memory devices Memo_Dv0... Write processing is executed.

  In this interleave writing technique, two new write user data Data_PD00... Data_PD03, Data_PD04. The data is transferred to another selected nonvolatile memory device Memo_DvN in two time zones through the internal common bus Int_Bus. First, in response to a write instruction from the host, the memory controller Memo_Cnt continues to the internal buffer memory Buffer0 of one nonvolatile memory device Memo_Dv0 through the internal common bus Int_Bus from time T1 to time T3 in FIG. The first write user data Data_PD00... Data_PD03 of the two new write user data Data_PD00... Data_PD03, Data_PD04... Data_PD07 is transferred together with the write command Pr_CMD and the write physical address Add_PD00. More precisely, the write command Pr_CMD and the write physical address Add_PD00... Add_PD03 are transferred from the memory controller Memo_Cnt to one non-volatile memory device Memo_Dv0 between time T1 and time T2, and from time T2 to time T3. First write user data Data_PD00... Data_PD03 and a write start command Ini_Wr_CMD are transferred from the memory controller Memo_Cnt to one nonvolatile memory device Memo_Dv0. Next, from time T3 to time T5 in FIG. 3, the first write user data Data_PD00... Data_PD03 internal write operation Int_Wr_Ope is executed from the internal buffer memory Buffer0 to the internal nonvolatile memory array of one nonvolatile memory device Memo_Dv0 Is done. In parallel with the period of this internal write operation Int_Wr_Ope, two new write user data Data_PD00... Subsequent write user data Data_PD04... Data_PD07 of Data_PD04. More precisely, the write command Pr_CMD and the write physical address Add_PD04... Add_PD07 are transferred from the memory controller Memo_Cnt to another non-volatile memory device Memo_DvN from time T3 to time T4, from time T4 to time T5. The subsequent write user data Data_PD04... Data_PD07 and the write start command Ini_Wr_CMD are transferred from the memory controller Memo_Cnt to another nonvolatile memory device Memo_DvN. As a result, the internal write operation Int_Wr_Ope of the first write user data Data_PD00... Data_PD03 from time T3 in one nonvolatile memory device Memo_Dv0 and another nonvolatile memory via the internal common bus Int_Bus from time T3 Subsequent write data to the device Memo_DvN Data_PD04... Data_PD07 access data Pr_CMD, Add_PD04... Add_PD07, Data_PD04. With this interleave writing technique, it is possible to improve the writing speed when writing two new user data that are continuously written from the host. This high-speed interleave writing operation is extremely effective when storing multimedia information such as image data and music data in the flash memory card Memo_Crd.

≪Mapping operation to different physical addresses of flash memory card≫
FIG. 4 illustrates an address conversion operation in which the flash memory card Memo_Crd shown in FIG. 1 performs mapping to different physical addresses with the same logical address from the host in order to take measures against power interruption during wear leveling or writing processing. It is a figure to do. In order to take measures against power interruption at the time of wear leveling or writing processing, mapping to different physical addresses with the same logical address from the host is as follows. That is, the logical address received together with the write instruction requested from the host device matches one of the past logical addresses corresponding to the physical addresses previously written in the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN. is there. When this coincidence is confirmed from the address conversion information stored in the management data area of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN, the memory controller Memo_Cnt performs the following processing of mapping to different physical addresses with the same logical address To start.

  That is, as shown in the figure, a plurality of page areas PD00... PD03, PD08... Of a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN included in one erase super block EB0 that is an old physical address corresponding to the same logical address. PD11, PD04... PD07, PD12... PD15 have already been stored with user data from the host with the same logical address. From this state, a case where a process for partially updating only the data in the page areas PD00... PD03 out of the plurality of page areas PD00... PD03, PD08... PD11, PD04. Suppose. In addition, as shown in the figure, the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN store write data to be written to the nonvolatile memory array Memo_Ary0... Memo_AryN and the internal nonvolatile memory array Memo_Ary0. Memory array Memo_Ary0... Internal buffer memories Buffer0... BufferN for storing read data read from Memo_AryN are included. A plurality of non-volatile memory devices Memo_Dv0... Memo_DvN non-volatile memory array Memo_Ary0... Yes. That is, an erase block including a plurality of page areas PD00... PD03, PD08... PD11 of the nonvolatile memory array Memo_Ary0 of the first nonvolatile memory device Memo_Dv0 and a nonvolatile memory array Memo_Ary1 of the second nonvolatile memory device Memo_Dv1. An erase block including a plurality of page areas (not shown), and similarly, from a plurality of page areas PD04... PD07, PD12, PD15 of the nonvolatile memory array Memo_AryN of the (N−1) th nonvolatile memory device Memo_DvN. One erase super block EB0 is configured by linking with the erase block. In this way, one erase super block EB0 obtained by linking a plurality of erase blocks of a nonvolatile memory array Memo_Ary0 ... Memo_AryN of a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN is a plurality of nonvolatile memory devices Memo_Dv0. Is a management unit of the erase operation. Each of the plurality of page areas PD00... PD03, PD08... PD11 of the nonvolatile memory array Memo_Ary0 of one nonvolatile memory device Memo_Dv0 includes a 512-byte user data area and a 16-byte management data area. Therefore, in the non-volatile memory array Memo_Ary0 of one non-volatile memory device Memo_Dv0, the unit of writing is each page area of 528 bytes in total of the user data area of 512 bytes and the management data area of 16 bytes. One erase block which is an erase unit in the nonvolatile memory array Memo_Ary0 of one nonvolatile memory device Memo_Dv0 is a plurality of page areas PD00... PD03, PD08... PD11 each having 528 bytes, and a total of 528 × 8 = 4224 bytes. It has become. However, the memory controller Memo_Cnt manages an erasing operation in units of one erasing super block EB0 that links a plurality of page areas of a non-volatile memory array Memo_Ary0 ... Memo_AryN of a plurality of non-volatile memory devices Memo_Dv0... Memo_DvN. Only the data in the page areas PD00... PD03 of the plurality of page areas PD00... PD03, PD08... PD11, PD04... PD07, PD12. Assume that the processing to be performed is requested from the host. In this case, the old physical address corresponding to the same logical address from the host is one erase super block EB0, and the new physical address corresponding to the same logical address from the host is another erase super block EBL. Therefore, it is necessary to change the mapping of the physical address corresponding to the same logical address. For this purpose, it is necessary to write update data PD00 ′... PD03 ′ from the host to another erase super block EBL, which is a new physical address of one nonvolatile memory device Memo_Dv0, via the internal buffer memory Buffer0. It is. In addition to this, the non-updated data PD04... PD07, PD12... PD15 not updated by the host is transferred from one erase super block EB0 that is an old physical address of another nonvolatile memory device Memo_DvN to another one that is a new physical address. It is also necessary to copy to the erase super block EBL via the internal buffer memory BufferN. Note that another erase super block EBL has already been erased and can be used for data writing at any time. Similarly, the non-updated data PD08... PD11 not updated by the host is also stored in the internal buffer from one erase superblock EB0 which is an old physical address of one nonvolatile memory device Memo_Dv0 to another erase superblock EBL which is a new physical address. It is necessary to copy via the memory Buffer0. Update data PD00 '... PD03' and non-update data PD04 ... PD07, PD08 ... PD11, PD12 ... PD15 are safely passed through the internal buffer memory Buffer0 ... BufferN during another erase super block EBL which is a new physical address. When stored, unnecessary old data PD00... PD03, PD04... PD07, PD08... PD11, PD12. Garbage collection is performed. As a result, one erase super block EB0 having an old physical address can be reused for the next writing.

  FIG. 5 is a waveform diagram for explaining the process of changing the mapping of the physical address corresponding to the same logical address shown in FIG. 4 by the memory controller studied by the present inventors prior to the present invention described at the beginning. is there. This memory controller supports the interleave writing technique described with reference to FIGS. First, the memory controller performs data transfer including a write command, a write physical address, and write data to one nonvolatile memory device of a plurality of nonvolatile memory devices via an internal shared bus. However, once this data transfer is started, the memory controller occupies the internal shared bus of the flash memory card until the transfer of the write data unit of 4 pages (528 × 4 = 2112 bytes) is completed. Therefore, from time T1 to time T3 in the figure, the memory controller sets the chip selection signal / CE0 to the low level that is the enable state in order to select one nonvolatile memory device Memo_Dv0. From time T1 to time T2, the memory controller writes a write command Pr_CMD for writing the update data PD00 ′. And write addresses Add_PD00 ′... Add_PD03 ′ are output to the internal common bus Int_Bus. The write command Pr_CMD and the write address Add_PD00 ′... Add_PD03 ′ transferred via the internal common bus Int_Bus are respectively latched in the command latch and address latch of one nonvolatile memory device Memo_Dv0. Further, the memory controller outputs update data Data_PD00 ′... Data_PD03 ′ of 4 pages (2112 bytes) from the host to the internal common bus Int_Bus from time T2 to time T3 in FIG. The write update data Data_PD00 ′... Data_PD03 ′ transferred via the internal common bus Int_Bus is latched in the internal buffer memory Buffer0 of one nonvolatile memory device Memo_Dv0. When transfer of four pages of write data units from the memory controller via the internal common bus Int_Bus to the internal buffer memory Buffer0 of one nonvolatile memory device Memo_Dv0 is completed by time T3, command latch and address latch An internal write operation Int_Wr_Ope of four pages of write data in one nonvolatile memory device Memo_Dv0 using the internal buffer memory Buffer0 is started. On the other hand, the ready / busy signal line R / B at the low level (ready state) at time T3 notifies the memory controller that the internal common bus Int_Bus has been released. In order to select another nonvolatile memory device Memo_DvN from time T3, the memory controller sets the chip selection signal / CEN to a low level that is in an enabled state. In this state, the memory controller sends the internal read command Int_Rd_CMD and the internal read address Add_PD04... Add_PD07 for reading the non-updated data PD04... PD07 from one erase super block EB0 which is an old physical address to the internal common bus Int_Bus. Output. The internal read command Int_Rd_CMD and the internal read address Add_PD04... Add_PD07 transferred via the internal common bus Int_Bus are respectively latched in the command latch and address latch of the other nonvolatile memory device Memo_DvN. When the data transfer from the memory controller via the internal common bus Int_Bus to the other one of the nonvolatile memory devices Memo_DvN and the internal read command to the address latch and the internal read address is completed by the time T4, from the time T4 An internal read operation Int_Rd_Ope using a command latch and an address latch in the other nonvolatile memory device Memo_DvN is started. Until the time T5, the internal read operation Int_Rd_Ope from the one erase super block EB0, which is the old physical address of the other non-volatile memory device Memo_DvN, to the internal buffer memory BufferN is completed, and this internal buffer memory is not used until time T5. Internal write Int_Wr_Ope of non-updated data PD04... PD07 from Buffer N to another erase super block EBL which is a new physical address of another nonvolatile memory device Memo_DvN is possible.

  In the waveform diagram of FIG. 5, the time between two adjacent times was estimated by the present inventors as follows.

From time T1 to time T2: 0.2 μSec
From time T2 to time T3: 70 μSec
From time T3 to time T4: 0.2 μSec
From time T4 to time T5: 100 μSec
Therefore, in the change processing of the mapping of the physical address corresponding to the same logical address shown in FIG. 5, the non-update to the other one erase super block EBL which is the new physical address of the other one nonvolatile memory device Memo_DvN In order to enable the internal writing Int_Wr_Ope of the data PD04... PD07, it is necessary to wait about 170 μSec from time T1 to time T5. Therefore, if the internal write Int_Wr_Ope of the non-updated data PD04... PD07 to the other one erase super block EBL which is the new physical address of the other one nonvolatile memory device Memo_DvN is required for about 100 μSec, another one from the time T1 Approximately 270 μSec elapses until the end time T6 of the internal write Int_Wr_Ope of the non-update data PD04... PD07 to one erase super block EBL.

  FIG. 6 is a waveform diagram illustrating a process of changing the mapping of physical addresses corresponding to the same logical address shown in FIG. 4 in the flash memory card Memo_Crd according to one embodiment of the present invention shown in FIG. Note that the memory controller Memo_Cnt of the flash memory card Memo_Crd according to one embodiment of the present invention shown in FIG. 6 also supports the interleave writing technique described with reference to FIGS. However, the memory controller Memo_Cnt of the flash memory card Memo_Crd according to the embodiment of the present invention shown in FIG. It is determined that a write process is necessary, and also determines that an internal read process and an internal write process from another nonvolatile memory device Memo_DvN are necessary.

  First, since the ready / busy signal R / B0 of one non-volatile memory device Memo_Dv0 is in a low-level ready state before time T6 in the figure, the memory controller selects one non-volatile memory device Memo_Dv0. Then, the chip selection signal / CE0 is set to the low level which is the enable state. Therefore, from time T6 to time T7 in the figure, the memory controller writes the update data PD00 ′... PD03 ′ from the host to another erase super block EBL which is a new physical address of one nonvolatile memory device Memo_Dv0. Write command Pr_CMD and write address Add_PD00 ′... Add_PD03 ′ are output to the internal common bus Int_Bus. The write command Pr_CMD and the write address Add_PD00 ′... Add_PD03 ′ transferred via the internal common bus Int_Bus are respectively latched in the command latch and address latch of one nonvolatile memory device Memo_Dv0. By the time T7, the latch of the write command Pr_CMD and the write address Add_PD00 ′... Add_PD03 ′ is completed in the command latch and address latch of one nonvolatile memory device Memo_Dv0. Before time T7, the ready / busy signal R / BN of the other non-volatile memory device Memo_DvN is in a low-level ready state, so that the memory controller selects another non-volatile memory device Memo_DvN. The chip selection signal / CEN is set to the enabled low level. Accordingly, from time T7 to time T8, the memory controller reads the internal read command Int_Rd_CMD and the internal read address Add_PD04 ... Add_PD07 for reading the non-updated data PD04 ... PD07 from one erase super block EB0 which is the old physical address. The start command Ini_Rd_CMD is output to the internal common bus Int_Bus. The internal read command Int_Rd_CMD, the internal read start command Ini_Rd_CMD, and the internal read address Add_PD04... Add_PD07 transferred via the internal common bus Int_Bus are respectively latched in the command latch and the address latch of the other nonvolatile memory device Memo_DvN. . By time T8, the data transfer from the memory controller via the internal common bus Int_Bus to the command latch and the address latch of the other nonvolatile memory device Memo_DvN and the internal read start command and the internal read address is completed. Then, the internal read operation Int_Rd_Ope using the command latch and the address latch in the other one nonvolatile memory device Memo_DvN is started from time T8. After time T8, the memory controller sets the chip selection signal / CEN to a high level which is a disenabled state in order to deselect another non-volatile memory device Memo_DvN. By time T9, the internal read operation Int_Rd_Ope from the one erase super block EB0, which is the old physical address of the other non-volatile memory device Memo_DvN, to the internal buffer memory BufferN is completed. On the other hand, after time T8, the memory controller changes the chip selection signal / CEN from the high level in the disabled state to the low level in the enabled state in order to resume the selection of one nonvolatile memory device Memo_DvN. Further, the memory controller outputs the update data Data_PD00 ′... Data_PD03 ′ from the host and the write start command Ini_Wr_CMD to the internal common bus Int_Bus from time T8 to time T9 in FIG. The write update data Data_PD00 ′... Data_PD03 ′ and the write start command Ini_Wr_CMD transferred via the internal common bus Int_Bus are respectively latched in the internal buffer memory Buffer0 and the command latch of one nonvolatile memory device Memo_Dv0. When the transfer Data_Tr_Pr_Data of four pages of write data units from the memory controller to the internal buffer memory Buffer0 of one nonvolatile memory device Memo_Dv0 via the internal common bus Int_Bus is completed at the latest by time T9, the command latch and The internal write operation Int_Wr_Ope of the four pages of write data in one nonvolatile memory device Memo_Dv0 using the address latch and the internal buffer memory Buffer0 is started.

  In the waveform diagram of FIG. 6, the time between two adjacent times was estimated by the present inventors as follows.

From time T6 to time T7: 0.2 μSec
From time T7 to time T8: 0.2 μSec
From time T8 to time T9: 100 μSec (internal read operation of 4-page write data Int_Rd_Ope in another non-volatile memory device Memo_DvN)
Incidentally, between time T8 and time T9, 70 μSec processing time is required for the transfer Data_Tr_Pr_Data of four pages of write data units to the internal buffer memory Buffer0 of one nonvolatile memory device Memo_Dv0. However, it is not the processing time of transfer Data_Tr_Pr_Data of 4 pages to one nonvolatile memory device Memo_Dv0 of about 70 μSec, but the internal data of 4 pages of write data in another nonvolatile memory device Memo_DvN of about 100 μSec. The passage of time from time T8 to time T9 is determined by the processing time of the read operation Int_Rd_Ope. In order to select another non-volatile memory device Memo_DvN during the period from time T9 to time T9 ′, the memory controller sets the chip selection signal / CEN of the other non-volatile memory device Memo_DvN to the low level in the enabled state. Set. During this time, the memory controller performs internal write for the internal write Int_Wr_Ope of the non-updated data PD04... PD07 from the internal buffer memory BufferN to another erase superblock EBL that is the new physical address of the other nonvolatile memory device Memo_DvN. The write command Int_Pr_CMD, the internal write address Add_PD04... Add_PD07, and the internal write start command Ini_Pr_CMD can be output to the internal bus Int_Bus.

  Therefore, in the process of changing the mapping of the physical address corresponding to the same logical address shown in FIG. In order to enable the internal writing Int_Wr_Ope of the data PD04... PD07, it is only necessary to wait for a time of approximately 100 μSec from time T6 to time T9 ′. Therefore, if the processing of the internal write Int_Wr_Ope of the non-updated data PD04. Only about 200 μSec elapses until the end time T10 of the internal write Int_Wr_Ope of the non-update data PD04... PD07 to one erase super block EBL.

  The high-speed change processing of the physical address mapping shown in FIG. 6 is performed by frequently updating the same digital content created by word processing software, spreadsheet / software, drawing / software, etc. This is extremely effective when content is stored in the flash memory card Memo_Crd.

<< Flash Memory Card According to Other Embodiments >>
FIG. 7 is a diagram showing a configuration of a flash memory card Memo_Crd according to another embodiment of the first invention. The difference between the flash memory card Memo_Crd shown in FIG. 1 and the flash memory card Memo_Crd according to the first embodiment of the first invention shown in FIG. 1 will be described. In the embodiment shown in FIG. 7, a plurality of ready / busy signal lines R / B0 ... R / BN of a plurality of nonvolatile memory devices Memo_Dv0 ... Memo_DvN are connected to a single wired OR-connected ready / busy signal line Wired_OR_R / B. Commonly connected. Therefore, also in the embodiment shown in FIG. 7, from time T6 to time T7 in FIG. 6, the memory controller hosts the other erase superblock EBL, which is the new physical address of one nonvolatile memory device Memo_Dv0. A write command Pr_CMD for writing update data PD00 ′... PD03 ′ and a write address Add_PD00 ′... Add_PD03 ′ are output to the internal common bus Int_Bus. The write command Pr_CMD and the write address Add_PD00 ′... Add_PD03 ′ transferred via the internal common bus Int_Bus are respectively latched in the command latch and address latch of one nonvolatile memory device Memo_Dv0. By the time T7, the latching of the command latch and address latch write command Pr_CMD and the write address Add_PD00 ′ to Add_PD03 ′ of one nonvolatile memory device Memo_Dv0 is completed. When the command latch and the address latch are completed at time T7, the status register of one nonvolatile memory device Memo_Dv0 changes from the busy state to the ready state. Prior to time T7, the other nonvolatile memory device Memo_DvN is not accessed by the memory controller Memo_Cnt via the internal shared bus Int_Bus, so the status register of the other nonvolatile memory device Memo_DvN is also in the ready state. . The memory controller Memo_Cnt outputs a write command Pr_CMD for writing to one nonvolatile memory device Memo_Dv0 and a write address Add_PD00 '... Add_PD03' from the time T6 to the internal common bus Int_Bus, and then outputs the status of one nonvolatile memory device Memo_Dv0. Regularly check if the register has changed from busy to ready. The status register of one nonvolatile memory device Memo_Dv0 has changed from the busy state to the ready state at time T7, and the status register of the other one nonvolatile memory device Memo_DvN is also in the ready state at time T7. This is determined by the memory controller Memo_Cnt. Then, after time T7, the memory controller Memo_Cnt outputs the internal read command Int_Rd_CMD and the internal read address Add_PD04 ... Add_PD07 for reading the non-updated data PD04 ... PD07 to the other non-volatile memory device Memo_DvN to the internal common bus Int_Bus. To do. The internal read command Int_Rd_CMD and the internal read address Add_PD04... Add_PD07 transferred via the internal common bus Int_Bus are latched in the command latch and address latch of the other nonvolatile memory device Memo_DvN, respectively. When the command latch and the address latch are completed at time T8, the status register of the other nonvolatile memory device Memo_DvN is changed from the busy state to the ready state. The memory controller Memo_Cnt outputs the internal read command Int_Rd_CMD and the internal read address Add_PD04... Add_PD07 to the other non-volatile memory device Memo_DvN from the time T7 to the internal common bus Int_Bus, and then outputs the other non-volatile memory device Memo_DvN. Periodically check whether the status register has changed from busy to ready. The status register of one other nonvolatile memory device Memo_DvN has changed from the busy state to the ready state at time T8, and the status register of one nonvolatile memory device Memo_Dv0 is also in the ready state at time T8. This is determined by the memory controller Memo_Cnt. Then, after time T8, the memory controller Memo_Cnt outputs update data Data_PD00 ′... Data_PD03 ′ from the host to one nonvolatile memory device Memo_Dv0 to the internal common bus Int_Bus. The write update data Data_PD00 ′... Data_PD03 ′ transferred via the internal common bus Int_Bus is latched in the internal buffer memory Buffer0 of one nonvolatile memory device Memo_Dv0. As described above, a plurality of ready / busy signal lines R / B0... R / BN of a plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN are commonly connected to a single wired OR connection ready / busy signal line Wired_OR_R / B. However, the memory controller Memo_Cnt periodically checks the contents of the status registers of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN, so that any one of the plurality of nonvolatile memory devices Memo_Dv0... Memo_DvN via the internal common bus Int_Bus. It is possible to determine whether or not the memory device can be selected.

  FIG. 8 is a diagram showing a configuration of a flash memory card Memo_Crd according to one embodiment of the second invention. The difference between the flash memory card Memo_Crd shown in FIG. 1 and the flash memory card Memo_Crd according to the first embodiment of the first invention shown in FIG. 1 will be described.

  In one embodiment of the second present invention shown in FIG. 8, the memory controller Memo_Cnt includes a plurality of nonvolatile memories via the internal shared bus Int_Bus as shown in the waveform diagram of the internal shared bus Int_Bus shown in FIG. Data transfer to devices Memo_Dv0... Memo_DvN is performed at a predetermined frequency. The predetermined frequency of data transferred from the memory controller Memo_Cnt to the internal shared bus Int_Bus is relatively high. Accordingly, the write enable / read enable signal WE / RE from the memory controller Memo_Cnt also has a relatively high frequency. Here, in the write enable / read enable signal WE / RE, for example, a high level indicates a write enable state, and a low level indicates a read enable state. However, the two chip selection signals / CE0 and / CEN for the memory controller Memo_Cnt to select at least two nonvolatile memory devices Memo_Dv0 and Memo_DvN selected from the plurality of nonvolatile memory devices Memo_Dv0 ... Memo_DvN are lower than a predetermined frequency. Has a relatively low frequency. Further, the phases of the two chip selection signals / CE0 and / CEN are different, and at least two selected nonvolatile memory devices Memo_Dv0 and Memo_DvN are alternately selected by the two chip selection signals / CE0 and / CEN. Accordingly, the nonvolatile memory device selected by the chip selection signal is accessed by the memory controller Memo_Cnt. Therefore, in FIG. 9, the low level period of the chip selection signal / CE0 for selecting the nonvolatile memory device Memo_Dv0 and the low level period of the chip selection signal / CEN for selecting the nonvolatile memory device Memo_DvN are alternated.

  Since the high level write enable / read enable signal WE / RE is sampled at the timing when the chip selection signal / CE0 for selecting the nonvolatile memory device Memo_Dv0 changes from the high level to the low level, the nonvolatile memory device Memo_Dv0 performs the write operation. Execute. Therefore, the data Da0, Da1, Da2, Da3... Da8, Da9 output from the memory controller Memo_Cnt to the internal bus Int_Bus during the low level period of the chip selection signal / CE0 for selecting the nonvolatile memory device Memo_Dv0 is the nonvolatile memory device Memo_Dv0. Are written into the non-volatile memory array Memo_Ary0.

  Since the high level write enable / read enable signal WE / RE is sampled at the timing when the chip selection signal / CEN for selecting the nonvolatile memory device Memo_DvN changes from the high level to the low level, the nonvolatile memory device Memo_DvN is also the same. Perform a write operation. Since the memory controller Memo_Cnt sets the address latch enable signal ALE to high level and the command latch enable signal CLE to high level during the low period of the chip selection signal / CEN for selecting the nonvolatile memory device Memo_DvN, the memory The column address signals CA0 and CA1, the row address signals RA0 and RA1, and the write command Cmd1 transferred from the controller Memo_Cnt to the internal bus Int_Bus are latched in the address latch and command latch of the nonvolatile memory device Memo_DvN, respectively. Therefore, the data X, X, Db0, Db1, and Db2 output to the internal bus Int_Bus during the low period of the chip selection signal / CEN according to the column address signals CA0 and CA1 and the row address signals RA0 and RA1 are stored in the nonvolatile memory. It is written to the non-volatile memory array Memo_AryN of the device Memo_DvN.

  Processing of writing data Da0, Da1, Da2, Da3... Da8, Da9 into nonvolatile memory device Memo_Dv0 to nonvolatile memory array Memo_Ary0 and nonvolatile memory device of data X, X, Db0, Db1, Db2 Memo_DvN The process of writing to the array Memo_AryN can be performed in parallel. As a result, in the nonvolatile semiconductor memory device in which the memory controller and the plurality of nonvolatile memory devices are connected by the internal shared bus, the parallel operation rate of the plurality of nonvolatile memory devices can be improved.

  Further, as a modified embodiment of FIG. 8, L (L> 2) non-volatile memory devices Memo_Dv0... Memo_DvL−1 selected from a plurality of N non-volatile memory devices Memo_Dv0. It can be accessed sequentially by L selection signals / CE0... / CEL-1 having a low frequency of L and having a phase difference of 2π / L. One example of N is N = 8, and one example of L is L = 4. In this case, the frequencies of the four selection signals / CE0, / CE1, / CE2, / CE3 are 1/4 of the predetermined frequency, and the four selection signals / CE0, / CE1, / CE2, / CE3 The phases are different from each other by π / 2.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the flash memory card of the present invention can be used not only as a removable device in a host device but also as a non-volatile semiconductor memory device fixedly incorporated in an electronic device such as a mobile phone terminal. With this built-in nonvolatile semiconductor memory device, even if the end user inadvertently shuts off the power supply of the electronic device during the writing process, the old data with the old physical address can be reliably stored.

  The non-volatile memory array Memo_Ary0... Memo_AryN of the non-volatile memory devices Memo_Dv0. At this time, it is recommended that the internal buffer memories Buffer0 ... BufferN of the non-volatile memory devices Memo_Dv0 ... Memo_DvN also be a plurality of internal buffer memory banks.

  Furthermore, the nonvolatile memory cell of the nonvolatile memory array Memo_Ary0 ... Memo_AryN of the nonvolatile memory devices Memo_Dv0... Memo_DvN is not only a flash memory cell having a floating gate but also an interface trap level between a gate nitride film and a gate oxide film immediately below the control gate. It is also possible to make a nonvolatile memory cell that captures electrons. The present invention is also applicable to nonvolatile semiconductor memories such as phase change memory and MRAM.

FIG. 1 is a diagram showing a configuration of a flash memory card according to one embodiment of the first invention. FIG. 2 shows that the memory controller of the flash memory card shown in FIG. 1 supports the interleave writing technique. FIG. 3 shows that the memory controller of the flash memory card shown in FIG. 1 supports a so-called interleave writing technique. FIG. 4 illustrates an address conversion operation in which the flash memory card shown in FIG. 1 performs mapping to different physical addresses with the same logical address from the host in order to take measures against power interruption during wear leveling or writing processing. FIG. FIG. 5 is a waveform diagram for explaining the process of changing the mapping of the physical address corresponding to the same logical address shown in FIG. 4 by the memory controller studied by the present inventors prior to the present invention. FIG. 6 is a waveform diagram illustrating a process of changing the mapping of the physical address corresponding to the same logical address shown in FIG. 4 in the flash memory card according to one embodiment of the present invention shown in FIG. FIG. 7 is a diagram showing the configuration of a flash memory card according to another embodiment of the first invention. FIG. 8 is a diagram showing the configuration of a flash memory card according to one embodiment of the second invention. FIG. 9 is a diagram for explaining the operation of the flash memory card according to one embodiment of the second invention.

Explanation of symbols

Memo_Crd Nonvolatile Semiconductor Memory Device Memo_Cnt Memory Controller Int_Bus Internal Common Bus / CE0 Chip Selection Signal / CEN Chip Selection Signal R / B0 Ready / Busy Signal R / BN Ready / Busy Signal Memo_Dv0 Nonvolatile Memory Device Memo_DvN Nonvolatile Memory Device Me0 Nonvolatile Memory Device Me0 Memory array Memo_AryN Non-volatile memory array Buffer0 Internal buffer memory BufferN Internal buffer memory

Claims (29)

A memory controller, a plurality of nonvolatile memory devices, and an internal shared bus connected between the memory controller and the plurality of nonvolatile memory devices,
Each of the plurality of nonvolatile memory devices stores an internal nonvolatile memory array and internal write data written to the internal nonvolatile memory array, while storing internal read data read from the internal nonvolatile memory array Internal buffer memory to
In response to an instruction from the host, the memory controller selects one nonvolatile memory device from a plurality of nonvolatile memory devices, and the memory controller selects the one nonvolatile memory device via the internal shared bus. Transfer the access data of the command and address corresponding to the instruction from the host to the memory device,
Prior to completion of transfer of user data based on the instructions from the host via the internal shared bus between the one non-volatile memory device and the memory controller, the memory controller While the selection of the memory device is interrupted, the other non-volatile memory device of the plurality of non-volatile memory devices is selected, and the memory controller selects the other non-volatile memory device selected via the internal shared bus The command and address access data for internal data transfer between the internal nonvolatile memory array of the other nonvolatile memory device and the internal buffer memory of the other nonvolatile memory device are selected and transferred to The other non-volatile memory device is configured to transmit the command for the internal data transfer. In response to said access data with the address, and executes the internal data transfer between the internal non-volatile memory array and the internal buffer memory,
During the internal data transfer, the memory controller resumes selection of the one non-volatile memory device, and resuming the selection results in the internal shared bus between the one non-volatile memory device and the memory controller. A nonvolatile semiconductor memory device that transfers user data based on an instruction from the host via the host. A plurality of selection signal lines connected between the memory controller and the plurality of nonvolatile memory devices;
The memory controller selects the one nonvolatile memory device from the plurality of nonvolatile memory devices via one selection signal line of the plurality of selection signal lines,
2. The nonvolatile semiconductor device according to claim 1, wherein the memory controller selects the other one nonvolatile memory device from the plurality of nonvolatile memory devices via another selection signal line of the plurality of selection signal lines. Storage device. A plurality of ready / busy signal lines connected between the memory controller and the plurality of nonvolatile memory devices;
Whether the memory controller can select the one nonvolatile memory device via the one selection signal line from the ready state and the busy state of one ready / busy signal line of the plurality of ready / busy signal lines To determine
From the ready state and busy state of another one ready / busy signal line of the plurality of ready / busy signal lines, the memory controller sends the other one non-volatile memory device via the other one select signal line. The nonvolatile semiconductor memory device according to claim 2, wherein it is determined whether or not selection is possible. A plurality of ready / busy signal lines from the plurality of nonvolatile memory devices are commonly connected to one common ready / busy signal line;
When the memory controller periodically checks the contents of the status registers of the plurality of nonvolatile memory devices, any one of the plurality of nonvolatile memory devices can be selected via the internal common bus. The nonvolatile semiconductor memory device according to claim 2, wherein it is determined whether or not there is.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device 3. The nonvolatile semiconductor memory device according to claim 2, wherein a write operation and a data transfer of the subsequent write user data to the other nonvolatile memory device via the internal common bus are executed in parallel.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device 4. The nonvolatile semiconductor memory device according to claim 3, wherein a write operation and a data transfer of the subsequent write user data to the other nonvolatile memory device via the internal common bus are executed in parallel.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device 5. The nonvolatile semiconductor memory device according to claim 4, wherein a write operation and a data transfer of the subsequent write user data to the other nonvolatile memory device via the internal common bus are executed in parallel.   The memory controller generates different physical addresses by address conversion during a plurality of write processes using the same logical address from the host, and actual writing in the nonvolatile semiconductor memory device is executed using the different physical addresses. By doing so, at least one of wear leveling and storage of old data at the old physical address at the time of write processing is enabled. When new data at the new physical address at the time of write processing is stored, the old physical address of the old physical address is stored. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the memory controller executes garbage collection for erasing old data. A memory controller, a plurality of nonvolatile memory devices, and an internal shared bus connected between the memory controller and the plurality of nonvolatile memory devices,
Each of the plurality of nonvolatile memory devices stores an internal nonvolatile memory array and internal write data written to the internal nonvolatile memory array, while storing internal read data read from the internal nonvolatile memory array Internal buffer memory to
In response to an instruction from the host, the memory controller selects one nonvolatile memory device from the plurality of nonvolatile memory devices, and the memory controller writes and writes a write command to the selected one nonvolatile memory device. Start transferring the physical address,
After the start of the transfer of the write command and the write physical address to the one non-volatile memory device, prior to completion of transfer of the write data to the internal buffer memory of the one non-volatile memory device, the memory The controller interrupts the selection of the one nonvolatile memory device, while selecting another nonvolatile memory device from the plurality of nonvolatile memory devices, the memory controller is selected via the internal shared bus. The transfer of the internal read command and the internal read physical address to the one other non-volatile memory device is started, and in the selected one other non-volatile memory device, the internal read command, the internal read address, In response to the internal non-volatile memory array The internal read operation of the parts buffer memory is started,
After the start of the internal read operation in the other non-volatile memory device, the memory controller interrupts the selection of the other non-volatile memory device, while selecting the one non-volatile memory device. After restarting the selection of the one non-volatile memory device, the memory controller starts transferring write data to the internal buffer memory of the one non-volatile memory device via the internal shared bus. The transfer of the write data from the memory controller to the internal buffer memory of the one nonvolatile memory device via the internal shared bus, and the internal nonvolatile memory in the other nonvolatile memory device In parallel with the internal read operation from the memory array to the internal buffer memory The nonvolatile semiconductor memory device which is line. A plurality of selection signal lines connected between the memory controller and the plurality of nonvolatile memory devices;
The memory controller selects the one nonvolatile memory device from the plurality of nonvolatile memory devices via one selection signal line of the plurality of selection signal lines,
The non-volatile semiconductor according to claim 9, wherein the memory controller selects the other non-volatile memory device from the non-volatile memory devices via another selection signal line of the plurality of selection signal lines. Storage device. A plurality of ready / busy signal lines connected between the memory controller and the plurality of nonvolatile memory devices;
Whether the memory controller can select the one nonvolatile memory device via the one selection signal line from the ready state and the busy state of one ready / busy signal line of the plurality of ready / busy signal lines To determine
From the ready state and busy state of another one ready / busy signal line of the plurality of ready / busy signal lines, the memory controller sends the other one non-volatile memory device via the other one select signal line. The nonvolatile semiconductor memory device according to claim 10, wherein it is determined whether or not selection is possible. A plurality of ready / busy signal lines from the plurality of nonvolatile memory devices are commonly connected to one common ready / busy signal line;
When the memory controller periodically checks the contents of the status registers of the plurality of nonvolatile memory devices, any one of the plurality of nonvolatile memory devices can be selected via the internal common bus. The nonvolatile semiconductor memory device according to claim 10, wherein it is determined whether or not there is.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device The nonvolatile semiconductor memory device according to claim 10, wherein a write operation and a data transfer of the subsequent write user data to the other nonvolatile memory device via the internal common bus are executed in parallel.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device The nonvolatile semiconductor memory device according to claim 11, wherein a write operation and data transfer of the subsequent write user data to the other nonvolatile memory device via the internal common bus are executed in parallel.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device 13. The nonvolatile semiconductor memory device according to claim 12, wherein a write operation and a data transfer of the subsequent write user data to the other nonvolatile memory device via the internal common bus are executed in parallel.   The memory controller generates a different physical address by address conversion in each of a plurality of write processes using the same logical address from the host, and the actual write in the nonvolatile semiconductor memory device is the different physical address To enable at least one of wear leveling and storage of old data at the old physical address during write processing, and when new data at the new physical address is stored during the write processing, the old data is stored. 16. The nonvolatile semiconductor memory device according to claim 9, wherein the memory controller executes garbage collection for erasing the old data at a physical address. A memory controller, a plurality of nonvolatile memory devices, and an internal shared bus connected between the memory controller and the plurality of nonvolatile memory devices,
Each of the plurality of nonvolatile memory devices stores an internal nonvolatile memory array and internal write data written to the internal nonvolatile memory array, while storing internal read data read from the internal nonvolatile memory array Internal buffer memory to
In response to the logical address received with the write instruction requested from the host being inconsistent with any of the past logical addresses corresponding to the physical addresses previously written to the plurality of non-volatile memory devices. The memory controller transmits two consecutive new write user data in accordance with the write instruction from the host to one nonvolatile memory device selected from the plurality of nonvolatile memory devices and one other nonvolatile memory device selected Between the selected one non-volatile memory device and the selected other non-volatile memory device via the internal common bus in a time-sharing manner in two time zones. Each newly written user data from each internal buffer memory to each internal nonvolatile memory array Internal write operation is performed,
In response to the logical address received with the write instruction requested from the host matching one of the past logical addresses corresponding to the physical address previously written to the plurality of non-volatile memory devices. The memory controller is configured to update the data written in the areas of the plurality of nonvolatile memory devices having the old physical address corresponding to the matched logical address with the data updated according to the write instruction requested from the host and the non-update. For the data to be updated, any non-volatile memory device of the plurality of non-volatile memory devices having a new physical address corresponding to the matched logical address Any of the above through the internal buffer memory of the nonvolatile memory device The update data from the host is written to the internal nonvolatile memory array of the nonvolatile memory device, and the non-volatile memory device is configured to transfer the update data from the host to any one of the nonvolatile memory devices in parallel in time. The data written in the area of any one of the plurality of nonvolatile memory devices having an old physical address corresponding to the matched logical address regarding the data to be updated is internally stored in any internal buffer memory The non-updated data that is read and then internally read into any of the internal buffer memories is internally written to any internal nonvolatile memory array of any of the nonvolatile memory devices . A plurality of selection signal lines connected between the memory controller and the plurality of nonvolatile memory devices;
The memory controller selects the one nonvolatile memory device from the plurality of nonvolatile memory devices via one selection signal line of the plurality of selection signal lines,
The nonvolatile semiconductor device according to claim 17, wherein the memory controller selects the other nonvolatile memory device from the nonvolatile memory devices via another selection signal line of the plurality of selection signal lines. Storage device. A plurality of ready / busy signal lines connected between the memory controller and the plurality of nonvolatile memory devices;
Whether the memory controller can select the one nonvolatile memory device via the one selection signal line from the ready state and the busy state of one ready / busy signal line of the plurality of ready / busy signal lines To determine
From the ready state and busy state of another one ready / busy signal line of the plurality of ready / busy signal lines, the memory controller sends the other one non-volatile memory device via the other one select signal line. The nonvolatile semiconductor memory device according to claim 18, wherein it is determined whether or not selection is possible. A plurality of ready / busy signal lines from the plurality of nonvolatile memory devices are commonly connected to one common ready / busy signal line;
When the memory controller periodically checks the contents of the status registers of the plurality of nonvolatile memory devices, any one of the plurality of nonvolatile memory devices can be selected via the internal common bus. The nonvolatile semiconductor memory device according to claim 18, wherein it is determined whether or not there is.   The memory controller generates a different physical address by address conversion in each of a plurality of write processes using the same logical address from the host, and the actual write in the nonvolatile semiconductor memory device is the different physical address To enable at least one of wear leveling and storage of old data at the old physical address during write processing, and when new data at the new physical address is stored during the write processing, the old data is stored. 21. The nonvolatile semiconductor memory device according to claim 17, wherein the memory controller executes garbage collection for erasing the old data at a physical address. A memory controller, a plurality of nonvolatile memory devices, and an internal shared bus connected between the memory controller and the plurality of nonvolatile memory devices,
Each of the plurality of nonvolatile memory devices stores an internal nonvolatile memory array and internal write data written to the internal nonvolatile memory array, while storing internal read data read from the internal nonvolatile memory array Internal buffer memory to
In response to an instruction from the host to rewrite data stored in the internal nonvolatile memory array of any one of the plurality of nonvolatile memory devices, the memory controller transfers to the one nonvolatile memory device. After transferring a command and an address for updating data via the internal shared bus, the memory controller transfers the other nonvolatile memory device to the other nonvolatile memory device of the plurality of nonvolatile memory devices. A command and an address for reading the data not stored in the internal nonvolatile memory array, which is not subject to data update, to the internal buffer memory of the other nonvolatile memory device;
Thereafter, in parallel with the one other nonvolatile memory, the memory controller transfers update data for updating the data to the internal buffer memory of the one nonvolatile memory device via the internal shared bus. A non-volatile semiconductor storage device in which an internal read operation for reading the data not subject to data update to the internal buffer memory is executed in a memory device. In the one non-volatile memory device, the update data transferred to the internal buffer memory is changed to a new physical address different from an old physical address in which the stored data is stored before the data update in the internal non-volatile memory array. An internal write operation to write to the address is executed,
In response to an internal write command and address transferred from the memory controller to the other non-volatile memory device via the internal shared bus, the other non-volatile memory device transmits the internal buffer memory. Internally writing the read data that is not subject to data update to a new physical address that is different from the old physical address that stored the data that is not subject to data update before updating the data in the internal nonvolatile memory array The nonvolatile semiconductor memory device according to claim 22, wherein a write operation is performed. The old physical address storing the stored data before the data update in the internal nonvolatile memory array of the one nonvolatile memory device and the internal nonvolatile memory of the other nonvolatile memory device. The same logical address as the logical address from the host corresponding to the old physical address that has stored the data that is not the target of the data update in the memory array is rewritten from the host that rewrites the stored data. The memory controller receives with the instruction,
Responsive to the same logical address received with the instruction from the host to rewrite the data, the memory controller is responsible for the new physical address of the one non-volatile memory device and the other non-volatile 24. The nonvolatile semiconductor memory device according to claim 23, wherein the new physical address of the memory device is generated by address conversion. The old physical address of the one nonvolatile memory device and the new physical address of the one nonvolatile memory device are arranged in different erase blocks in the internal nonvolatile memory array of the one nonvolatile memory device, respectively.
The old physical address of the other non-volatile memory device and the new physical address of the other non-volatile memory device are different from each other in the internal non-volatile memory array of the other non-volatile memory device. The nonvolatile semiconductor memory device according to claim 24, wherein the nonvolatile semiconductor memory device is arranged in an erase block.   The memory controller includes: the one non-volatile memory device selected from the plurality of non-volatile memory devices and two other non-volatile memory devices that receive two consecutive new write user data in accordance with a write instruction from the host; In response to the write instruction from the host, the memory controller responds to the write instruction from the memory controller through the internal common bus to the internal buffer memory of the one nonvolatile memory device. The first write user data among the new write user data is transferred, and the memory block is connected via the internal common bus during the internal write operation from the internal buffer memory of the one nonvolatile memory device to the internal nonvolatile memory array. The subsequent write user data of the two consecutive new write user data is transferred from the controller to the internal buffer memory of the other non-volatile memory device, whereby the internal of the non-volatile memory device The write operation and the data transfer of the subsequent write user data to the other non-volatile memory device via the internal common bus are performed in parallel. The nonvolatile semiconductor memory device described. A memory controller, a plurality of nonvolatile memory devices, and an internal shared bus connected between the memory controller and the plurality of nonvolatile memory devices,
The memory controller executes data transfer at a predetermined frequency to the plurality of nonvolatile memory devices via the internal shared bus,
The memory controller accesses at least two nonvolatile memory devices selected from the plurality of nonvolatile memory devices alternately with at least two selection signals having a frequency lower than the predetermined frequency and having different phases. Semiconductor memory device.   28. The nonvolatile semiconductor memory device according to claim 27, wherein the two selection signals have a frequency that is substantially half the predetermined frequency, and the two selection signals have substantially opposite phases.   The memory controller selects L (L> 2) non-volatile memory devices selected from the plurality of non-volatile memory devices and has a low frequency of 1 / L of the predetermined frequency, and L is different in phase by 2π / L. 28. The nonvolatile semiconductor memory device according to claim 27, wherein the nonvolatile semiconductor memory device is sequentially accessed by a plurality of selection signals.

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