JP2007208705A - Spread spectrum clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spread spectrum clock generating circuit being capable of further dispersing a spectrum component and having the high reduction efficiency of a peak in a spectrum, by generating a modulation signal by an analog processing capable of widely spreading the frequency component of a clock and frequency-diffusing even the modulation signal by an efficient circuit configuration. <P>SOLUTION: A phase comparison means for comparing the phases of a reference clock and a feedback clock and outputting an error signal corresponding to a phase difference and a loop filter smoothing the error signal are fitted to the spread spectrum clock generating circuit. A modulation generating means for modulating the smoothed error signal and generating a spread spectrum modulation signal, and a clock generating means for generating the clock of a frequency corresponding to the spread spectrum modulation signal, are further fitted to the spread spectrum clock generating circuit. The modulation generating means generates the modulation signal where the frequency is spread. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a spread spectrum clock generation circuit.

With respect to the spread spectrum clock generation circuit, there is a technique for reducing the spectrum peak by switching the modulation signal to a plurality of different periods to disperse the spectrum components compared to the modulation signal having a constant period (see, for example, Patent Document 1). .
JP 2004-207846 A

  However, the background art described above has the following problems.

  In recent years, a spread spectrum clock generator (SSCG) has been used as a solution for suppressing EMI noise emitted from electronic devices. SSCG performs frequency modulation on a clock to disperse the frequency at which EMI noise occurs and reduce EMI.

  FIG. 1 is a block diagram showing the configuration of a conventional SSCG circuit.

  The frequency dividing circuit 2 performs multiplication setting of the SSCG circuit 1. The phases of the reference input signal and the feedback signal divided by the frequency divider circuit 2 are compared by the phase comparator 3, and a pulse signal corresponding to the compared phase difference is output by the charge pump 4. The comparison result is smoothed by the loop filter 5 and then output to the adder 7. The modulation generation circuit 6 generates an SSCG modulation waveform and outputs it to the adder 7. The adder 7 adds the outputs of the loop filter 5 and the modulation generation circuit 6 and outputs the result as a control signal to a voltage controlled oscillator (hereinafter referred to as VCO) 8. The VCO 8 outputs an output signal that has been frequency modulated in accordance with the control signal from the adder 7.

  FIG. 2 is an example of a modulation signal waveform of the conventional SSCG. (A) is a triangular wave with a fixed period, (b) is a sine wave.

  FIG. 3A shows the spectrum of the clock signal that has not been subjected to spread spectrum, and FIG. 3B shows the spectrum of the clock signal that has been spread spectrum by the SSCG circuit.

  The conventional SSCG having such a modulation waveform performs frequency modulation, so that the spectrum of the output clock is spread as shown in FIG. For example, when the modulation frequency is 30 kHz, the spectrum component of the output clock is always generated at intervals of 30 kHz, so that the spectrum reduction effect is small.

  In Patent Document 1, by switching the modulation signal to a plurality of different periods, the spectrum components are dispersed compared to the modulation signal having a constant period, and the spectrum peak is reduced.

  FIG. 2C shows a modulation waveform in which the modulation signal is switched to a plurality of different periods. FIG. 3C shows a spectrum in which the peak is further reduced by frequency modulation.

  The analog modulator described in Patent Document 1 incorporates a plurality of oscillation circuits and switches them with a switch in order to switch the modulation period. For this reason, if a large number of output periods of the modulator are switched in order to disperse the spectrum component, it is necessary to add an oscillation circuit for each different frequency, resulting in an increase in circuit scale.

  Therefore, an object of the present invention is to generate a modulation signal by analog processing that can spread the frequency component of the clock widely, and to spread the spectrum component by frequency spreading with an efficient circuit configuration, thereby further dispersing the spectrum component, and thereby increasing the spectrum peak. An object of the present invention is to provide a spread spectrum clock generation circuit having a high reduction rate.

In order to solve the above problems, a spread spectrum clock generation circuit according to the present invention compares a phase of a reference clock and a feedback clock and outputs an error signal corresponding to the phase difference, and a loop for smoothing the error signal. Spread spectrum clock generation comprising: a filter; modulation generation means for modulating a smoothed error signal to generate a spread spectrum modulation signal; and clock generation means for generating a clock having a frequency corresponding to the spread spectrum modulation signal In the circuit, the modulation generation means generates a modulation signal having a spread frequency. By configuring in this way, the modulation generation unit generates a modulation signal by analog processing capable of widely spreading the frequency component of the clock. By spreading the frequency of modulated signals with an efficient circuit configuration, spectrum components are reduced. Can be dispersed.

  According to an embodiment of the present invention, a spectrum signal can be further dispersed by generating a modulation signal by analog processing that can spread the frequency component of the clock widely, and also by spreading the frequency of the modulation signal with an efficient circuit configuration. A spread spectrum clock generation circuit with a high peak reduction rate can be realized.

Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings.
In all the drawings for explaining the embodiments, the same reference numerals are used for those having the same function, and repeated explanation is omitted.

  A configuration of a spread spectrum clock generation circuit (hereinafter referred to as an SSCG circuit) according to an embodiment of the present invention will be described with reference to FIG.

  The SSCG circuit 101 according to this embodiment includes a phase comparator 103 to which a reference input signal as a reference clock and an output signal of a frequency dividing circuit 102 described later are input, and a charge to which an output signal of the phase comparator 103 is input. A pump 104, a loop filter 105 to which an output signal of the charge pump is input, a modulation generation circuit 106 to which an output signal of the loop filter 105 is input, and a clock generation circuit 107 to which an output signal of the modulation generation circuit 106 is input And a frequency dividing circuit 102 to which an output signal of the clock generation circuit 107 is input.

  The frequency divider circuit 102 sets the multiplication of the SSCG circuit 101. The phase of the reference input signal and the phase of the feedback signal divided by the frequency divider circuit 102 are compared by the phase comparator 103, and a pulse signal corresponding to the compared phase difference is output by the charge pump 104.

  The comparison result is smoothed by the loop filter 105 and then output to the modulation generation circuit 106.

  The modulation generation circuit 106 modulates the signal from the loop filter 105 to generate a spread spectrum modulation signal.

  The clock generation circuit 107 generates a clock having a frequency corresponding to the input spread spectrum modulation signal.

  The SSCG circuit 101 is characterized in that a modulation generation circuit 106 generates a modulation signal having a spread frequency.

  FIG. 5 shows a modulation signal waveform of the SSCG circuit according to this embodiment. In this embodiment, the frequency of the modulation signal is diffused with respect to the waveform having a constant period as shown in FIGS. 2A and 2B, and the spectrum component of the clock is further dispersed. Compared with the conventional one, the reduction rate of the spectrum peak is high.

  Next, the SSCG circuit 201 according to the first embodiment of the present invention will be described with reference to FIG.

  The frequency dividing circuit 202 performs multiplication setting of the SSCG circuit 201. The phase of the reference input signal and the phase of the feedback signal divided by the frequency dividing circuit 202 are compared by the phase comparator 203, and a pulse signal corresponding to the compared phase difference is output by the charge pump 204. The comparison result is smoothed by the loop filter 205 and then output to the adder 207.

  The modulation wave oscillation circuit 206 is an oscillation circuit whose oscillation frequency can be controlled by an input current amount ICONT, and outputs a triangular wave O1 generated from a constant current source to the adder 211, and is formed by a triangular wave having a period corresponding to ICONT. The analog modulated wave O3 is output to the adder 207.

  Also, the modulation wave oscillation circuit 206 outputs a digital signal O2 having the same period as the analog modulation wave O3 to the modulation wave period control circuit 209.

  The VREF circuit (reference voltage generation circuit) 210 outputs the reference voltage to the adder 211. The adder 211 adds (synthesizes) the reference voltage output from the VREF circuit 210 and the triangular wave O1 as the first analog modulation signal output from the modulation wave oscillation circuit 206, and a voltage controlled oscillator (hereinafter referred to as VCO). The control signal is output to 212.

  The VCO 212 outputs the frequency-modulated output signal CK1 to the modulation wave period control circuit 209 in accordance with the control signal output from the adder 211.

  The modulation wave period control circuit 209 compares the phase of the frequency-modulated signal CK1 output from the VCO 212 and the digital clock signal O2 output from the modulation wave oscillation circuit 206, and converts the output signal of the phase difference into a current value. And output to the modulated wave oscillation circuit 206.

  Next, the modulated wave oscillation circuit 206 will be described with reference to FIG.

  First, a circuit as a first oscillating means for generating the triangular wave O1 will be described.

  A circuit that generates the triangular wave O1 includes a PMOS MP1, an inverter 300, an NMOS MN1, and hysteresis comparators 301 and 302 that receive the outputs of the inverter 300 and reference voltages VRH1 and VRL1, which are connected in series between the power supply and GND. And an RS latch circuit 303 to which the outputs of the hysteresis comparators 301 and 302 are input to the set input and the reset input, and an inverter 300 to which the output of the RS latch circuit 303 is input.

  The voltages PC1 and NC1 controlled by the current control circuit 304 are input to the gates of MP1 and MN1, respectively.

  A capacitor C1 is connected between the output of the inverter 300 and GND.

  With the above configuration, a triangular wave O1 is obtained at the output of the inverter 300.

  Next, a circuit as a second transmitting means for generating the analog modulated wave O3 and the digital clock signal O2 as the second analog modulated signal will be described. A circuit similar to the circuit that generates the triangular wave described above is configured.

  The voltages PC2 and NC2 controlled by the current control circuit 304 are input to the gates of MP2 and MN2, respectively.

  With the above configuration, the triangular wave O3 is obtained at the output of the inverter 400 as in the circuit for generating the triangular wave O1.

  Modulated wave oscillation circuit 206 outputs triangular waves O1 and O3 from inverters 300 and 400, and outputs digital clock output O2 from RS latch circuit 403. The digital clock output from the RS latch circuit 403 is a digital signal having a period equal to the period of the triangular wave generated from the inverter 400. That is, the modulated wave oscillation circuit 206 is based on the signal CK1 frequency-modulated according to the control signal generated based on the reference voltage and the digital clock signal O2 generated based on the reference voltages (VRH2, VRL2). The output period of the analog modulated wave O3 is controlled so as to be equal to the period corresponding to the signal generated in this way, that is, ICONT.

  Next, a current control circuit 304 as current control means will be described with reference to FIG.

  The current control circuit 304 amplifies the constant current source I1 with a current mirror circuit, and supplies a current that flows to the inverter 300 with the control voltages PC1 and NC1.

  Further, the current control circuit 304 amplifies a current obtained by synthesizing the constant current source I1 and ICONT input from the modulation wave period control circuit 209 with a current mirror circuit, and supplies a current flowing to the inverter 400. As a result, the voltages PC2 and NC2 change according to the amount of input current, and the amount of current flowing through the inverter 400 changes.

  The modulated wave oscillation circuit 206 outputs a triangular wave having a constant period determined by the constant current source I1 and the capacitor C1.

  Further, the modulation wave oscillation circuit 206 can change the output frequency of the triangular wave output from the inverter 400 by changing the amount of current supplied to the inverter 400 according to the amount of current input by the current control circuit 304. It becomes possible. That is, when the amount of current input to the current control circuit 304 of the modulation wave oscillation circuit 206 is small, the output frequency of the triangular wave is low, and when the amount of current input to the current control circuit 304 of the modulation wave oscillation circuit 206 is large. The output frequency of the triangular wave is high.

  Next, the modulation wave period control circuit 209 will be described with reference to FIG.

  The frequency dividing circuit 501 divides the output signal CK1 of the VCO 212 and outputs it to the phase comparator 502 as CK2.

  The phase comparator 502 compares the phase of the output signal CK2 from the frequency dividing circuit 501 with the phase of the digital clock signal O2 from the modulated wave oscillation circuit 206, and outputs a pulse signal corresponding to the compared phase difference to the charge pump 503. To output.

  The comparison result is smoothed by the loop filter 504 and then output to the VI conversion circuit (voltage-current conversion circuit) 505.

  The VI conversion circuit 505 converts the voltage of the smoothed pulse signal input from the loop filter 504 into a current and outputs the current to the modulated wave oscillation circuit 206 as ICONT.

  The modulated wave oscillation circuit 206 generates a triangular wave O1 having a constant period by the constant current source I1 of the current control circuit 304.

  The reference voltage output from the VREF circuit 210 and the triangular wave O1 output from the modulation wave oscillation circuit 206 are added by the adder 211 and input to the VCO 212 as a control signal. The VCO 212 outputs an output signal CK1 that is frequency-modulated according to the input control signal.

  The modulation wave period control circuit 209 uses the signal CK2 obtained by dividing the frequency modulated signal CK1 in the phase comparator 502 as a reference, and the phase of the digital clock signal O2 from the modulation wave oscillation circuit 206 is relative to this CK2. If it is advanced, a negative pulse of the phase difference is output from the charge pump 503. By doing so, the output voltage of the loop filter 504 is lowered, and the output current of the VI conversion circuit 505 is reduced. As a result, the frequency of the analog modulated wave O3 of the modulated wave oscillation circuit 206 is lowered in response to the decrease in current.

  That is, the phase comparator 502 determines that the frequency of the digital clock signal O2 of the modulated wave oscillation circuit 206 is higher than the frequency of the output signal of the frequency divider circuit that divides the output signal of the VCO 212. Control to reduce the conversion current. As a result, the oscillation frequency of the analog modulation signal O3 of the modulation wave oscillation circuit 206 is controlled to be small.

  On the other hand, when the phase of the digital clock signal O2 from the modulation wave oscillation circuit 206 is delayed with respect to the reference signal CK2 in the phase comparator 502, the modulation wave cycle control circuit 209 receives a phase difference from the charge pump 503. The positive pulse is output. In this way, the output voltage of the loop filter 504 is increased, and the output current of the VI conversion circuit 505 is increased. As a result, the frequency of the analog modulated wave O3 of the modulated wave oscillation circuit 206 increases in response to an increase in current.

  That is, the phase comparator 502 determines that the frequency of the digital clock signal O2 of the modulated wave oscillation circuit 206 is lower than the frequency of the output signal of the frequency divider circuit that divides the output signal of the VCO 212. The control current is controlled to increase. As a result, control is performed so that the oscillation frequency of the analog modulation signal O3 of the modulated wave oscillation circuit 206 is increased.

  As described above, the modulation wave period control circuit 209 makes the phase of the digital signal output O2 of the modulation wave oscillation circuit 206 equal to the period of the signal CK2 obtained by dividing the frequency-modulated signal CK1 output from the VCO 212. Make corrections.

  Thereby, the analog modulated wave O3 becomes a frequency-modulated triangular wave. The analog modulated wave is output to the adder 207.

  Next, an output waveform output from the modulated wave oscillation circuit 206 will be described with reference to FIG.

  10A shows the triangular wave O1, FIG. 10B shows the digital clock output O2, FIG. 10C shows the analog modulation wave O3, and FIG. 10D shows the time versus frequency of the digital clock output O2.

  The frequency-modulated triangular wave obtained in this way is output from the VCO 208 as an SSCG clock as a modulation signal.

  As described above, according to the present embodiment, a modulation signal is generated by analog processing capable of widely diffusing the frequency component of the clock from the modulated wave oscillation circuit, and the modulation signal is also frequency-spread with an efficient circuit configuration. By doing so, the modulation frequency can be finely dispersed as compared with the conventional one, and the spectrum component can be further dispersed, so that the reduction rate of the spectrum peak can be increased.

  Next, an SSCG circuit according to a second embodiment of the present invention will be described with reference to FIG.

  In the SSCG circuit described with reference to FIG. 6, the voltage is added in the adder 211 and the adder 207, whereas in the SSCG circuit according to the present embodiment, the current is added.

  Changes from the SSCG circuit described with reference to FIG. 6 will be described below.

  The voltage indicating the comparison result smoothed by the loop filter 205 is converted into a current value by the VI converter 603 and input to the adder 604.

  On the other hand, the analog modulated wave O 3 output from the modulated wave oscillation circuit 206 is converted into a current value by the VI converter 602 and input to the adder 604.

  The adder 604 adds the smoothed pulse signal converted into the current value output from the VI converter 603 and the analog modulated wave converted into the current value output from the VI converter 602. And output to the ICO 605 as a control signal.

  The ICO 605 outputs a clock having a frequency corresponding to the control signal from the adder 604.

  The IREF circuit (reference current generation circuit) 607 outputs the reference current to the adder 608. The adder 608 adds the reference current from the IREF 607 and the triangular wave O1 from the modulation wave oscillation circuit 206 converted into a current value by the VI converter 606, and outputs the result as a control signal to the current control oscillator ICO609.

  The ICO 609 outputs the frequency-modulated output signal CK 1 to the modulation wave period control circuit 209 in accordance with the control signal output from the adder 608.

  As in the first embodiment, an SSCG clock is output from the ICO 605 using a frequency-modulated triangular wave as a modulation signal.

  In the embodiment of the present invention, the modulation signal whose frequency is spread by the modulation generation circuit is generated and used as the modulation signal of the SSCG circuit. By doing so, the modulation frequency can be finely dispersed and the spectrum component can be dispersed. For this reason, it is possible to increase the reduction rate of the peak of the spectrum.

  In the embodiment of the present invention, the output cycle of the modulation generation circuit is controlled so as to be equal to the cycle of the signal generated from the frequency-modulated signal. That is, the period is equal to the signal according to the signal generated based on the signal modulated based on the control signal generated based on the reference voltage and the digital clock signal generated based on the reference voltage. The output cycle was controlled. In this way, the modulation signal can be accurately frequency spread.

  Further, in the embodiment of the present invention, the control means for the output frequency of the modulation generation circuit is provided with an oscillation circuit capable of controlling the oscillation frequency by the amount of current, and the output frequency of the modulation generation circuit is changed by varying this amount of current. I made it spread. That is, the modulation generation means is provided with modulation wave oscillating means whose oscillation frequency can be controlled by the amount of current, and the modulation wave oscillating means varies the current amount so that the output frequency is diffused. By doing so, it is possible to accurately spread the frequency of the modulated signal.

  In the embodiment of the present invention, the modulation generation circuit includes a VREF circuit (reference voltage generation circuit) that generates a reference voltage, a first analog modulation signal having a constant period, and a frequency whose frequency changes according to the amount of current. 2 analog modulation signals, a modulation wave oscillation circuit that outputs a digital clock equal to the period of the second analog modulation signal, and an adder that adds the output of the VREF circuit and the first analog modulation signal of the modulation wave oscillation circuit A voltage controlled oscillator that generates a clock having a frequency according to an output signal from the adder, a signal generated based on the output signal from the voltage controlled oscillator, and a phase of a digital clock from the modulation wave oscillator circuit And the modulation wave period control circuit for outputting the comparison result to the modulation wave oscillation circuit, and the output of the loop filter and the second analog modulation signal from the modulation wave oscillation circuit are added. And to and an adder.

  By adding the output of the VREF circuit and the first analog modulation signal of the modulation wave oscillation circuit, it is possible to generate the frequency-modulated clock CK1, which is the source of the SSCG modulation signal, from the voltage controlled oscillator.

  In the embodiment of the present invention, the modulation wave period control circuit includes a frequency dividing circuit that divides the output signal of the voltage controlled oscillator, an output signal of the frequency dividing circuit, and a digital clock output signal of the modulation wave oscillation circuit. And a phase comparator that outputs an error signal corresponding to the phase difference, a loop filter that smoothes the error signal from the phase comparator, and an output voltage from the loop filter is converted into a current. And a VI conversion circuit for outputting to the modulated wave oscillation circuit.

  With this configuration, it is possible to perform phase comparison between the signal obtained by dividing the frequency-modulated clock CK1 and the digital clock output signal of the modulated wave oscillation circuit.

  Also, in an embodiment of the present invention, the modulation wave period control circuit includes a digital clock of the modulation wave oscillation circuit that is higher than a frequency of the output signal of the frequency divider circuit that divides the output signal of the voltage controlled oscillator in the phase comparator. When the signal frequency is higher, control is performed so that the conversion current of the VI converter circuit is reduced and the oscillation frequency of the second analog modulation signal of the modulation wave oscillation circuit is reduced, and the output signal of the voltage controlled oscillator is When the frequency of the digital clock signal of the modulation wave oscillation circuit is lower than the frequency of the output signal of the frequency division circuit that divides the frequency, the conversion current of the VI conversion circuit is increased, and the second analog of the modulation wave oscillation circuit is increased. Control was made to increase the oscillation frequency of the modulation signal.

  With this configuration, the second analog modulation signal of the modulated wave oscillation circuit can be controlled to be equal to the period of the signal obtained by dividing the frequency-modulated clock CK1.

  In the embodiment of the present invention, the modulated wave oscillation circuit includes a first oscillating unit that oscillates at a constant period, a second oscillating unit whose oscillation frequency can be controlled by an amount of current, and the first oscillating unit. And a current control unit for supplying a constant current to the second oscillation unit and supplying a current corresponding to the input current.

  With this configuration, it is possible to generate the first analog modulation signal that is the source of the modulation signal and the second analog modulation signal that is the SSCG modulation signal from the modulation wave oscillation circuit.

  Further, in an embodiment of the present invention, in the modulated wave oscillating circuit, the first and second oscillating units are configured by a triangular wave generating circuit, and the first analog modulation signal is output from the first oscillating unit, The second analog modulation signal is output from the second oscillation unit, and the digital clock output is output from the output of the latch circuit that generates the triangular wave of the second oscillation unit.

  With this configuration, it is possible to form the second analog modulation signal serving as the SSCG modulation signal with a triangular wave of an analog signal that can spread the frequency component widely.

  In the embodiment of the present invention, the clock generation circuit is constituted by a voltage controlled oscillator. This makes it possible to generate a frequency-modulated clock according to the control voltage from the adder.

  In the embodiment of the present invention, the spread spectrum clock generation circuit includes a reference current generation circuit for generating a reference current, a first analog modulation signal having a constant period, and a current amount according to the modulation generation circuit. A second analog modulation signal whose frequency changes; a modulation wave oscillation circuit which outputs a digital clock signal having a period equal to the period of the second analog modulation signal; and the first analog modulation signal converted into a current value A first VI converter that adds the output of the reference current generation circuit and the output current of the first VI converter to generate a control current, and the control A first current control oscillation circuit that outputs a clock having a frequency according to the current; a signal generated based on an output signal from the first current control oscillation circuit; and a digital clock from the modulation wave oscillation circuit A modulation wave period control circuit that compares the phase with the signal and outputs the comparison result to the modulation wave oscillation circuit; a second VI converter that converts the second analog modulation signal into a current value; A third VI converter for converting the output voltage of the loop filter into a current; a second for adding the output of the second VI converter and the output of the third VI converter; And a second current-controlled oscillator that outputs a clock having a frequency corresponding to the control current from the second adder.

  With this configuration, it is possible to generate a frequency-modulated clock according to the control current from the adder.

  The spread spectrum clock generation circuit according to the present invention can be applied to electronic equipment.

It is a block diagram showing a spread spectrum clock generation circuit. It is explanatory drawing which shows the modulation signal waveform of a spread spectrum clock generation circuit. It is explanatory drawing which shows the spectrum waveform of a clock signal. 1 is a block diagram showing a spread spectrum clock generation circuit according to an embodiment of the present invention. FIG. It is explanatory drawing which shows the modulation signal waveform of the spread spectrum clock generation circuit concerning one Example of this invention. 1 is a block diagram showing a spread spectrum clock generation circuit according to an embodiment of the present invention. FIG. It is a block diagram which shows the modulation wave oscillation circuit concerning one Example of this invention. It is explanatory drawing which shows the current control circuit concerning one Example of this invention. It is a block diagram which shows the modulation wave period control circuit concerning one Example of this invention. It is explanatory drawing which shows the output waveform of the modulation wave oscillation circuit concerning one Example of this invention. 1 is a block diagram showing a spread spectrum clock generation circuit according to an embodiment of the present invention. FIG.

Explanation of symbols

  1 101 201 601 Spread spectrum clock generation circuit

Claims (10)

Phase comparison means for comparing the phase of the reference clock and the feedback clock and outputting an error signal according to the phase difference;
A loop filter for smoothing the error signal;
Modulation generation means for modulating the smoothed error signal to generate a spread spectrum modulation signal;
Clock generating means for generating a clock having a frequency corresponding to the spread spectrum modulation signal;
In a spread spectrum clock generation circuit comprising:
The spread spectrum clock generation circuit, wherein the modulation generation unit generates a modulation signal having a spread frequency. The spread spectrum clock generation circuit according to claim 1,
The modulation generation means has a cycle according to a signal generated based on a signal modulated based on a control signal generated based on a reference voltage and a digital clock signal generated based on the reference voltage. A spread spectrum clock generation circuit, characterized in that the output period is controlled to be equal. The spread spectrum clock generation circuit according to claim 1 or 2,
The modulation generating means includes a modulated wave oscillating means capable of controlling the oscillation frequency by the amount of current,
The spread spectrum clock generation circuit, wherein the modulation wave oscillating means spreads the output frequency by changing the amount of current. The spread spectrum clock generation circuit according to claim 1,
The modulation generating means includes
A reference voltage generating means for generating a reference voltage;
A modulated wave that outputs a first analog modulation signal having a constant period, a second analog modulation signal whose frequency changes according to the amount of current, and a digital clock signal having a period equal to the period of the second analog modulation signal Oscillation means;
First adding means for adding the output of the reference voltage generating means and the first analog modulation signal of the modulated wave oscillating means;
Voltage-controlled oscillation means for generating a clock having a frequency according to an output signal from the first addition means;
Modulated wave period control for comparing the phase of the signal generated based on the output signal from the voltage controlled oscillating means and the digital clock signal from the modulated wave oscillating means and outputting the comparison result to the modulated wave oscillating means Means,
Second addition means for adding the output of the loop filter and the second analog modulation signal from the modulated wave oscillation means;
A spread spectrum clock generation circuit comprising: The spread spectrum clock generation circuit according to claim 4,
The modulated wave period control means includes:
A frequency divider for dividing the output signal of the voltage controlled oscillator;
Phase comparison means for comparing the phase of the output signal of the frequency divider and the digital clock signal and outputting an error signal according to the phase difference;
A loop filter for smoothing the error signal from the phase comparison means;
A spread spectrum clock generation circuit comprising: voltage-current conversion means for converting the smoothed error signal into current. The spread spectrum clock generation circuit according to claim 5,
The phase comparison means includes
When the frequency of the digital clock signal of the modulation wave oscillating means is higher than the frequency of the output signal of the frequency dividing circuit that divides the output signal of the voltage controlled oscillating means, the conversion current of the voltage-current converting means is decreased. Control and
When the frequency of the digital clock signal of the modulation wave oscillating means is lower than the frequency of the output signal of the frequency dividing circuit that divides the output signal of the voltage controlled oscillating means, the conversion current of the voltage-current converting means is increased. A spread spectrum clock generation circuit characterized by controlling as described above. The spread spectrum clock generation circuit according to claim 3,
The modulated wave oscillating means includes:
First oscillation means for oscillating at a constant period;
A second oscillating means whose oscillation frequency can be controlled by the amount of current;
Current control means for supplying a constant current to the first oscillating means and supplying a current corresponding to a constant current and an input current to the second oscillating means;
A spread spectrum clock generation circuit comprising: The spread spectrum clock generation circuit according to claim 7,
The first and second oscillation means comprise a latch circuit and a triangular wave generation circuit,
The first oscillating means outputs the first analog modulation signal;
The spread spectrum clock generation circuit, wherein the second oscillating means outputs the second analog modulation signal, and the latch circuit outputs the digital clock signal. The spread spectrum clock generation circuit according to claim 1,
The spread spectrum clock generation circuit, wherein the clock generation means includes a voltage controlled oscillator. The spread spectrum clock generation circuit according to claim 1,
The modulation generating means includes
A reference current generating means for generating a reference current;
A modulated wave that outputs a first analog modulation signal having a constant period, a second analog modulation signal whose frequency changes according to the amount of current, and a digital clock signal having a period equal to the period of the second analog modulation signal Oscillation means;
First voltage-current conversion means for converting the first analog modulation signal into a current value;
A first adding means for adding the output of the reference current generating means and the output current of the first voltage-current converting means to generate a control current;
First current control oscillation means for outputting a clock having a frequency corresponding to the control current;
Modulation that compares the phase of the signal generated based on the output signal from the first current control oscillation means and the digital clock signal from the modulation wave oscillation means, and outputs the comparison result to the modulation wave oscillation means Wave period control means;
Second voltage-current conversion means for converting the second analog modulation signal into a current value;
Third voltage-current converting means for converting the output voltage of the loop filter into current;
Second addition means for adding the output of the second voltage-current conversion means and the output of the third voltage-current conversion means;
A spread spectrum clock generation circuit comprising: a second current control oscillation unit that outputs a clock having a frequency corresponding to a control current from the second addition unit.

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