JP2007205852A - Semiconductor device and on-resistance measuring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a measuring method which accurately measure the on-resistance at high accuracy without adding a new process even after sealing a semiconductor chip in a package. <P>SOLUTION: A test signal 12 and control signal 13 are inputted a control circuit 3. An output of the control circuit 3 is connected to nodes G1 and G2 in the semiconductor device. The node G1 is connected to a gate of a power transistor 1, and the node G2 is connected to a gate of a monitor transistor 2. The drain of the power transistor 1 and monitor transistor 2 is connected to an external terminal D of the semiconductor device 100, and a source is connected to an external terminal S of the semiconductor device 100. A constant current source 10 is connected between the external terminal D of the semiconductor device 100 and a power supply Vdd, and the external terminal S of the semiconductor device 100 is grounded. A voltmeter 11 is connected between the external terminals D and S. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an on-resistance measuring method, and more particularly, to an on-resistance measuring method for a power transistor built in the semiconductor device, and more particularly to an on-resistance at a rated load current of a power transistor in which many small transistors are connected in parallel. The present invention relates to a configuration of a semiconductor device and a measuring method capable of accurately obtaining resistance.

  Conventionally, a power transistor for controlling a large current is generally manufactured in a separate chip from a large-scale integrated circuit (LSI) because of a different manufacturing process, and is configured to be externally attached to the LSI. However, in response to the demand for miniaturization of devices, recently, power transistors have been built into LSIs. That is, the power transistor built in the LSI generally employs a structure in which a large number of small transistors having the same characteristics are connected in parallel. By doing so, the frequency characteristics and response speed of the power transistor can be improved, and the power transistor can be designed using a small transistor having characteristics almost similar to those of other transistors on the LSI.

  Here, when a large current control power transistor is incorporated in an LSI, the problem is the measurement of the on-resistance of the power transistor. However, since the on-resistance is low, the contact resistance generated when the probe of the measuring device is connected to the external terminal of the semiconductor device cannot be ignored, and an accurate on-resistance cannot be measured.

  The power transistor is used as a drive circuit for lighting an LED lamp or a switching element of a DC-DC converter. Therefore, in order to guarantee the brightness of the LED lamp, it is essential to manage the on-resistance of the power transistor. In addition, in order to perform overcurrent protection of the DC-DC converter, more accurate on-resistance management is required in applications where the current flowing through the switching transistor is detected by the voltage drop of the transistor.

Patent Document 1 discloses a method for accurately measuring the on-resistance of a power transistor in which a large number of small transistors are connected in parallel. According to Patent Document 1, a first MISFET in which a number of MIS transistors are connected in parallel, a transistor cell having the same size as the transistor cell constituting the FET, and a transistor having a sufficiently smaller number of transistors than the first MISFET are connected in parallel. Two MISFETs are formed in the vicinity of the same semiconductor, the on-resistance is measured by the second MISFET at the wafer test stage, the on-resistance of the first MISFET is estimated, and after the on-resistance measurement, the first MISFET and the second MISFET are wire bonded. For example, a technique is disclosed in which the devices are electrically connected by such means as to operate as one FET.
JP 2001-308329 A

  However, the conventional method disclosed in Patent Document 1 requires an electrical connection means such as wire bonding after the on-resistance measurement, and thus a new process is added. Further, if the electrical connection step is omitted and the first and second MISFETs are not connected, the second MISFET is wasted. Furthermore, there is a problem that the on-resistance cannot be measured with high accuracy after the semiconductor chip is sealed in the package.

  In view of such problems, the present invention provides a semiconductor device and a measurement method capable of performing on-resistance measurement with high accuracy even after a semiconductor chip is sealed in a package without adding a new process. Objective.

  In order to solve such a problem, the present invention provides a power transistor configured by connecting a group of transistors having the same characteristics in parallel, and a source or emitter electrode and a drain or collector electrode of the power transistor are externally connected. A monitor transistor in which at least one transistor having the same characteristics as the transistor group is connected in parallel with the power transistor, and a gate of the power transistor and the monitor transistor. Or a control circuit that independently controls the base voltage, and the control circuit is configured to connect the power transistor and an electrode other than the gate or base of the monitor transistor in common, and in the test mode, the power transistor The gate or base voltage is controlled so that the operation of the monitor transistor can be arbitrarily controlled, and the power transistor is enabled in the normal mode, and the monitor transistor is arbitrarily operated. The gate or base voltage is controlled so as to be controllable.

  In the present invention, a monitor transistor is connected in parallel to a power transistor constituted by a plurality of transistor groups. A control circuit capable of individually controlling the gates of the power transistor and the monitor transistor is provided, and in the test mode, control is performed so that the power transistor does not operate, and measurement is performed by the monitor transistor. In the normal mode, both the power transistor and the monitor transistor are operated.

The control circuit includes: a voltage measuring unit that measures a potential between a source or emitter electrode and a drain or collector electrode of the monitor transistor; and a constant current source that supplies a current to the drain or collector electrode. By setting the semiconductor device to the test mode, the potential between the source or emitter electrode of the monitor transistor and the drain or collector electrode is measured by the voltage measuring means, and the power transistor and the monitor transistor are measured based on the measurement result. The combined on-resistance R is estimated.
In order to measure the on-resistance of the monitor transistor, it can be obtained by calculation by passing a constant current through the monitor transistor and measuring the voltage drop between the drain and source at that time. For this purpose, voltage measuring means for measuring the potential between the source or emitter electrode of the monitor transistor and the drain or collector electrode, and a constant current source for supplying current to the drain or collector electrode are provided.

The number of transistors constituting the power transistor is N, the number of transistors constituting the monitor transistor is n, and the on-resistance of the monitor transistor is calculated based on the voltage measured by the voltage measuring unit. Where r is an estimated value of the combined on-resistance Rs of the power transistor and the monitor transistor, Rs = (r × n) / (N + n).
The resistance value connected in parallel is 1 / the number of resistors connected in parallel, assuming that the resistance values are equal. Therefore, the estimated value of the combined on-resistance Rs of the monitor transistor is Rs = (r × n) / where R is the on-resistance of the monitor transistor, N is the number of transistor groups, and n is the number of transistors constituting the monitor transistor. (N + n).

According to a fourth aspect of the present invention, the number of transistor groups constituting the power transistor is N, the number of transistors constituting the monitor transistor is n, and the on-resistance of the monitor transistor calculated based on the voltage measured by the voltage measuring means Where r is an estimated value of the on-resistance R of the power transistor, R = (r × n) / N.
The resistance value connected in parallel is 1 / the number of resistors connected in parallel, assuming that the resistance values are equal. Accordingly, the estimated value of the on-resistance R of the power transistor is R = (r × n) / N, where r is the on-resistance of the monitor transistor, N is the number of transistor groups, and n is the number of transistors constituting the monitor transistor. It can ask for.

5. The voltage measuring means according to claim 5, wherein the on-resistance r of the monitor transistor is a voltage drop generated in the monitor transistor when a current I1 approximately n / (N + n) times a rated load current is passed through the monitor transistor. And when the measurement result is V1, it is obtained by r = V1 / I1.
Assuming that all transistors connected in parallel are equal, the sum of the currents flowing through the transistors is the rated current. Therefore, if a current I1 approximately n / (N + n) times the rated load current is passed through the monitor transistor, the on-resistance r of the monitor transistor is estimated by r = V1 / I1 by measuring the voltage drop at that time. I can do it.

A semiconductor device comprising: a power transistor configured by connecting a group of transistors having the same characteristics in parallel; and a terminal for extracting a source or emitter electrode and a drain or collector electrode of the power transistor to the outside In the device on-resistance measurement method, a monitor transistor in which at least one transistor having the same characteristics as the transistor group is connected in parallel with the power transistor, and a gate or base voltage of the power transistor and the monitor transistor are independent of each other. A control circuit for controlling the power transistor, and when the power transistor and an electrode other than the gate or base of the monitor transistor are connected in common, the control circuit disables the power transistor in a test mode. In addition, the gate or base voltage is controlled so that the operation of the monitor transistor can be arbitrarily controlled, the power transistor can be operated in the normal mode, and the operation of the monitor transistor can be arbitrarily controlled. As described above, the gate or base voltage is controlled.
There exists an effect similar to Claim 1.

7. The control circuit according to claim 7, comprising voltage measuring means for measuring a potential between a source or emitter electrode and a drain or collector electrode of the monitor transistor, and a constant current source for supplying a current to the drain or collector electrode. By setting the semiconductor device to the test mode, the potential between the source or emitter electrode of the monitor transistor and the drain or collector electrode is measured by the voltage measuring means, and the power transistor and the monitor transistor are measured based on the measurement result. The combined on-resistance R is estimated.
There exists an effect similar to Claim 2.

The on-resistance of the monitor transistor calculated on the basis of the voltage measured by the voltage measuring means, wherein the number of the transistor groups constituting the power transistor is N, the number of the transistors constituting the monitor transistor is n, Where r is an estimated value of the combined on-resistance Rs of the power transistor and the monitor transistor, Rs = (r × n) / (N + n).
There exists an effect similar to Claim 3.

9. The monitor transistor on-resistance calculated based on the number of transistors constituting the power transistor, N, the number of transistors constituting the monitor transistor, and the voltage measured by the voltage measuring means Where r is an estimated value of the on-resistance R of the power transistor, R = (r × n) / N.
There exists an effect similar to Claim 4.

10. The voltage measuring unit according to claim 10, wherein the on-resistance r of the monitor transistor is a voltage drop generated in the monitor transistor when a current I1 approximately n / (N + n) times a rated load current is passed through the monitor transistor. And when the measurement result is V1, it is obtained by r = V1 / I1.
The same effect as that of claim 5 is achieved.

  According to the first and sixth aspects of the invention, the control circuit disables the power transistor in the test mode, allows the operation of the monitor transistor to be arbitrarily controlled, and enables the power transistor in the normal mode. At the same time, since the gate or base voltage is controlled so that the operation of the monitor transistor can be arbitrarily controlled, in the test mode, the power transistor is turned off and measurement can be performed with a small current of only the monitor transistor. When the measurement is completed, the monitor transistor can be used effectively by operating both of them.

Further, in the second and seventh aspects, the voltage measuring means and the constant current source are provided, and the control circuit puts the semiconductor device into the test mode so that the potential between the monitor transistor source or emitter electrode and the drain or collector electrode is measured. Since the combined on-resistance R of the power transistor and the monitor transistor is estimated based on the measurement result, the on-resistance can be easily estimated by connecting a simple measuring means to the outside.
In claims 3 and 8, the estimated value of the combined on-resistance Rs is obtained by Rs = (r × n) / (N + n). Therefore, the on-resistance r of the monitor transistor is easily calculated from the measured voltage drop. Can be sought.

Further, in the fourth and ninth aspects, since the estimated value of the on-resistance R of the power transistor is obtained by R = (r × n) / N, the on-resistance r of the monitor transistor is easily calculated from the measured voltage drop. Can be sought.
Further, in claims 5 and 10, the on-resistance r of the monitor transistor is V1 when a voltage drop generated in the monitor transistor when a current I1 approximately n / (N + n) times the rated load current is passed through the monitor transistor is V1. Since it calculates | requires by r = V1 / I1, it can obtain | require easily only by measuring a voltage drop.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 100 is a circuit diagram in the case where the monitor transistor 2 is configured by one small transistor Ms in the configuration of the power transistor 1 and the monitor transistor 2. That is, the semiconductor device 100 includes a small transistor group (M1 to Mn) 1 constituting a power transistor and a small transistor (Ms) 2 constituting a monitor transistor.

The power transistor 1 is composed of NMOS transistors M1 to Mn. The drains, sources and gates of the NMOS transistors M1 to Mn are connected in common. The drain is drawn out from the external terminal D of the semiconductor device. Similarly, the source is pulled out from the external terminal S. The gate is connected to a node G1 inside the semiconductor device, and is connected to a control circuit described later.
The monitor transistor 2 is composed of an NMOS transistor Ms. The drain and source of the NMOS transistor Ms are connected to the drain and source of the power transistor 1, respectively, and the gate is connected to a node G2 inside the semiconductor device and connected to a control circuit described later.
In the present embodiment, the monitor transistor 2 is the one located at the end of the small transistor group, but any transistor in the small transistor group may be used.

  FIG. 2 is a circuit diagram of the configuration of the power transistor and the monitor transistor according to the present invention, wherein the monitor transistor is composed of a plurality of small transistors. 1a to 1c are small transistor groups (M1 to Mn) constituting power transistors, and 2a and 2b are small transistor groups (Ms1, Ms2) constituting monitor transistors. The power transistors 1a to 1c are composed of NMOS transistors M1 to Mn. The drains, sources and gates of the NMOS transistors M1 to Mn are connected in common. The drain is drawn out from the external terminal D of the semiconductor device. Similarly, the source is pulled out from the external terminal S. The gate is connected to a node G1 inside the semiconductor device, and is connected to a control circuit described later.

The monitor transistors 2a and 2b are composed of NMOS transistors Ms1 and Ms2. The monitor transistors Ms1 and Ms2 also have their drains, sources, and gates connected in common, and the drains and sources are connected to the drains and sources of the power transistors 1a to 1c, respectively. The gate is connected to a node G2 inside the semiconductor device, and is connected to a control circuit described later.
The number of monitor transistors 2 may be any number as long as it is sufficiently smaller than the number of power transistors 1. What is important is that the arrangement and number of monitor transistors 2 are selected so that the ratio of the number of power transistors 1 to the number of monitor transistors 2 matches the ratio of the on-resistance of power transistor 1 to the on-resistance of monitor transistor 2 as much as possible. It is to be.

FIG. 3 is a diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram in which a control circuit is added to the transistor shown in FIG. 1. A circuit surrounded by a broken line 3 is a control circuit. A test signal 12 and a control signal 13 are input to the control circuit 3. The output of the control circuit 3 is connected to nodes G1 and G2 in the semiconductor device. The node G1 is connected to the gate of the power transistor 1, and the node G2 is connected to the gate of the monitor transistor 2.
The drains of the power transistor 1 and the monitor transistor 2 are connected to the external terminal D of the semiconductor device 100, and the sources are connected to the external terminal S of the semiconductor device 100.
A constant current source 10 is connected between the external terminal D of the semiconductor device 100 and the power supply Vdd, and the external terminal S of the semiconductor device 100 is grounded. Further, a voltmeter 11 is connected between the external terminals D and S.
The control circuit 3 includes a NOR circuit NOR3a and an inverter INV3b. The test signal 12 is connected to one input of the NOR circuit NOR3a. The control signal 13 is connected to the other input of the NOR circuit NOR3a and the input of the inverter INV3b.

FIG. 4 is a diagram showing the truth value of the operation of the control circuit 3. This will be described with reference to FIG. When the test signal 1212 is high level (H) in each No, the test mode is set. In this state, the output of the NOR circuit NOR3a is always at the low level (L), so that the node G1 is kept at the low level (L) and the power transistor 1 is turned off.
Although the control signal 13 is input to the NOR circuit NOR3a and the inverter INV3b, as described above, the control signal 13 applied to the NOR circuit NOR3a is blocked by the test signal 12, so that the output of the NOR circuit NOR3a is affected. Not give. The signal input to the inverter INV3b is inverted and output to change the level of the node G2. Since the gate of the monitor transistor 2 is connected to the node G2, the monitor transistor 2 is turned on when the control signal 13 is at a low level (L) and turned off when the control signal 13 is at a high level (H).
That is, when the test signal 12 is input, the power transistor 1 is turned off, and the monitor transistor 2 is on / off controlled by the level of the control signal 13.

When the test signal 12 is at a low level (L), the normal mode is set. In this state, since the output of the NOR circuit NOR3a outputs a signal obtained by inverting the level of the control signal 13, the two outputs of the control circuit 3 output the same signal.
That is, when the test signal 12 is not input, the power transistor 1 and the monitor transistor 2 are simultaneously turned on / off by the control signal 13. Thus, in the normal state, the monitor transistor 2 also operates in a state where it is connected in parallel to the power transistor 1, so that the monitor transistor 2 can be used without waste.

When measuring the on-resistance (r) of the monitor transistor 2, the test signal 12 is set to the high level (H) and the control signal 13 is set to the low level (L). That is, the power transistor 1 is turned off and the monitor transistor 2 is turned on.
Since the constant current I1 is supplied from the constant current source 10 to the external terminal D of the semiconductor device 100, this current flows through the monitor transistor 2 to generate a voltage drop V1. This voltage is measured with a voltmeter 11.

The on-resistance (r) of the monitor transistor can be calculated by (Equation 1).
r = V1 / A1 (Equation 1)
The combined on-resistance (R) of the power transistor 1 and the monitor transistor 2 is expressed as follows when the number of small transistors constituting the power transistor 1 is N and the number of small transistors constituting the monitor transistor 2 is n. It can be inferred by calculation according to 2).
R = (r × n) / (N + n) (Formula 2)
The current value I1 when the on-resistance (r) of the monitor transistor 2 is measured is the same ON as the rated load current with a small current obtained by multiplying the rated load current of the combined transistor of the power transistor 1 and the monitor transistor 2 by n / (N + n). Since the resistance can be measured, the measurement error due to the contact resistance between the measurement probe and the semiconductor terminal can be reduced, so that an accurate on-resistance can be measured. Since the combined on-resistance (R) of the power transistor 1 and the monitor transistor 2 is inferred from the accurately measured on-resistance of the monitor transistor, the combined on-resistance is also an accurate value.

FIG. 5 is a diagram showing a second embodiment of the present invention. FIG. 5 is a circuit diagram showing another embodiment in which a control circuit is added to the transistor shown in FIG. 1. A circuit surrounded by a broken line 3 is a control circuit.
A test signal 12 and a control signal 13 are input to the control circuit 3. The output of the control circuit 3 is connected to the nodes G1 and G2 in the semiconductor device 100. The node G1 is connected to the gate of the power transistor 1, and the node G2 is connected to the gate of the monitor transistor 2.
The control circuit 3 includes a NOR circuit NOR3a and an AND circuit AND3c. The test signal 12 is connected to one input of the NOR circuit NOR3a and one input of the AND circuit AND3c. The control signal 13 is connected to the other input of the NOR circuit NOR3a and the other input of the AND circuit AND3c.

  FIG. 6 is a diagram showing the truth value of the operation of the control circuit 3. When the test signal 12 is at a high level (H), it is a test mode. In this state, the output of the NOR circuit NOR3a is always at the low level (L), so that the node G1 is kept at the low level (L) and the power transistor 1 is turned off. Further, since one input of the AND circuit AND3c is set to the high level (H), the gate of the AND circuit AND3c is opened, and the control signal 13 can pass through the AND circuit AND3c.

Although the control signal 13 is also input to the NOR circuit NOR3a and the AND circuit AND3c, as described above, the control signal 13 applied to the NOR circuit NOR3a is blocked by the test signal 12, so that the output of the NOR circuit NOR3a Does not affect. The control signal 13 changes the level of the node G2 through the AND circuit AND3c opened by the test signal 12. Since the gate of the monitor transistor 2 is connected to the node G2, the monitor transistor 2 is turned on when the control signal 13 is at a high level (H) and turned off when the control signal 13 is at a low level (L).
That is, when the test signal 12 is input, the power transistor 1 is turned off, and the monitor transistor 2 is on / off controlled by the level of the control signal 13.

When the test signal 12 is at a low level (L), the normal mode is set. In this state, the output of the NOR circuit NOR3a outputs a signal obtained by inverting the level of the control signal 13. Further, since one input of the AND circuit AND3c is at a low level, the gate is closed and the output of the AND circuit AND3c remains at a low level (L), and the monitor transistor 2 is turned off.
That is, when the test signal 12 is not input, the power transistor 1 is on / off controlled by the control signal 13, but the monitor transistor 2 is turned off.
In this embodiment, the monitor transistor 2 does not contribute to the circuit operation in the normal state, and thus waste occurs. However, if the number of small transistors constituting the monitor transistor 2 is as small as one or two, the power transistor 1 is configured. In view of the fact that the number of small transistors to be reached usually reaches several hundred, it is a waste that can be almost ignored.

When measuring the on-resistance (r) of the monitor transistor 2, the test signal 12 is set to the high level (H) and the control signal 13 is set to the high level (H). That is, the power transistor 1 is turned off and the monitor transistor 2 is turned on.
Since the constant current I1 is supplied from the constant current source 10 to the external terminal D of the semiconductor device 100, this current flows through the monitor transistor 2 to generate a voltage drop V1. This voltage is measured with a voltmeter 11.
The on-resistance (r) of the monitor transistor can be calculated by the above-described (Equation 1).

The on-resistance (R) of the power transistor 1 is calculated by (Equation 3), where N is the number of small transistors constituting the power transistor 1 and n is the number of small transistors constituting the monitor transistor 2. Can be analogized.
R = (r × n) / N (Equation 3)
Since the current value I1 when measuring the on-resistance (r) of the monitor transistor 2 is a small current obtained by multiplying the rated load current of the power transistor 1 by n / N, the same on-resistance as the rated load current can be measured. Since the measurement error due to the contact resistance of the semiconductor terminal can be reduced, accurate on-resistance can be measured. Since the on-resistance (R) of the power transistor 1 is inferred from the on-resistance of the monitor transistor thus accurately measured, the value is accurate.

  In the examples so far, the power transistor 1 and the monitor transistor 2 have been described with respect to NMOS transistors, but the present invention is not limited to NMOS transistors, and the same applies to PMOS transistors, bipolar PNP transistors, and NPN transistors. Needless to say, the method can measure the on-resistance with high accuracy.

It is a circuit diagram of a semiconductor device concerning one embodiment. FIG. 5 is a circuit diagram in the case where the monitor transistor is configured by a plurality of small transistors in the configuration of a power transistor and a monitor transistor. FIG. 2 is a circuit diagram in which a control circuit is added to the transistor shown in FIG. 1 in the first embodiment of the present invention. FIG. 4 is a diagram showing a truth value of the operation of the control circuit 3. FIG. 9 is a circuit diagram showing another embodiment in which a control circuit is added to the transistor shown in FIG. 1 in the second embodiment of the present invention. FIG. 4 is a diagram showing a truth value of the operation of the control circuit 3.

Explanation of symbols

  1 power transistor, 2 monitor transistor, 3 control circuit, 3a NOR circuit NOR, 3b inverter INV, 10 constant current source, 11 voltmeter, 12 test signal, 13 control signal, 100 semiconductor device, D, S external terminal

Claims (10)

In a semiconductor device comprising: a power transistor configured by connecting a group of transistors having the same characteristics in parallel; and a terminal for extracting the source or emitter electrode and the drain or collector electrode of the power transistor to the outside.
A monitor transistor in which at least one transistor having the same characteristics as the transistor group is connected in parallel with the power transistor;
A control circuit for independently controlling the gate or base voltage of the power transistor and the monitor transistor,
The control circuit disables the operation of the power transistor in the test mode and can arbitrarily control the operation of the monitor transistor when the power transistor and an electrode other than the gate or base of the monitor transistor are connected in common. The gate or base voltage is controlled so that the power transistor can be operated in the normal mode, and the gate or base voltage is controlled so that the operation of the monitor transistor can be arbitrarily controlled. A featured semiconductor device. Voltage measuring means for measuring the potential between the source or emitter electrode and the drain or collector electrode of the monitor transistor, and a constant current source for supplying current to the drain or collector electrode,
The control circuit sets the semiconductor device in the test mode so that the potential between the source or emitter electrode and the drain or collector electrode of the monitor transistor is measured by the voltage measuring unit, and the power transistor is based on the measurement result. The semiconductor device according to claim 1, wherein a combined on-resistance R of the monitor transistor is estimated.   When the number of transistor groups constituting the power transistor is N, the number of transistors constituting the monitor transistor is n, and the on-resistance of the monitor transistor calculated based on the voltage measured by the voltage measuring means is r The semiconductor device according to claim 1, wherein an estimated value of a combined on-resistance Rs of the power transistor and the monitor transistor is obtained by Rs = (r × n) / (N + n).   When the number of transistor groups constituting the power transistor is N, the number of transistors constituting the monitor transistor is n, and the on-resistance of the monitor transistor calculated based on the voltage measured by the voltage measuring means is r 3. The semiconductor device according to claim 1, wherein the estimated value of the on-resistance R of the power transistor is obtained by R = (r × n) / N.   The on-resistance r of the monitor transistor is obtained by measuring a voltage drop generated in the monitor transistor when a current I1 approximately n / (N + n) times a rated load current is passed through the monitor transistor by the voltage measuring means, 4. The semiconductor device according to claim 1, wherein the measurement result is obtained by r = V1 / I1 where V1 is V1. On-resistance measurement of a semiconductor device comprising: a power transistor configured by connecting a group of transistors having the same characteristics in parallel; and a terminal for extracting the source or emitter electrode and the drain or collector electrode of the power transistor to the outside In the method
A monitor transistor in which at least one transistor having the same characteristics as the transistor group is connected in parallel with the power transistor;
A control circuit for independently controlling the gate or base voltage of the power transistor and the monitor transistor,
The control circuit disables the operation of the power transistor in the test mode and can arbitrarily control the operation of the monitor transistor when the power transistor and an electrode other than the gate or base of the monitor transistor are connected in common. The gate or base voltage is controlled so that the power transistor can be operated in the normal mode, and the gate or base voltage is controlled so that the operation of the monitor transistor can be arbitrarily controlled. A method for measuring an on-resistance of a semiconductor device. Voltage measuring means for measuring the potential between the source or emitter electrode and the drain or collector electrode of the monitor transistor, and a constant current source for supplying current to the drain or collector electrode,
The control circuit sets the semiconductor device in the test mode so that the potential between the source or emitter electrode and the drain or collector electrode of the monitor transistor is measured by the voltage measuring unit, and the power transistor is based on the measurement result. 7. The method of measuring an on-resistance of a semiconductor device according to claim 6, wherein a combined on-resistance R of the monitor transistor is estimated.   When the number of transistor groups constituting the power transistor is N, the number of transistors constituting the monitor transistor is n, and the on-resistance of the monitor transistor calculated based on the voltage measured by the voltage measuring means is r The on-resistance measurement of a semiconductor device according to claim 6, wherein an estimated value of a combined on-resistance Rs of the power transistor and the monitor transistor is obtained by Rs = (r × n) / (N + n). Method.   When the number of transistor groups constituting the power transistor is N, the number of transistors constituting the monitor transistor is n, and the on-resistance of the monitor transistor calculated based on the voltage measured by the voltage measuring means is r The method for measuring the on-resistance of a semiconductor device according to claim 6, wherein the estimated value of the on-resistance R of the power transistor is obtained by R = (r × n) / N.   The on-resistance r of the monitor transistor is obtained by measuring a voltage drop generated in the monitor transistor when a current I1 approximately n / (N + n) times a rated load current is passed through the monitor transistor by the voltage measuring means, 9. The method of measuring an on-resistance of a semiconductor device according to claim 6, wherein the measurement result is obtained by r = V1 / I1 where V1 is V1.

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