JP2007200357A - Disk control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a disk control device of a module structure allowing almost free extension of channel adaptors and disk adaptors and ensuring high reliability and availability. <P>SOLUTION: The DKC (disk control device) 5 comprises clusters A (40) and B (50) having different AC supply sources. Each cluster can be constituted by a plurality of channel adaptor modules, a plurality of disk adaptor modules, a plurality of switch modules, and one cache module. Each channel adaptor module or disk adaptor module can set a plurality of paths for data transfer with a specific cache module. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a disk subsystem connected to a mainframe host computer, and more particularly to a disk controller having a module structure so that channel adapters and disk adapters can be easily added.

  A disk subsystem connected to a mainframe host computer includes a disk control unit (DKC) and a disk unit (DKU). The disk controller includes a channel adapter that controls data transfer with a host computer via a channel interface, and a disk adapter that controls data transfer with the disk device via a disk interface. In order to obtain higher performance, recent disk control apparatuses have a plurality of channel adapters and a plurality of disk adapters, and a disk subsystem that executes data transfer between the host computer and the disk apparatus in parallel has become mainstream. .

  FIG. 2 is a diagram showing a first configuration example of a conventional disk subsystem. DKC2 and DKU3 each have a power source A (18) and a power source B (28) that supply AC power independently, and a component that receives power from each power source is called a cluster. In this example, the channel adapter 10, disk adapter 11, cache memory 14, and bus arbiters 15, 16 belong to cluster A (17), and channel adapter 20, disk adapter 21, cache memory 24, and bus arbiters 25, 26 belong to cluster B (27). ). It is possible to provide a plurality of channel adapters and a plurality of disk adapters for one cluster. One cache memory for each cluster is shared by the plurality of channel adapters and disk adapters, and temporarily stores data transferred between the host processor 1 and the DKU 3. The DKU 3 includes a plurality of disk drives 30 and is connected to the disk adapters 11 and 21 through disk interfaces. The DKU 3 may have a disk array configuration.

  Each adapter is connected to two sets of common buses 12 and 22, and the cache memories 14 and 24 are accessible from all the adapters. The common bus 12 is supplied with power by a power source A (18) and terminated by a terminator 13. The common bus 22 is supplied with power by a power source B (28) and terminated by a terminator 23. A bus arbiter 15 and a bus arbiter 25 are connected to the common bus 12 and arbitrate the bus access right of the common bus 12. A bus arbiter 16 and a bus arbiter 26 are connected to the common bus 22 and arbitrate the bus access right of the common bus 22. In this configuration example, the bus arbiter is duplicated and provided in the event of one failure. The common bus 12 and the common bus 22 are mounted on one platter (mother board).

  FIG. 3 is a diagram showing a second configuration example of a conventional disk subsystem. The disk subsystem of this configuration example includes a cluster A (17) that is supplied with the power source A (18) and a cluster B (27) that is supplied with the power source B (28). The channel adapter 10, the cache memory 14, and the disk adapter 11 belong to the cluster A (17), and the channel adapter 20, the cache memory 24, and the disk adapter 21 belong to the cluster B (27). As shown in the figure, the cache memories 14 and 24 are connected to both the channel adapters 10 and 20, and are connected to both the disk adapters 11 and 21, respectively. That is, two data transfer paths can be used between the channel adapters 10 and 20 and the disk adapters 11 and 21 via the cache memories 14 and 24.

  In each of the conventional configuration examples described above, each channel adapter, disk adapter, cache memory, and common bus are physically independent, and even if a failure occurs in any module or common bus, the failure site is blocked. Thus, data transfer between the host processor 1 and the DKU 3 can be continued in parallel with failure recovery measures such as component replacement.

  Conventionally, DKC has responded to the demand for higher performance and increased storage capacity of the disk subsystem by increasing the storage capacity of the cache memory and adding adapters. However, in the configuration shown in the first configuration example, the addition of adapters is restricted for the following reason. First, to increase the number of adapters, it is necessary to increase the size of the platter and lengthen the wiring of the common bus in order to secure the adapter mounting area. However, this increases the total wiring length of the bus and transmits bus signals. The characteristics deteriorate and high-speed transmission becomes impossible. Further, since a platter adapted to the maximum configuration is mounted on the disk control device, there is a disadvantage that the floor area of the device becomes large.

  Further, since many adapters are connected on the same bus, the failure rate of the bus increases. In addition, because of the common bus structure, the failure of the connection adapter that is not transferring data is propagated to the adapter that is actually transferring data, so it is very difficult to identify the failed part. In addition, when a plurality of clusters are provided in the disk controller, a module that receives the power supply and a common bus become unusable due to any power failure, and a bus arbiter that arbitrates the bus access right of the common bus. It becomes unusable. For example, since the common bus 22 becomes unusable in addition to the bus arbiters 25 and 26 when the power source B (28) is turned off, the bus arbiter 16 is also unusable.

  In the configuration shown in the second configuration example, in order to increase the number of adapters per cluster, it is necessary to increase the connection line between the channel adapter and the cache memory and the connection line between the disk adapter and the cache memory. The number of signal lines entering the cache memory is increased, and the increase in the number of adapters is limited due to restrictions of LSI pin necks and package connector pin necks. In addition, when one of the power supplies is turned off, only one data transfer path can be used between the channel adapter and the disk adapter. If higher reliability is required, the connection line between the channel adapter and the cache memory and the connection line between the disk adapter and the cache memory must be increased by a factor of two or more. Expansion is limited. Furthermore, since there is a limit to the number of adapters that can be supplied by one power supply, it is necessary to provide a power supply that can supply the power consumption and total current when the maximum configuration is assumed. Limited.

  An object of the present invention is to provide a disk control device with high reliability, availability, and maintainability in which channel adapters and disk adapters can be added almost without limitation.

  The present invention includes a plurality of channel adapter modules that control data transfer with an external channel, a plurality of disk adapter modules that control data transfer with a disk, a cache memory, the channel adapter module, and the At least one cache module accessed from the disk adapter module and connected to the channel adapter module and the disk adapter module by a connection line, and connected to the cache module and between any of the adapter modules and the cache module A disk controller having at least one switch module for setting a transmission path, wherein either one of the channel adapter module and the disk adapter module is a specific cache module; Wherein the disk control apparatus configured capable of setting a plurality of paths for the data transfer between the modules.

  The present invention also provides a plurality of channel adapter modules that control data transfer to and from external channels and each have an independent power source, and a plurality of disk adapter modules that control data transfer to and from the disk and each have an independent power source, A cache module having a cache memory and having an independent power source accessed from the channel adapter module and the disk adapter module, and connected to the channel adapter module and the disk adapter module by a connection line, and connected to the cache module. A set of modules having an AC power supply from an independent AC supply source, each of which has at least one switch module having an independent power source and a transmission path between the adapter module and the cache module. And composed of a plurality of clusters, and wherein the disk control unit having the structure connected by the the said switch modules belonging to one cluster and cache modules belonging to the cache module and other clusters of belonging the cluster connection line.

  As described above, according to the disk control device of the present invention, a plurality of switch modules are interposed and connected between the channel adapter module and the disk adapter module and the cache module, and a plurality of stages of switch modules are interposed. Since it is configured to be connectable, the conventional common bus and pin neck problems can be avoided, and channel adapters and disk adapters can be added almost unlimitedly. At this time, since an independent power supply is provided for each module, the problem of the conventional power supply capability can be avoided. In addition, a failure detection mechanism for checking data to be transferred between modules for each cable assembly between the modules and for each data transfer direction, a mechanism for monitoring the cable connection between the modules, a failed module, and A disk control device with good reliability, availability, and maintainability can be provided by closing a connection line to the module and exchanging parts while continuing to operate other modules.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing the configuration of the DKC 5 of this embodiment. The DKC 5 includes a cluster A (40) and a cluster B (50) that are separated by the AC supply sources 49 and 59. The cluster A (40) includes a channel adapter module 41, a disk adapter module 42, switch modules 43 and 44, and a cache module 45. The cluster B (50) includes a channel adapter module 51, a disk adapter module 52, switch modules 53 and 54, and a cache module 55. The channel adapter module 41 and the switch module 43 of the cluster A (40) are connected to each channel adapter module 41 by a maximum of four cable assemblies 47, and the switch module 43 and the cache module 45 are connected to one cable assembly. 48 is connected. The channel adapter module 41 and the disk adapter module 42 are connected to the switch module 43 and the switch module 44, respectively, and the cache module 45 is connected to the switch modules 43, 44, 53, and 54. The same applies to cluster B (50). Up to four channel adapter modules 41 and 51 and disk adapter modules 42 and 52 can be mounted for each switch module. Each of the switch modules 43, 44, 53, and 54 has a selector on the input side and the output side, and selects one of the eight input lines and two of the output lines to select the channel adapter. A data transfer path is formed with the cache module. Each module has an individual power supply 46 mounted thereon. Since there is no common bus connecting each module, there is no platter, and there is no common power supply between modules, so there are no restrictions on power consumption and total current. 41 and 51 and the disk adapter modules 42 and 52 can be added almost unlimitedly.

  The operation of the DKC 5 when data is transferred from the host processor 1 to the cache memory and double-written to the cache modules 45 and 55 will be described below. The channel adapter module 41 receives the data transferred from the host processor 1, temporarily stores it in the built-in buffer, and issues a transfer request to the switch module 43. The switch module 43 arbitrates transfer requests from other channel adapter modules 41 and disk adapter modules 42. The switch module 43 grants transfer permission to the channel adapter module 41 when data transfer paths are secured between the channel adapter module 41 and the switch module 43, between the switch module 43 and the cache module 45, and between the switch module 43 and the cache module 55. Issue. The channel adapter module 41 immediately transfers data to the switch module 43 via the cable assembly 47. Data can be transferred to the cache module 45 and the cache module 55 without buffering the transfer data inside the switch module 43. When the cache module 45 and the cache module 55 have received all the data to be transferred, the cache module 45 and the cache module 55 send a data transfer end signal to the switch module 43. The switch module 43 terminates the use of the data transfer path for the channel adapter module 41 in accordance with these notifications.

  For example, when the power supply from the AC supply source 59 is stopped, the channel adapter module 51, the disk adapter module 52, the switch modules 53 and 54, and the cache module 55 belonging to the cluster B (50) stop operating. On the other hand, the modules belonging to cluster A (40) receiving power supply from the AC supply source 49 continue to operate in the data read / write mode of only the cache module 45. Even when a failure occurs in the cable assembly 47, the switch module 43, or the cable assembly 48, the channel adapter module 41 can access the cache module 45 via the switch module 44.

  Table 1 shows the number of connection adapters and channel adapters when the cluster is down for the method of the present invention shown in FIG. 1, the first configuration example shown in FIG. 2, and the second configuration example shown in FIG. It is a table | surface which compares the number of paths which can be used between cache memories. As can be seen from this table, the DKC according to the present invention is excellent in the expandability and reliability of the adapter.

  FIG. 4 is a diagram showing the internal configuration of the fault detection and data protection relationship of the channel adapter module 41, the switch module 43, and the cache module 45.

  The switch module 43 includes a selector 61, a selector 62, a failure detector 63, a failure detector 64, and an arbitration unit 68. The same applies to the switch modules 44, 53, and 54. The cache module 45 includes a failure detector 65, a failure detector 66, a data write protection unit 69, and a cache memory 70. The same applies to the cache module 55. The channel adapter module 41 has a failure detector 67. The same applies to the channel adapter module 51 and the disk adapter modules 42 and 52. One cable of the cable assembly 47 accommodates the data line 90 and the control lines 81, 83, 84, 91, 92. The cable assembly 48 accommodates the data line 90 and the control lines 82 and 84. The failure detector 64 is transferred from the channel adapter module 41 to the cache module 45, the failure detector 65 is transferred to the cache module 45, and the failure detector 63 is transferred from the cache module 45 to the channel adapter module 41. The data / failure detector 67 checks the data transferred to the channel adapter module 41. The channel adapter module 41 incorporates a microprocessor and receives a fault interrupt signal detected by the channel adapter module 41 to identify a fault location.

  When the channel adapter module 41 receives data from the host processor 1, it adds a data guarantee code such as horizontal parity and vertical parity to the received data and stores it in the built-in buffer, and sends it to the switch module 43 via the control line 91. Issue a transfer request. The arbitration unit 68 of the switch module 43 issues a transfer permission via the control line 92 when the data transfer path to the cache module 45 is secured. The channel adapter module 41 immediately transfers data to the switch module 43 via the data line 90. The selectors 61 and 62 select the data line 90, and the data passes through the selector 61 and the selector 62 and is transferred to the cache module 45. The data is checked by the failure detector 64 between the selector 61 and the selector 62 for a data guarantee code. The failure detector 65 of the cache module 45 checks the data guarantee code of the transferred data, and if there is no failure, it is written in the cache memory 70.

  When an error occurs in the data transferred from the channel adapter module 41 to the switch module 43 due to the failure of the cable assembly 47, the failure detector 64 checks the data guarantee code of the transferred data to detect the failure, The fault detection is reported to the fault detector 65 of the cache module 45 via the control line 82. The failure detector 65 checks the data guarantee code of the data transferred from the switch module 43, but requests the data write protection unit 69 to inhibit data write regardless of whether or not a failure is detected. The data write protector 69 suppresses writing of data that may have an error.

  For example, when not only the cable assembly 47 but also the cable assembly 48 fails, a multi-bit error exceeding the detection capability of the data guarantee code occurs in the transfer data, and the failure detector 65 cannot detect this error. There is. This failure detection function can prevent erroneous data from being written to the cache memory 70. In this way, the failure detector 64 is provided in the switch module 43, and an error in data transferred from the channel adapter module 41 to the cache module 45 via the cable assembly 47, the switch module 43 and the cable assembly 48 is checked, and the failure is detected. It is important from the aspect of reliability to perform write protection of the data.

  When the channel adapter module 41 accesses the cache module 45 and transfers data, the cache module 45 returns a response to the channel adapter module 41 via the data line 90. When there is no response from the cache module 45 within a predetermined time, the channel adapter module 41 considers that there is no response and sends an interrupt signal to the microprocessor. The failure part that caused the non-response may be the cable assembly 47, the switch module 43, the cable assembly 48, or the cache module 45 on the access path to the cache module 45.

  In the DKC configuration in which the switch module 44 exists, the failure site can be specified by the following procedure. When the microprocessor of the channel adapter module 41 knows no access response by the failure interrupt signal, the failure detector 64 in the switch module 43, the failure detector 65 in the cache module 45, and the failure detection are performed along the path through the switch module 44. The detection information of the detector 63 is collected, and the detection information of the failure detector 67 is obtained. Since the data and the response signal flow in the order of the channel adapter module 41 to the switch module 43, the cache module 45, the switch module 43, and the channel adapter module 41, the failure detection of the data is performed by the failure detector 64, the failure detector 65, The detection is performed in the order of the detector 63 and the failure detector 67. Therefore, it can be seen that the part in front of the detector that first detected the failure is broken.

Further, since the channel adapter module 41 is connected to the failure detector 63, the failure detector 64, and the failure detector 65 by the control line 81 and the control lines 83 and 84, respectively, the DKC configuration or the switch module in which the switch module 44 does not exist. In the case where the failure information of the detector cannot be collected via 44, the failure site can be identified from the failure information obtained from the failure detector 64, the failure detector 65, the failure detector 63, and the failure detector 67.
FIG. 5 is a diagram showing a cable for connecting each module and a mechanism for monitoring the cable connection. The channel adapter module 41 has a connection confirmation unit 101 corresponding to the cable connection with the switch modules 43 and 44. The switch module 43 has a cable enable output unit 102 corresponding to the cable connection with each channel adapter module 41 and the disk adapter module 42. Further, the switch module 43 has a connection confirmation unit 103 corresponding to the cable connection with the cache modules 45 and 55. The cache module 45 has a cable enable output unit 102 corresponding to the cable connection with each switch module 43, 44, 53, 54. The connection confirmation unit 101 includes a configuration information check 113, a signal check 114, and a pull-up resistor 115. The cable enable output unit 102 includes an output driver 111 and a cable enable control 112. The control line 116 is a signal line that connects the connection confirmation unit 101 and the cable enable output unit 102.

  When the power of the switch module 43 is turned on, the cable enable control 112 of the cable enable output unit 102 fixes the cable enable signal on the control line 116 to the LOW level. The connection confirmation unit 101 of the channel adapter module 41 monitors the signal level by the signal check 114. When the cable assembly 47 fails or the connector 20 is disconnected, the cable enable signal is disconnected from the cable enable control 112 of the drive source, and is fixed at the HIGH level by the pull-up resistor 115 of the connection confirmation unit 101. The signal check 114 detects that the signal has become HIGH level and reports it to the configuration information check 113. The configuration information check 113 compares with the LOW data set in advance, detects that the path that should have been connected because it does not match the expected LOW data, and detects in the channel adapter module 41 Report to the failure processing unit 130. The failure processing unit 130 reports a failure to the microprocessor that controls the channel adapter module 41. The microprocessor logically closes the path of the cable assembly 47 in which an abnormality has occurred due to the execution of the control program.

  The connection confirmation unit 103 of the switch module 43 includes a failure processing unit 130 in addition to the configuration information check 113, the signal check 114, and the pull-up resistor 115, and is similar to the cable enable output unit 102 of the cache module 45. Monitor cable connections. When the connection confirmation unit 103 detects the opening of the cable assembly 48, it reports a failure to the microprocessor of the channel adapter module 41. The channel adapter module 41 logically blocks the path of the cable assembly 48 where the fault has occurred.

  Similar cable connection monitoring is possible even if the cable enable output unit 102 is provided in the switch module 43 and the opposing connection confirmation unit 103 is provided in the cache module 45.

  The DKC 5 always performs the above-described cable connection monitoring while the apparatus is operating, and prevents failures that occur during data transfer and data corruption due to failures.

  The DKC 5 can take many configuration patterns from a small-scale configuration to a large-scale configuration depending on the number of installed modules and combinations thereof. Therefore, a table for managing the device configuration is provided in DKC5, the paths between installed modules are set, and the connection status of each path is checked when the device is turned on after DKC5 is powered on. By doing so, it can be checked whether or not the operating device configuration matches the configuration set in the configuration management table.

  FIG. 6 is a diagram showing another configuration of the DKC 5, and is a configuration diagram when modules are further added to the configuration shown in FIG. In this example, four channel adapter modules 151, four disk adapter modules 152, and switch modules 153 and 154 are added to the DKC 5 shown in FIG. The extension procedure is described below.

  The channel adapter module 51 and the disk adapter module 52 of the cluster B (50) access the cache module 45 and the cache module 55 via the switch module 53 and the switch module 54. First, the channel adapter module 151, the disk adapter module 152, the switch module 153, and the switch module 154 to be added are mounted on the DKC6 device, the added modules are connected by the cable assembly 47, and the individual power supply of each module is turned on. . The microprocessor in the added module waits until a path diagnosis request is received from the already operating module.

  The switch module 53 is connected to the channel adapter module 51, the disk adapter module 52, the cache module 45, and the cache module 55 that can use the switch module 53 in accordance with instructions from the microprocessor in the channel adapter module 51 or the disk adapter module 52. A logical block instruction is issued, and access to the cache modules 45 and 55 via the switch module 53 is prohibited. With this logical block instruction, each module inhibits the function of the connection confirmation mechanism that monitors the cable connection with the switch module 53, and inhibits the function of the failure detection mechanism that checks the transfer data. Next, the connector on the switch module 53 side of the cable assembly between the switch module 53 and the cache module 45 is pulled out and connected to the switch module 153 to be added. Similarly, the connector on the switch module 53 side of the cable assembly between the switch module 53 and the cache module 55 is pulled out and connected to the switch module 154 to be added. The switch module 53 and the switch module 153 are connected to each other, and the switch module 53 and the switch module 154 are connected to each other by a cable assembly. As a result, the channel adapter module 51 and the disk adapter module 52 form physical paths to the cache module 45 and the cache module 55 via the switch module 53, the switch module 153, and the switch module 154. The microprocessor of the channel adapter module 51 or the disk adapter module 52 diagnoses the added path, confirms that the path is logically connected, and then opens the path to the other channel adapter module 51, the disk adapter. The module 52, the switch module 53, the switch module 153, the switch module 154, the cache module 45, and the cache module 55 are notified, and the cache modules 45 and 55 can be accessed via the added path. In the same procedure, the switch module 54 is closed, the cable is replaced, and the cable is added to perform physical path addition and path diagnosis. The above expansion processing and expansion work can be performed while continuing access to the cache modules 45 and 55.

  The above embodiment was accompanied by the addition of the channel adapter module 151 and the disk adapter module 152, but is also applied to the path diagnosis after the blockage, replacement, and recovery of the failed module and the connected cable assembly, A series of processes and operations can be executed while continuing to access the cache module. The present invention is also applied to failure recovery when the cluster operation is stopped when the AC power supply system is stopped.

  FIG. 7 is a diagram illustrating another configuration of the DKC 5. The system is composed of DKC5-1 and DKC5-2, which are independent disk control devices, and these device housings are connected by a cable assembly 200. The switch modules 53 and 54 in the cluster B (50) of the DKC 5-1 are connected to the cache module 55 in the cluster B (50) of the DKC 5-2. Further, the switch modules 53 and 54 in the cluster B (50) of the DKC5-2 are connected to the cache module 55 in the cluster B (50) of the DKC5-1. With this configuration, the channel adapter module 51 and the disk adapter module 52 of the DKC 5-2 and the channel adapter module 51 and the disk adapter module 52 of the DKC 5-1 can access the cache module 55 of different devices. The advantage of this configuration is that when one of the DKCs 5-1 and 5-2 is stopped, the operation can be continued by the other DKC, and the AC of the cluster A (40) of the DKC5-1 and the cluster A (40) of the DKC5-2. Even if the supply is stopped, the operation can be continued by the cluster B (50) of the DKC5-1 and the cluster B (50) of the DKC5-2. Further, the switch modules 43 and 44 of the cluster A (40) of the DKC5-1 are connected to the cache module 45 of the cluster A (40) of the DKC5-2, and the switch modules 43 and 44 of the cluster A (40) of the DKC5-2 are connected. And the cache module 45 of the cluster A (40) of the DKC 5-1 can be connected to each other.

It is a figure which shows the structure of the disk control apparatus of embodiment. It is a figure which shows the 1st structural example of the conventional disk subsystem. It is a figure which shows the 2nd structural example of the conventional disk subsystem. It is a figure which shows the internal structure of the apparatus regarding the failure detection relationship of embodiment. It is a figure which shows the structure of the mechanism which monitors the cable connection of embodiment. It is a block diagram of the other disk control apparatus of an embodiment, and is a figure which shows the mode of module addition. It is a figure which shows the structure of the further another disk control apparatus of embodiment.

Explanation of symbols

5: DKC, 40: cluster A, 50: cluster B, 41, 51: channel adapter module, 42, 52: disk adapter module, 43, 44,
53, 54: Switch module, 45, 55: Cache module, 47, 48: Cable assembly

Claims (5)

A plurality of channel adapter modules for controlling data transfer to and from an external channel; a plurality of disk adapter modules for controlling data transfer to and from a disk; and a cache memory having the channel adapter module and the disk adapter module At least one cache module to be accessed is connected to the channel adapter module and the disk adapter module by a connection line, and connected to the cache module to set a transmission path between any adapter module and the cache module A plurality of switch modules,
One of the channel adapter module and the disk adapter module is configured to be capable of setting a plurality of paths for data transfer with a specific cache module. A plurality of channel adapter modules that control data transfer to and from the external channel and each have an independent power supply, a plurality of disk adapter modules that control data transfer to and from the disk and each have an independent power supply, and a cache memory A cache module that is accessed from the channel adapter module and the disk adapter module and has an independent power source; and is connected to the channel adapter module and the disk adapter module by a connection line; A plurality of switch modules each having an independent power supply and setting a transmission path to the cache module;
A set of modules that receive AC supply from independent AC supply sources is composed of a plurality of clusters as one cluster, and the switch module belonging to one cluster, the cache module in the cluster to which it belongs, and the cache module belonging to another cluster A disk control device having a configuration connected by a connection line.   A first failure detector for detecting an error in data transferred from one of the channel adapter module and the disk adapter module to the switch module in the switch module, and transferred from the cache module to the switch module A second fault detector for detecting an error in the data, and a third fault detector for detecting an error in the data transferred from the switch module to the cache module in the cache module. One of the module and the disk adapter module is provided with a fourth fault detector for detecting an error in data transferred from the switch module to one of the channel adapter module and the disk adapter module. Claim 1 or claim 2 Disk controller.   A mechanism for outputting a first signal for confirming cable connection is provided in the switch module, and a mechanism for detecting the first signal in one of the channel adapter module and the disk adapter module via a connection line. A mechanism for outputting a second signal for confirming the cable connection is provided to one of the cache module and the switch module, and the second signal is provided to the other of the cache module and the switch module via a connection line. 3. The disk control device according to claim 1, further comprising a detection mechanism.   When a module to be blocked occurs in the disk controller, issue a block command for the module from one of the channel adapter module and the disk adapter module to all other modules connected to the module through a connection line; 3. The disk control apparatus according to claim 1, wherein the module and a transmission path from the module to another module are closed.

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