JP2007189672A - Channel estimation apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an accurate channel estimate in a channel estimation apparatus for acquiring the channel estimate which is used for compensation of a target signal to be compensated based on a signal for channel estimation. <P>SOLUTION: A first acquisition means acquires the channel estimate for each slot based on the signal for channel estimation. Second acquisition means 41-47 acquires an amount of compensation for frequency drift with finer resolution than the slot size based on the signal for channel estimation. The third acquisition means 48 combines the channel estimate for each slot obtained by the first acquisition means and the amount of compensation for frequency drift acquired by the second acquisition means to acquire the channel estimate to compensate both of them. The channel estimate acquired by the third acquisition means is used for compensation of the target signal to be compensated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a channel estimation apparatus for receiving and demodulating modulated signals having in-phase and quadrature components, and in particular, channel estimation suitable for a direct sequence code division multiple access (DS-CDMA) system. Relates to the device.

For example, in a base station apparatus of a mobile communication system employing a W (Wideband) -CDMA scheme, various schemes for obtaining a channel estimation amount of an uplink baseband signal for uplink signals received from the mobile station apparatus have been proposed. .
FIG. 6 shows a configuration example of a channel estimation circuit provided in the baseband signal processing unit of the base station apparatus.
6, (a) shows the slot number in the frame, (b) shows the symbol number in each slot, and (c) shows the UL (Up-Link) DPCCH (individual uplink). 4 shows a configuration example of IQ data after despreading for (physical control channel), and (d) shows a configuration example of IQ data to be despread for UL DPDCH (dedicated uplink physical data channel).

An example of the operation performed in the channel estimation circuit of this example is shown.
For the (n−1) th slot (Slot # n−1), a pilot symbol (Pilot Symbol) in the UL-DPCCH after despreading obtained from the received signal and a known reference referenced from the reference pilot table 51 The pilot symbol (reference pilot symbol) is complex-multiplied by the complex multiplier 52, and the phase rotation amount (symbol phase rotation amount) for each pilot symbol is calculated. The adder 53 accumulates the symbol phase rotation amount in one slot. The accumulated result is divided by the number of symbols accumulated by the averaging unit 54 (5 in this example) and averaged to obtain the slot average phase rotation amount, so that the accumulated result is despread. The same gain as the UL-DPCCH signal. The slot average phase rotation amount and the weighting coefficient W (n−1) are multiplied by the multiplication unit 55.

The same processing is performed on the nth slot (Slot # n) by the processing units 51a to 55a similar to the case of the (n-1) th slot.
Further, the same processing is performed on the (n + 1) th slot (Slot # n + 1) by the same processing units 51b to 55b as in the (n-1) th slot.
Here, the pattern of the reference pilot symbols and the weighting factors W (n−1), W (n), and W (n + 1) are usually constant in each slot, but may be different.

  The multiplication result for the (n−1) th slot is delayed by one slot time by the delay unit 56 and added by the addition unit 57 with the multiplication result for the nth slot. The addition result is delayed by one slot time by the delay unit 58 and added to the multiplication result for the (n + 1) th slot by the addition unit 59. That is, it functions as a 3-tap FIR (Finite Impulse Response) filter that performs weighted addition of the average phase rotation amount for three slots.

The result of addition by the adding unit 59 is normalized by the averaging unit 60 or averaged (divided by the number of added slots and the like) to obtain a channel estimation amount, whereby the UL-DPCCH signal after despreading is obtained. The gain is not changed by the slot format.
Then, the channel estimation amount obtained based on the UL-DPCCH is complex-multiplied with the IQ data after despreading of the UL-DPDCH to compensate for the phase rotation generated in the UL-DPDCH.
Thus, in order to obtain the UL-DPDCH channel estimation amount, in addition to the slot average phase rotation amount obtained using the pilot symbol of the corresponding slot, the slot average phase rotation amount for each of the front and rear slots is necessary. become.

  Depending on the difference in uplink slot format, the symbol position and number of pilot, TFCI (Transport Format Combination Indicator), FBI (FeedBack Infomation, indicated as F in the figure), and TPC (Transmission Power Control) are different. In the configuration for obtaining the channel estimator using the FIR filter, weighting coefficients W (n−1), W (n), and W (n + 1) corresponding to the slot format are set in order to achieve uniform error distribution in the slot. There is a need to.

Japanese Patent No. 3497480 JP-T-2004-538720 Japanese Patent No. 3727455

However, the channel estimation circuit as described above has the following problems.
First, since the UL-DPDCH channel estimation amount is maintained only for the slot period, there is a serious problem (problem 1) that reception quality deteriorates due to frequency drift.
In addition, for both UL-DPCCH and UL-DPDCH, despreading is calculated with a symbol period, whereas channel estimation is calculated with a slot period, so that variations in reception quality occur due to setting of chip offset (ChipOffset). There was a problem (Problem 2).

Here, the uplink dedicated channel is multiplexed by distributing the reception timing by the chip offset for each user. That is, interference between users is reduced by chip offset.
Further, when a plurality of user signals are processed in parallel in the base station apparatus, it is easier to perform the batch processing by matching the positions of the pilot symbols for all user signals (that is, absorbing the offset in the slot). At this time, if the UL-DPDCH despread symbol and the channel estimation amount calculated in the slot period are simply matched at each slot timing (without making the chip offset in-phase), a maximum one-slot shift will occur. As a result, the reception characteristic is dependent on chip offset.

The present invention has been made in view of such a conventional situation, and an object of the present invention is to provide a channel estimation device capable of obtaining an accurate channel estimation amount.
Specifically, in the present invention, an accurate channel estimation amount is obtained by compensating for a frequency drift or compensating for a chip offset.

In order to achieve the above object, a channel estimation apparatus according to the present invention acquires a channel estimation amount used for compensation of a signal to be compensated based on a channel estimation signal with the following configuration.
That is, the first acquisition unit acquires a channel estimation amount for each slot based on the channel estimation signal. A second acquisition unit acquires a compensation amount of the frequency drift with a resolution finer than the slot based on the channel estimation signal. A channel in which the third acquisition unit combines the channel estimation amount for each slot acquired by the first acquisition unit and the compensation amount of the frequency drift acquired by the second acquisition unit, and compensates for both. Get an estimate. The channel estimation amount acquired by the third acquisition unit is used for compensation of the signal to be compensated.

  Therefore, a channel estimation amount that compensates for both the channel estimation amount for each slot and the frequency drift compensation amount with finer resolution than the slot is acquired based on the signal for channel estimation, and the signal to be compensated is obtained. Since it can be used for compensation, it is possible to obtain an accurate channel estimation amount by compensating for the frequency drift, and thus it is possible to accurately compensate for the phase rotation of the signal to be compensated.

Here, various signals may be used as the channel estimation signal and the signal to be compensated, respectively.
As the channel estimation amount, for example, a phase rotation amount corresponding to the reverse rotation of the phase rotation generated in the signal to be compensated is used.
Further, as the channel estimation amount for each slot, for example, a channel estimation amount having a resolution of 1 slot is used.
In addition, various resolutions finer than one slot may be used as the resolution of the frequency drift compensation amount. Usually, the finer the resolution, the higher the accuracy and the greater the processing load. It is preferable that a resolution that is effective above is set.

The channel estimation apparatus according to the present invention has the following configuration as one configuration example.
That is, the channel estimation apparatus is provided in a base station apparatus that communicates wirelessly with a plurality of mobile station apparatuses by the CDMA method. The channel estimation signal is a UL-DPCCH signal wirelessly transmitted from the mobile station apparatus to the base station apparatus, and the signal to be compensated is wirelessly transmitted from the mobile station apparatus to the base station apparatus. These are UL-DPDCH signals, and for these signals, chip offsets for shifting the radio transmission timing are set for each mobile station apparatus.
In addition, the first acquisition unit provided in the channel estimation apparatus includes a fourth acquisition unit, a weighting unit, and a first averaging unit.
The fourth acquisition means delays the channel estimation signals received from the respective mobile station apparatuses by a time corresponding to each of the plurality of mobile station apparatuses so that the timing shift in the slot due to the chip offset is adjusted for a plurality of mobile station apparatuses. In parallel, the average phase rotation amount for each slot is acquired. The weighting means gives the weight for each slot determined based on the chip offset set for each mobile station apparatus to the average phase rotation amount for each slot acquired by the fourth acquisition means. The first averaging means averages the average phase rotation amount for each slot weighted by the weighting means for a plurality of slots around the slot to be channel estimated.
Then, the first acquisition unit acquires the averaged result by the first averaging unit as the channel estimation amount of the slot to be channel estimation target.

  Therefore, chip offsets are set for signals for channel estimation and signals to be compensated transmitted from a plurality of mobile station apparatuses (users) to the base station apparatus, and are received from the plurality of mobile station apparatuses in the base station apparatus. Even when the average phase rotation amount for each slot is obtained by aligning timing deviations due to chip offsets for the channel estimation signals, the amount of time offset is used to align the channel estimation signals. The weight for each slot is determined, the average phase rotation amount for each slot is weighted, and the average phase rotation amount for each slot after weighting is averaged for a plurality of slots to estimate the channel for each slot. Therefore, it is possible to obtain a precise channel estimator by compensating for the chip offset. , Thereby, the phase rotation compensation subject to signal can be accurately compensated.

Here, various numbers may be used as the number of the plurality of mobile station devices to be processed in parallel by the base station device.
Various modes may be used as the chip offset.
Various modes may be used as the weighting mode for each slot, for example, based on the amount of time for delaying the channel estimation signal received from each mobile station apparatus according to the chip offset. A mode is used in which weighting is performed for each slot so as to improve the accuracy of the channel estimation amount finally obtained.
Moreover, as a method of giving weighting, for example, a method of multiplying by a weighting coefficient is used.

Further, as the average phase rotation amount for each slot, for example, a value obtained by averaging phase rotation amounts for symbols included in the slot or symbols outside the slot is used for each slot.
In addition, various modes may be used as a mode for averaging the average phase rotation amount for each slot to which weighting is given with respect to a plurality of slots around the slot to be channel estimation target. A mode in which the average phase rotation amount of the slots to be estimated and the average phase rotation amount of the slots before and after the slot can be used can be used.

The channel estimation apparatus according to the present invention has the following configuration as one configuration example.
That is, the channel estimation signal includes pilot symbols and other symbols.
The first acquisition unit provided in the channel estimation apparatus includes a fifth acquisition unit, a sixth acquisition unit, and a second averaging unit.
The fifth acquisition means acquires a phase rotation amount based on a pilot symbol included in the channel estimation signal. The sixth acquisition means acquires the phase rotation amount based on symbols other than the pilot symbols included in the channel estimation signal. The second averaging means averages the phase rotation amount acquired by the fifth acquisition means and the phase rotation amount acquired by the sixth acquisition means.
Then, the first acquisition unit acquires an averaged result by the second averaging unit as an average phase rotation amount for each slot.

  Therefore, since the average phase rotation amount for each slot is obtained using not only the pilot symbols included in the channel estimation signal but also symbols other than the pilot symbols, for example, the average for each slot using only the pilot symbols is obtained. Compared with the case where the amount of phase rotation is acquired, a more accurate channel estimation amount can be obtained, and thus the phase rotation of the signal to be compensated can be accurately compensated.

Here, various configurations may be used as the configuration of the channel estimation signal. For example, a configuration including a pilot symbol, a TFCI symbol, an FBI symbol, and a TPC symbol can be used.
Further, as symbols other than the pilot symbol used for acquiring the phase rotation amount, one or more kinds of various symbols may be used. For example, one or both of a TFCI symbol and a TPC symbol can be used.

The channel estimation apparatus according to the present invention has the following configuration as one configuration example.
That is, in a channel estimation device that calculates a channel estimation amount used for compensation of a reception signal to be compensated based on a channel estimation signal included in the reception signal,
A reference pilot table storing a reference of the channel estimation signal;
For each symbol of the channel estimation signal, a pilot in-phase unit that outputs a value indicating a phase rotation of the received channel estimation signal with reference to the reference pilot table;
An fD estimation unit that estimates a fading frequency based on a value indicating the phase rotation;
An IIR filter that outputs a corresponding channel estimation value with a processing delay time within one symbol from an input immediately before the value indicating the phase rotation, based on the value indicating the phase rotation;
A filter control unit that controls a filter parameter of the IIR filter based on the estimated fading frequency.
In addition, the filter control unit controls the filter parameters so that the phase delay of the IIR filter is substantially constant at the estimated fading frequency.

As described above, according to the channel estimation device according to the present invention, the channel estimation amount including the frequency drift compensation amount having a resolution finer than one slot is acquired based on the channel estimation signal. By compensating for the frequency drift, the phase rotation of the signal to be compensated can be accurately compensated.
In addition, according to the channel estimation apparatus of the present invention, since the average phase rotation amount for each slot is obtained using symbols other than the pilot symbols included in the channel estimation signal, the average phase rotation for each slot is obtained. The effect of averaging when acquiring the quantity can be enhanced, and the phase rotation of the signal to be compensated can be accurately compensated.

  Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 show a configuration example of a circuit (channel estimation circuit) constituting the channel estimation apparatus according to Embodiment 1 of the present invention. 1 and 2 are divided into two parts for convenience of illustration, but they are integrated.
1A shows a slot number (Slot No.) in a frame used for communication, and FIG. 1B shows a symbol number corresponding to SF (spreading factor) = 256 in each slot. (C) shows a configuration example of IQ data after despreading for UL-DPCCH (dedicated uplink physical control channel), and in FIG. 2, (d) shows UL-DPDCH (dedicated). 4 shows a configuration example of IQ data after despreading (uplink physical data channel).
The IQ data represents I data and Q data of a complex signal. The I data is in-phase component data, and the Q data is quadrature component data.

In this example, one frame is composed of 15 slots (Slot # 0 to 14), and one slot is composed of 10 symbols (0 to 9). Is composed of 256 chips. For example, a plurality of frames are continuously communicated.
Also, in this example, the despread IQ data for one slot of UL-DPCCH is a pilot symbol which is known information on the transmitting side and the receiving side, and TFCI for notifying the transmission format pattern. (TransportFormat Combination Indicator) symbol, feedback information FBI (Feedback Informtion) symbol, and TPC (Transmit Power Control) symbol that is information for performing transmission power control. The pilot symbol is composed of five consecutive symbols (0 to 4), the TFCI symbol is composed of two consecutive symbols (5, 6), and the FBI symbol is one symbol (7). The TPC symbol is composed of two consecutive symbols (8, 9).
Moreover, in this example, the despread IQ data of UL-DPDCH is configured to include user data symbols.

The channel estimation circuit of this example is provided in a baseband signal processing unit of a base station apparatus in a mobile communication system adopting a DS-CDMA system.
The base station apparatus of this example communicates wirelessly with a mobile station apparatus (user), and receives a UL-DPCCH signal or a UL-DPDCH signal wirelessly transmitted from the mobile station apparatus. The channel estimation circuit of this example processes the data after these signals are despread, and can be applied in each finger (for example, a delay lock loop) during Rake synthesis.

In this example, the DPCH (uplink dedicated physical channel) is composed of UL-DPCCH transmitted in the Q phase (orthogonal phase) and UL-DPDCH transmitted in the I phase (in-phase), and the mutual correlation is ignored. It is assumed that the signal is spread with a possible spreading code and orthogonally modulated. In the case of DPCH, the modulation signal is a kind of QPSK (Quadrature Phase Shift Keying) and has phase information. For this reason, the receiving side performs quadrature detection on the modulated signal, projects the UL-DPCCH received signal onto the Q phase and makes a hard decision on the Q phase, and projects the UL-DPDCH received signal onto the I phase to perform the I phase. Make a hard decision.
Further, in the channel estimation circuit of this example, DPCH is a processing target, and in order to obtain one channel estimation amount, only the same signal (including fingers) from the same user is processed, and the channel obtained by DPCH The estimated amount is used only for the DPCH. (For example, even for the same user, the channel estimation amount is obtained by a method suitable for the channel format and the like for each individual channel without diverting it to the uplink random access channel (PRACH) which is another channel.) Since the signal input to the channel estimation circuit of the example and processed is the signal after despreading, the input signal is separated for each user. Further, when supporting multi-users, parallel processing is possible if the slot format of the uplink DPCCH is the same, but it may be processed serially in time series assuming different cases.

The channel estimation circuit of this example includes a reference pilot table 1, a complex multiplication unit 2, and a processing unit for obtaining an average phase rotation amount corresponding to the (n-1) th slot (Slot # n-1). Adder 3, complex multiplier 4, RAKE combiner 5, TFCI hard determiner 6, complex multiplier 7, complex multiplier 8, RAKE combiner 9, TPC hard determiner 10, complex A multiplication unit 11, an addition unit 12, an addition unit 13, and an averaging unit 14 are provided.
The average phase rotation amount corresponding to the nth slot (Slot # n) and the (n + 1) th slot (Slot # n + 1) is also obtained by the same processing means. That is, the averaging unit 14 from the reference pilot table 1 repeatedly operates in the slot period, so that the nth slot (from the (n-1) th and nth slot DPCCHs) as described later for an arbitrary n ( The average phase rotation amount corresponding to Slot # n) is obtained.

In addition, the channel estimation circuit of this example is a processing unit for performing weighting control, a weighting control unit 21, a multiplication unit 22 corresponding to the (n−1) th slot, and a multiplication corresponding to the nth slot. A multiplier 22b corresponding to the (n + 1) th slot.
Further, the channel estimation circuit of this example includes a delay unit 23, an adder unit 24, a delay unit 25, and a processing unit for averaging the average phase rotation amount for a plurality of (three in this example) slots. , An adding unit 26 and an averaging unit 27 are provided.

Further, the channel estimation circuit of this example includes a frequency drift compensation unit 31 as a processing unit for compensating for the frequency drift.
The frequency drift compensation unit 31 includes a frequency drift detection unit 41, a frame interval averaging unit 42, a RAKE combining unit 43, an exponential weighted averaging unit 44, a tangent calculation unit 45, and a normal for compensating for frequency drift. A conversion table 46, a table conversion unit 47, and a complex multiplication unit 48.

Here, in this example, the channel estimation amount indicates a phase compensation amount for returning the phase rotation obtained from the result of estimating the phase rotation. For this reason, when the UL-DPDCH despread IQ data is complex multiplied by the channel estimation amount, the phase rotation generated in the UL-DPDCH despread IQ data is compensated. Note that the UL-DPCCH slot used for detecting the channel estimation amount and the UL-DPDCH slot that compensates for phase rotation (reverse rotation) by complex multiplication of the channel estimation amount have the same timing. It is.
The frequency drift indicates that the phase rotates with the flow of time (symbol flow).

An example of the operation performed in the channel estimation circuit of this example is shown.
First, an operation for obtaining the average phase rotation amount for the (n−1) th slot will be described.
The reference pilot table 1 stores, for example, a pattern of referenced pilot symbols (reference pilot symbols) in a memory.
The complex multiplier 2 has, for example, five complex multipliers corresponding to the symbols constituting the pilot symbols, and for each symbol, the pilot in the UL-DPCCH after despreading obtained from the received signal The symbol is multiplied by a known pilot symbol referenced from the reference pilot table 1 to calculate a phase rotation amount (symbol phase rotation amount) for each symbol, and the five symbol phase rotation amounts are added. Output to part 3.
The adding unit 3 adds the five symbol phase rotation amounts that have been in-phased to accumulate the symbol phase rotation amount in the pilot, and outputs the addition result to the adding unit 13.
This process is a process for calculating a phase rotation amount using a known pilot symbol, and in this example, the phase rotation amount obtained in this process is referred to as a pilot symbol phase rotation amount.

  In this example, in order to obtain the average phase rotation amount for the (n-1) th slot (Slot # n-1), the hard decision symbol has already been determined at that time (n-2) th slot ( The TFCI symbol and TPC symbol of Slot # n-2) are also used. In this example, the TFCI symbol consists of two symbols, the TPC symbol consists of two symbols, and processing is performed for each of these four symbols.

The complex multiplier 4 includes, for example, two complex multipliers corresponding to the symbols constituting the TFCI symbol, and for each TFCI symbol in the (n-2) th slot (Slot # n-2), The pilot symbol phase rotation amount of Slot # n-2 calculated using the pilot section of the slot is extrapolated backward to compensate for phase rotation, and the TFCI symbol projected onto the orthogonal axis is output to the RAKE combining unit 5 .
Similarly, the complex multiplier 8 has, for example, two complex multipliers corresponding to the symbols constituting the TPC symbol, and each TPC in the (n-2) th slot (Slot # n-2). The symbol is also subjected to extrapolation detection with the pilot symbol phase rotation amount of Slot # n-2, and the TPC symbol projected onto the orthogonal axis is output to the RAKE combining unit 9.
Alternatively, when processing the TFCI symbol and TPC symbol of the (n-2) th slot, not only the pilot symbol of the slot but also the average phase rotation amount used for phase rotation compensation before the hard decision (n-3) The slot average phase rotation amount of Slot # n-2 calculated using the TFCI symbol and the TPC symbol of the second slot can be used. In any case, these detections (demodulations) are extrapolation detections because the amount of phase rotation only in the forward direction is used.

The RAKE combining unit 5 inputs a TFCI symbol projected onto the orthogonal axis from each of the two symbols constituting the TFCI symbol, and is provided in each of the other fingers (not shown). The TFCI symbols projected on the orthogonal axis output from the equivalent of the multiplication unit 4 are input, the TFCI symbols of all valid fingers are combined at the maximum ratio, and the result is output to the TFCI hard decision unit 6.
Similarly, the RAKE combining unit 9 projects the TPC symbol projected on the orthogonal axis output from the complex multiplication unit 8 for each of the two symbols constituting the TPC symbol, and other fingers (not shown). Similarly, the TPC symbol projected on the orthogonal axis is input, and RAKE synthesis is performed, and the result is output to the TPC hard decision unit 10.
Here, each finger has a processing unit similar to that shown in FIGS. 1 and 2, for example. In each finger, processing is performed on the main wave or delayed wave (multipath) of the same signal from the same user, and information obtained thereby is notified to other fingers as necessary. In this example, in each finger, the phase rotation amount of the previous slot is multiplied by the complex multiplication units 4 and 8 and the amplitude is squared. Therefore, the RAKE combining unit 9 simply adds the inputs. The RAKE combining of this example is intended to obtain a more reliable decoded data by combining a plurality of signals received through different paths, etc., so diversity combining signals from other antennas or different detection A signal detected by a method (delay detection, etc.) may be synthesized.

The TFCI hard decision unit 6 extracts the sign bit of the Q-phase data after RAKE combining for each of the two symbols constituting the TFCI symbol, normalizes the result, and outputs the result to the complex multiplication unit 7. That is, it is used as a reference pattern in the same manner as the reference pilot table 1.
Similarly, the TPC hard decision unit 10 increases the accuracy by synthesizing the symbols and averaging because the two symbols constituting the TPC symbol are limited to either the “00” pattern or the “11” pattern. Let The sign bit of the Q-phase data after inter-symbol synthesis is extracted, and the result is normalized and output to the complex multiplication unit 11.
The complex multiplier 7 has, for example, two complex multipliers corresponding to each symbol constituting the TFCI symbol, and the pattern obtained from the despread symbol in the TFCI section and the TFCI hard decision unit 6 for each symbol. (Sign bit) is subjected to complex conjugate multiplication, and the phase rotation amount calculated thereby is output to the adder 12.
Similarly, the complex multiplier unit 11 includes, for example, two complex multipliers corresponding to the symbols constituting the TFCI symbol. For each symbol, the despread symbol in the TFCI interval and the TFCI hard decision unit 6 The obtained pattern (sign bit) is subjected to complex conjugate multiplication, and the phase rotation amount calculated thereby is output to the adding unit 12.

The adding unit 12 adds the four input symbol phase rotation amounts, and outputs the addition result to the adding unit 13.
This process is a process for calculating the phase rotation amount using the TFCI symbol and the TPC symbol. In this example, the phase rotation amount obtained in this process is referred to as a feedback determination symbol phase rotation amount. The feedback determination symbol phase rotation amount is more reliable than the pilot symbol phase rotation amount.
In this example, the FBI symbol is not used for calculating the average phase rotation amount. In general, however, the pilot symbol, TFCI symbol, and TPC symbol bits are always transmitted from the transmission side. This is because the bit of the FBI symbol may be turned off depending on conditions.

The adding unit 13 adds the pilot symbol phase rotation amount input from the adding unit 3 and the feedback determination symbol phase rotation amount input from the adding unit 12, and outputs the addition result to the averaging unit 14.
The averaging unit 14 averages the addition result input from the addition unit 13 by dividing the addition result by the number of symbols subjected to the addition (9 in this example), and outputs the averaged result to the multiplier 22. To do.
In this example, this averaged result is referred to as the average phase rotation amount of the corresponding slot (here, Slot # n−1).

Here, due to the division in the averaging unit 14, the averaged result has the same gain as the UL-DPCCH signal after despreading.
The reason for equal gain in this way is that there are several types of UL-DPCCH slot formats, and the number of pilot symbols is not necessarily five, so that the reception characteristics do not change due to changes in the number of pilot symbols. This is also to prevent overflow in complex multiplication of the channel estimation amount and the UL-DPDCH despread signal in the subsequent stage.

The same processing is performed on the nth slot (Slot # n) by the same processing unit as in the (n−1) th slot, and the average phase rotation of the nth slot is performed by the averaging unit 14a. The amount is calculated and output to the multiplier 22a at a predetermined timing of the nth slot.
The same processing is performed on the (n + 1) th slot (Slot # n + 1) by the same processing unit as in the (n−1) th slot, and the averaging unit 14b performs the (n + 1) th slot. Is calculated and output to the multiplier 22b at a predetermined timing of the (n + 1) th slot.
Here, in this example, the pattern of the reference pilot symbol is different for each slot. The reason for this is to achieve frame synchronization by synchronous detection using pilot symbols. For example, 3GPP TS25.211 defines a reference pilot symbol pattern.

Next, an operation for obtaining the estimated phase rotation amount (average phase rotation amount) in the nth slot based on the (n−1) th, nth, and (n + 1) th three slots will be described.
For example, the weighting control unit 21 inputs information on a chip offset given at the time of call setting for each user, and based on this, weighting coefficients W (n−1) and W (n) for each slot. , W (n + 1) are controlled and output to the multipliers 22, 22a, 22b corresponding to the slots.
Each multiplier 22, 22 a, 22 b corresponding to each slot receives the corresponding response inputted from the weight controller 21 when the slot average phase rotation amount is inputted from each averaging unit 14, 14 a, 14 b corresponding to each slot. The weighting coefficients W (n−1), W (n), and W (n + 1) are multiplied. The multiplication unit 22 corresponding to the (n−1) th slot outputs the multiplication result to the delay unit 23, the multiplication unit 22a corresponding to the nth slot outputs the multiplication result to the addition unit 24, and the (n + 1) th slot. The multiplication unit 22 b corresponding to the slot outputs the multiplication result to the addition unit 26.

The delay unit 23 delays the multiplication result for the (n−1) -th slot input from the multiplication unit 22 by one slot time, and outputs the delayed result to the addition unit 24.
The adder 24 adds the multiplication result for the nth slot input from the multiplier 22 a and the input from the delay unit 23, and outputs the addition result to the delay unit 25.
The delay unit 25 delays the input from the addition unit 24 by one slot time and outputs the delayed result to the addition unit 26.
The adder 26 adds the multiplication result for the (n + 1) -th slot input from the multiplier 22 b and the input from the delay unit 25, and outputs the addition result to the averaging unit 27.
As a result, a delay of 2 slots is given to the average phase rotation amount of the (n−1) th slot, and a delay of 1 slot is given to the average phase rotation amount of the nth slot. At the timing of the (n + 1) th slot, weighted addition of the phase rotation amounts for those three slots is achieved.

The averaging unit 27 averages the addition result input from the addition unit 26 by dividing by the number of slots in which the addition has been performed (3 in this example), and the averaged result is the frequency drift compensation unit 31. To the complex multiplier 48. Here, due to the division in the averaging unit 27, the averaged result becomes equal in gain to the UL-DPCCH signal after despreading.
In this example, the averaged result obtained by the averaging unit 27 is referred to as the channel estimation amount of the corresponding slot (here, Slot # n).

  As described above, in this example, in order to obtain the UL-DPDCH channel estimation amount, in addition to the slot average phase rotation amount obtained using the pilot symbol of the corresponding slot, the slot average phase rotation for each of the front and rear slots. Use quantity. The reason for this is to improve the reception quality. In general, the noise resistance improves as the number of slots to be averaged increases, but it has a trade-off relationship that it becomes weak against frequency drift.

Here, the chip offset and weighting control performed in this example will be described in detail.
In the chip offset, the frame timing is shifted for each user, and the transmission / reception timing is shifted.
The chip offset is the same for uplink communication from the user (mobile station device) to the base station device and for downlink communication from the base station device to the user (mobile station device).
For example, in the downlink communication, when the chip offsets match for each user, all the positions of the pilot symbol synchronization word (Sync Word) (for example, the pattern of “11” in QPSK (Quadrature Phase Shift Keying)) Therefore, the IQ amplitude after user multiplexing at the synchronization word position (timing) becomes extremely large with respect to the average value. If there is no correlation between users, the IQ amplitude after multiplexing has a normal distribution. However, when the chip offsets match in this way, there is a problem that the relationship is lost.
For this reason, in this example, the transmission / reception timing of each user is distributed by chip offset to reduce inter-user interference.

An example of weighting control is shown with reference to FIG.
In this example, there are five users (User # 0 to User # 4), and each user has a different chip offset in 512 chip increments.
Specifically, the chip offset for User # 0 is 0 chip, the chip offset for User # 1 is 512 chips, the chip offset for User # 2 is 1024 chips, and the chip offset for User # 3 is 1536 chips. The chip offset of User # 4 is 2048 chips, and the frame is delayed by the amount of each chip offset.

  In FIG. 3, (a) shows a reference slot period and slot number (Slot No.), (b) shows frame timing (Frame Timing), and (c) shows five users. 4 shows despread IQ data, (d) shows despread IQ data accumulated with chip offsets for five users, and (e) shows the phase of UL-DPCCH for five users. The amount of rotation is shown, (f) has shown the weighting coefficient about five users.

As shown in FIG. 3C, the despread IQ data of each user is input at a symbol period while maintaining the chip offset. This is the same for both DPCCH and DPDCH.
In the channel estimation circuit, if the start positions of the pilot symbols are different for each user signal, for example, serial processing in units of users is required.
However, as another example, if a storage buffer capable of storing a maximum of 10 symbols (corresponding to one slot) in the previous stage is provided, the start positions of the pilot symbols can be matched for each user, so that Parallel processing is possible. In this example, such a configuration is adopted. A DSP (Digital Signal Processor) that performs baseband signal processing usually has a pipeline configuration, and can achieve high speed by parallel processing.

In such a configuration of this example, the timing for updating the value of the channel estimation amount does not depend on the chip offset for each user, and has a predetermined slot period. Then, all users are updated at the same timing.
That is, as shown in FIG. 3D, the slot offset between users due to the chip offset is absorbed by the internal buffer, and the beginning of each symbol field is made coincident, so that user parallel processing can be performed, and the baseband signal Processing speed can be increased.
Specifically, in the example of FIG. 3D, the user # 0 whose chip offset is 0 chip (= 0 symbol) is delayed by 10 symbols, and the user whose chip offset is 512 chips (= 2 symbols). # 1 is delayed by 8 symbols, user # 2 whose chip offset is 1024 chips (= 4 symbols) is delayed by 6 symbols, and user # 3 whose chip offset is 1536 chips (= 6 symbols) The user # 4 having a chip offset of 2048 chips (= 8 symbols) is delayed by 2 symbols.
As shown in FIG. 3E, the DPCCH phase rotation amount differs for each user, and all users are updated at the same timing without depending on the chip offset.

In such a configuration of this example, a shift of one slot at the maximum occurs in matching (that is, data demodulation) between the UL-DPDCH despread IQ data updated in the symbol period and the channel estimation amount. If the timing of this matching does not match, when there is a frequency drift, the phase rotation due to the frequency drift cannot be compensated, and the reception quality deteriorates.
In order to match the timing, as an example, it may be possible to use a configuration in which a delay buffer for adjusting timing is provided between the despreading unit of the UL-DPDCH and the data demodulating unit. However, in this configuration, since the amount of despread data of UL-DPDCH is generally larger than the amount of despread data of UL-DPCCH, it may be difficult due to memory limitations from the viewpoint of hardware implementation. .

Therefore, as another example, in order to achieve timing coincidence, in this example, weight estimation control of channel estimation is performed according to the chip offset, thereby obtaining the same effect as timing adjustment.
In this example, as shown in FIG. 3 (f), for each user, the weighting coefficient W (n-1) for the (n-1) -th slot and the n-th slot according to the size of the chip offset. The ratio between the weighting coefficient W (n) for the slot and the weighting coefficient W (n + 1) for the (n + 1) th slot is changed. Specifically, as shown in FIG. 3 (f), the smaller the chip offset, the greater the weight of the earlier signal position (left side in the figure), and the larger the chip offset, the slower the signal. The weight of the position (right side in the figure) is increased.

Here, in FIG. 3F, curves P0 to P4 representing the characteristics of the weighting coefficient for each user are shown with the horizontal axis as the signal position (timing) and the vertical axis as the magnitude. The vertical axis value (the length of the arrow in the figure) of the curves P0 to P4 at the center position of each slot (the center position of the horizontal axis value) is the magnitude of the weighting coefficient (ratio in this example) for each slot. To do.
In this example, the ratio changes, but the weighting coefficient W (n-1) for the (n-1) th slot, the weighting coefficient W (n) for the nth slot, and the weighting coefficient for the (n + 1) th slot. The total value {W (n-1) + W (n) + W (n + 1)} with W (n + 1) matches. For this reason, there is no difference in the amplitude of the channel estimation amount due to the chip offset.
If the weight offset control according to the chip offset is not performed and W (n-1): W (n): W (n + 1) = 1: 2: 1 is fixed, a user having a chip offset of 1024 chips. The reception characteristics of # 2 are the best, and the reception characteristics of user # 0 whose chip offset is 0 chip and user # 4 whose chip offset is 2048 chips are deteriorated.

Next, the operation in the frequency drift compensation unit 31 will be described.
The frequency drift detector 41 receives the symbol phase rotation amount (pilot symbol from which the modulation component has been removed) output from the complex multiplier 2, and specifically, the x-th in the pilot symbol for any integer x The data of the symbol (sym # x) and the data of the (x + 1) th symbol (sym # x + 1) are input.
The frequency drift detection unit 41 uses the input adjacent symbol phase rotation amounts and multiplies them by complex conjugate multiplication to obtain a frequency drift vector per symbol (= 256 chips) and outputs it to the frame interval averaging unit 42 To do. Alternatively, an arbitrary symbol of the despread DPCCH may be input and subjected to delay detection, and a signal obtained by removing a modulation component by complex conjugate multiplication with a symbol determination value as necessary may be output. Thus, the frequency drift vector is generally obtained as a time difference of the phase rotation amount.

The frame interval averaging unit 42 averages the interval for one frame with respect to the input frequency drift vector, and outputs the averaged result to the RAKE combining unit 43. This averaging suppresses noise components.
The RAKE combining unit 43 inputs the averaged result of the frequency drift vectors output from the frame interval averaging unit 42 and the frame interval averaging unit 42 equivalent to other fingers (not shown). All the averaged results are added, and the result is output to the exponential weighted averaging unit 44. The RAKE combining unit 43 does not need to perform strict RAKE combining that performs weighting in proportion to the slot average received power of each finger path, and may simply add.

The exponential weighting averaging unit 44 averages (moving averages) a longer section than the frame using a predetermined forgetting factor λ with respect to the input from the RAKE combining unit 43, and the averaged result is a tangent calculating unit 45. Output to. The exponential weighting averaging unit 44 is configured by, for example, an IIR (Infinit Impulse Response) filter having two taps.
Here, the reason for the two-stage configuration of the frame interval averaging unit 42 and the exponential weighting averaging unit 44 is that there is a possibility that the averaging time may be insufficient with only the preceding frame interval averaging unit 42, and the latter stage This is because with only the exponential weighting averaging unit 44, the forgetting factor λ is small in the long interval average, and accuracy may not be obtained in the fixed point arithmetic.
The frequency drift does not normally change instantaneously but gradually changes due to aging deterioration of the crystal oscillator, etc., so it is preferable to perform averaging over a long section.

The tangent calculation unit 45 divides the Q-phase amplitude and the I-phase amplitude with respect to the input from the exponential weighted averaging unit 44 to obtain a tangent value (for example, (Q-phase amplitude / I-phase amplitude) value). The tangent value or arc tangent value (deflection angle) is output to the table conversion unit 47.
The normalization table 46 for compensating for the frequency drift stores, for example, a correspondence between a tangent value (or declination) and a standardized vector I / Q amplitude value corresponding thereto.

  The table conversion unit 47 reads the IQ amplitude value corresponding to the tangent value input from the tangent calculation unit 45 with reference to the normalization table 46, and delays in 512 chip increments based on the I / Q amplitude value. Are generated and output to the complex multiplier 48. The five-stage frequency compensation vectors are generated by giving the phase rotation in 512 chip steps based on the current IQ amplitude value to the last final frequency compensation vector stored in the table conversion unit 47 in five stages. .

  The complex multiplier 48 has five complex multipliers, inputs the channel estimation amount output from the averaging unit 27 to each complex multiplier, and outputs the five steps output from the table converter 47. Each of the frequency compensation vectors is input to a corresponding complex multiplier, and each of the complex multipliers performs complex conjugate multiplication of the channel estimation amount and the corresponding frequency compensation vector, and outputs the result. These five outputs are obtained by generating a five-step channel estimation amount having a delay of 512 chips, and the frequency drift is compensated by 512 chips.

The five outputs from the complex multiplication unit 48 are channel estimation amounts obtained based on the UL-DPCCH (compensated for frequency drift every 512 chips), and each of these five outputs is converted into the UL-DPDCH. The phase rotation generated in the UL-DPDCH is compensated by performing complex multiplication with the 512-chip portion corresponding to each of the despread IQ data. Here, the demodulation of UL-DPDCH is an interpolation detection because the amount of phase rotation before and after the corresponding symbol is used.
In this example, the channel estimator and the frequency compensation vector compensate for (reversely rotate) the phase rotation generated in the UL-DPDCH by complex multiplication, so that the phase rotation in the direction opposite to the phase rotation is performed. Will be generated.

Next, with reference to FIGS. 4A to 4G, the processing performed in the frequency drift compensation unit 31 will be described in detail.
FIG. 4A shows an example of time transition of the I / Q signal of the pilot despreading vector that is an input signal to the frequency drift detector 41.
In this example, UL-DPCCH including pilot symbols is modulated by a BPSK (Binary Phase Shift Keying) method, and each pilot symbol for every 256 chips can take a binary value corresponding to a known pilot bit pattern and is continuously generated by frequency drift. Phase rotation is added.
Let αi (i = 0, 1,..., N _pilot −1) be the phase rotation angle of each pilot symbol. Here, N _pilot is the number of pilot symbols per slot.
In the example of FIG. 4A, N _pilot = 5 and the pilot bit pattern is {1, 1, 1, 0, 1}.
(Equation 1) shows the determination result of each pilot symbol bit, and {1} varies due to frequency drift, but the BPSK demodulation result is 1 (the phase rotation angle is π / 2). Where {0} varies due to frequency drift, but the BPSK demodulation result is 0 (the phase rotation angle is −π / 2).

FIG. 4B shows an example of a frequency drift vector between pilot symbols obtained by delay detection as an output from the frequency drift detector 41.
In this example, four frequency drift vectors are generally obtained for each of the five pilot symbols shown in FIG. The angle of these four frequency drift vectors is θj (j = 0, 1,..., N _pilot −2). Each angle θj is expressed as (Equation 2).

FIG. 4C shows an example of the frequency drift vector after the averaging by the frame interval averaging unit 42.
When the angle of the frequency drift vector after the averaging is θ _{frm_ave} and the number of slots per frame is 15, it is expressed as (Equation 3). The number of symbols to be averaged is {15 × (N _pilot −1)}.

FIG. 4D shows an example of the frequency drift vector after the averaging by the exponential weighting averaging unit 44.
If the angle of the averaged frequency drift vector is θ _{wght_ave} , it is expressed as (Equation 4). Here, the forgetting factor is λ, and the angle of the frequency drift vector held last time is θ _{wght_ave_old} .

FIG. 4E shows an example of the frequency drift compensation vector per 256 chips obtained inside the table conversion unit 47. When the angle of the frequency drift compensation vector per 256 chips is φ, it is expressed as (Equation 5).
The range in which frequency drift compensation is possible is − (π / 2) <θwght_ave <(π / 2). It cannot follow the phase rotation beyond this range.

In this example, information on the I / Q amplitude values of the normalized vector shown in FIG. 4E corresponding to the tangent value of the vector shown in FIG. Is remembered.
Further, the reason why the sign (±) of the vector shown in FIG. 4D is inverted in this way to obtain the vector shown in FIG. 4E is due to the frequency drift per symbol in FIG. This is to obtain reverse rotation phase information to compensate for the fact that the phase rotation amount has been obtained.

FIG. 4 (f) shows an example of the frequency drift compensation vector that is finally updated in the previous slot. Let φ _init be the angle of the frequency drift compensation vector that was last updated in the previous slot.
In this example, φ5 corresponding to the frequency drift compensation vector (5) shown in FIG. _4G in the previous slot is used as φinit, but the channel estimation amount output from the averaging unit 27 is optimal. If the timing is appropriately selected, φ _init can be made unnecessary (that is, 0).

FIG. 4G shows an example of five-stage frequency drift compensation vectors (1) to (5) having a resolution of 2φ (= 512 chips) output from the table conversion unit 47.
When the angle of these five stages of frequency drift compensation vectors (1) to (5) is φk (k = 0, 1, 2,..., {(2560 chips / 512 chips) −1}), ).

Here, (1) is a frequency drift compensation vector φ0 suitable for the position of 256 chips from the top in one slot, and (2) is a frequency drift compensation vector suitable for the position of 768 chips from the top in the slot. φ1 and (3) is a frequency drift compensation vector φ2 suitable for the position of 1280 chips from the head in the slot, and (4) and (5) are the same.
FIG. 2D shows the result of complex multiplication of the frequency drift compensation vectors φ0 to φ4 for one slot and the channel estimation amount from the averaging unit 27 by the complex multiplier 48. Thus, the phase of the signal portion centered on the position corresponding to each in one slot of the DPDCH (in this example, the position of 256 chips, 768 chips, 1280 chips, 1792 chips, 2304 chips from the head) Rotation is compensated.
4A to 4D, the amplitude varies according to the reception level. In FIGS. 4E to 4G, the amplitude is constant because it is normalized. Concentric circles in the figure indicate the magnitude of the amplitude after normalization. Between FIG.4 (d) and FIG.4 (e), it is normalized and the amplitude becomes large.

Next, a specific example of the reception quality improvement effect realized by the channel estimation circuit of this example will be shown.
First, an example of deterioration of BER (Bit Error Rate) characteristics due to frequency drift will be described with reference to FIG.
FIG. 7A shows an example of demodulated data of UL-DPDCH.
In FIG. 7B and FIG. 7C, the horizontal axis indicates the chip shift from the center position of the slot, and the vertical axis indicates the BER when error correction (FEC: Forward Error Correction) is not performed. It is. This is a complex multiplication of the channel estimator obtained by the averaging unit 60 shown in FIG. 6 and UL-DPDCH despread data, and the I phase of the UL-DPDCH symbol projected on the in-phase axis is hard-decisioned. It is the characteristic of BER about a result. This channel estimator has a center of gravity at the center position of the slot and does not compensate for frequency drift.
If there is no frequency drift, the BER characteristic of the user data shows a uniform characteristic in the slot. However, when there is a frequency drift, as shown in FIGS. 7B and 7C, the BER characteristics of the user data are slot boundaries (left and right in the figure) with the center position of the slot as a vertex. It becomes a characteristic of a quadratic curve in which errors increase as it approaches.

Next, with reference to FIG. 5, an example of the improvement effect of the BER characteristic by the frequency drift compensation in the channel estimation circuit of this example will be shown.
FIG. 5A shows an example of demodulated data of UL-DPDCH.
In FIG. 5B, the horizontal axis indicates the chip deviation from the center position of the slot, and the vertical axis indicates the BER when error correction (FEC) is not performed.
In FIG. 5C, the horizontal axis indicates the chip shift from the center position of the slot, and the vertical axis indicates each of the five types of frequency drift compensation vectors (1) to (5) shown in FIG. The BER in the case where error correction (FEC) is not performed is shown.

  The BER characteristic shown in FIG. 5B is obtained by performing complex multiplication of the 5-stage channel estimation amount obtained by the complex multiplication unit 48 in the channel estimation circuit of this example and the UL-DPDCH despread data on the in-phase axis. This is a BER characteristic for a result of hard decision on the I phase of the UL-DPDCH symbol projected onto. As shown in FIG. 5C, the five-stage channel estimation amounts obtained by the complex multiplier 48 are points separated from the beginning of the slot by 256 chips, 768 chips, 1280 chips, 1792 chips, and 2304 chips, respectively. The frequency drift component is canceled by the frequency drift compensation vector having the center of gravity at the center.

The BER characteristics of five stages as shown in FIG. 5C are combined to realize the BER characteristics as shown in FIG. 5B as a whole.
As is clear from the comparison between the BER characteristic of the comparative example shown in FIG. 7B and the BER characteristic of the present example shown in FIG. 5B, the channel estimation amount of this example is larger than that of the comparative example. Since the resolution is subdivided from 2560 chips (= 1 slot) to 512 chips, the degree of characteristic deterioration at points outside the five-stage center of gravity is suppressed, and uniform (or more uniform) within the slot (Near) BER characteristics can be realized.

As described above, in the channel estimation circuit of this example, when calculating the average phase rotation amount, channel estimation with high noise suppression is achieved by the effect of averaging by using TFCI symbols and TPC symbols that are symbols other than pilot symbols. Is possible. By using hard decision data such as TFCI instead of the reference pilot, channel estimation can be performed from E-DPCCH having no pilot symbol.
In addition, in the channel estimation circuit of this example, the resolution of the channel estimation amount is subdivided into small chips (512 chips in this example), and the frequency drift component is canceled to reduce the reception quality due to the frequency drift. For example, the reception quality can be improved to the same level as when the frequency drift is 0 ppm or very small.
Further, in the channel estimation circuit of this example, even when a chip offset is used, it is possible to obtain a stable reception quality having no chip offset dependency.

  In the channel estimation circuit of this example, means for acquiring a channel estimation amount for each slot by the functions of the processing units 1 to 14, 14a, 14b, 21, 22, 22a, 22b, and 23 to 27 shown in FIG. The first acquisition means) is configured, and means for acquiring the frequency drift compensation amount by the functions of the processing units 41 to 47 other than the complex multiplication unit 48 included in the frequency drift compensation unit 31 shown in FIG. Acquisition means), and means (third acquisition means) for acquiring a channel estimation amount that compensates for the frequency drift by the function of the complex multiplication unit 48 included in the frequency drift compensation unit 31 shown in FIG. Has been.

  Further, in the channel estimation circuit of this example, means (fourth acquisition means) for acquiring the average phase rotation amount for each slot by the functions of the processing units 1 to 14, 14a, 14b before weighting shown in FIG. The weighting control unit 21 and the functions of the multiplication units 22, 22a, and 22b constitute means (weighting means) for weighting the average phase rotation amount for each slot, and the delay units 23, 25 and Means (first averaging means) for averaging the average phase rotation amount for each slot after weighting are configured by the functions of the adding sections 24 and 26 and the averaging section 27.

  Further, in the channel estimation circuit of this example, means (fifth acquisition means) for acquiring the phase rotation amount based on the pilot symbol is configured by the functions of the reference pilot table 1, the complex multiplier 2 and the adder 3. Means for acquiring a phase rotation amount based on symbols other than the pilot symbols by the functions of the complex multipliers 4 and 8, the RAKE combining units 5 and 9, the hard decision units 6 and 10, the complex multipliers 7 and 11, and the adder 12. 6 acquisition means), and means for averaging these phase rotation amounts (second averaging means) is constituted by the functions of the adding section 13 and the averaging section 14.

FIG. 8 is a block diagram of a demodulator according to Embodiment 2 of the present invention. In this example, description will be made without assuming RAKE combining, but RAKE combining may be performed after demodulation by channel estimation.
This example includes an IIR LPF (Low Pass Filter) that calculates a channel estimation amount with a processing delay within one symbol time based on the phase rotation amount obtained for each symbol of the pilot symbol, and includes a cutoff frequency of the filter and Q Is different from the first embodiment in that it is adaptively controlled based on the fading frequency (drift frequency) obtained by the fading estimation unit.

Control CH despreading section 101 despreads UL-DPCCH with spreading factor 256 (symbol rate = 15 ksps), and outputs an I / Q (complex) format despread signal.
The pilot in-phase unit 102 extracts a pilot symbol from the despread signal input from the control CH despread unit 101, performs complex conjugate multiplication with a known pilot symbol input from the reference pilot table 1, and performs the pilot conjugate for each pilot symbol. Outputs the amount of phase rotation.
Slot averaging section 104 accumulates the symbol phase rotation amount in one slot, averages the accumulated number of symbols, and outputs a slot average phase rotation amount equal in gain to the UL-DPCCH despread signal.
The f _D estimation unit 105 calculates the inner product of the slot average phase rotation amounts of the adjacent slots, estimates f _D (fading frequency) from the magnitude, and outputs it. f _D and the frequency drift of the first embodiment are the same, and the f _D estimation unit 105 may have the same configuration as the frequency drift detection unit.

LPF control unit 106 is input to f _D estimate from f _D estimator 105, and the cut-off frequency f _C appropriate in accordance with the f _D estimates, to determine the Q (Quality) value outputs.
Channel estimation value calculation section 107 is an IIR type LPF (or complex BPF), and receives a phase rotation amount from pilot in-phase conversion section 102, and is based on f _C and Q value input from LPF control section 106. A band filter process is performed, and the result is output as a channel estimation value in a symbol corresponding to the phase rotation amount input immediately before. As described above, since the channel estimation value is updated for each pilot symbol, finer resolution and followability than the conventional slot period can be obtained. Therefore, it is possible to select and use a channel estimation amount corresponding to a position close to each of the UL-DPCCH Pilot, TFCI, FBI, and TPC fields. Note that the channel estimation value calculation unit 107 is stopped while the phase rotation amount is not input.

Pilot demodulation section 108 performs phase compensation on the despread signal of the pilot section input from control CH despreading section 101 by complex conjugate multiplication with the channel estimation value input from channel estimation value calculation section 107, and performs Q-axis The value reduced to is output as pilot demodulated data.
Pilot error rate measuring section 109 compares pilot demodulated data input from pilot demodulating section 108 with known pilot data input from reference pilot table 1 and outputs the result as a physical channel error rate (PhyCH BER).
The frame synchronization determination unit 110 compares the physical channel error rate input from the pilot error rate measurement unit 109 with a specified value, determines that synchronization is established when it is lower than the specified value, and is out of synchronization when it is higher, and the result Is output. Note that the period from the call setting to the initial synchronization establishment may be set as the initial synchronization wait, and the case where the radio wave propagation environment deteriorates rapidly after the initial synchronization establishment and is out of synchronization may be distinguished as out of synchronization.

The TFCI demodulating unit 111 performs phase compensation by performing complex conjugate multiplication on the despread signal of the TFCI unit input from the control CH despreading unit 101 by the channel estimation value input from the channel estimation value calculating unit 107, and performs Q-axis compensation. The value reduced to is output as TFCI soft decision data.
The TFCI decoding unit 112 accumulates one frame (30 bits) of the TFCI soft decision data input from the TFCI demodulation unit 111, decodes it with a secondary Reed-Muller code, and outputs TFCI (10 bits) that varies with the frame period. .

The FBI demodulating unit 113 performs phase compensation by performing complex conjugate multiplication on the FBI part of the despread signal input from the control CH despreading unit 101 by the channel estimation value input from the channel estimation value calculation unit 107, and performs Q-axis compensation. The value reduced to is output as FBI soft decision data.
The FBI command generation unit 114 detects and outputs information on the S field for site selection diversity transmission and the D field for closed loop transmission diversity from the FBI soft decision data input from the FBI demodulation unit 113.

The TPC demodulating unit 115 performs phase compensation by performing complex conjugate multiplication on the despread signal of the TPC portion input from the control CH despreading unit 101 with the channel estimation value input from the channel estimation value calculating unit 107, and performs Q-axis compensation. The value reduced above is output as TPC soft decision data.
The TPC command generator 116 combines the TPC soft decision data input from the TPC demodulator 115 for one slot (for two symbols), and determines the sign of the Q-phase value based on the slot period. When the sign is positive, TPC command = 0, and when the sign is negative, TPC command = 1 is output.

The data CH despreading section 117 despreads the UL-DPDCH at any of spreading factors = 512, 256, 128, 64, 32, 16, 8, 4 (symbol rate = 7.5, 15, 30, 60, 120, 240, 480, 960 ksps), and I / Q Output data despread signal in (complex) format.
The delay unit 118 is a buffer for matching the timing of matching of the data despread signal and the channel estimation value in the data demodulator 119 at the subsequent stage, and the delay corresponding to the delay required for the channel estimation processing on the control CH side is inverted. Give to spread signal and output. If the chip offset is not considered, a delay of at least about 1 slot has occurred from the control CH side in order to estimate the channel by interpolation in the first embodiment. However, in this example, about 1 symbol is used instead of 1 slot. Delay is sufficient and buffer capacity can be reduced.

The data demodulating unit 119 performs phase compensation on the data despread signal input from the delay unit 118 by the complex conjugate multiplication with the channel estimation value input from the channel estimation value calculation unit 107, and results on the I axis. Is output as data CH soft decision data. If the complex division is performed instead of the complex conjugate multiplication, the amplitude fluctuation as well as the phase can be compensated.
The data decoding unit 120 performs a series of decoding processes such as deinterleaving, rate matching, error correction, and CRC detection on the data CH soft decision data input from the data demodulation unit 119.

FIG. 9 is a configuration diagram of the LPF control unit 106 and the channel estimation calculation unit 107 of this example.
The IIR filter parameter control unit 401, based on the f _D estimated value input from the f _D estimation unit 105, for example, when walking (low speed), when traveling on a general road (medium speed), when traveling on a highway (high speed), and the Shinkansen The f _C and Q values of the IIR filter suitable for the fading speed of the mobile terminal at the time of boarding (super high speed) are obtained and output. The f _C and Q values are hereinafter referred to as LPF parameters. In some cases, f _D and f _C must be distinguished from positive and negative.
The association between the f _D estimated value and the f _C and Q values is performed, for example, by acquiring a relationship in which reception quality is best in advance by actual measurement or simulation, storing it in a memory as a table, and reading it out. . Considering simply, a proportional relationship is estimated between the f _D estimated value and the optimum f _C.
The IIR filter coefficient calculation unit 402 is based on the f _C and Q values input from the IIR filter parameter control unit 401 and multiplies coefficients b ₀ , b ₁ ,... That define the feedback term components (403 to 405) of the IIR filter. , B _k-1 and multiplication coefficients a ₀ , a ₁ ,..., A _k that define the non-feedback term components (406 to 409) of the IIR filter are calculated by a known method. The multiplication factor can be a complex number. The possibility of LPF parameters relating to other filter characteristics will be described later.
Reference numerals 403 to 414 denote elements constituting the channel estimation calculation unit 107, and reference numerals 410 to 412 denote delay devices such as latches that delay one symbol time, which is an operation unit time of the IIR filter, and are also referred to as taps. . The transfer function of the IIR filter configured as described above is recursively expressed by the following equation.
Where x (n) is a phase rotation amount (representing a complex signal) input from the pilot in-phase unit 102, y (n) is a channel estimation value that is output from the channel estimation calculation unit 107, and w (n) is IIR. An intermediate output of the filter, n is an index counted for each symbol when UL-DPCCH is in a pilot interval. In other words, the IIR filter of this example operates only when the phase rotation amount of the pilot symbol is input as x (n), and stops for other symbols to hold the state of the previous symbol. The adder 413 performs addition of (Expression 7), and the adder 414 performs addition of (Expression 8). In addition, when n = 0, W (−1), W (−2),..., W (−k) have constants appropriate for x (n) (for example, 1 / (1− (b ₀ + b ₁ +... Set the product multiplied by + b _k-1 ))).

  FIG. 10 is a schematic diagram showing the configuration and operation timing around the channel estimation calculation unit 107 of this example. In the figure, Ref. Pilot Table represents the reference pilot table 1, 5 multipliers represent the pilot in-phase unit 102, IIR Filter represents the channel estimation calculation unit 107, and a single multiplier after the selector (SEL). Represents the Data demodulator 119.

  Here, assuming that the index is n in the x-th symbol (but limited to the pilot symbol) in an arbitrary slot, y is obtained from (Expression 7) and (Expression 8) based on the phase rotation amount w (n) input at that time. When (n) is output, y (n) becomes the DPDCH phase compensation IQ signal (channel estimation value) of the x-th symbol. That is, y (n) is selected by a selector (SEL) that can be optionally provided, and is complex-multiplied by the DPDCH despread IQ signal at the time corresponding to the x-th symbol to become a DPDCH demodulated IQ signal. Note that one slot of DPDCH has symbols continuously by the number obtained by dividing 2560 by the DPDCH spreading factor (SF), but the DPDCH phase compensation IQ signal given in one slot is the number of pilot symbols of DPCCH. (5) Only. For this reason, the DPDCH phase compensation IQ signal in the immediately preceding pilot symbol (sym # 4) is continuously used when it is outside the pilot interval. This DPDCH phase compensation IQ signal is also used for demodulation (hard decision) of fields (TFCI, etc.) other than the DPCCH pilot.

Since real filters are causal, they have a delay (group delay) greater than zero. Therefore, in order to obtain a channel estimation value of the symbol from the amount of phase rotation of the xth symbol, the phase delay must be set to zero. Since it is difficult to obtain a characteristic in which the phase delay is constant over a wide frequency range with a limited number of taps, adaptive control of LPF parameters including the phase delay is effective. If the fading frequency f _D to be compensated is known, it is easy to adjust the filter coefficient so as to make the phase delay constant for the specific f _D , and control is performed independently of the f _C and the Q value. However, a mode in which the control is indirectly performed by the f _C and the Q value is also conceivable.
The phase delay can be canceled by applying a phase rotation corresponding to f _D to the output y (n) of the IIR filter. Furthermore, as shown in FIG. 2 of the first embodiment, a configuration for calculating the phase rotation with the passage of time is provided, and the DPDCH phase compensation IQ signal in symbols other than the pilot interval is applied to the 6th to 10th individual symbols. It may be calculated.

The demodulating device of this example is suitable for RACH as well as DPCH because it does not require long-term averaging over a plurality of slots. RACH is a burst signal within 2 frames received at the time of attachment or detachment.
According to this example, since the channel estimation value is subdivided from slot to symbol, it can be demodulated using a channel estimation amount closer to the timing of the corresponding demodulation section of DPDCH (appropriate center of gravity position). . Further, the processing delay required for demodulation can be shortened from about 1 slot (667 μs) to about 1 symbol (66.7 μs @ SF256), and the memory capacity can be reduced accordingly.

FIG. 2 is a schematic diagram illustrating a configuration and operation timing of a channel estimation circuit according to the first embodiment. FIG. 3 is a diagram illustrating a configuration and operation timing of a channel estimation circuit according to the first embodiment. FIG. 3 is a timing diagram illustrating an example of weighting control according to the first embodiment. FIG. 3 is a diagram for explaining an example of frequency drift compensation according to the first embodiment. FIG. 6 is a diagram illustrating an example of an improvement effect of BER characteristics by frequency drift compensation according to the first embodiment. The figure which shows the structural example of the conventional channel estimation circuit. The figure which shows an example of deterioration of the BER characteristic by a frequency drift. FIG. 6 is a block diagram of a demodulator including a channel estimation circuit according to the second embodiment. The block diagram of the channel estimation calculation part etc. of Example 2. FIG. The schematic diagram which shows the structure of the periphery of the channel estimation calculation part of Example 2, and operation | movement timing.

Explanation of symbols

Reference pilot table 2, 4, 7, 8, 11, 48, 52, 52a, 52b .. Complex multiplication unit 3, 12, 13, 24, 26, 53, 53a, 53b, 57, 59 ··· Adder, 5, 9, 43 · · RAKE combiner, 6 · · TFCI hard determiner, 10 · · TPC hard determiner, 14, 14a, 14b, 27, 54, 54a, 54b , 60 .. Averaging unit, 21.. Weighting control unit, 22, 22a, 22b, 55, 55a, 55b ... Multiplying unit, 23, 25, 56, 58 ... Delay unit, 31 ... Frequency drift compensation unit 41 ·· Frequency drift detection unit, 42 ·· Frame interval averaging unit, 44 ·· Exponential weighting averaging unit, 45 ·· Tangent operation unit, 46 ·· Normalization table, 47 ·· Table conversion unit,
101... Control CH despreading unit 102.. Pilot in-phase unit 104.. Slot averaging unit 105.. F _D estimation unit 106.. LPF control unit 107. ..Pilot demodulator 109 109 Pilot error rate measurement unit 110 Frame synchronization determination unit 111 TFCI demodulation unit 112 TFCI decoding unit 113 FBI demodulation unit 114 FBI command generation 115, TPC demodulator, 116, TPC command generator, 117, data CH despreader, 118, delay unit, 119, data demodulator, 120, data decoder,
401 ··· IIR filter parameter control unit, 402 ··· IIR filter coefficient calculation unit, 403 to 409 ·· Coefficient multiplier, 410 to 412 ·· Delay device, 413, 414 ··· Adder.

Claims (5)

In a channel estimation apparatus for acquiring a channel estimation amount used for compensation of a signal to be compensated based on a signal for channel estimation,
First acquisition means for acquiring a channel estimation amount for each slot based on the channel estimation signal;
Second acquisition means for acquiring a compensation amount of frequency drift at a resolution finer than the slot based on the channel estimation signal;
A channel estimation amount for each slot acquired by the first acquisition means and a frequency drift compensation amount acquired by the second acquisition means are combined to acquire a channel estimation amount that compensates for both; And obtaining means,
The channel estimation amount acquired by the third acquisition unit is used for compensation of the signal to be compensated.
A channel estimation apparatus. The channel estimation apparatus according to claim 1,
Provided in a base station device that communicates wirelessly with a plurality of mobile station devices by CDMA,
The channel estimation signal is a UL-DPCCH signal wirelessly transmitted from the mobile station apparatus to the base station apparatus, and the signal to be compensated is wirelessly transmitted from the mobile station apparatus to the base station apparatus. These are UL-DPDCH signals, and for these signals, chip offsets for shifting the timing of radio transmission are set for each mobile station device,
The first acquisition means delays the channel estimation signals received from each mobile station apparatus by a time corresponding to each of the plurality of mobile station apparatuses so as to adjust the timing shift due to the chip offset in parallel. A fourth acquisition means for processing to acquire an average phase rotation amount for each slot; and a weight for each slot determined based on a chip offset set for each mobile station apparatus. Weighting means for giving to the average phase rotation amount for each slot acquired by the above, and averaging the average phase rotation amount for each slot weighted by the weighting means for a plurality of slots centered on the slot to be channel estimated First averaging means for converting the averaged result of the first averaging means to the channel estimation Obtaining a channel estimate of the elephant slot,
A channel estimation apparatus. In the channel estimation apparatus according to claim 1 or 2,
The channel estimation signal includes pilot symbols and other symbols,
The first acquisition means includes fifth acquisition means for acquiring a phase rotation amount based on a pilot symbol included in the channel estimation signal, and a symbol other than the pilot symbol included in the channel estimation signal. 6th acquisition means for acquiring the phase rotation amount based on the second average for averaging the phase rotation amount acquired by the fifth acquisition means and the phase rotation amount acquired by the sixth acquisition means And obtaining an averaged result by the second averaging means as an average phase rotation amount for each slot.
A channel estimation apparatus. In a channel estimation device that calculates a channel estimation amount used for compensation of a reception signal to be compensated based on a channel estimation signal included in the reception signal,
A reference pilot table storing a reference of the channel estimation signal;
For each symbol of the channel estimation signal, a pilot in-phase unit that outputs a value indicating a phase rotation of the received channel estimation signal with reference to the reference pilot table;
An fD estimation unit that estimates a fading frequency based on a value indicating the phase rotation;
An IIR filter that outputs a corresponding channel estimation value with a processing delay time within one symbol from an input immediately before the value indicating the phase rotation, based on the value indicating the phase rotation;
A filter control unit for controlling a filter parameter of the IIR filter based on the estimated fading frequency;
A channel estimation apparatus comprising: The channel estimation apparatus according to claim 4, wherein the filter control unit controls a filter parameter so that a phase delay of the IIR filter is substantially constant at the estimated fading frequency.