JP2007188517A - Timing distribution device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce redoing at a downstream process, to shorten a design period and to improve design quality by timing distribution and timing verification in consideration of a floor plan at an upstream process regarding the timing distribution of an LSI and a PCB in system circuit design. <P>SOLUTION: This timing distribution device is equipped with: a plurality of timing distribution creation parts 54a-54e which are provided so as to correspond to a plurality of design hierarchies respectively, receive block information regarding functions of circuits from a plurality of timing information data bases 57a-57e having net list information regarding a wiring form and output a timing distribution value obtained by distributing a delay value generated by a delay element of the circuit; and a corporation manager 53 between hierarchies which dynamically changes connection among each of the plurality of timing distribution creation parts 54a-54e, transmits and receives correction information concerning the timing distribution value to and from each of the plurality of timing distribution creation parts 54a-54e. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a timing distribution apparatus suitable for use in, for example, large-scale circuit design.

In general, in designing a circuit of a semiconductor chip (hereinafter referred to as a semiconductor circuit), an entire electronic device such as a semiconductor or a printing plate, or an element or subsystem constituting the electronic device (hereinafter referred to as a system circuit), a designer (User) uses a technique called division design in which the entire circuit is divided into two or more units and each unit is designed independently.
This unit means a unit having a predetermined circuit function and is called a circuit module or a module. In the following description, in order to distinguish a unit before processing from a unit after processing, the unit before processing is referred to as a unit to be processed or a unit to be designed. Furthermore, the unit after the processing is referred to as a processed unit or a processed unit.

  In addition, a method of designing in a state in which one unit includes (includes) another independently designed unit is called hierarchical design. In this hierarchical design, the unit to be included is lower, the unit to be included is higher, and has hierarchical properties. The partial circuits that are designed to be divided are finally integrated into one unit with the entire circuit as the highest hierarchy. In the following description, the term hierarchical design is used to indicate general division design.

  FIG. 43 is a conceptual diagram of hierarchical design. A semiconductor circuit 100 (hereinafter may be referred to as a chip) 100 shown in FIG. 43 is a top-level circuit, and includes circuit modules (hereinafter also referred to as modules) 100x and 100y. The module 100x includes modules 101x and 102x, and the module 100y includes modules 101y and 102y. Further, the modules 101x and 101y include modules 103x and 103y, respectively, and the modules 102x and 102y include modules 104x and 104y, respectively. Thereby, the designer can design each module individually, and the design efficiency is improved.

Further, since the scale of circuits is increasing year by year, circuit design apparatuses (hereinafter sometimes referred to as design apparatuses) are required to have an ability to process larger-scale data.
And, it is called collective design to design the entire semiconductor circuit at once regardless of the hierarchical design. This collective design is not performed for circuits larger than a certain scale mainly for reasons of hardware capability of the design apparatus, and hierarchical design is generally performed.

In other words, the working memory has a limitation on its capacity and a processing time. The design apparatus uses a large amount of work memory or the like for processing due to circuit change or the like. The processing such as the circuit change will be described with reference to FIGS.
FIG. 44 is a block diagram of the semiconductor circuit design apparatus. A design apparatus 500 shown in FIG. 44 is for designing a semiconductor circuit, and includes an automatic design processing unit 200 and a circuit information database 300. The circuit information database 300 holds information on circuit elements (for example, flip-flops and registers). Further, the automatic design processing unit 200 executes circuit design, and includes an HDL (Hardware Description Language) conversion processing unit 200a, an individualization processing unit 200b, a test circuit generation processing unit 200c, and a load adjustment processing unit. 200d and an HDL output processing unit 200e.

Here, the HDL conversion processing unit 200a performs HDL conversion on the HDL source code (hereinafter sometimes abbreviated as source code) and holds the unit to be processed in the circuit information database 300. The unit 200b assigns the names of different modules generated by the designer's circuit change so as not to overlap.
The test circuit generation processing unit 200c generates a test circuit, and generates information such as a hierarchy name, an additional terminal or additional gate name, and a connection order between modules. Furthermore, the load adjustment processing unit 200d adjusts the load of the module, and generates information such as a hierarchy name, an input terminal load, and an output terminal drive capability. In addition, the HDL output processing unit 200e reflects the processing result in the source code after these processes are performed.

  In a large-scale circuit design, when a plurality of circuits having the same function are required, a technique called multiple references is generally used. The multiple reference is a technique in which a module having a necessary function is designed as a unit to be processed, and the upper layer refers to the unit to be processed a plurality of times. As a result, the designer can omit the repeated arrangement of the modules, can load information on the same module into the working memory, and can prevent redundant calculation. A unit that is referred to only once with respect to the multiple references is called a single reference. Next, the specificization will be described with reference to FIGS. 45 (a) and 45 (b).

  45A and 45B are diagrams for explaining the unique processing. The chip 150a shown in FIG. 45 (a) is a circuit before being unique, and has two identical modules 151. The module 151 has a module 151a (denoted as A). The information of the module 151a is written in the circuit information database 300 as a data image 154a (labeled A).

  On the other hand, a chip 150b illustrated in FIG. 45B is a circuit after being unique, and includes a module 151 and a module 152. Here, the module 152 is obtained by making the module 151 unique, and further includes a module 152a (denoted with A ′) duplicated from a module circuit included therein. The information of these modules 151a and 152a is written in the circuit information database 300 as data images 154b (labeled A-0) and 154c (marked A-1), respectively. ing.

Here, the chip 150a shown in FIG. 45A includes a plurality of units (for example, the module 151) that are referred to in a certain period of the design process (hereinafter, sometimes referred to as a process). The unique process means a process necessary for the designer to change a state in which a plurality of references are made into a single reference possible state as shown in FIG. 45B in a subsequent process.
Specifically, the designer copies the unit (module 151) as many times as the number of times it is referred to, and changes the name of the unit to move the module to the unit that is single-referenced. To do. For example, in the case shown in FIG. 45 (b), only one copy is made. Thus, at the same time as the duplication, the unique names A-0 and A-1 are assigned to the original module 151a and the duplicated module 152a, respectively, and the designer can distinguish them.

  Further, in FIG. 44, the change in each process is written in the circuit information database 300 by the unique processing unit 200b, and the unique processing is completed. Thereafter, in the test circuit generation processing unit 200c and the load adjustment processing unit 200d, the contents changed in the unique processing are read from the circuit information database 300, a test circuit is generated, and the load adjustment is performed. It is done.

Also, ECO (Engineering Change Order) design is often used as a method different from hierarchical design or collective design. This ECO design is a technique in which only a part of the unit to be processed is changed and the other part of the circuit is redesigned without change, and the ECO design can be applied to a hierarchical design.
The reason why this ECO design is used is mainly because the redesign of only a part of the semiconductor circuit shortens the processing time than the redesign of the entire circuit.

  46 (a) to 46 (c) are diagrams for explaining the ECO design. The chip 250a shown in FIG. 46 (a) has been once designed (hereinafter sometimes referred to as normal design), and is before the ECO design. Here, the module 252a (denoted with C) is a circuit element of the module 251a. That is, both the module 251a and the module 252a are modules to which a test circuit and a clock circuit are added, and are automatically generated by the design apparatus. Further, the module 252a is written in the circuit information database 300 as a data image 260a (labeled C).

  A chip 250a shown in FIG. 46 (b) is for starting the ECO design. The chip 250a shown in FIG. 46 (b) is obtained by changing the circuit of the module 252a in the chip 250a shown in FIG. 46 (a) without adding a test circuit. That is, the module 252a changed is replaced with the module 252b (labeled C '), and the image is displayed. Further, the changed module 252b is written in the circuit information database 300 as a data image 260b (labeled C ′).

A chip 250a shown in FIG. 46C is at the end of the ECO design. In addition to changing the module 252b, a test circuit is added and replaced with the module 252c (denoted with C ″). It is a thing.
At this time, the circuit of the module 252b has the same circuit as the circuit before the test circuit of the module 252a is added, and the circuit to which the change is added. When the designer generates the test circuit again for the module 252b, the designer designs the part other than the changed part to be the same as the circuit of the module 252a. Here, if the difference between the previously designed module 252a and the module 252c designed using the ECO design is slight, the designer only needs to redesign the part to be changed in the layout design. Therefore, the designer can shorten the time required for the design.

  Incidentally, in the hierarchical design in FIGS. 44 to 46, the capacity of the database with respect to the recent design scale is extremely large, and it is difficult for the design apparatus to load all the data into the work memory. In order to avoid this memory shortage, the designer creates circuit data in black box in advance when using a design device for collective design, which requires a complicated repetitive procedure. Yes.

  On the other hand, even when a designer uses a design device suitable for split design, if the design device does not have a function for managing information related to a portion not to be processed, the designer correctly recognizes the portion to be processed. In addition, it is necessary to know information of related parts other than the part to be processed. In addition, the designer must individually specify information other than the parts to be processed, and give related information to the design apparatus for split design.

Here, if the design information is not referred to, there is a possibility that a unique name different from the proper name at the time of normal design (see FIG. 8 to be described later) may be given in the ECO design. The names may become inconsistent when comparing.
In the conventional ECO design, the circuit is restored while comparing the old circuit and the new circuit. In this ECO design, since circuit comparison and difference analysis are performed, complicated processing is required. Therefore, the designer has the trouble of designating information by himself / herself.

Next, with reference to FIGS. 47 to 49, timing distribution in system design such as device design and device design as system circuits will be described. In system design, timing distribution including PCB (Printed Circuit Board) design and LSI (Large Scale Integration) design is designed.
FIG. 47 is a diagram for explaining timing distribution. PCBs 140a and 140c are connected to both ends of the PCB 140b shown in FIG. 47 via connector pins (not shown). The PCBs 140a and 140c have LSIs 240 and 241 respectively. Here, the timing distribution means that the time required for signal transmission from the LSI 240 to the LSI 241 is allocated, and the designer considers how much transmission time is allocated among the PCBs 140a to 140c. . The position where the LSI is placed on the PCB is examined based on conditions called setup conditions and hold conditions. Here, the setup condition refers to a condition in which the signal propagation time falls within a predetermined time, and the hold condition refers to a condition for accurately matching data with a clock for the data.

  For example, if the LSI 240 on the PCB 140a is placed on the side far from the LSI 241 on the PCB 140c, the wiring becomes long and a signal delay occurs. In addition, the signal delay is adversely affected by wiring that is too short as it deviates from the hold condition. Therefore, it is necessary to examine the delay time in each of the case where the LSI 240 and the LSI 241 are brought close to each other and the case where the LSI 240 is kept away from each other. The specification for allocating the delay time is called a timing specification.

In FIG. 47, a is negative slack, c is positive slack, and request information indicating that the distribution value should be divided from the negative slack a side to the positive slack c side is transmitted. It has become so.
In the conventional design flow of timing allocation, after examining the initial architecture of the system, the PCB and LSI are divided, the timing specifications are set as constraints, and the design and implementation of the LSI inside the lower hierarchy etc. (hereinafter, implementation) Are called).

  In examining these timing specifications, first, a specification that defines the relationship between a clock and data called an AC (Alternative Current) specification is designed between the PCB and the LSI, and is implemented so as to match the specification. . Here, there are cases where the timing specification cannot be satisfied as a result of the implementation, and it is important to know the limit value of the timing specification.

FIG. 48 is a flowchart for explaining the outline of the device design. First, the device specification is examined (step W1), the architecture is designed (step W2), and the circuit function is assigned to the PCB or LSI for division design (step W3).
When a PCB is selected in step W3, PCB design is started in step W4. In addition to logic design, timing design, waveform analysis, mounting design, and thermal design are performed. In step W5, the PCB is implemented. The On the other hand, when an LSI is selected in step W3, LSI design is started in step W6, logic design, timing design, layout design, and power consumption analysis are performed, and LSI is implemented in step W7.

FIG. 49 is a flowchart for explaining timing design. First, when the system specifications are determined (step W50), the system architecture is examined (step W51), and the PCB / LSI is separately examined (step W52).
In step W53, the PCB timing specifications are examined, and in step W54, the PCB is implemented. In step W55, the LSI timing specifications are examined, and in step W56, the LSI is implemented.

In the process of individually implementing these LSI and PCB, STA (Static Timing Analysis) is used, and this STA can statically verify the timing without generating a simulation pattern.
Moreover, the following publicly known literature is known about timing distribution.
In the technique described in Japanese Patent Laid-Open No. 5-181929 (hereinafter referred to as publicly known document 1), when delay verification of a hierarchical logic circuit is performed, delay verification of an upper hierarchy logic circuit is performed on the lower hierarchy logic circuit. Design and delay verification can be performed even if not completed. This publicly known document 1 discloses a delay time verification method for hierarchical timing distribution of circuit blocks.

  The technique described in Japanese Patent Application Laid-Open No. 9-212533 (hereinafter referred to as publicly known document 2) is based on a critical path that straddles between hierarchies when optimizing hierarchically designed hardware for each hierarchy. The delay constraint to the path is appropriately distributed for each hierarchy, and the delay is optimized efficiently. This publicly known document 2 discloses a distribution optimization method. The critical part is a part where a delay is not allowed, and when a delay occurs in this part, the timing cannot be appropriately assigned.

  Then, the delay distribution is efficiently performed by the techniques described in these known documents 1 and 2.

However, according to the conventional method, there are many items that are manually input by the designer, which leads to a complicated design procedure, increasing the burden on the designer, and causing an error.
In addition, when a designer changes a circuit for which design has been completed, an external terminal is added or deleted due to the change, which may cause a mismatch in the terminal configuration between the upper layer and the lower layer. is there. Therefore, in the conventional design method, if the terminal configurations do not match, there is a problem that an inconsistency occurs between the upper layer and the lower layer, which is recognized as an error, and the design efficiency becomes very poor.

  In addition, regarding the timing distribution, in the architecture design study, the designer tries by changing the value many times. Therefore, the designer cannot clearly know the detailed timing until the deterministic value for the target PCB or LSI is mapped from the library to the target circuit, and the designer once has a predetermined delay. Values are assigned to PCBs or LSIs for other considerations.

For this reason, in the process where the designer cannot directly see the circuit elements such as flip-flops, the timing distribution of the entire system has many uncertain parts, and the timing of the entire system cannot be determined. There is a problem that it cannot respond flexibly.
In addition, each circuit block made up of LSI, PCB, etc. is not closely linked. Furthermore, in order to calculate an estimate of latency (time required for processing) and a delay value for a circuit block having circuit elements, a designer must actually perform an implementation design. On the other hand, in the critical part (part where delay is not allowed), the linkage between the architecture determination and the actual implementation process is sparse. Therefore, there are problems that it is difficult to examine one architecture in detail and to inherit a floor plan (for example, a floor plan from PCB to LSI) across physical layers to another circuit block.

Further, with the progress of deep sub-micron LSI, the proportion of wiring delay is more conspicuous than gate delay, and the influence of wiring delay, particularly delay in the global wiring portion, is increasing.
Furthermore, in order to wire between arranged pins, there is a method based on the Manhattan length, and the wiring length is calculated simply and at high speed by this method. FIG. 50 is a diagram for explaining the Manhattan length. The circuit module 170 shown in FIG. 50 includes circuit modules I51 and I50, which are connected by paths L1 and L2. Each of these paths L1 and L2 corresponds to a Manhattan length and represents a perpendicular distance between two points.

However, these techniques have poor accuracy in places where the wiring congestion is high, and the processing speed becomes difficult in actual wiring. Specifically, the following (1-1) to (1-13) occur.
(1-1) The designer implements based on the determined specification, but it is difficult to judge the quality of the specification and the floor plan, and the design cannot be performed when the timing allocated in the specification is biased. Or the redundant circuit for timing adjustment increases.

(1-2) When a plurality of designers perform distributed design in parallel based on the specifications of the design part, it is difficult for each designer to grasp the timing distribution of the upper hierarchy and the lower hierarchy in his own design. It is difficult to distribute and verify the timing of the entire system composed of PCBs and LSIs.
(1-3) When the timing specifications are not satisfied when the designer implements, the designers must negotiate with other designers affected by the change for the specification change, and cannot be changed. In some cases, it is necessary to change the upper architecture, which greatly increases the design period.

(1-4) As for the accuracy of the used parts or circuit blocks, the accuracy defined in the timing library is different. Therefore, when designing by combining a plurality of parts, a part with poor accuracy affects a part using the part with high precision, and the designer cannot accurately grasp the timing of the part.
(1-5) Since the above Manhattan length wiring does not consider the diagonal wiring on the PCB, a difference from the actual wiring delay appears greatly.

(1-6) If the wiring congestion level is dense, the wiring delay value calculated by the Manhattan length has a large error from the delay value of the actual wiring, and a timing error is likely to occur.
(1-7) In the netlist expressed by the circuit diagram or source code, the perspective relationship between the pins on the transmission side and the pins on the reception side is logically determined until a layout result is obtained. The designer cannot know.

  (1-8) A technology between PCB technology and LSI technology when considering whether to transmit signals using wiring on the PCB or to arrange a module inside the LSI when dividing LSI and PCB More man-hours are required to switch and judge. Further, when a design is inherited from an PCB floor plan to an LSI floor plan, the designer must input the floor plan again using an LSI-dedicated floor plan tool, which increases man-hours.

(1-9) When examining specifications, it is difficult for a designer to determine whether to use a temporary wiring or an actual wiring for the wiring of each net.
(1-10) It is difficult to grasp the number of necessary wiring layers.
(1-11) Due to the increase in the number of pins of LSI, the man-hour for allocating timing for each pin is large.

(1-12) In the PCB architecture design process, the designer cannot perform waveform analysis before the LSI is completed.
(1-13) In the architecture design process, due to the influence of wiring delay, the designer cannot examine whether signals between blocks can be transmitted in one clock.
In addition, although the flow direction of the flowchart shown in FIG. 49 is unidirectional, timing distribution may be determined in the architecture design process, and it is necessary to be able to change the design process flexibly.

  The present invention was devised in view of such problems, and in system circuit design, with regard to LSI and PCB timing distribution, the downstream process is reworked by timing distribution and timing verification in consideration of the floor plan in the upstream process. The purpose is to provide a timing distribution device that can reduce the design period and improve the quality while reducing the design period, and also to allow other designers to refer to the contents of the change when the circuit is changed. And

  Therefore, the timing distribution device of the present invention is provided corresponding to each of a plurality of design hierarchies, and receives block information related to the function of the circuit from a plurality of timing information databases having netlist information related to the wiring form, A plurality of timing distribution creation units capable of outputting timing distribution values obtained by allocating delay values generated by delay elements, and connections between each of the plurality of timing distribution creation units are dynamically changed, and a plurality of timing distributions It is characterized by comprising an inter-tier cooperation manager that transmits and receives correction information related to the timing distribution value and between each of the creating units (claim 1).

  The timing distribution creating unit is configured as an agent having a hierarchical entity having design information provided corresponding to each of a plurality of design hierarchies and program data for processing the design information. The cooperation manager may be configured as a manager that is connected to a timing distribution creating unit as an agent and transmits / receives information on timing distribution values to / from each of a plurality of design layers.

  Thus, according to the timing distribution device of the present invention, in hierarchical design, blocks related to circuit functions from a plurality of timing information databases provided corresponding to each of a plurality of design hierarchies and having netlist information relating to wiring forms. Dynamically change the connection between each of the multiple timing distribution generators and the multiple timing distribution generators that can output timing distribution values obtained by allocating delay values caused by delay elements of the circuit. In addition, since it is configured with inter-tier cooperation managers that send and receive correction information related to timing distribution values between each of a plurality of timing distribution creation units, the scope of influence when timing specifications are changed Reference can be made immediately, and there is no reference error in specification changes. In addition, the combination of temporary wiring and actual wiring can improve both floor plan execution speed and accuracy. Furthermore, hierarchical entities can be used, a distributed design environment can be constructed, only the necessary parts can be detailed in top-down design, and the quality of the timing specifications divided by trial examination can be examined by one design team at the time of implementation. Problem can be predicted and rework can be reduced (claim 1).

  Further, the timing distribution creating unit is configured as an agent provided corresponding to each of a plurality of design hierarchies and having a hierarchy entity having design information and program data for processing the design information, and an inter-layer cooperation manager May be configured as a manager that is connected to a timing distribution creation unit as an agent and transmits / receives information on timing distribution values to / from each of a plurality of design hierarchies. When timing-driven layout processing that combines design and physical layout is performed, the flow of information between each logical hierarchy and physical hierarchy is clarified, and cooperation is facilitated (claim 2).

Embodiments of the present invention will be described below with reference to the drawings.
(A) Description of First Embodiment of the Present Invention FIG. 1 is a configuration diagram of a circuit design apparatus according to a first embodiment of the present invention. A circuit design apparatus 1 (hereinafter sometimes referred to as a design apparatus 1) shown in FIG. 1 designs a semiconductor circuit, and includes a circuit information database 2, an automatic design processing unit 3, and a design information database 5. It is configured with.

  Here, the circuit information database 2 holds information about the circuit, and the automatic design processing unit 3 can read the information about the circuit from the circuit information database 2 and process the circuit for each unit to be processed. The design information database 5 includes design information including circuit element specific information obtained in the automatic design processing unit 3, change history information indicating the history of circuit changes, and circuit terminal load / drive capability information. Is to hold.

As a result, the automatic design processing unit 3 reads out information about the circuit from the circuit information database 2, performs circuit processing for each unit to be processed, and writes the obtained design information and the like in the design information database 5. The automatic design processing unit 3 reads desired design information from the design information database 5 according to the processing content.
Here, the circuit information database 2 holds circuit information for each processed unit (processed unit) in hierarchical design or ECO design, and other circuit modules process the circuit for each unit to be processed. Information can be referred to.

  In the circuit information database 2, source codes described in a hardware description language are classified and written in a format that can be easily processed by a computer program. For example, the hierarchy corresponding to the entity of the VHDL source code and the module of the Verilog HDL source code has various information. That is, each layer has component information such as a layer name, a layer terminal, a net list, a logic gate to be included, and a lower layer, and names and connection information thereof.

  Next, the design information database 5 holds information about changes made to the circuit and effects on other layers as information, and also holds a program for generating a test circuit and a program for optimizing the circuit. As a result, the circuit is created and updated. The design information database 5 includes a plurality of holding units (not shown) that can store circuit elements in individual files. Therefore, the design information is reflected in the circuit design, and the work efficiency such as the design period is improved.

Furthermore, in the design information database 5, the information shown in the following (2-1) to (2-4) is classified and held.
(2-1) Uniqueization information Instance name, name before uniqueization, name after uniqueization, and unit name that is the target of uniqueization processing. Here, the instance name is a unique name of a cell included in the target unit. Also, the unique processing (hierarchical unique processing) means that in the hierarchical design, when the upper layer refers to a unit having a predetermined function multiple times, the referenced unit is duplicated by the number of times of multiple references and the unique name is It means changing to a single reference unit that is given and referenced only once.

(2-2) Test circuit information The hierarchy name, the name and function of the additional terminal, the name and function of the added logic gate, and the connection order of the connection relationship (scan chain).
(2-3) Hierarchical Load Information Hierarchy name, size, input terminal name and load, output terminal name and drive capability, and fanout number.

(2-4) Hierarchy information The hierarchy name held in the circuit information database 2 and the vertical relationship between the hierarchies.
Thus, since each information is classified and held, the designer can design the circuit efficiently.
Next, the automatic design processing unit 3 includes an HDL reading unit 3a, a parameter input unit 3b, a processing result output unit 3c, and a calculation processing unit 4. The HDL reading unit 3 a reads a source code written in the HDL language and inputs the read data to the calculation processing unit 4.

  The parameter input unit 3b inputs a user-specified parameter (hereinafter sometimes referred to as a parameter) designated by the designer to the calculation processing unit 4. This parameter relates to the flow of processing. For example, in hierarchical design, information on which hierarchy is to be started, and a plurality of test circuits read by a test circuit rule input unit 3d (see FIG. 3) described later. It relates to information about which one of the information is to be selected.

  Furthermore, the processing result output unit 3c outputs the processing contents automatically designed by the calculation processing unit 4 in a fixed format, so that the designer can check the processing contents or perform subsequent design. It can be used for. The function of the automatic design processing unit 3 is realized by a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc., although not shown.

In addition, as a result, the designer simply inputs one parameter to the parameter input unit 3b, and these processes are automatically executed. The designer does not input separate parameters in each process. become able to.
Further, the calculation processing unit 4 performs circuit calculation processing. The calculation processing unit 4 includes an HDL conversion processing unit 4a, an individualization processing unit 4b, a test circuit generation processing unit 4c, a load adjustment processing unit 4d, and an HDL output processing unit 4e. It is composed.

The HDL conversion processing unit 4a receives a source code and a parameter, converts the source code based on the contents specified in the parameter, and outputs the converted data to the circuit information database 2.
FIG. 5 is a conceptual diagram of HDL conversion according to the first embodiment of the present invention. The HDL source codes 40a (CHIP), 40b (submod A), and 40c (sub mod B) shown in FIG. 5 are converted by the HDL conversion processing unit 4a (see FIG. 1) and written in the circuit information database 2. It is like that.

  Also, the data images 41a, 41b, and 41c shown in FIG. 5 conceptually represent what is held in the circuit information database 2. For example, terminal load / drive capability information (terminal information and (Abbreviated), net information, and element information are classified and held. Note that the HDL conversion may be performed all at once or dividedly and performed a plurality of times.

  Next, the unique processing unit 4b (see FIG. 1) reads the unique information from the design information database 5 and assigns different unique names to each unit to be processed. Further, the unique processing unit 4b reads the parameters and the circuit information database 2 converted by the above processing, and duplicates the plural reference unit data or changes the unique name.

  Further, the test circuit generation processing unit 4c can read the change history information from the design information database 5 and generate a test circuit of an upper hierarchy. The load adjustment processing unit 4d reads the terminal load / driving capability information from the design information database 5 and gives design information to each of the terminals included in the upper layer circuit, and adjusts the load based on the design information. .

  The HDL output processing unit 4e reads the parameters input by the parameter input unit 3b and the circuit information database 2, and writes necessary data in the source code (HDL source code). The unique processing unit 4b, the test circuit generation processing unit 4c, and the load adjustment processing unit 4d are all connected to the circuit information database 2 and the design information database 5, and read and hold data stored in them. Can be written.

  Each of the unique processing unit 4b, the test circuit generation processing unit 4c, and the load adjustment processing unit 4d performs hierarchical design and ECO design. Here, the hierarchical design is to design a circuit in a state in which one unit to be processed hierarchically includes other independently designed units. This hierarchical design makes it possible to design a large-scale circuit for each part.

The ECO design is to redesign without changing the part of the unit to be processed and changing the other part of the circuit.
With the hierarchical design and the ECO design, the design apparatus 1 can use the same operation procedure for circuit design.
Next, the unique processing unit 4b will be described in more detail with reference to FIG. 2, the test circuit generation processing unit 4c with reference to FIG. 3, and the load adjustment processing unit 4d with reference to FIG.

  FIG. 2 is a block diagram of the unique processing unit 4b according to the first embodiment of the present invention. The unique processing unit 4b shown in FIG. 2 processes a plurality of reference units in the circuit information database 2 for a single reference by assigning a unique name and duplicating data. In addition, the unique processing unit 4b has an additional function to cope with hierarchical design and ECO design, and includes a processing unit 100b that processes a circuit and a control unit 100a that controls the processing unit 100. The processing unit 100a and the control unit 100b are each realized by software, for example.

Here, since the thing which has the same code | symbol as what was mentioned above has the same thing or a similar function, the further description is abbreviate | omitted. The thick line between each part shown in FIG. 2 represents having connected. In addition, it can also be made to connect between each part other than these, respectively.
First, the processing unit 100b includes a design information reading unit 6b, a processing data acquisition unit 7b, a multiple reference analysis unit 8b, a unique name generation unit 9b, a circuit data replication unit 10b, a circuit information writing unit 11b, and a design information writing unit 12b. .

  The design information reading unit 6b reads the design information written in the design information database 5, and associates the hierarchical name before uniqueization with the hierarchical name after uniqueization, and uses the hierarchical name before uniqueization. It is possible to refer to the circuit data after uniqueization. Accordingly, the unique processing unit 4b can obtain the presence / absence of the unique processing and the hierarchical names before and after the unique processing, and determine whether or not the circuit data is unnecessary for processing and suppress the occurrence of the same unique name. Therefore, the design efficiency is improved.

  In addition, in the ECO design, the unique processing unit 4b uses the normal design information (design information of the design once completed before the ECO design) to design a circuit that is the same as the circuit that is normally designed except for the changed part. It is like that. Further, the design information reading unit 6b relates to the processing result of the first unit A obtained by processing the first unit A (the position of the first unit A obtained by processing the first unit A, etc.). The first unit information is read from the design information database 5. The design information reading unit 6b is connected to a memory (not shown) that temporarily holds data.

The processing data acquisition unit 7b acquires unit circuit data to be processed from the circuit information database 2 based on the processing target / non-processing target determined by the processing target determination unit 7a.
Thus, when the unique processing unit 4b processes the upper layer, the processing result for the lower layer is written in the design information database 5 by the design information writing unit 12b. The information held in the design information database 5 is read via the design information reading unit 6b, and then processed / unprocessed for the lower hierarchy written in the design information database 5 by the processing target determination unit 7a. The processing is recognized, and the processing target / non-processing target for the lower hierarchy is determined based on the recognition result.

In addition, the multiple reference analysis unit 8b searches for a location where a plurality of the same circuit units are used in the circuit, and determines a hierarchy, a cell, and a black box for the type of the circuit unit at the location. The multi-reference analysis unit 8b can efficiently perform the unique processing and can perform fine design.
Furthermore, the unique name generation unit 9b generates a unique name so that the reference relationship is the same as the reference relationship held in the design information database 5 when it is determined as the processing target by the processing target determination unit 7a. When it is determined that it is a processing target, a unique name different from the already assigned unique name is generated.

In other words, the proper name generation unit 9b generates a name so as to assign a proper name to each circuit unit that is determined as a processing target by the processing target determination unit 7a and is determined to be referred to plurally by the multiple reference analysis unit 8b. It is.
In addition, when designing each part using hierarchical design, the unique name generation unit 9b is also set for a single reference unit so that unique names do not overlap between circuits exceeding the design unit. Assign a unique name according to the naming rules (rules for assigning unique names).

Further, in the ECO design, the unique name generation unit 9b needs to assign the same unique name as the unique name assigned in the normal design to the circuit units having the same reference relationship, and is therefore stored in the design information database 5. The unique name for the ECO processing target circuit is generated using the reference relationship information and the unique name information.
In addition, the proper name generation unit 9b generates a proper name for each of the multiple reference units and the single reference unit determined by the multiple reference analysis unit 8b.

Furthermore, the unique name generation unit 9b should perform processing based on the naming rules set by the unique name assignment rule setting unit 9a except when an existing unique name is used in the design information database 5 in ECO design. For each unit, a unique name different from the unique name assigned to the already processed unit is generated.
As a result, when the processing object determination unit 7a determines that the unit to be processed is written with design information, a unique name is generated so as to have the same reference relationship, and the design information about the unit to be processed If it is determined that there is no writing, a unique name different from the already assigned unique name is generated.

This unique processing will be described later with reference to FIG.
The circuit data duplicating unit 10b assigns the unique name generated by the unique name generating unit 9b to each of a plurality of reference units and a single reference unit, and duplicates the circuit data. The circuit data is, for example, a circuit module 45 (see FIG. 6). The circuit information writing unit 11b writes circuit information in a database on the storage device.

In addition, the design information writing unit 12 b is connected to the design information database 5 and writes the processed hierarchy design information into the design information database 5. As a result, the information on the unique processing is accumulated and can be used to determine a portion that does not need to be processed at the time of higher layer processing or to assign the same unique name in the ECO design.
Further, the design information writing unit 12b collects first unit information related to the processing result of the first unit A and writes the first unit information in the design information database 5.

Next, the control unit 100a shown in FIG. 2 includes a design information reading control unit 6a, a processing target determination unit 7a, a multiple reference analysis control unit 8a, a unique name assignment rule setting unit 9a, a circuit data duplication control unit 10a, and circuit information writing. It has a control unit 11a and a design information write control unit 12a.
First, the design information reading control unit 6a analyzes the parameters obtained from the parameter input unit 3b, determines whether or not to acquire the unique information from the design information database 5, and inputs the design information reading unit 6b. It is an instruction.

The processing target discriminating unit 7 a discriminates the processing target / non-processing target for the unit to be processed based on the design information written in the design information database 5. The processing object discriminating unit 7a can obtain information held in the design information database 5 through the design information reading unit 6b.
Then, the processing target determination unit 7a determines whether or not the design information (specification information) for the unit currently being processed is written in the design information database 5 and recognizes that the lower hierarchy has been processed. The acquisition of the circuit data is stopped. Therefore, the working memory can be saved.

Further, the processing target determination unit 7a is a second unit to be processed next based on the first unit information regarding the processing result of the first unit A obtained by processing the first unit A in the design information. It is also determined whether or not the unit included in B is a processed unit.
As a result, the processing target discriminating unit 7a can easily determine the target portion to be processed based on the parameter input by the designer in the parameter input unit 3b and the unique information obtained from the design information reading unit 6b. It is determined to be.

Further, the processing object determination unit 7a controls the processing data acquisition unit 7b, whereby the processing data acquisition unit 7b acquires processing data from the circuit information database 2. Therefore, information regarding the portion to be processed can be easily obtained.
When the unique processing unit 4b performs the divided design based on the circuit hierarchical structure, when processing the upper layer, first, the design information reading unit 6b first processes the lower layer written in the design information database 5. The processed / unprocessed is read, and the processing target determining unit 7a determines the processing target / non-processed for the lower hierarchy based on the processed / unprocessed.

  Subsequently, the multi-reference analysis control unit 8a controls the multi-reference analysis unit 8b. The unique name assignment rule setting unit 9a sets a naming rule based on the design information database 5 so as to assign a unique name to each unit to be processed, based on parameters relating to the names of circuit elements. Then, the unique name assigning rule setting unit 9a analyzes the naming rule included in the parameter and the existing unique name included in the unique information.

Thereby, the unique name generation unit 9b can generate a unique name that conforms to the naming rule and does not overlap with other unique names.
The circuit data replication control unit 10a assigns a unique name to each of a plurality of reference units that are referred to a plurality of units and a single reference unit that is referred to a single reference and replicates data based on a naming rule. Specifically, the circuit data duplication control unit 10a controls the circuit data duplication processing so that the plurality of units to be referenced are individually referred to individually.

The circuit information writing control unit 11a controls the circuit information writing unit 11b. As a result, the process of writing the unique name and the copied data to the circuit information database 2 is controlled.
Furthermore, the design information writing control unit 12a controls the design information writing unit 12b. Then, the design information writing control unit 12a stores in the design information database 5 the unit name before the unit specification, the unit name after the specification, the information for specifying the position in the entire circuit, etc. Control to write.

In FIG. 2, information necessary for control is input from the design information database 5 to the control unit 100a through a route (dotted line) labeled L3, and a circuit ( The data of the design target) is processed from the design information database 5 through the route (dotted line) labeled L4 by the processing unit 100b.
In this way, control data and circuit data are transmitted in two systems, respectively, so that the design can be made efficiently.

Next, the process of the unique process part 4b is demonstrated using FIG. The unique processing unit 4b uses two types of methods so as not to duplicate unique names.
FIG. 6 is a diagram for explaining the unique processing according to the first embodiment of the present invention. The circuit module 43 shown in FIG. 6 includes circuit modules 43a and 43b (hereinafter, the circuit modules 43a and 43b are referred to as modules 43a and 43b, respectively), and these each include a circuit module 45. Here, the module 45 is a flip-flop or a latch circuit, for example, and is named A. The modules 43a and 43b are registers and counters, respectively, and their names are X and Y, respectively.

  The first method is a method in which a designer changes the setting of a naming rule for each unit to be processed using a parameter, and generates a name based on the set naming rule. In FIG. 6, the unique processing unit 4b sets the three modules 45 included in the module 43a to, for example, AX-0, AX-1, and AX-2, and includes two modules 45b included in the module 43b. These modules 45 are AY-0 and AY-1. That is, parameters are analyzed, and a plurality of referenced units (module 45) are duplicated as many times as the number of times they are referenced (three times or twice), and the duplicated unit (module) name is currently processed. It is generated so as not to overlap with the unit name inside.

  The second method is a method in which the designer generates names other than the names held in the design information database 5. That is, the unique processing unit 4b designates the three modules 45 included in the module 43a as A-0, A-1, and A-2, respectively, and assigns a name to the module 43b. Referring to the two modules 45 included in the module 43b without using A-0, A-1, and A-2 so that the names held in the design information database 5 are not duplicated, A −3, A-4.

Thus, in the hierarchical design, first, a naming rule is set for each unit to be processed based on parameters designated by the designer in the unique name assignment rule setting unit 9a (see FIG. 2). In the generation unit 9b, a unique name is generated for a unit to be processed based on the naming rule so as to be different from a unique name given to a unit that has already been processed.
According to these methods, a new name is generated based on the original unique name and the naming rule specified by the designer. For this reason, even if a plurality of new names are generated by the unique processing, the names can be clearly identified, and it becomes easy for the designer to group the names. Group by power unit. Furthermore, duplication of the processed unit and the name of the unit currently being processed is avoided.

Accordingly, when a new name is generated, the design information database 5 is referred to, and based on the set naming rules, the unique name information loaded in the setting information database 5 and the working memory (not shown) A unique name is generated.
For this reason, in the hierarchical design, even if the unique processing is performed for each part of the circuit, the names are given in consideration of all the names generated in the entire circuit, so that there is no duplication of names.

In this way, the unique processing unit 4b, when processing the upper layer, processes the lower layer included as a unit to be processed instead of acquiring information from the circuit information database 2 for the included lower layer. Information can be acquired from the design information database 5 in which results and the like are held.
Two types of circuit design methods of the present invention will be described.

In the first circuit design method of the present invention, first, the unique processing unit 4b reads out information about the circuit from the circuit information database 2 that holds information about the circuit, and designs a circuit for each unit to be processed. In the automatic design processing unit 3, the first unit information related to the processing result of the first unit A obtained by processing the first unit A is generated (processing generation step).
Subsequently, the unique processing unit 4b collects design information including the specific information of the circuit element being generated in the process generation step, the change history information indicating the history of changing the circuit, and the terminal load / drive capability information of the circuit. (Design information collection step)

The unique processing unit 4b writes the design information collected in the design information collecting step for each unit to be processed in the design information database 5 connected to the automatic design processing unit 3 and holding the design information (design information). Writing step).
Furthermore, when the unique unit 4b processes another unit later, the design information related to the first unit A is processed to process the second unit B based on the design information written in the design information writing step. (Refer step).

And the unique process part 4b recognizes the reference relationship about the design information regarding the 1st unit A referred in the reference step (recognition step). Therefore, the information in the design information database 5 is used, and it is checked whether or not the second unit B includes the already processed first unit A.
Subsequently, the unique processing unit 4b refers to the unit information regarding the position and the processing result held in the circuit information database 2 based on the reference relationship obtained in the reference step (circuit information database reference step). Next, the unique processing unit 4b updates the circuit data subjected to the design process (circuit information database writing step).

In this way, in the case of inclusion, it is automatically recognized whether or not the first unit A has been processed.
Accordingly, the design information writing unit 12b collects the first unit information related to the position of the first unit A and the processing result, and the first unit information is written into the design information database 5 and written. The first unit information is read by the design information reading unit 6b. Then, the processing target discriminating unit 7a discriminates whether or not the second unit B includes the first unit A based on the first unit information. It is determined whether the unit A is a processed unit.

Therefore, since the unique processing unit 4b automatically determines the processed unit, it is not necessary to read out the lower hierarchy from the circuit information database 2, and thus the work unit used for the specific processing is used. Memory capacity can be saved significantly.
In the second circuit design method of the present invention, first, the unique processing unit 4b reads out information about the circuit from the circuit information database 2 that holds information about the circuit, and selects a circuit for each unit to be processed. In the automatic design processing unit 3 that can be designed, the fourth unit including the third unit C is processed (first processing step).

Next, the unique processing unit 4b collects third unit information related to the processing result of the third unit C being generated in the first processing step (third unit information collecting step).
Further, the unique processing unit 4b writes the third unit information collected in the third unit information collecting step into a design information database connected to the automatic design processing unit 3 and holding design information (design information writing step). .

Then, based on the third unit information written in the design information writing step, the unique processing unit 4b changes the fourth unit from the third processed unit obtained by changing the third unit C. It is determined whether or not the obtained fourth processed unit is included, and it is determined whether or not the third processed unit is equivalent to the third unit C (determination step).
As described above, by using the two types of circuit design methods of the present invention, it is possible to perform continuous processing by full automation, and it is possible to reduce the processing time and hence the design period.

  A designer or a person in charge of system construction (hereinafter sometimes referred to as a designer or the like) constructs the design apparatus 1 using a personal computer or a workstation (hereinafter referred to as a computer). That is, a designer or the like creates a software program and stores it in a hard disk of a computer, and the program can execute the above-described processing on the computer.

  The program of the present invention reads out information related to a circuit from the circuit information database 2 that holds information related to the circuit, designs a circuit for each unit to be processed, and provides circuit element specific information obtained by the design. The design information database 5 is made to function so as to hold design information including change history information indicating a history of circuit change and terminal load / drive capability information of the circuit.

In other words, the function of the automatic design processing unit 3 is realized by the program being read and executed by the CPU of the computer.
Note that the method of installing the program of the present invention on the hard disk is based on a reading device of the computer, such as a CD-ROM (Compact Disk-Read Only Memory), a CD-R (CD-Recordable), a CD-RW (CD -Rewritable) and recording media such as floppy disks.

In this way, designers and the like can easily construct an environment for designing a large-scale circuit.
Moreover, the program of this invention functions to make a computer perform each step shown below. That is, the program of the present invention first reads the information about the circuit from the circuit information database 2 holding the information about the circuit, and in the automatic design processing unit 3 that can design the circuit for each unit to be processed, first, The first unit information related to the processing result of the first unit A obtained by processing the unit A is generated (processing generation step), the unique information of the circuit element being generated, and the change history representing the history of changing the circuit Design information including information and circuit terminal load / drive capability information is collected (design information collection step).

Then, this program writes the collected design information for each unit to be processed in the design information database connected to the automatic design processing unit 3 and holding the design information (design information writing step), and the written design In order to process the second unit B based on the information, the design information related to the first unit A is referred to (reference step).
Further, the program recognizes the reference relationship for the design information related to the first unit A that has been referenced (recognition step), and based on the obtained reference relationship, the position and processing result held in the circuit information database 2 The unit information is referred to (circuit information database reference step), and the computer is caused to function so as to update the designed circuit data (circuit information database write step).

In this way, continuous processing is possible by full automation, so that the processing time can be reduced and the design period can be shortened.
Further, the program of the present invention causes a computer to function so as to execute the following steps. That is, the program of the present invention reads the information about the circuit from the circuit information database 2 holding the information about the circuit, and in the automatic design processing unit 3 that can design the circuit for each unit to be processed, the third unit Is processed (first processing step), third unit information related to the processing result of the third unit being generated is collected (third unit information collecting step), and the collected third unit is collected. The unit information is written in a design information database connected to the automatic design processing unit 3 and holding the design information (design information writing step).

Subsequently, the program calculates the fourth processed unit obtained by changing the fourth unit D from the third processed unit obtained by changing the third unit based on the written third unit information. In addition to determining whether or not to include, the computer is caused to function to determine whether or not the third processed unit is equivalent to the third unit (determination step).
In this way, continuous processing is possible by full automation, so that the processing time can be reduced and the design period can be shortened.

Next, the unique process in the ECO design will be described.
FIGS. 7A to 7D and FIG. 8 are diagrams for explaining the unique processing in the ECO design according to the first embodiment of the present invention. The chip 80 shown in FIG. 7A includes modules A and C, and each of the module A and the module C includes a module B. In the normal design, when uniqueization is executed, a unique module name as shown in FIG. Then, as shown in FIG. 7B, the module A is written with the name A-1 and the module C is written with the name C-1 in the change history. Similarly, module B in module A is written as name B-1, and module B in module C is written as name B-2.

  The circuit shown in FIG. 7C is a circuit for starting ECO design when the logic of any module (for example, module B) of this circuit is changed. Then, it is determined whether or not the information about the unit currently being processed is held in the design information database 5, and if it is held, it is written in the design information database 5 as shown in FIG. The name is generated so that the reference relationship is the same as the reference relationship. On the other hand, when not held, a name is generated so as not to overlap with the name of another unit written, although not shown.

If the design information is not referred to, a unique name different from the unique name at the time of normal design as shown in FIG. 8 may be given in the ECO design. Names may become inconsistent when compared.
Therefore, in the ECO design, the part other than the part where the circuit change has occurred can be restored to the same level as the old circuit. In other words, in the unique process, the hierarchical name after the unique process is assigned the same name as when designing the old circuit, so that the ECO process can be continued from the circuit before the unique process.

Further, the unique processing unit 4b uses the unique information when the unique information data is input from the design information database 5 created by the design of the old circuit, and uses the unique information in the hierarchy having the same instance name. The same unique name as that of the old circuit can be automatically given to those that have not yet been made unique.
In this way, the hierarchy of the old and new circuits can be matched.

  In this way, since the unique processing unit 4b reads the unique information at the time of normal design as the design information, the entire chip 80 shown in FIG. 7C uses the circuit before the unique design. Even if reprocessing is not performed, reprocessing may be performed using circuit information in the design completion state of the chip 80 shown in FIG. 7B and circuit information of the module (for example, module B) that has been changed. Is possible. At this time, even if the design information when the normal design is completed indicates that “all modules have been specified”, in the ECO design process, the parameter-designated ECO design target module is forcibly restarted. It is processed.

Further, details of the test circuit generation processing unit 4c and the load adjustment processing unit 4d shown in FIG. 1 will be described in detail with reference to FIGS. 3 and 4, respectively.
FIG. 3 is a block diagram of the test circuit generation processing unit 4c according to the first embodiment of the present invention. The test circuit generation processing unit 4c shown in FIG. 3 has an additional function to cope with hierarchical design and ECO design, and a processing unit 101b that processes the circuit and a control unit 101a that controls the processing unit 101b. And a test circuit rule input unit (test circuit rule input unit) 3d is provided on the input side of the control unit 101a. Further, what is shown in FIG. 3 and has the same reference numerals as those described above has the same or similar functions, and therefore further explanation is omitted. The thick lines between the parts are the same as those shown in FIG.

  Here, the test circuit rule input unit 3d inputs test circuit information on how to generate a test circuit to the test circuit generation processing unit 4c. The test circuit information is, for example, details about a method called scan (takes out a signal from the circuit or sets the signal), a method called bist (embedding a circuit for automatic last), and the like. Information. Then, the designer selects a desired file from a plurality of files in which necessary test circuit information is written, and thus the selected file is automatically read when the design apparatus 1 is activated. It is supposed to be.

First, unlike the processing unit 100b of the unique processing unit 4b, the processing unit 101b includes a circuit analysis unit 8d, a test circuit generation unit 9d, and a hierarchical consistency restoration unit 10d.
Based on the design information database 5, the circuit analysis unit 8d uses the normal design information and test circuit rules created during normal design for the ECO design target unit, and can generate the same test circuit as during normal design. The identification data for identifying each of the parts where a new test circuit is to be generated is extracted. Thereby, the usage amount of the working memory is optimized.

  Based on the identification data extracted by the circuit analysis unit 8d, the test circuit generation unit 9d generates the same test circuit for the portion that can generate the same test circuit as that at the time of normal design for the ECO design target unit. A test circuit is generated in accordance with a test circuit rule for a portion where a circuit is to be generated. Thereby, the design efficiency of the test circuit in the ECO design is greatly improved.

Based on the design information stored in the design information database 5, the hierarchical consistency restoration unit 10d detects terminal mismatch between the terminal added for test signal input to the lower hierarchy and the terminal in the hierarchy referenced by the upper hierarchy. Thus, the operability of the designer in the ECO design is greatly improved.
Further, the hierarchical consistency restoration unit 10d restores hierarchical consistency by using normal-time design information for normal design, ECO design target unit, and terminal information in the upper hierarchy among the design information in ECO design. It is like that.

  Next, unlike the control unit 100a of the unique processing unit 4b, the control unit 101a includes a circuit analysis control unit 8c, a test circuit generation control unit 9c, and a hierarchical consistency restoration control unit 10c. Here, the circuit analysis control unit 8c controls the circuit analysis unit 8d, the test circuit generation control unit 9c controls the test circuit generation unit 9d, and the hierarchical consistency restoration control unit 10c performs hierarchical matching. It controls the property restoration unit 10d.

The control unit 101a and the processing unit 101b are each realized by software, for example.
As in the unique processing unit 4b (see FIG. 2), information necessary for control is input from the design information database 5 to the control unit 101a through the route labeled L3, Is processed by the processing unit 101b from the design information database 5 through the route labeled L4.

In this way, control data and circuit data are transmitted in two systems, respectively, so that the design can be made efficiently.
Next, the hierarchical design of the test circuit generation processing unit 4c will be described with reference to FIGS. 9A and 9B, and the ECO design will be described with reference to FIGS.
9A and 9B are diagrams for explaining test circuit generation processing in the hierarchical design according to the first embodiment of the present invention. The circuit module C (module C) shown in FIG. 9A includes two circuit modules (two internal squares). In addition, the circuit module D shown in FIG. 9B includes other circuit modules in addition to the module C.

  Then, the test circuit generation processing unit 4c reads the terminal name from the circuit information database 2 in order to connect the module C shown in FIG. 9B and another module. More specifically, it is determined whether or not the third unit C is written in the design information database 5 by the processing object determination unit 7a (see FIG. 3). When it is determined that the third unit C has been written, the design information held in the design information database 5 for the third unit C is read, and necessary design information is acquired by the processing data acquisition unit 7b. Then, the test circuit generation unit 9d generates a test circuit via the circuit analysis unit 8d.

In other words, in the hierarchical design, when the third unit C is processed and then the fourth unit D including the third unit C is processed, the third unit C is converted into the fourth unit D. Even if it is referred to, whether or not the information is stored in the design information database 5 is automatically determined, and when it is stored, the circuit of the fourth unit D is changed by the information.
Next, FIGS. 10A to 10D are diagrams for explaining the test circuit generation processing in the ECO design according to the first embodiment of the present invention, taking a test scan chain as an example. explain. The chip 82 shown in FIG. 10A includes a circuit module G (module G), and the module G includes a plurality of flip-flops (FF). The circuit shown in FIG. 10B is a scan completion circuit, and a plurality of flip-flops (FF) in the module G are connected to each other, and terminal information of the circuit is given to the module G and the circuit. Is connected to the terminal.

  In the test circuit generation process, it is necessary to restore the test circuit of the old circuit except for the part changed by the ECO process. Therefore, the test circuit generation processing unit 4c reads the design information database 5 created in the design of the old circuit, and adds the same terminal, the same logic gate, the connection of the same test scan chain, etc. Restore the equivalent test circuit. Then, a new test circuit is generated at a location where the circuit has been changed.

For example, the circuit shown in FIG. 10C is obtained by changing the module G by the designer, and becomes a module G ′. This module G ′ is in a state where the scan completion circuit does not exist, like the module G of FIG.
The module G ′ shown in FIG. 10D is a restored test circuit, and the test circuit generation processing unit 4 c reads the history information from the design information database 5 and recognizes the connection between the flip-flops and the test terminal name. Then, a test scan chain equivalent to the old circuit is generated.

In this way, in the test circuit generation process, the added terminal information, the added logic gate information, and the test circuit connection information are written as design information.
Further, in this way, in the upper layer processing, each circuit module acquires the lower layer test circuit information from the design information database 5 to generate the upper layer test circuit.

Further, in this way, in the ECO design, it is not necessary to compare the old circuit and the new circuit, and the comparison of the circuit and the difference analysis are not required, so that complicated processing is unnecessary. Since the designer does not need to input information, the design efficiency is greatly improved.
In this way, design information when the old circuit is designed is used, and the parts other than the circuit change portion of the new circuit can be automatically restored to the same level as the old circuit.

  In addition, the test circuit generation processing unit 4c shown in FIG. 3 uses the design information database instead of the circuit information database 2 for the included lower layer when processing the upper layer, similarly to the unique processing unit 4b. 5 to obtain information. Specifically, the test circuit generation processing unit 4c acquires a processing result or the like designed as a unit for processing a lower hierarchy, and automatically determines the processed part.

In this way, the circuit information database 2 for the lower hierarchy is not required, and the capacity of the working memory used for the test circuit generation process can be greatly saved.
Next, the load adjustment processing unit 4d will be described with reference to FIG.
FIG. 4 is a block diagram of the load adjustment processing unit 4d according to the first embodiment of the present invention. The load adjustment processing unit 4d shown in FIG. 4 includes a processing unit 102b that processes a circuit and a control unit 102a that controls the processing unit 102b. 4 having the same reference numerals as those described above have the same or similar functions, and thus redundant description is omitted. These are all connected to the circuit information database 2 and the design information database 5.

Unlike the processing unit 100b of the unique processing unit 4b, the processing unit 102b includes a terminal load / driving capability setting unit 8f, a load analysis unit 9f, and a circuit adjustment unit 10f. Unlike the control unit 100a of the unique processing unit 4b, the control unit 102a includes a terminal load / drive capability setting control unit 8e, a load analysis control unit 9e, and a circuit adjustment control unit 10e.
Here, the terminal load / drive capability setting unit 8f gives load information and drive capability information obtained by load adjustment processing in the lower layer to each of the lower layer terminals referenced from the upper layer circuit. The terminal load / driving capacity setting unit 8 f sets the hierarchical load capacity value of the hierarchical terminal stored in the design information database 5.

  The load analyzing unit 9f analyzes a terminal capacity that can be driven by a logic gate (logic element), and extracts a terminal that cannot be driven. Specifically, the load analysis unit 9f cannot drive by evaluating the driving capacity of the logic gate and the total load capacity calculated from the load capacity and wiring capacity of the driven logic gate and the hierarchical terminal in the processed hierarchy. The part is extracted. Here, the load capacity and drive capability of the hierarchical terminal in the processed hierarchy are set by using the information in the design information database 5 by the terminal load / drive capability setting unit 8f.

More specifically, when the driven side is a logic gate, the load capacity value is obtained from a technology library (not shown). Also, the load capacity of the wiring to be driven is calculated based on the wiring length and the number of branches. When the driving side is a logic gate, the driving capability value is acquired from the technology library.
The circuit adjustment unit 10f adjusts the undriveable terminals extracted by the load analysis unit 9f. Specifically, the circuit adjustment unit 10f replaces the logic gate from which the error has been extracted by the load analysis unit 9f with a logic gate having a larger driving capability, or buffers the portion having a large fanout number. Adjust to distribute load by inserting into circuit. Thereby, each terminal in the circuit is adjusted to an appropriate capacity.

The terminal load / drive capability setting control unit 8e, load analysis control unit 9e, and circuit adjustment control unit 10e control the terminal load / drive capability setting unit 8f, load analysis unit 9f, and circuit adjustment unit 10f, respectively. is there.
As in the unique processing unit 4b (see FIG. 2), information necessary for control is input from the design information database 5 through the route labeled L3 to the control unit 102a. Is processed by the processing unit 102b from the design information database 5 through the route labeled L4.

As a result, load information is adjusted for each divided unit, and design information is created by setting the load and drive capacity obtained from the specifications of the logic gate in the hierarchy to each terminal of the highest hierarchy of that unit. The Then, when load adjustment is executed in a higher hierarchy, processing is performed by obtaining the load and drive capability information from the design information database 5.
Next, the load adjustment process will be described with reference to FIGS.

  FIGS. 11A to 11D are diagrams for explaining load adjustment processing in the hierarchical design according to the first embodiment of the present invention, and are mainly processed by the circuit adjustment unit 10f. . The chip 83 shown in FIG. 11A includes modules A, B, C, and D, and a logic gate (hereinafter sometimes referred to as a gate) LG exists between the modules A and B. There is also.

  First, when the load adjustment of the module A or the like is performed, a circuit composed of logic gates as shown in FIG. 11B is included. Since the gate G1 shown in FIG. 11B drives the four logic gates of the gate group G2, there is a possibility that the driving capability is insufficient and the driving becomes impossible. Here, in order to enable driving, the gate G1 is replaced with a logic gate having a larger driving capability with the same logic, or a buffer 66 is inserted as shown in FIG. The number of logic gates driven by the gate is reduced. The load adjustment of each of the modules A to D is processed by such a method.

Further, when the load adjustment of the module A is processed, the input terminal of the module terminal (also referred to as a hierarchical terminal) can be represented by the load capacity value of the logic gate that is driven beyond that, The output terminal of a module terminal can be represented by the drive capability of a logic gate that transmits a signal to that terminal.
In this way, as shown in FIG. 11 (d), the terminal load / drive capability information is written as a file in the design information database 5 for each of the modules A to D.

As a result, in the hierarchical design, after the modules A to D have once completed the load adjustment, the chip level load adjustment is executed, and information on the driving ability and the load of the modules A to D is used.
In addition, the load adjustment processing unit 4d shown in FIG. 4 is similar to the unique processing unit 4b and the test circuit generation processing unit 4c. Instead, the design information database 5 is accessed to obtain a processing result or the like designed as a unit for processing a lower hierarchy, and the processed portion is automatically determined.

In this way, the circuit information database 2 for the lower hierarchy is unnecessary, and the capacity of the working memory can be greatly saved in circuit calculation.
With the above configuration, the flow of circuit data will be described with reference to FIG. 12, the hierarchical design will be described with reference to FIGS. 13 and 14, and the ECO design will be described in detail with reference to FIGS.

  FIG. 12 is a diagram for explaining the flow of circuit data according to the first embodiment of the present invention. A circuit module image 42a (hereinafter referred to as a module 42a) shown in FIG. 12 is a data image held in the circuit information database 2, and includes submodules A and B (submod A, submod B). The submodule A includes circuit elements A1 and A2, and the submodule B includes circuit elements B1 and wirings D1, D2, and D3.

  Furthermore, the circuit module image 42b (hereinafter referred to as module 42b) is a data image after being processed by the automatic design processing unit 3. The sub-module A of the module 42a is wired between the circuit elements A1 and A2 by the test circuit generation process, and is given test terminals A3 and A4 (labeled SI and SO). Further, in the sub-module B of the module 42a, the circuit element B2 is provided on the wirings D1 to D3 by load adjustment.

  The data images 41d and 41e are both stored in the design information database 5, and the test terminal information generated by the test circuit generation processing and the scan chain information are generated by the circuit generation of the submodule A of the module 42b. Retained as information. Further, the information generated by the load adjustment process is held as the load capacity information and drive capability information of the submodule B.

Thus, in order to process the module 42a at a time, even when the working memory is insufficient, the processing of the submodule A, the processing of the submodule B, and the processing of the module 42a using the design information database 5 are sequentially performed. By doing so, processing can be performed with a small working memory.
FIG. 13 is a diagram showing a data image of the semiconductor circuit A according to the first embodiment of the present invention. A semiconductor circuit A shown in FIG. 13 is a chip (hereinafter sometimes referred to as chip A) in a predetermined hierarchy, and circuit modules B and D (hereinafter referred to as modules B and D) and two circuit modules. C (hereinafter referred to as module C). Further, these modules B, C, and D each include a sub module X.

Then, for this semiconductor circuit A, HDL conversion processing, unique processing, test circuit generation processing, and load adjustment processing are executed in the order of modules B, C, D, X, and A.
In the following description, this module is also used as a unit (unit to be processed or processed unit).
FIG. 14 is a flowchart for explaining hierarchical design according to the first embodiment of the present invention. First, in step A1, the data of the semiconductor circuit (chip) A described in HDL is converted into the circuit information database 2. Modules B, C, and D are held in the circuit information database 2 by the HDL conversion.

Next, module B and the module belonging to module B are processed in step A2. That is, the unique processing is performed (step A2x), the test circuit generation processing is performed (step A2y), and the load adjustment processing is performed (step A2z). Further, the information changed by these processes is held in the design information database 5 respectively.
Subsequently, the processing of module C and the module belonging to module C is performed in step A3. That is, the unique processing (step A3x), the test circuit generation processing (step A3y), the load adjustment processing (step A3z), and the information changed by these processing are held in the design information database 5, respectively. .

Similarly, processing of module D and modules belonging to module D is performed in step A4. That is, the unique processing (step A4x), the test circuit generation processing (step A4y), the load adjustment processing (step A4z), and the information changed by these processing are held in the design information database 5, respectively.
Then, in step A5, it is determined whether or not a hierarchy that may cause a shortage of working memory capacity due to chip level processing has already been processed. If it has not been processed, the route passes through the N route to step A6. The unprocessed hierarchy is processed, and when it has been processed, the Y route is taken.

  Here, when processing the chip A in step A7, the information on the included modules B, C, and D is already held in the design information database 5, so that the information on the chip A is obtained from the circuit information database 2. It is read, necessary information is acquired from the design information database 5, and the circuit is changed. Furthermore, no reference is made to the entities relating to modules that have already been processed.

  First, an unprocessed portion of the chip A is subjected to a unique process (step A7x), a test circuit generation process (step A7y), and a load adjustment process (step A7z). In the test circuit generation process and load adjustment, the information of the modules B, C, and D held in the design information database 5 is referred to change the circuit of the chip A. Here, the actual circuit information is not referred to. Subsequently, in step A8, gate level data (HDL data or the like) of the completed chip A is output as the gate level, and the process proceeds to the physical design process.

As described above, when the information of the chip A is read from the circuit information database 2, only necessary information is acquired from the design information database 5, and design is performed without acquiring information for circuits that do not need to be changed.
Further, even when a plurality of processed modules are referred to in this way, the information held in the design information database 5 is used, so that the circuit of the module in the upper hierarchy can be changed.

Next, the ECO process will be described.
FIG. 15 is a view showing a data image of another semiconductor circuit (chip) A according to the first embodiment of the present invention. The chip A shown in FIG. 15 includes circuit modules B, C, D, and E (hereinafter referred to as modules B, C, D, and E). Here, the submodule Y-0 included in the module C is a module after the designer has completed the design once. The submodule Y-0 is replaced with a submodule having the name Y ′ due to a design change by the designer. Note that the names A, B, C, and D shown in FIG. 15 are all different from those shown in FIGS.

As a premise, the whole chip A to be designed has already been designed using the design apparatus 1. Then, it is assumed that the designer holds the design information database 5 generated at the completion of the design in addition to the circuit information database 2 including the circuit information of the module to be subjected to ECO processing.
When the designer does not change the logic of the circuit, the designer does not change the circuit that has been designed by using the design apparatus 1 but changes the circuit before that. This circuit is a circuit created by a designer based on specifications. The changed information is re-input to the circuit information database 2 by HDL conversion.

Then, the designer inputs the changed module name as a parameter to the design apparatus 1. The design apparatus 1 reads out the hierarchical information in the design information database 5 from this name, selects only the necessary circuit information from the circuit information database 2 and loads it into the working memory.
Here, when a plurality of modules to be subjected to ECO design are modules that are referred to, and designation is necessary, the design apparatus 1 refers to designation information in the design information database 5. If the referenced module is a module that has existed at the time of previous uniqueization, the same name is assigned again.

On the other hand, if the referenced module is a module that does not exist in the unique information of the design information database 5 and is newly added, the design apparatus 1 holds it in the currently referred design information database 5. Change the name so that it does not overlap with other modules within the scope of the information.
If the designer adds a terminal that was not at the time of the previous process or reduces the number of terminals and does not design the ECO, the design apparatus 1 generates an error as an HDL description violation. On the other hand, when it is ECO design, the design apparatus 1 refers to the design information database 5 and accepts the temporary inconsistency.

  Furthermore, the design apparatus 1 refers to the design information database 5 and restores the same circuit as the circuit added at the previous processing as much as possible even if it is included in the module that is the target of ECO design. . At this time, the correspondence between the information in the design information database 5 and the circuit in the ECO design target module is determined by a match of instance names or the like, and both are included in the additional circuit having the same configuration as the previous process. To be processed.

Next, the ECO process will be described with reference to FIGS. FIGS. 16A and 16B are flowcharts for explaining the ECO processing according to the first embodiment of the present invention. Here, FIG. 16A shows a normal process, and FIG. 16B shows an ECO process of the present invention.
First, in FIG. 16A, the HDL data of the unfinished semiconductor circuit A is converted into the circuit information database 2 (step B1), subjected to unique processing (step B2), and subjected to test circuit generation processing (step B3). Then, the load adjustment processing is performed (step B4), and the HDL data of the semiconductor circuit A completed as the gate level is output (step B5).

  In FIG. 16B, the HDL data of the semiconductor circuit A once completed and the HDL data of the submodule Y whose circuit has been changed are converted into the circuit information database 2 (step C1), and step C2 In FIG. 5, the unique process is performed based on the history of the normal process to obtain a new submodule Y ′, and this name Y ′ is changed to the name Y-0. Further, the restoration of the hierarchical structure is confirmed (step C3), the test circuit generation process is performed based on the history at the time of normal processing (step C4), the restoration of the connection relation is confirmed (step C5), and the history at the time of normal processing is based. Then, the load adjustment processing is performed (step C6), and the HDL data of the semiconductor circuit A for which the ECO processing is completed is output (step C7).

  As described above, the design apparatus 1 according to the present invention performs the processing when each layer is processed without referring to the circuit information database 2 over the entire circuit in the hierarchical design or ECO design of a large-scale semiconductor circuit, or the previous processing. Since the design information database 5 automatically extracted is referenced and the relationship between modules is automatically recognized and processed, the amount of work memory used can be optimized and the designer's burden can be designed in a batch. Can be reduced to the same level.

In addition, since all the processes are automated in this way, it is possible to execute multiple processes continuously, reducing the processing time and consequently the design period, and the unique process and test. Design efficiency is improved for each of the circuit generation processing and the load adjustment processing.
In this way, for example, terminal boundary information and design information such as terminals are automatically input, and from the history information, a non-processing target part in the current processing is automatically determined, and the non-processing target part Is automatically extracted and used to process the part currently being designed.

Therefore, in this way, hierarchical design can be easily realized, and hierarchical design of large-scale circuits can be performed very efficiently.
(B) Description of Second Embodiment of the Invention The second embodiment relates to a timing distribution device in circuit design. In this circuit design, timing distribution including PCB design and LSI design is designed.

  FIG. 17 is a diagram showing a circuit design process according to the second embodiment of the present invention. First, a system specification is designed (step P1), a system architecture is examined in step P2 (step P2x), and block division of PCB and LSI is designed (step P2y). Subsequently, after the PCB timing specifications are designed (step P3), the PCB is implemented (step P4). On the other hand, for the LSI, after the timing specification is designed (step P5), the LSI is implemented (step P6).

  The design of the PCB timing specifications and the design of the LSI timing specifications can be carried out by sharing data closely with each other. The timing distribution device of the present invention is preferably used in a process between Step P2 to Step P3 or Step P5, and is preferably used for distributed design, and has a significant influence on the implementation of PCB or LSI. Give. The steps P3 and P5 are designed independently, but the data under design can be referred to each other.

  FIG. 18 is a diagram showing the process of block division design according to the second embodiment of the present invention. Of the step names shown in FIG. 18, the same steps as those shown in FIG. 17 represent the same steps. Here, in step P2y, the block is divided into PCB and LSI, and block information is generated. In step P7, timing distribution (PCB, LSI) is designed. Specifically, the timing distribution is determined based on block information, constraint definition information, HDL source code (hereinafter sometimes abbreviated as source code) and library data described later. On the other hand, design contents are reflected in the source code (step P8), logic simulation with timing becomes possible (step P9), and PCB or LSI is implemented (steps P4 and P6).

  FIG. 19 is a configuration diagram of a circuit design apparatus according to the second embodiment of the present invention. The circuit design device 1a shown in FIG. 19 (hereinafter sometimes referred to as the design device 1a) designs a circuit, and includes a timing distribution device 51 and a distribution report creation unit 50d. Yes. 19 is connected to layout CAD devices 52a and 52c and a waveform analysis CAD device 52b. Here, the layout CAD devices 52a and 52c are designed for the layout for LSI / PCB, respectively, and the waveform analysis CAD device 52b is for analyzing the waveform of the circuit. Both the LSI and the PCB are analyzed. Can design.

  FIG. 20 is a block diagram of a timing distribution device 51 according to the second embodiment of the present invention. The timing distribution device 51 (hereinafter also referred to as the present device 51) shown in FIG. 20 determines a timing distribution value in hierarchical design, and includes an inter-layer cooperation manager 53 and a timing distribution creation unit 54a. To 54e and timing information databases (hereinafter also referred to as TDB [Timing Data Base]) 57a to 57e.

  This timing distribution value (hereinafter sometimes referred to as a distribution value) means a first distribution value in wiring between circuit blocks and a second distribution value inside a circuit block unit. The first distribution value is allocated to the inter-block wiring delay value, wiring length, and wiring load capacity, and the second distribution value is a gate delay value that takes into account variations and temperatures due to the transistor manufacturing process, and the processing is completed. The number of delay cycles indicating the time until completion and the delay value in the wiring inside the block are allocated.

  The inter-tier cooperation manager 53 is connected to each of the timing distribution creation units 54a to 54e, and transmits / receives correction information related to the timing distribution value between each of the timing distribution creation units 54a to 54e. The timing distribution creating units 54a to 54e are provided corresponding to the plurality of design hierarchies, respectively, and block information related to the function of the circuit is input from the TDBs 57a to 57e having a net list related to the wiring form, and the delay of the circuit A timing distribution value obtained by allocating a delay value generated by an element can be output.

Further, each of the TDBs 57a to 57e is a database based on a netlist expression, and holds constraint definition information among hierarchical entities, timing information after provisional layout and actual layout in a state in which the wiring form is conscious. . Note that the content held in consideration of the wiring form will be described later with reference to FIGS.
Here, the hierarchy entity manages information for each hierarchy and will be described later with reference to FIGS. The netlist is the output of parts in the circuit, wiring connection information, position information, etc. in a text file list format. By reading this netlist, the designer can input parts one by one. In other words, all the components can be arranged on the circuit.

  Furthermore, the constraint definition information is constraint information related to timing, for example, means that there is a limit of how many nm (nanometer) or less to transmit a signal from one terminal to another terminal, In the circuit design, this means information indicating a location where component placement is prohibited, the height of the component, and the like. The timing information is information after the floor plan (arrangement position information) is generated, and the contents are held in a netlist expression that is conscious of the wiring form. The netlist expression conscious of the wiring form relates to the name assignment of the netlist, and details thereof will be described later with reference to FIGS. 33 (a) to 33 (c).

  Next, transmission / reception of distribution values between the distribution managers 56a to 56e shown in FIG. 20 and the inter-tier cooperation manager 53 will be described. The floor plan unit 55a is connected to the logic / constraint information holding unit 64a, and distributes the timing based on the floor plan regarding the arrangement of circuit elements and the wiring between the circuit elements, and performs temporary wiring. The distribution manager 56a is connected to the logic / constraint information holding unit 64a and the timing information holding unit 65a, and outputs a delay value based on the net list. The distribution managers 56b to 56e are connected to the logic / constraint information holding units 64b to 64e and the timing information holding units 65b to 65e, respectively, and output delay values based on the netlist. Details of the logic / constraint information holding unit 64a and the timing information holding unit 65a will be described later with reference to FIG.

FIG. 21 is a diagram for explaining transmission / reception of distribution values between layers according to the second embodiment of the present invention. The inter-layer cooperation manager 53 shown in FIG. 21 is configured to transmit / receive data to / from each distribution manager 56a to 56e in charge of each hierarchical entity to obtain necessary information.
Further, the inter-tier cooperation manager 53 receives the timing distribution specification change request transmitted by one of the TDBs 57a to 57e, extracts other TDBs 57a to 57e that can be affected by the timing distribution specification change, and extracts the other TDBs 57a to 57e. 57e is inquired of whether or not the timing distribution value can be changed. When the timing distribution value can be changed from other TDBs 57a to 57e, the changeable value is output to the desired TDBs 57a to 57e. Further, when the timing distribution value is changed, the hierarchical entity higher than the changed hierarchy is updated.

  That is, other hierarchies that are affected by changes in timing specifications by the designer are automatically extracted, and whether or not the changes can be made is inquired to the TDBs 57a to 57e of the hierarchies via the inter-layer cooperation manager 53 and the distribution managers 56a to 56e. It is. In addition, if the result of whether or not the change is possible is that the timing distribution value can be changed, a change notification is issued to the designer. Thereby, the change of timing specification is notified quickly.

When the timing distribution value is changed, the inter-layer cooperation manager 53 automatically selects only necessary portions from the TDBs 57a to 57e of the hierarchical entity whose timing has been changed for the hierarchical entity higher than the hierarchical entity. Are taken in as timing distribution values.
The distribution manager 56d shown in FIG. 21 is the same as the distribution manager 56a, and the TDB 57d is also the same as the TDB 57a, and further description is omitted.

FIG. 22 is a diagram for explaining transmission / reception of distribution values between an upper layer and a lower layer according to the second embodiment of the present invention. 22 that have the same reference numerals as those described above have the same or similar functions, and will not be described further.
As a result, since the uppermost layer can obtain distribution values from the lower layer, static timing analysis (STA) in the entire system is possible. This STA means that the timing is verified without a test bench.

Further, the inter-layer cooperation manager 53 extracts and inputs circuit blocks for which timing information data is insufficient to the TDBs 57a to 57e, and notifies the designer of the insufficient circuit blocks. As a result, the work efficiency of the designer is improved.
Next, FIG. 23 schematically shows the distribution managers 56a to 56e shown in FIG.

  FIG. 23 is a view for explaining a hierarchical entity according to the second embodiment of the present invention. Each circle shown in FIG. 23 represents a hierarchical entity provided for each design hierarchy, and has a tree structure. Specifically, this hierarchical entity is a collection of design information necessary for each design hierarchy. Here, the design information means TDB, net list, block information, constraint definition information, layout information, provisional / actual layout, timing information, and the like.

Therefore, in the hierarchical design, the hierarchical entity and the program for processing the hierarchical entity data are divided into one design hierarchy for each hierarchy. In other words, the timing of the entire system is distributed by using object orientation (agent orientation).
Thereby, a plurality of design layers can communicate with each other via the inter-layer cooperation manager 53.

  The hierarchy entity 90a (PCB block) shown in FIG. 23 transmits an estimate request and a back annotation request to the hierarchy entity 90b (LSI2 block), and receives an estimate response and an actual delay value response from the hierarchy entity 90b. To do. Further, the hierarchical entity 90b transmits and receives similar requests or responses between the hierarchical entity 90c (HLB2-2 block) and the hierarchical entity 90d (HLB2-1 block). The same applies to each hierarchical entity other than these. The estimate request / back annotation request and the estimate response / actual delay value response are executed by programs called the inter-tier cooperation manager 53 and the distribution manager 56a, respectively. An HLB (Hierarchy Layout Block) represents a sub-block in the LSI.

  Therefore, the apparatus 51 is configured as an agent in which the timing distribution creation units 54a to 54e are provided corresponding to each of a plurality of design hierarchies and have hierarchical entities having design information and program data for processing the design information. At the same time, the inter-layer cooperation manager 53 is configured as a manager that is connected to the timing distribution creating units 54a to 54e as agents and transmits / receives information regarding timing distribution values to / from each of a plurality of design layers.

  Further, the inter-tier cooperation manager 53 (see FIG. 21, FIG. 22, etc.) can change the combination of the distribution managers 56a to 56e. Accordingly, the hierarchical entities corresponding to the inter-layer cooperation manager 53 and the distribution managers 56a to 56e can be freely and dynamically changed according to the design object. Therefore, a plurality of circles hanging (connected) in a specific circle in the tree structure shown in FIG. 23 can be collected and replaced with a plurality of other circles.

  Accordingly, hierarchical entities can operate in close cooperation between layers in order from the whole to a part, and further from a part to another part. For this reason, when a designer divides a circuit block to be designed into lower blocks, it becomes easy to determine whether or not the timing specifications are divided by trial examination. In addition, since the division is performed from the upper part to the lower part, the designer can obtain the timing distribution value from the approximate value to the detailed value, and can predict or examine the timing critical part in the architecture design. .

  In addition, with respect to a portion whose timing is critical, only the target portion is subjected to the actual layout, so that it is possible to perform prior verification. Furthermore, since the designer can design with reference to the distribution values in other circuit blocks, erroneous distribution can be prevented. Also, the difference between the required time (constraint) and the arrival time (delay value) is called slack margin, and is examined by the sign of this value. That is, if slack is negative, it is a violation of delay, and if it is positive, it is within the timing requirement range. When the requirement specified in the timing specification at the time of implementation cannot be satisfied (delay violation), negative slack can be improved by consuming positive slack allocated to other portions.

Note that the timing distribution creating units 54b to 54e have the same configuration as the timing distribution creating unit 54a, and thus redundant description is omitted. Next, the timing distribution creating unit 54a shown in FIG. 20 will be described with reference to FIG.
FIG. 24 is a block diagram of the timing distribution creation unit 54a according to the second embodiment of the present invention. The timing distribution creating unit 54a shown in FIG. 24 includes a floor plan unit 55a, a distribution manager 56a, a logic / constraint information holding unit 64a, a timing information holding unit 65a, an HDL annotator 58e, an HDL compiler 58f, an distribution report creating unit 50d, a waveform. An analysis information creating unit 58h and a waveform analysis information holding unit 58i are provided. Hereinafter, the logic / constraint information holding unit 64a, the timing information holding unit 65a, and the waveform analysis information holding unit 58i may be referred to as holding units 64a, 65a, and 58i, respectively. Also, what is shown in FIG. 24 and has the same reference numeral as that described above has the same or similar function, and therefore redundant description is omitted. Note that items marked with [1] and [2] (represented by circled numbers 1 and 2 in the figure, respectively) will be described with reference to FIG.

In the following description, the numbers with circles shown in FIG. 21, FIG. 22, FIG. 24, and FIG.
Here, the holding unit 64a holds a logic / constraint information having constraint information related to a net list, block information, and wiring related to a design language source code. 58c (hereinafter, the constraint condition holding unit 58b and the structural partial netlist holding unit 58c may be referred to as holding units 58b and 58c, respectively). The holding unit 58b receives the constraint definition information, and holds the area occupied by the component and the timing specification as a constraint based on the information. The holding unit 58c receives the block information and holds the net list. Is.

The floor plan unit 55a is connected to the holding unit 64a, and performs temporary wiring by allocating timing based on the floor plan regarding the arrangement of circuit elements and wiring between circuit elements. The timing information holding unit (timing information) 65a is connected to the floor plan unit 55a and holds the block information, the net list, and the timing information.
Here, in the calculation using two or more distribution values, the minimum value and the maximum value of the distribution values are automatically generated, and the delay value is calculated. This accuracy difference is obtained by performing a reverse rounding operation to the range where the original numerical value is obtained by rounding off. Here, as an example, in order to match the number of significant digits to 2.227 ns (nanoseconds), which is a calculation target of the delay value, a numerical value (1. 145 to 1.244 ns) will be described.

Therefore, other hierarchies are automatically extracted, and whether or not the change is possible is inquired to the TDBs 57a to 57e of each hierarchy. A change notification is issued. Thereby, a flexible design change becomes possible.
Assume that the delay value is held at 1.2 ns in the timing library. Therefore, the designer sets the error range to 0.09 ns (0.099999... Ns) for rounding. When a range having the error range of 0.09 ns and a delay value of 1.2 ns is obtained by rounding off to the second decimal place, the minimum value is 1.15 ns and the maximum value is 1.24 ns. In other words, 1.2 ns can be obtained by rounding the delay value during this period to the second decimal place.

  Next, the designer calculates a minimum value and a maximum value for each of these minimum value 1.15 ns and maximum value 1.24 ns, and for 1.15 ns, the minimum value 1.145 ns to the maximum value 1.154 ns. Further, for 1.24 ns, the range from the minimum value 1.235 ns to the maximum value 1.244 ns is obtained. And based on the obtained range, the range of the minimum value 1.145 ns to the maximum value 1.244 ns is obtained.

Therefore, 2 significant digits are expanded to 4 digits, and a 2-digit delay value (1.2 ns) can be obtained as a 4-digit delay value (1.145 to 1.244 ns). A delay value with a number of digits can be generated.
In another timing library, when the delay value is 4 significant digits (calculation target 2.237 ns), both the minimum value and the maximum value are 2.237 ns.

As described above, the accuracy of the distribution value is automatically determined between data having different accuracy based on the data held in the timing library. For this reason, even when a high-speed component and a low-speed component are connected, calculation is possible regardless of the difference in accuracy that occurs in these components.
It is also possible to use a plurality of timing libraries with different accuracy. Furthermore, it becomes easy to grasp slack by expressing the minimum value / maximum value including an error.

That is, the distribution manager 56a has availability information regarding whether or not the distribution value can be changed in the direction in which the margin decreases, so that a critical path can be extracted from each distribution value. Possible parts can be extracted. As a result, the distribution of the circuit can be corrected, and the designer can easily know the corrected part.
The HDL annotator 58e writes information resulting from the timing distribution value in the source code, reads desired data from the timing information holding unit 65a, and writes necessary data in the source code. The HDL annotator 58e is also configured to write a net list relating to the wiring form in the source code. That is, for the description of the time required for signal substitution, the value distributed by the HDL annotator 58e is back-annotated in the source code, and the delay value is set or changed. In addition, when this back annotation is performed, a netlist expression conscious of the wiring form is also written as a comment sentence in the source code.

Thereby, the user interface between a designer and this apparatus 51 becomes closer.
The HDL compiler 58f receives source code and parameters and outputs the data to the structure partial netlist holding unit 58c.
Further, the waveform analysis information creation unit 58h generates information for PCB waveform analysis from I / O buffer information (input / output buffer information) of the LSI layer. Therefore, the designer can easily analyze the waveform.

  The waveform analysis information holding unit 58i is connected to the waveform analysis information creation unit 58h and the waveform analysis CAD device 52b, and in addition to the timing distribution value written by the waveform analysis information creation unit 58h, Each PCB block holds data about a netlist necessary for waveform analysis. Therefore, it functions as a library for waveform analysis. The waveform analysis information holding unit 58i is connected to the waveform analysis CAD device 52b, and the waveform analysis information holding unit 58i can refer to the data.

FIG. 25 is a block diagram of a floor plan unit 55a according to the second embodiment of the present invention. The floor plan unit 55a shown in FIG. 25 includes an arrangement processing unit 59f, a physical technology information holding unit 59c, actual wiring / provisional wiring. An execution unit 60, a wiring information holding unit (wiring information) 59d, and a conversion unit 59e are provided.
The placement processing unit 59f is connected to the holding unit 64a, presents a portion where the distribution value as attribute information can be improved and corrected based on slack from the constraint information, and holds the placement information resulting from the delay element information. An arrangement support unit 59a that presents a portion that can be improved and modified based on slack from the constraint information, and an arrangement information holding that holds arrangement information caused by delay element information Part 59b.

  The actual wiring / provisional wiring execution unit 60 is connected to the placement processing unit 59f, performs cooperation with the actual wiring and temporary wiring, and outputs wiring information. The Manhattan length temporary wiring unit 60a, the diagonal Manhattan length temporary A wiring unit 60b, actual wiring cooperation units 60c and 60d, an extraction unit 60e, and a name assigning unit 60f are provided. Here, the actual wiring is a wiring method in which the wiring layer is considered, the wiring is wired in three dimensions, the collision with other wiring and the wiring width are considered, and the processing time is long. Temporary wiring is a wiring technique in which wiring is wired in two dimensions and does not take into account a short circuit between wirings.

The actual wiring / temporary wiring execution unit 60 performs temporary wiring based on the Manhattan length temporary wiring, the oblique Manhattan length temporary wiring, and the actual wiring. This improves the accuracy even in places where the wiring congestion is high.
Then, the actual wiring / provisional wiring execution unit 60 reads the delay value and the load capacity for the selected hierarchy from the physical technology information holding unit 59c, and distributes the delay value per unit wiring length by changing the delay time. ing. Therefore, when the timing specification is changed, recalculation can be performed immediately.

The Manhattan length temporary wiring unit 60a performs the Manhattan length temporary wiring for both the PCB and the LSI based on the placement result of the placement support unit 59a. Therefore, the efficiency of wiring work is improved.
The oblique Manhattan length temporary wiring section 60b (hereinafter, sometimes referred to as the temporary wiring section 60b) performs temporary wiring using diagonal wiring that is obliquely wired with respect to the edge of the PCB based on the placement result of the placement support section 59a. Yes, it is a wiring technique used for PCB. Therefore, the efficiency of wiring work is also improved.

FIG. 26 is a view for explaining the oblique Manhattan length temporary wiring according to the second embodiment of the present invention, where P is a pin, and the pin P is wired. This wiring algorithm is as shown in the following (3-1) to (3-3).
(3-1) The temporary wiring unit 60b generates a diagonal wiring component based on a preset diagonal wiring rate.

(3-2) The provisional wiring section 60b wires the portion of the wiring length corresponding to the diagonal wiring ratio of the total wiring length by 45 degrees with respect to the corner portion in the Manhattan wiring.
(3-3) If the path has negative slack (surplus time), the temporary wiring unit 60b performs rewiring by increasing the diagonal wiring rate. Here, as shown in FIG. 26, the total wiring length of the diagonal wiring portion is a route half of the wiring length of the corresponding portion of the orthogonal wiring portion.

Further, the actual wiring / provisional wiring execution unit 60 performs actual wiring based on the margin calculated for the timing distribution value obtained by the temporary wiring and the wiring congestion level indicating the wiring density. Thereby, since temporary wiring or real wiring is automatically switched according to wiring congestion degree, a trade-off can be utilized effectively and a designer's effort can be reduced.
In addition, the extraction unit 60e extracts the wiring congestion level. Therefore, the actual wiring / temporary wiring execution unit 60 performs temporary wiring and actual wiring based on the wiring prohibition area and the wiring congestion degree. This wiring congestion degree is automatically extracted using two types of algorithms.

27 and 28 are diagrams for explaining an algorithm for extracting the degree of wiring congestion according to the second embodiment of the present invention, where circuit blocks B1 and B2 are arranged, and between these blocks, They are connected by a large number of lines (lines included in a circle labeled L).
First, the first algorithm is called a simple algorithm and is as shown in the following (4-1) and (4-2).

(4-1) A line is drawn between the terminals of each circuit block.
(4-2) Count the number of lines per unit area labeled S1 shown in FIG. 27, and use that value as the wiring congestion level.
The second algorithm is an algorithm using the Manhattan length, and is as shown in the following (5-1) and (5-2).

(5-1) As in the case of right-angled wiring shown in FIG. 28, wiring is performed along the grid lines while avoiding the macro circuit blocks B1 and B2 and the wiring prohibited area.
(5-2) The number of wirings per unit area marked with S2 shown in FIG. 28 is counted, and the value is used as the wiring congestion degree.
Further, the actual wiring cooperation units 60c and 60d cooperate to wire the LSI and the PCB. Of these, the actual wiring cooperation unit 60c is for the LSI, and the actual wiring cooperation unit 60d is for the PCB. The actual wiring link unit 60c is connected to the layout CAD device 52a to transmit / receive data, and the actual wiring link unit 60d is connected to the layout CAD device 52c to transmit / receive data. .

Therefore, the temporary wiring and the detailed actual wiring depending on the circuit block to be designed can be mixed and wired, and the timing distribution value can be extracted.
In addition, the actual wiring / provisional wiring execution unit 60 outputs information for analysis related to information lacking in actual wiring so as to be linked with a design apparatus that supports other computers capable of performing only actual wiring. Yes.

As a result, when the device 51 performs actual wiring, the designer is notified of insufficient information, the designer creates information necessary for analysis based on the information, and the information is used as a layout CAD device dedicated to actual wiring. 52a and 52c can be transmitted and wired.
In addition, the actual wiring / provisional wiring execution unit 60 performs wiring by using a real wiring that requires a long calculation time and a temporary wiring that has a short calculation time, and extracts a timing distribution value.

As a result, the designer first examines the timing specifications by provisional wiring, and can change the timing distribution based on the result obtained by the examination and perform actual wiring.
Furthermore, in FIG. 25, the floor plan unit 55a can change the scale (size) or shape of the circuit block while performing actual wiring and temporary wiring.
FIG. 29 is a diagram schematically showing the enlargement of the arrangement region according to the second embodiment of the present invention. The arrangement area of the circuit block I20 shown in FIG. 29 is expanded to obtain a circuit block I21. D, E, and F that did not enter I20 can be arranged in I21. On the other hand, it is possible to reduce an arrangement region that is too large. Therefore, flexible layout design is possible.

In addition, in FIG. 25, the floor plan unit 55a can change the wiring width in the circuit block while performing actual wiring and temporary wiring. When this wiring width is small, the wiring capacity is small, and when it is large, the wiring capacity is large. Therefore, since the wiring width can be changed, the circuit can be designed flexibly.
The wiring information holding unit 59d is connected to the actual wiring / provisional wiring execution unit 60 and holds wiring information. The conversion unit 59e is connected to the wiring information holding unit 59d and the physical technology information holding unit 59c, and converts the wiring information into a delay value based on the wiring length and the load capacity and outputs the result. The physical technology information holding unit 59c holds a delay value per unit length and a load capacity per unit length in association with each other. These values (libraries) are prepared for each wiring width and wiring layer, and are prepared and held for each PCB technology (PCB technology) and LSI technology (LSI technology). A delay value is calculated from the wiring length using this physical technology information.

Accordingly, the conversion unit 59e reads the delay value per unit length from the physical technology information holding unit 59c based on the physical wiring length, and converts the wiring length and the delay value. In addition, the conversion unit 59e reads the delay value based on the unit capacity based on the load capacity, and converts the load capacity and the delay value. Thereby, the delay value is easily calculated from the wiring length.
Furthermore, the actual wiring / provisional wiring execution unit 60 (see FIG. 25) can change the physical technology for the selected hierarchy, reads the delay value and the load capacity from the physical technology information holding unit 59c, and performs unit wiring. The delay time per long is automatically set and distributed according to the selected physical technology. That is, since the physical technology of the circuit block can be changed, a physical technology that satisfies the timing constraint can be searched.

  Furthermore, when the actual wiring / provisional wiring execution unit 60 determines whether or not it can be reached within the time (one period) that must be reached based on the clock frequency used as the constraint condition, and determines that it cannot be reached. Insertion of buffers and flip-flops is instructed to a net list between a plurality of circuit blocks. Thereby, since the buffer or the like is inserted only when the virtual pin cannot be reached, the constraint condition can be satisfied effectively.

  FIG. 30 is a view for explaining timing distribution inside the LSI according to the second embodiment of the present invention. The chip 61 shown in FIG. 30 includes circuit modules (modules) 61a to 61e, and terminals (outer peripheral parts are rectangular) on the outer periphery or inside thereof. Each of the modules 61a to 61e is provided with a virtual pin (displayed in a circle) at the end of the module. This virtual pin is connected to a virtual pin provided in another module, and is shared by, for example, a clock (CLK).

  Then, the actual wiring / provisional wiring execution unit 60 arranges terminals (virtual pins) included in the circuit block based on the constraint information. That is, the position of the virtual pin is preferentially provided at a predetermined position on the module end from the negative slack. Then, at that position, the slack when wiring with the Manhattan length is calculated, and if no negative slack is generated, the position is determined. The other modules 61b to 61e shown in FIG. 30 are the same as the module 61a. In the PCB design, the oblique Manhattan length is also included. Therefore, the arrangement is simplified.

  Further, the virtual pin Q of the module 61b is connected to the critical net 61f, and the flip-flop 61g is connected to the critical net 61f. Thereby, when the critical net 61f has negative slack and the timing condition cannot be satisfied, a flip-flop, a buffer, or an inverter is inserted so as to satisfy the timing condition.

By inserting this flip-flop, the signal output from the virtual pin Q is delayed by one cycle in the flip-flop, but between the virtual pin Q and the flip-flop 61g, the flip-flop 61g and the terminal A of the module 61c. The setup condition is satisfied.
Therefore, based on the distribution value and the given clock frequency, it is calculated whether or not the circuit block pins and virtual pins can reach from other circuit block pins and virtual pins in one clock, and cannot be reached. In some cases, flip-flops and the like are inserted into the net list between circuit blocks. In addition, the chip 61 in this example has a delay value of 6 ns when wired for a length of 9 mm (millimeters), and thus operates if the operating frequency is 166 MHz (megahertz) or less.

As described above, the timing can be adjusted before the RTL (Register Transfer Level) design. Next, the setting of the timing distribution value will be described.
In FIG. 24, the timing distribution creation unit 54a outputs a timing distribution value based on other preset timing specifications and the timing distributed by the floor plan unit 55a. Then, the distribution report creation unit 50d refers to the timing specification and the timing condition distributed by the floor plan unit 55a, and outputs the validity of the floor plan and the timing specification as a distribution report. This distribution report is a text file in which distribution values are described, and is used for reference by a designer.

Furthermore, functions between the source code and the timing distribution creation unit 54a will be described.
The timing distribution creating unit 54a reads the timing distribution value back-annotated at the time of logic design or layout consideration using the source code by the HDL compiler 58f. Specifically, in addition to the net list, source code including a timing delay value necessary for simulation is read. Therefore, the designer can easily perform the simulation.

Next, the distribution manager 56a shown in FIG. 24 is connected to the holding unit 64a, the timing information holding unit 65a, the TDB 57a, and the inter-layer cooperation manager 53, and outputs a delay value based on the netlist.
FIG. 31 is a block diagram of the distribution manager 56a according to the second embodiment of the present invention, and the distribution managers 56b to 56e shown in FIG. 31 have the same structure as the distribution manager 56a. The distribution manager 56a is a distribution editor 63a, a database reference registration unit 63e, an own layer TDB output / another layer TDB automatic reflection unit (an own layer TDB output / another layer TDB reflection unit; hereinafter referred to as a TDB output reflection unit). .) 63d and an arbitration control unit 63f. The distribution editor 63a is connected to the holding unit 64a for timing distribution, and the database reference registration unit 63e is connected to the distribution editor 63a, the holding unit 64a, and the timing information holding unit 65a, and the net list and the distribution value. And has a TDB registration unit 63b and a TDB reference unit 63c. The TDB registration unit 63b writes data to the TDB 57a, and the TDB reference unit 63c reads data from the TDB 57a.

  Further, the TDB output reflection unit 63d inputs / outputs the timing distribution information of its own hierarchy and the timing distribution information of another hierarchy. That is, data relating to other layers (other layers, lower layers) is reflected in the TDB 57 a via the inter-layer cooperation manager 53, and data relating to its own layer (own hierarchy) is reflected via the inter-layer cooperation manager 53. Of the other TDBs 57b to 57e, it is reflected in the hierarchy one level higher than the own hierarchy. Whether to reflect or not is controlled by the arbitration control unit 63f. The arbitration control unit 63f is connected to the TDB output reflection unit 63d and the distribution editor 63a, arbitrates whether to select the distribution value from the own layer or another layer, and whether the distribution value can be reflected. Is to determine.

  Thereby, the arbitration control unit 63f determines whether or not the timing constraint is satisfied by using the data of the own layer and the data of the other layer, and if it satisfies, it can be reflected, and if it does not satisfy, it is reset so that it cannot be reflected. Make a request. At the time of resetting, the data of the own hierarchy is read from the TDB 57a by the TDB output reflecting unit 63d, and a message that resetting is necessary is input to the distribution editor 63a via the arbitration control unit 63f. In response to a data transmission request from the distribution managers 56a to 56e in other layers, the data is output via the inter-layer cooperation manager 53. Further, after requesting data of other layers to the inter-layer cooperation manager 53, the desired other layer data transmitted is input to the distribution editor 63a and repeated until the constraint information is satisfied, and the constraints are satisfied. Is written to the TDB 57a.

Note that the configuration of the distribution managers 56b to 56e (see FIG. 20) is also the same as that of the distribution manager 56a, and thus a duplicate description is omitted.
FIG. 32 is a diagram for explaining skew calculation according to the second embodiment of the present invention, and the netlist 62a shown in FIG. 32 includes circuit modules I1, I2, I3, I4, and I5 (displayed as squares). ) In FIG. 32, for example, the phase of a signal output from I1 (representing I1 means the circuit module I1 and the same applies to other circuit modules) is delayed when propagating on the PCB. Also, when input to the I2 circuit module, it is delayed due to the influence of the input pin capacitance.

  Based on this, the designer calculates a delay value between I1 and I3, a delay value between I1 and I4, and a delay value between I1 and I5, respectively. Here, the elements of delay generation are internal delays of I1 and I2 (represented as a and c), delay values between I1 and I2 (represented as b), and I2 to I3 and I2 There is a delay value (denoted as d, e, f, g) between I4, I2 and I5.

  For example, in the calculation for obtaining the phase difference between I1 to I3 (delay time) and I1 to I5 (delay time), the difference between the delay values from the normal reference point (corresponding to the delay value a of I1). Is calculated. Here, since the delay values of a, b, c, and d are all based on paths common to both I1 to I3 and I1 to I5, variations between circuit modules and wiring variations are taken into consideration. Not. Therefore, the phase difference can be calculated by the difference between (delay value e + I3 input pin capacitance) and (delay value f + delay value g + I5 input pin capacitance). These two input pin capacities have manufacturing variations even if the same logic circuit is implemented in I3 and I5.

For this reason, the distribution manager 56a calculates a skew representing the phase difference of the arrival times of the signals based on the wiring paths other than the common wiring path among the wiring paths of the netlist related to the wiring form.
In other words, based on the netlist, the path is traced from the direction opposite to the signal propagation direction, and when the common part appears, the part that is not the common part is extracted to automatically calculate the calculation with the common part removed. It is executed automatically.

  33 (a) to 33 (c) are diagrams for explaining netlist expressions according to the second embodiment of the present invention. The net list 62 shown in FIG. 33A is a logic circuit having circuit modules I1, I2, I3, and I4 (hereinafter abbreviated as module I1 etc.), and the port A of the module I1 outputs a signal. The ports B, C, and D of the modules I2 to I4 are for inputting signals. Further, in FIGS. 33B and 33C, wired physical layouts are displayed, respectively. The chip 63 shown in FIG. 33 (b) represents what is implemented.

Here, the sub-signal name can be represented by “I1.A-I2.B-I3.C-I4.D”. In the netlist expression, the delimiter is “-” and the delimiter from the instance name is “.”. Here, the fan-out of port A is 3, which means that ports B, C, and D are driven, respectively, and are wired in this order in a single stroke.
The netlist expression shown in FIG. 33C is for a case where there are equal length sections (AB and AC are equal in length) in the netlist. That is, in this case, parentheses are added to the equal length parts, and the sub-signal name is represented by “I1.A- (I2.B-I3.C) -I4.D”. When the delay is limited, for example, the delay value is described using “#”, and the sub-signal name is “I1.A- (1.4 ns # I2.B-I3.C) -1.2 ns #. I4.D.

Furthermore, other constraints such as load capacity, wiring length, wiring width, wiring layer designation, etc. can be described by sub-signal names such as the following (6-1) to (6-3). Here, pf represents picofarad, μm (micrometer) represents a wiring length, and w represents a wiring width (μm). LA and LB each represent a wiring layer.
I1. A- (0.3pf # I2.B-I3.C) -1.2 ns # I4. D
... (6-1)
I1. A- (1.4 ns # I2.B-I3.C) -31.2 μm # I4. D
... (6-2)
0.6w # LA, LB # I1. A-I2. B-I3. C-I4. D
... (6-3)
That is, the LA layer is wired with a width of 0.6 μm, and all of the wirings I1 to I2, I1 to I3, and I1 to I4 are restricted from being drawn with a single stroke in the LB layer.

Furthermore, in the case of PCB design, “/” is used instead of “−” in the diagonal wiring portion when the diagonal wiring is performed. For example, the sub-signal name is represented by “I1.A / I2.B-I3.C-I4.D”.
Therefore, the distribution manager 56a is configured to give the wiring path a name representing the wiring form as the sub-signal name, and is configured to name the sub-signal name and the fan-out number in association with each other. It will be.

Although not shown, the distribution manager 56a displays a gradation corresponding to the value of the restriction information on the operation screen for the wired portion, and the distribution manager 56a is a diagram showing a circuit block. In addition, the timing distribution value and the range of values that can be allocated the timing are displayed.
In this manner, since variations in common portions can be removed, a highly reliable circuit can be designed.

  In the hierarchical design, the program of the present invention is configured such that a computer is provided corresponding to each of a plurality of design hierarchies, and block information relating to the function of the circuit is input from TDBs 57a to 57e having net lists relating to wiring forms. Are connected to each of the timing distribution creation units 54a to 54e and the timing distribution creation units 54a to 54e that can output the timing distribution values obtained by allocating the delay values generated by the delay elements, and the timing distribution creation units 54a to 54e, respectively. It is for functioning as an inter-tier cooperation manager 53 that transmits and receives correction information related to timing distribution values.

That is, the functions of the timing distribution creating unit 54a and the inter-tier cooperation manager 53 are respectively configured to store a program stored in a recording medium (not shown) such as a hard disk of a computer used as the timing distribution device 51, and the CPU of the computer. Is realized by reading and operating.
The method of installing the program of the present invention on a recording medium such as a hard disk uses a recording medium such as a CD-ROM, CD-R, CD-RW, and floppy disk in accordance with the reading device of the computer. It has become.

With the above-described configuration, the operation of the timing distribution device 51 of the present invention will be described in detail with reference to FIGS.
FIG. 34 is a diagram showing a block design process according to the second embodiment of the present invention. The process shown in FIG. 34 represents that the three-layer timing design for the PCB, LSI, and sub-blocks in the LSI proceeds simultaneously.

  First, after the system specifications are designed (step P1), the PCB design designated as step P10 is started. First, in step P10a, when designing an LSI, the route attached with 1 is passed through, and the processes after step P20 are performed. The PCB is designed through the route attached with 2, using VHDL, VHDL +, etc. Is coded (step P10b). Then, when the source code is obtained at step P10b, the implementation of the PCB is started at step P40 through the route labeled 1 and when the source code is obtained at step P10b, 2 is obtained. In step P10c, the timing distribution is created through the attached route. Further, when the timing is distributed, it is executed in cooperation with the TDBs 57a to 57e and the inter-tier cooperation manager 53 in Step P10f. Thereafter, a floor plan is generated (step P10d), and the floor plan is read by the layout CAD device (PCB physical layout CAD device) 52c (step P10e). This floor plan is used for the PCB implementation in Step P40.

  The same applies to LSIs and sub-blocks within LSIs. When designing an LSI in step P10a, the LSI design is started in step P20a through the route labeled 1. When designing a sub-block in the LSI in this step P20a, the route after 1 is passed through the route attached with 1, and the processing after step P30 is performed. The LSI is designed through the route attached with 2 through VHDL, VHDL + Etc. (step P20b).

  If the source code is obtained in step P20b, the LSI is implemented in step P41 through the route labeled 1 and if the source code is obtained in step P20b, 2 is appended. In step P20c, a timing distribution is created. Further, when the timing is distributed, the TDBs 57a to 57e and the inter-tier cooperation manager 53 are linked in Step P20f. Thereafter, a floor plan is generated (step P20d), and the floor plan is read by the layout CAD device (LSI physical layout CAD device) 52a (step P20e). This floor plan is used for LSI implementation in step P41.

  For the sub-blocks in the LSI, first, design is started (step P30a), and coding is performed using VHDL, VHDL +, etc. (step P30b). Then, when the source code is obtained in step P30b, the implementation of LSI sub-blocks is started in step P41 through the route labeled 1, and the source code is obtained in step P30b. The timing distribution is created in step P30c through the route labeled 2. Further, when the timing is distributed, the TDBs 57a to 57e and the inter-tier cooperation manager 53 are linked in Step P30f. Thereafter, a floor plan is generated (step P30d), and the floor plan is read by the layout CAD device 52a (step P30e). This floor plan is used for LSI implementation in step P41.

Therefore, since each circuit block can grasp the timing information of other circuit blocks in real time, recalculation can be performed immediately when the timing specification is changed, thereby improving the design efficiency.
In addition, by timing distribution using the distributed design environment, the designer designs while considering the influence on other circuit blocks, and when there is an influence, the designer designs while checking whether it is within the allowable range by using the distribution report.

  FIG. 35 is a flowchart for explaining timing distribution according to the second embodiment of the present invention. Source code describing block constraint definition information and a target block netlist or timing specifications is input to the timing distribution creation units 54a to 54e of each design hierarchy (step Q10), and a floor plan unit 55a and a distribution manager 56a are input. Then, the timing distribution process is performed (step Q11), the timing distribution value of each block is written in each of the TDBs 57a to 57e (step Q12), the distribution report is output, and the distribution value is examined (step Q13).

Accordingly, since a plurality of designers can refer to the timing specifications and the implementation conditions at the same time, miscommunication among the designers can be prevented.
The timing specifications held in the TDBs 57a to 57e are treated as constants with the attribute information set to unchangeable for the already determined parts, and the changed parts are immediately written to the TDBs 57a to 57e. It is. For a portion that extends across multiple hierarchies, the inter-hierarchy cooperation manager 53 is immediately reflected in the TDBs 57a to 57e of the upper hierarchy.

Next, data transmission / reception between the inter-tier cooperation manager 53 and the distribution managers 56a to 56e shown in FIGS. 21 and 22 will be described with reference to FIGS.
36 to 38 are all flowcharts for explaining a part of the timing distribution according to the second embodiment of the present invention. What is shown in FIG. 36 is when data is updated between intermediate hierarchies, and corresponds to the locations marked A- [1] and A- [2] shown in FIG. Also, what is shown in FIG. 37 is a process for inquiring between the intermediate hierarchies, and corresponds to the locations marked B- [1] to B- [4] shown in FIG. What is shown in FIG. 37 is in the uppermost hierarchy and the intermediate hierarchy when inquiring about the overall timing. The flowcharts shown in FIGS. 36 to 38 perform message communication between the inter-tier cooperation manager 53 and the distribution manager.

As described above, the inter-tier cooperation manager 53 determines to which distribution manager the message from the distribution manager 56 a should be transmitted, and transmits the message data transmitted to the target distribution manager 5.
First, in step Q20 of FIG. 36, the AC specifications and clock skew distribution values of the virtual pins of the LSI sub-blocks in a certain hierarchy are taken into one higher hierarchy (for example, the TDB of the LSI). Subsequently, in step Q21, the AC spec and clock skew distribution value of each virtual pin of the LSI are taken into the upper hierarchy (for example, TDB of PCB).

  In step Q30 of FIG. 37, each of the distribution managers 56a to 56e inquires the inter-layer cooperation manager 53 about the distribution value of the other sub-blocks in the LSI. Next, the inter-tier cooperation manager 53 inquires the distribution value to the corresponding LSI block (one higher block) (step Q31). Since the LSI block holds the distribution value of the other LSI block instanced in the LSI, the inquired LSI block returns the distribution value to the inter-tier cooperation manager 53 (step Q32). The inter-tier cooperation manager 53 receives the distribution value of the other sub-blocks of the LSI for the sub-block of the LSI that issues the inquiry first (step Q33).

  Further, in step Q40 of FIG. 38, the distribution value is inquired for each component existing on the PCB from the highest hierarchy (PCB). Then, each component inquires the distribution value for each sub-block existing in each component (step Q41), and each sub-block determines its own block distribution value for the inquired original component. The parts are returned (Step Q42), and each part returns its own part distribution value to the inquiry source PCB (Step Q43). Note that the symbols [1] to [4] shown in FIG. 38 correspond to those shown in FIG.

  FIG. 39 is a flowchart for explaining the operation of the timing distribution creating units 54a to 54e according to the second embodiment of the present invention. First, the presence / absence of the source code is determined (step R1). If it exists, the connection information between the blocks is extracted from the source code through the route labeled Y, and a net list of the structure part is generated (step S1). R2) In step R3, it is determined whether or not there is a delay value description in the source code. If it exists, it passes through the Y route, and in step R4, the timing specifications are extracted from the constraint conditions (operation speed, gate scale, etc.) of the constraint definition information and the delay value description in the source code, and the constraint conditions are created. The If there is no delay value description in step R3, the process after step R9 is performed through the N route.

  If the source code does not exist in step R1, the connection information between blocks is extracted from the block information through the route labeled N, and a netlist of the structure part is generated (step R5). Step R6 In step R7, the constraint condition timing distribution creating unit 54a sends the net value from the structure partial net list holding unit 58c to determine whether or not to set the timing specification value. The list is read, and the timing specification is manually input by the distribution editor 63a (see FIG. 31) in the distribution manager 56a (see FIG. 21 [1]). Further, the set contents are written in the constraint condition holding unit 58b as the timing specifications of the constraint conditions (see FIG. 21 [2]). Further, if the timing specification value is not set in step R6, the route passes through the N route, and the timing specification value is set to empty (none) in step R9.

  Then, the distribution manager 56a examines distribution with reference to the distribution values of other layers (step R8), the floor plan unit 55a generates timing information after the floor plan (step R10), and the timing specifications and timing information. Are registered in the TDB 57a as distribution values through the distribution manager 56a (step R11). Then, the distribution report creation unit 50d outputs a distribution report (step R12), the timing information obtained by the floor plan unit 55a is reflected in the source code by the HDL annotator 58e (step R13), and the timing information is a waveform. The analysis information creating unit 58h converts the file into a waveform analysis CAD file and cooperates (step R14).

Next, by using the rounding method described above, a high precision component or circuit can be obtained by providing a range of delay time using a minimum value / maximum value for a value used by a low accuracy component or circuit block. It is designed by mixing parts or circuit blocks that are connected to the blocks and have different accuracy.
Further, the timing distribution of the PCB is generated using not only an existing method but also diagonal wiring. First, the wiring congestion degree is calculated using wiring based on Manhattan length and diagonal Manhattan length, and if the wiring congestion level is lower than the set condition, distribution is performed using wiring based on Manhattan length considering simple Manhattan length or diagonal wiring. .

On the other hand, when the degree of wiring congestion is higher than the set condition, one of the following (7-1) and (7-2) is used for timing distribution.
(7-1) The delay value is increased corresponding to the degree of wiring congestion, and a larger delay value is obtained.
(7-2) The actual wiring link units 60c and 60d respectively convert the data, perform the actual wiring using the existing method, convert to the delay value based on the wiring information, and distribute it.

  FIG. 40 is a flowchart for explaining the operation of the floor plan unit 55a according to the second embodiment of the present invention, and the same applies to the floor plan units 55b to 55e. The floor plan unit 55a receives the constraint condition and the structure partial net list (step R20), and the placement support unit 59a cooperates with the temporary wiring unit (Manhattan length temporary wiring unit 60a, oblique Manhattan length temporary wiring unit 60b). Then, the placement is determined in consideration of the wiring, the placement information is created (step R21), and the temporary wiring is executed based on the placement information (step R22).

  In step R23, it is determined whether the wiring congestion level has exceeded the set value or the slack has become equal to or less than the set condition. If any of the conditions is satisfied, the route passes through the Y route and the set value is set in step R24. For the portion exceeding, the actual wiring cooperation units 60c and 60d perform actual wiring using the layout CAD devices 52a and 52c to create wiring information. Further, the floor plan unit 55a converts the wiring length and the load capacity into a delay value using the physical technology information, and writes it into the logic / constraint information holding unit 64a (step R25). If none of the conditions is satisfied at step R23, the route plan unit 55a creates wiring information using the result of the temporary wiring (step R26) and performs the process of step R25.

Both FIG. 41 and FIG. 42 are flowcharts for explaining the operation of the distribution manager 56a according to the second embodiment of the present invention, and the same applies to the distribution managers 56b to 56e.
In step R30 shown in FIG. 41, the distribution manager 56a determines whether or not there is a TDB output request from the inter-tier cooperation manager 53. If there is a request, the distribution manager 56a passes the Y route, and in step R31, the TDB output reflection unit 63d. Inputs the contents of the TDB input / output portion of the own hierarchy to the inter-layer cooperation manager 53, and in step R32, the inter-layer cooperation manager 53 inputs the received contents to the distribution managers 56b to 56e of the other hierarchies.

  If it is determined in step R30 that there is no TDB output request, the route passes through the N route. In step R33, it is determined whether or not the contents of the TDBs 57a to 57e in the other layers are to be reflected. The distribution manager 56a issues a reference request for the contents of the TDBs 57a to 57e in the other layers to the inter-layer cooperation manager 53 (step R34), and the inter-layer cooperation manager 53 inputs / outputs the TDBs 57a to 57e from the other layers. When the contents of the part are received (step R35), the contents of the input / output parts of the TDBs 57a to 57e in the other layers are input to the distribution managers 56a to 56e that have made reference requests (step R36). Then, in step R37, it is determined whether or not the process has been completed. If the process has been completed, the process passes from the Y route. If not, the process ends. If not, the process from step R30 is performed through the N route. It is.

If the contents of the TDBs 57a to 57e in the other layers are not reflected in step R33, the route passes through the N route (labeled 1), and the process proceeds to step R38 shown in FIG. Also, what is marked 2 is executed after Step R39 or Step R41 shown in FIG.
In step R38 shown in FIG. 42, the distribution manager 56a determines whether or not to refer to the distribution contents of the other hierarchy using the distribution editor 63a. If so, the distribution manager 56a passes through the Y route and in step R39, Using the TDB reference unit 63c, the distribution value of the other hierarchy is read from the TDB 57a, and the process is completed. Further, in the case where reference is not made in step R38, the route passes through the N route, and in step R40, the distribution manager 56a determines whether or not to register constraint conditions and timing information in the TDBs 57a to 57e. In step R41, the distribution manager 56a registers the constraint conditions and timing information of its own hierarchy in the TDBs 57a to 57e using the TDB registration unit 63b. On the other hand, if registration is not performed in step R40, the process is terminated through the N route (step R37 in FIG. 41).

In this way, the timing conditions of the entire system can be satisfied by cooperation with other layers. Further, the floor plan unit 55a allows the designer to allocate timing accurately without worrying about the trade-off between the processing speed and the estimated accuracy.
According to the above (7-1) and (7-2), it is automatically selected whether to wire by temporary wiring or by actual wiring (see FIG. 40), and for each circuit block (logical block). This is because temporary wiring and actual wiring can be mixed on one PCB or one chip.

Thus, since temporary wiring or actual wiring is automatically switched according to the degree of wiring congestion, the trade-off can be effectively utilized, and the effort of the designer can be reduced. Further, when the wiring congestion degree threshold is exceeded during wiring, the number of wiring layers is increased each time the wiring congestion threshold is exceeded, and a final wiring layer is calculated.
In this way, it is possible to know the number of necessary wiring layers without re-laying out. Further, an attribute is given to each pin and each wiring, and a plurality of pins and a plurality of wirings are distributed together to reduce the man-hours for the distribution.

Next, the designer applies a netlist expression that is conscious of the wiring form, and the sub-signal name after layout is written into the HDL source code by the HDL annotator 58e. Information on the sub-signal name is taken in using the following modes (8-1) to (8-3).
(8-1) Information on the sub-signal name is taken into the HDL annotator 58e and reflected in the delay value description of the signal substitution statement of the source code. Thereby, a timing distribution value can be designated.

  (8-2) A netlist expression conscious of the wiring form is taken into the source code in the form of a comment sentence. As a result, the designer can proceed with understanding the distance and distance between the source pin and the sink pin after the floor plan, together with the number of fan-outs and the distribution value, in the HDL design. Also, the wiring form can be specified from the logical design before layout. Therefore, a floor plan is created before the RTL design describing the input of the register, and the length of the wiring path can be predicted in advance. For this reason, the designer can examine whether or not the signal propagation time is within one cycle, and if it is not within one cycle, an instruction can be given to insert a flip-flop or a buffer, and an early countermeasure can be taken.

(8-3) Information relating to the sub-signal name is taken into the waveform analysis information creation unit 58h, and information necessary for waveform analysis is output.
Furthermore, the physical technology information holds a delay value per unit wiring length and a load capacity for each technology, and the designer uses this information to create a subsystem from architecture design to PCB design. Each of the division and the subsystem division from architecture design to LSI design will be examined. Further, the designer examines portions that require detailed examination using the existing layout CAD devices 52a and 52c.

In addition, by using this physical technology information, the designer can change the technology (PCB or LSI) used for the circuit block when creating the floor plan. When changed, the delay value per unit wiring length and the load capacity used when creating the floor plan are automatically changed with reference to the physical technology information.
Furthermore, a library for PCB waveform analysis is generated using information held in the TDBs 57a to 57e of the LSI hierarchy. In addition, according to the above (8-1) to (8-3), the wiring form can be taken in as information necessary for waveform analysis from the PCB layer, and the PCB waveform can be analyzed before the LSI is completed. .

Further, the wiring delay value can be calculated by the following equation (9). Here, the crosstalk means noise caused by the closeness of the wiring interval. In order to remove the noise, the wiring interval is widened or the length of the portion where the crosstalk is generated is changed. .
Wiring delay value = (delay value per unit wiring length × wiring length) + (delay value per unit wiring length of crosstalk portion × wiring length of crosstalk portion) (9)
For example, for PCB technology or LSI technology, the delay value per unit wiring length is 7 ps / mm (picosecond / millimeter), the total wiring length is 157 mm, and the delay value per unit wiring length of the crosstalk portion is 1 ps / mm. When the wiring length of the crosstalk portion is 50 mm, the delay value is 7 ps × 157 + 1 ps × 50 = 1.149 ns.

Further, the data related to the floor plan is automatically converted into the layout data for implementation by the actual wiring cooperation units 60c and 60d, and the layout information is inherited. In addition, the designer is notified of insufficient information.
In this way, information on higher-level circuit blocks (for example, a PCB floor plan) information at the time of shrink (semiconductor miniaturization, density increases, and more circuits can be integrated within the same area, which reduces the chip area) Since it is inherited by a lower circuit block (LSI), the designer can effectively use design assets for layout information (PCB layout information).

Further, as described above, STA is performed based on the floor plan result, and if it does not fit in one cycle, a flip-flop or buffer insertion instruction is output as a distribution report. It is possible to design an RTL after allocating transmission delay in advance, predict problems during implementation, and reduce rework (iteration).
Accordingly, since the flip-flop considering the timing is inserted at the time of the architecture design in this way, the rework of the RTL redesign can be reduced. In addition, when inserting a flip-flop, the delay time is within the constraints by dividing the path even if the delay time that should satisfy the control condition (setup time) is exceeded, compared to when a buffer is inserted. Can be suppressed.

(C) Others The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.
For example, the exemplified names can be variously changed. Note that the data image in the above description is not limited to that format. In the first embodiment, an underscore symbol can be used instead of a hyphen symbol for the name.

The order of the unique processing, test circuit generation processing, and load adjustment processing is not limited to this order, and it goes without saying that various processing is performed or other processing is performed between these processing. The superiority of the present invention is not impaired even when the order is changed.
(D) Appendix (Appendix 1) A circuit information database that holds information about the circuit;
A design processing unit that reads out information about the circuit from the circuit information database and designs the circuit for each unit to be processed;
And a design information database for storing design information including at least circuit element specific information obtained in the design processing unit, change history information indicating a history of modification of the circuit, and terminal load / drive capability information of the circuit. A circuit design apparatus characterized by being configured as described above.

(Appendix 2) The design processing unit
A unique processing unit that reads the unique information from the design information database and assigns different unique names to the units to be processed;
A test circuit generation processing unit capable of reading the change history information from the design information database and generating a test circuit of an upper layer;
A load adjustment processing unit that reads out the terminal load / driving capability information from the design information database, assigns the design information to each of the terminals included in the upper layer circuit, and adjusts the load based on the design information; The circuit design device according to appendix 1, wherein the circuit design device is configured.

(Supplementary Note 3) At least one of the unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit includes:
One of the units to be processed is configured to perform a hierarchical design in which the circuit is designed in a state in which other independently designed units are hierarchically included. The circuit design device according to appendix 2.

(Supplementary Note 4)
Based on the design information database, on the basis of parameters relating to the names of the circuit elements, a proper name assignment rule setting unit for setting proper name assignment rules for assigning proper names for each of the units to be processed;
Based on the proper name assignment rule set by the proper name assignment rule setting unit, a proper name generation unit that generates a unique name different from the proper name assigned to the unit that has already been processed, in the unit to be processed; The circuit design device according to appendix 3, characterized by comprising:

(Supplementary Note 5)
Searching for locations where the same circuit unit is used more than once, and providing a multiple reference analysis unit for determining the hierarchy, cell, and black box for the type of circuit unit at the location,
The proper name generation unit
The circuit design device according to appendix 4, wherein a unique name is generated for each of a plurality of reference units and a single reference unit determined by the plurality of reference analysis units.

(Appendix 6) The unique processing unit
A circuit data duplicating unit for duplicating circuit data by allocating the unique name generated by the unique name generating unit to each of the plurality of reference units and the single reference unit. The circuit design apparatus according to appendix 5.
(Supplementary Note 7) When at least one of the unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit processes the upper layer,
A processing target determining unit that determines a processing target / non-processing target for a unit to be processed based on the design information written in the design information database;
A processing data acquisition unit configured to acquire circuit data of the unit to be processed from the circuit information database based on the processing target / non-processing target determined by the processing target determination unit. The circuit design apparatus according to appendix 3.

(Supplementary Note 8) At least one of the unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit includes:
The supplementary note 2 is characterized by comprising a processing target determining unit for determining a processing target / non-processing target for a unit to be processed based on the design information written in the design information database. Circuit design equipment.

(Supplementary note 9)
Based on the first unit information related to the processing result of the first unit obtained by processing the first unit in the design information, the unit included in the second unit to be processed next is the processed unit. 3. The circuit design device according to appendix 2, wherein the circuit design device is configured to determine whether or not.
(Supplementary Note 10) The test circuit generation processing unit
A hierarchical consistency restoration unit that eliminates terminal inconsistency between a terminal added as a test signal input in a lower hierarchy and a terminal in a hierarchy referenced by an upper hierarchy based on the design information held in the design information database The circuit design device according to appendix 3, characterized by comprising:

(Supplementary Note 11) At least one of the unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit includes:
A part of the unit to be processed is changed, and an engineering chain order design (hereinafter referred to as ECO design) is performed for redesign without changing other parts of the circuit. The circuit design device according to appendix 2.

(Supplementary Note 12) At least one of the unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit includes:
A design information reading unit that reads normal design information created by normal design;
A processing target determination unit that determines circuit data to be processed using the normal design information and ECO target unit information given by parameters;
12. The circuit design device according to appendix 11, wherein the circuit designed by using the normal design information is designed to design a circuit that is the same as a circuit that is normally designed except for the changed part.

(Supplementary note 13)
When the upper layer refers to the design information, the unit to be processed is duplicated as many times as the plurality of references, and the unique name is assigned to each unit to be processed after the addition.
A processing target determining unit that determines a processing target / non-processing target for a unit to be processed based on the design information written in the design information database;
When the processing target determination unit determines that the processing target is to be processed, the unique name is generated so that the reference relationship is the same as the reference relationship stored in the design information database, and the processing target determination unit determines that the processing target is not to be processed The circuit design device according to appendix 11, characterized by comprising a unique name generator for generating a unique name different from the already assigned unique name.

(Supplementary Note 14) The test circuit generation processing unit
Based on the design information database, using the normal design information and test circuit rules created during normal design for the ECO design target unit, a part that can generate the same test circuit as during normal design, and a new test circuit 12. A circuit design apparatus according to appendix 11, characterized by comprising a circuit analysis unit for extracting identification data for identifying each of the parts to be generated.

(Supplementary Note 15) The test circuit generation processing unit
A hierarchical consistency restoration unit that eliminates terminal inconsistency between a terminal added as a test signal input in a lower hierarchy and a terminal in a hierarchy referenced by an upper hierarchy based on the design information held in the design information database With
The hierarchical consistency restoration unit
Supplementary note 11 characterized in that it is configured to restore hierarchical consistency using normal design information about normal design, ECO design target unit, and terminal information in the higher hierarchy among the design information. The circuit design apparatus described.

(Supplementary Note 16) The test circuit generation processing unit
Based on the identification data extracted by the circuit analysis unit, for the ECO design target unit, the same test circuit is generated for the part that can generate the same test circuit as in normal design, and a new test circuit is to be generated 15. The circuit design device according to appendix 14, characterized by comprising a test circuit generation unit for generating a test circuit in accordance with the test circuit rules.

(Supplementary Note 17) The unique processing unit
A design information reading unit for reading the design information from the design information database;
The design information reading unit
Supplementary Note 2 or Supplementary Note, wherein the hierarchical name before uniqueization is associated with the hierarchical name after uniqueization so that the circuit data after uniqueization by the hierarchical name before uniqueization can be referred to 11. The circuit design device according to 11.

(Supplementary Note 18) The load adjustment processing unit
Analyzing the terminal capacitance that can be driven by the logic element, and extracting a terminal that cannot be driven,
3. The circuit design device according to appendix 2, characterized by comprising a circuit adjustment unit that adjusts the drive capability of the non-driveable terminal extracted by the load analysis unit.
(Supplementary note 19) The circuit information database is
In at least one of hierarchical design and engineering change order design (hereinafter referred to as ECO design),
A circuit information writing unit for writing circuit information to the circuit information database for each processed unit;
The circuit design apparatus according to appendix 1, characterized by comprising a reference unit connected to the circuit information writing unit and capable of referring to the circuit information written for each unit to be processed.

(Supplementary note 20) The design information database is
12. The circuit design device according to appendix 11, characterized by comprising a plurality of holding units capable of storing the circuit elements in individual files.
(Supplementary Note 21) In the circuit design method,
A first unit obtained by processing the first unit in a design processing unit that reads out information about the circuit from a circuit information database that holds information about the circuit and designs the circuit for each unit to be processed. A process generation step of generating first unit information relating to the process result of
A design information collecting step for collecting design information including unique information of at least circuit elements being generated in the process generating step, change history information indicating a history of changing the circuit, and terminal load / drive capability information of the circuit; ,
A design information writing step for writing the design information collected in the design information collecting step for each unit to be processed in a design information database connected to the design processing unit and holding the design information;
A step of referring to design information relating to the first unit to process the second unit based on the design information written in the design information writing step;
A recognition step for recognizing a reference relationship with respect to the design information related to the first unit referred to in the reference step;
A circuit information database reference step for referring to unit information regarding the position and processing result held in the circuit information database based on the reference relationship obtained in the reference step;
A circuit design method comprising a circuit information database writing step for updating circuit data subjected to design processing.

(Supplementary Note 22) In the circuit design method,
Read the information about the circuit from the circuit information database holding the information about the circuit, and process the fourth unit including the third unit in the design processing unit that can design the circuit for each unit to be processed. A first processing step;
A third unit information collecting step for collecting third unit information relating to the processing result of the third unit being generated in the first processing step;
A design information writing step for writing the third unit information collected in the third unit information collecting step into a design information database connected to the design processing unit and holding the design information;
Based on the third unit information written in the design information writing step, a third processed unit obtained by changing the third unit is obtained by changing the fourth unit. A circuit design method comprising: a step of determining whether or not to include a unit, and a determination step of determining whether or not the third processed unit is equivalent to the third unit .

(Supplementary note 23)
The information related to the circuit is read from the circuit information database holding the information related to the circuit, the circuit is designed for each unit to be processed, and the at least circuit element specific information obtained by the design is changed. A computer-readable recording medium on which a program is recorded for causing a function to hold design information including change history information representing a history and terminal load / drive capability information of the circuit in the design information database.

(Supplementary Note 24)
A first unit obtained by processing the first unit in a design processing unit that reads out information about the circuit from a circuit information database that holds information about the circuit and designs the circuit for each unit to be processed. A process generation step of generating first unit information relating to the process result of
A design information collecting step for collecting design information including unique information of at least circuit elements being generated in the process generating step, change history information indicating a history of changing the circuit, and terminal load / drive capability information of the circuit; ,
A design information writing step for writing the design information collected in the design information collecting step for each unit to be processed in a design information database connected to the design processing unit and holding the design information;
A step of referring to design information relating to the first unit to process the second unit based on the design information written in the design information writing step;
A recognition step for recognizing a reference relationship with respect to the design information related to the first unit referred to in the reference step;
A circuit information database reference step for referring to unit information regarding the position and processing result held in the circuit information database based on the reference relationship obtained in the reference step;
A computer-readable recording medium on which a program is recorded for causing a circuit information database writing step of updating circuit data subjected to design processing to be executed.

(Supplementary note 25)
Read the information about the circuit from the circuit information database holding the information about the circuit, and process the fourth unit including the third unit in the design processing unit that can design the circuit for each unit to be processed. A first processing step;
A third unit information collecting step for collecting third unit information relating to the processing result of the third unit being generated in the first processing step;
A design information writing step for writing the third unit information collected in the third unit information collecting step into a design information database connected to the design processing unit and holding the design information;
Based on the third unit information written in the design information writing step, a third processed unit obtained by changing the third unit is obtained by changing the fourth unit. A program is recorded for determining whether to include a unit and to execute a determination step for determining whether the third processed unit is equivalent to the third unit. Computer-readable recording medium.

(Supplementary note 26) In hierarchical design,
Block information related to the function of the circuit is input from a plurality of timing information databases having netlist information related to the wiring form provided corresponding to each of the plurality of design hierarchies, and delay values generated by delay elements of the circuit are allocated. A plurality of timing distribution generation units capable of outputting the obtained timing distribution values;
A connection between the plurality of timing distribution creation units is dynamically changed, and an inter-layer cooperation manager is provided that transmits and receives correction information related to the timing distribution value between each of the plurality of timing distribution creation units. A timing distribution device, characterized by being configured.

(Supplementary Note 27) The timing distribution creation unit is configured as an agent having a hierarchy entity having design information provided corresponding to each of the plurality of design hierarchies and program data for processing the design information. ,
27. The appendix 26, wherein the inter-layer cooperation manager is configured as a manager that is connected to the timing distribution creation unit as the agent and transmits / receives information on the timing distribution value with each of the plurality of design layers. Timing distribution device.

(Supplementary Note 28) The timing distribution creation unit
A logic / constraint information holding unit for holding logic / constraint information having at least a netlist relating to the source code of the design language, the block information and the constraint information relating to wiring;
A floor plan unit that is connected to the logic / constraint information holding unit and distributes timing based on a floor plan related to arrangement of circuit elements and wiring between circuit elements, and performs temporary wiring;
A timing information holding unit connected to the floor plan unit and holding the netlist information;
Item 27. The apparatus according to claim 27, further comprising: a distribution manager connected to the logic / constraint information holding unit and the timing information holding unit and outputting at least the delay value based on the netlist information. Timing distribution device.

(Appendix 29) The floor plan section
Connected to the logic / constraint information holding unit, presents a portion where the distribution value as attribute information can be improved and corrected based on slack from the constraint information, and holds the arrangement information resulting from the delay element information An arrangement processing unit to
An actual wiring / provisional wiring execution unit that is connected to the placement processing unit and performs linkage to temporary wiring and temporary wiring and outputs wiring information;
A wiring information holding unit that is connected to the real wiring / provisional wiring execution unit and holds the wiring information;
A physical technology information holding unit that holds physical technology information including at least a delay value per unit length corresponding to a wiring width and a wiring layer and a load capacity per unit length in order to output the timing information;
The wiring information holding unit and the physical technology information holding unit are connected to each other, and are configured to include a conversion unit that converts the wiring information into a delay value based on a delay length and a load capacity, and outputs the delay value. The timing distribution device according to appendix 28.

(Supplementary Note 30) The real wiring / provisional wiring execution unit
30. The timing distribution device according to appendix 29, wherein the timing distribution apparatus is configured to perform wiring in combination with an actual wiring that requires a long calculation time and a temporary wiring that has a short calculation time, and to extract the timing distribution value.
(Supplementary Note 31) The real wiring / provisional wiring execution unit
Manhattan-length temporary wiring for both printed circuit boards and large-scale integrated circuits based on the placement result of the placement support unit that presents parts that can be improved and modified based on slack from the constraint information. A Manhattan long temporary wiring section,
An oblique Manhattan length temporary wiring portion for temporary wiring using oblique wiring that is obliquely wired with respect to an edge of the printed circuit board based on the placement result;
30. The timing distribution device according to appendix 29, characterized by comprising an actual wiring link unit for wiring the printed circuit board and the large-scale integrated circuit.

(Supplementary Note 32) The real wiring / provisional wiring execution unit
32. The timing distribution device according to appendix 31, wherein the provisional wiring is configured based on the Manhattan long temporary wiring, the oblique Manhattan long temporary wiring, and the actual wiring.
(Supplementary Note 33) The actual wiring / temporary wiring execution unit
Supplementary note 29. The delay value and the load capacity of the selected hierarchy are read from the physical technology information holding unit and distributed by changing the delay time per unit wiring length. The timing distribution device described.

(Appendix 34) The real wiring / provisional wiring execution unit
32. The timing distribution device according to appendix 31, wherein the timing distribution device is configured to perform actual wiring based on the margin calculated with respect to the timing distribution value obtained by the temporary wiring and a wiring congestion degree representing a wiring density. .
(Appendix 35) The real wiring / provisional wiring execution unit
Item 31. The supplementary note 31 is configured to output information for analysis related to information deficient in the actual wiring so as to be linked with a design apparatus that uses another computer capable of performing only the actual wiring. Timing distribution device.

(Supplementary Note 36) The actual wiring / temporary wiring execution unit
32. The timing distribution device according to appendix 31, wherein the timing distribution device is configured to perform the temporary wiring and the actual wiring based on at least a wiring prohibited area and the wiring congestion degree.
(Appendix 37) The real wiring / provisional wiring execution unit
Based on the clock frequency used as the constraint condition, it is determined whether or not it can be reached within the time that must be reached. The timing distribution device according to appendix 31, wherein the timing distribution device is configured to instruct insertion of at least one of them.

(Supplementary Note 38) The actual wiring / temporary wiring execution unit
32. The timing distribution device according to appendix 31, wherein terminals included in the circuit block are arranged based on the constraint information.
(Appendix 39) The inter-tier cooperation manager
The timing information database is configured to extract and input the circuit block for which the timing information data is lacking, and to notify the designer of the lack of the circuit block. 28. The timing distribution device according to appendix 27.

(Appendix 40) The floor plan section
29. The timing distribution device according to appendix 28, wherein the wiring width in the circuit block is configured to be changed while performing actual wiring and temporary wiring.
(Supplementary note 41) The inter-tier cooperation manager
28. The timing distribution device according to appendix 27, wherein the combination of the plurality of distribution managers can be changed.

(Supplementary Note 42) The timing distribution creation unit further includes:
29. The timing distribution device according to appendix 28, further comprising a waveform analysis information generation unit that generates information for waveform analysis of a printed circuit board from input / output buffer information of a hierarchy of a large-scale integrated circuit.
(Supplementary Note 43) The timing distribution creation unit
29. The timing distribution device according to appendix 28, wherein the timing distribution device is configured to output the timing distribution value based on other preset timing specifications and the timing allocated by the floor plan unit. .

(Appendix 44) The floor plan section
29. The timing distribution device according to appendix 28, wherein the timing distribution device is configured so that at least one of the scale and shape of the circuit block can be changed while performing actual wiring and temporary wiring.
(Supplementary Note 45) The timing distribution creation unit
29. The timing distribution device according to appendix 28, wherein the timing distribution device is configured to read a timing distribution value back-annotated from a logic design or layout study using the source code.

(Supplementary Note 46) The timing distribution creation unit
29. The timing distribution device according to appendix 28, further comprising an annotator for writing information resulting from the timing distribution value into the source code.
(Appendix 47) The annotator is
47. The timing distribution device according to appendix 46, wherein the source code is configured to write net list information relating to a wiring form.

(Supplementary Note 48) The physical technology information holding unit
30. The timing distribution device according to appendix 29, wherein the wiring length, the delay value per unit length, and the load capacity per unit length are held in association with each other.
(Supplementary Note 49) The inter-tier cooperation manager
The timing distribution specification change request transmitted by one of the plurality of timing information databases is received, another timing information database that can be affected by the timing distribution specification change is extracted, and the other timing information database is extracted. 27. The timing distribution device according to appendix 26, configured to inquire whether the timing distribution value can be changed.

(Supplementary Note 50) The inter-tier cooperation manager
28. The timing distribution apparatus according to appendix 27, wherein the timing distribution device is configured to output a change possibility to a desired timing information database when receiving the change possibility of the timing distribution value from the other timing information database.
(Supplementary Note 51) The inter-tier cooperation manager
29. The timing distribution device according to appendix 28, wherein when the timing distribution value is changed, the hierarchy entity higher than the changed hierarchy is updated.

(Supplementary Note 52) The allocation manager
A distribution editor that is connected to the logic / constraint information holding unit and distributes timing;
A database reference registration unit connected to the distribution editor, the logic / constraint information holding unit, and the timing information holding unit and outputting the netlist information;
Own hierarchy timing information database output / other hierarchy timing information database reflection unit for inputting / outputting timing distribution information of own hierarchy and timing distribution information of other hierarchy;
28. The timing distribution device according to appendix 27, further comprising an arbitration control unit that performs arbitration.

(Supplementary Note 53) The allocation manager
29. The apparatus according to claim 28, wherein the skew representing the phase difference of the arrival times of the signals is calculated based on the net list information relating to the wiring form based on the wiring path other than the common wiring path. Timing distribution device.
(Supplementary Note 54) The allocation manager
29. The timing distribution device according to appendix 28, wherein the wiring path is configured to give a name representing a wiring form as a sub-signal name.

(Supplementary Note 55) The allocation manager
29. The timing distribution device according to appendix 28, wherein the sub-signal name and the fan-out number are associated and named.
(Supplementary Note 56) The allocation manager
29. The timing distribution device according to appendix 28, wherein a gradation corresponding to the value of the restriction information is displayed in a color on the operation screen for the wired portion.

(Supplementary Note 57) The allocation manager
29. The timing distribution apparatus according to appendix 28, wherein the timing distribution device is configured to display the timing distribution value and a range of values in which the timing distribution is possible in a diagram showing the circuit block.
(Supplementary Note 58) In designing a hierarchy, computers are
Provided corresponding to each of a plurality of design hierarchies, obtained by distributing block values related to the function of the circuit from a plurality of timing information databases having net list information related to the wiring form, and distributing delay values caused by delay elements of the circuit A plurality of timing distribution creation units capable of outputting timing distribution values;
A program is recorded that is connected to each of the plurality of timing distribution creation units, and functions as an inter-layer cooperation manager that transmits and receives correction information related to the timing distribution values between each of the plurality of timing distribution creation units. Computer-readable recording medium.

As described above, according to the circuit design device, the circuit design method, and the timing distribution device of the present invention as the related art of the present invention described in the supplementary notes, the following effects can be obtained.
(1) a circuit design apparatus in which a circuit information database that holds information about a circuit, a design processing unit that reads out information about a circuit from the circuit information database and processes the circuit for each unit to be processed, and a design processing unit Since it is configured with at least the design information database that holds design information including at least circuit element specific information, change history information that represents the history of circuit changes, and circuit terminal load / drive capability information, The usage amount of the working memory is optimized, and the burden on the designer in hierarchical design and ECO design can be reduced to the same level as in the case of batch design. In addition, continuous processing is possible through full automation, which can reduce processing time and thus the design period.

  (2) The design processing unit reads the unique information from the design information database and assigns different unique names to each unit to be processed, and the change history information from the design information database and the upper hierarchy The test circuit generation processing unit that can generate the test circuit of the device, and the terminal load / drive capability information is read from the design information database, design information is assigned to each of the terminals included in the upper layer circuit, and the load based on the design information In this way, design information such as hierarchy boundary information and terminals is automatically input, and the processing target part in the current processing is processed from the processing history. Is automatically determined, and the design information included in the unprocessed part is automatically extracted to process the part currently being designed. There is an advantage that can be used to.

  (3) The circuit design method reads the information about the circuit from the circuit information database holding the information about the circuit, and processes the first unit in the design processing unit that can design the circuit for each unit to be processed. A process generation step for generating first unit information related to the processing result of the first unit obtained in this way, unique information of at least circuit elements being generated in the process generation step, change history information representing a history of circuit changes, and Design information collection step that collects design information including circuit terminal load and drive capability information, and the design information collected in the design information collection step is connected to the design processing unit and processed into a design information database that holds the design information The design information writing step for each unit to be written and the second unit based on the design information written in the design information writing step. Are obtained in the reference step for referring to the design information related to the first unit, the recognition step for recognizing the reference relationship for the design information related to the first unit referenced in the reference step, and the reference step. A circuit information database reference step for referring to unit information relating to positions and processing results held in the circuit information database, and a circuit information database writing step for updating design-processed circuit data. Therefore, reading from the circuit information database for the lower hierarchy is not required, and the capacity of the working memory used for the unique processing can be greatly saved.

  (4) The timing distribution device is provided corresponding to each of the plurality of design layers in the hierarchical design, and block information related to the function of the circuit is input from a plurality of timing information databases having net list information related to the wiring form, A plurality of timing distribution generation units capable of outputting timing distribution values obtained by allocating delay values caused by delay elements of the plurality of timing elements, and dynamically changing connections between the plurality of timing distribution generation units, and a plurality of timings Since it is configured with inter-tier linkage managers that send and receive correction information related to timing distribution values between each of the distribution creation units, when the timing specifications are changed, the affected range can be referred to immediately, and the specifications Change reference mistakes are eliminated. In addition, the combination of temporary wiring and actual wiring can improve both floor plan execution speed and accuracy. Furthermore, hierarchical entities can be used, a distributed design environment can be constructed, only the necessary parts can be detailed in top-down design, and the quality of the timing specifications divided by trial examination can be examined by one design team at the time of implementation. Problem can be predicted and rework can be reduced.

  (5) The timing distribution creating unit is configured as an agent provided corresponding to each of a plurality of design hierarchies and having a hierarchy entity having design information and program data for processing the design information, and inter-tier cooperation The manager may be configured as a manager that is connected to the timing distribution creation unit as an agent and transmits / receives information on timing distribution values with each of a plurality of design hierarchies, and in this way, by an object-oriented hierarchical entity, When timing-driven layout processing that combines logical design and physical layout is performed, the flow of information between each logical hierarchy and physical hierarchy becomes clear, and cooperation is facilitated.

  (6) The unique processing unit may be configured to include a unique name assigning rule setting unit and a unique name generation unit. In this way, the original unique name before the circuit is changed by the designer New names are generated based on the setting values set by the designer, and even when multiple names are generated by referring to multiple names, the names can be clearly identified. Names can be easily grouped and grouped by unit to be processed. Also, duplication of the processed unit and the name of the unit currently being processed is avoided.

  (7) The unique processing unit searches for a location where a plurality of the same circuit units are used, and includes a multiple reference analysis unit for discriminating a hierarchy, a cell, and a black box for the type of the circuit unit at the location, and is unique The processing unit may be configured to generate a unique name for each of the multiple reference unit and the single reference unit determined by the multiple reference analysis unit, and the unique name generated by the unique name generation unit A name may be assigned to each of a plurality of reference units and a single reference unit, and a circuit data duplicating unit that duplicates circuit data may be provided. In this way, the unique processing can be performed efficiently, and Fine design is possible.

  (8) When the unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit respectively process the upper layer, the unit to be processed is based on the design information written in the design information database. Process data acquisition for acquiring a unit of circuit data to be processed from the circuit information database based on a process target determination unit for determining a process target / non-process target and a process target / non-process target determined by the process target determination unit In this way, it is possible to save working memory.

(9) The unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit respectively select the processing target / non-processing target for the unit to be processed based on the design information written in the design information database. It may be configured to include a processing target determination unit for determining, and in this way, information regarding a portion to be processed can be easily obtained.
(10) The second unit to be processed next is included based on the first unit information on the processing result of the first unit obtained by processing the first unit in the design information. It may be configured to determine whether or not the unit to be processed is a processed unit, and in this way, the location to be processed can be easily determined.

(11) Based on the design information held in the design information database, the terminal mismatch between the terminal added for test signal input to the lower layer and the terminal in the layer referenced by the upper layer based on the design information held in the design information database In this way, the operability of the designer in ECO design is greatly improved.
(12) The unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit may each be configured to perform ECO design, and in this way, an operation procedure with the same circuit design. Can be used.

  (13) The unique processing unit, the test circuit generation processing unit, and the load adjustment processing unit are given by a design information reading unit that reads normal design information created by normal design, and normal design information and parameters, respectively. A processing target discriminating unit for discriminating circuit data to be processed using the ECO target unit information is configured so that a circuit that is normally designed using normal design information and a circuit other than the changed part are designed in the same manner. In this way, continuous processing can be performed by full automation, and the processing time can be reduced, and thus the design period can be shortened.

  (14) The unique processing unit determines a processing target / non-processing target for a unit to be processed based on the design information written in the design information database, and a processing target in the processing target determination unit If it is determined, a unique name is generated so that the reference relationship is the same as the reference relationship held in the design information database. If it is determined that it is not to be processed, a unique name different from the already assigned unique name is generated. In this way, when the upper layer refers to the design information, the unit to be processed can be duplicated by the number of multiple references, and the processing after the addition is performed. Each unique unit can be given a unique name.

  (15) Based on the design information database, the test circuit generation processing unit generates the same test circuit as in the normal design using the normal design information and the test circuit rules created in the normal design for the ECO design target unit. And a circuit analysis unit that extracts identification data for identifying each of a portion where a new test circuit should be generated and a circuit analysis unit that extracts identification data. Optimized.

(16) The hierarchical consistency restoration unit is configured to restore the hierarchical consistency using the normal design information about the normal design, the ECO design target unit, and the terminal information in the upper hierarchy among the design information. In this way, a large-scale circuit can be designed for each part.
(17) Based on the identification data extracted by the circuit analysis unit, the test circuit generation processing unit generates, for the ECO design target unit, the same test circuit for a portion that can generate the same test circuit as in normal design, A portion that should generate a test circuit may be configured to include a test circuit generation unit that generates a test circuit in accordance with the test circuit rule. In this way, the design efficiency of ECO design is greatly improved. .

(18) Even if the design information reading unit is configured to associate the hierarchical name before uniqueization with the hierarchical name after uniqueization and refer to circuit data after uniqueization by the hierarchical name before uniqueization. In this way, it is possible to obtain the presence / absence of the unique process and the hierarchy names before and after the unique process.
(19) The load adjustment processing unit analyzes the terminal capacity that can be driven by the logic element, and extracts a non-driveable terminal, and the drive capability of the non-driveable terminal extracted by the load analysis unit A circuit adjustment unit to be adjusted may be provided, and in this way, each terminal in the circuit is adjusted to an appropriate capacity.

(20) A circuit information database is connected to the circuit information writing unit for writing circuit information to the circuit information database for each processed unit in the hierarchical design and the ECO design, and connected to the circuit information writing unit for each unit to be processed. A reference unit that can refer to the written circuit information may be provided. In this way, design efficiency is improved.
(21) The design information database may be configured to include a plurality of holding units that can store circuit elements in individual files. In this way, the design information is reflected in the circuit design, and the design period, etc. Work efficiency is improved.

  (22) The circuit design method collects, in the design processing unit, the first processing step for processing the fourth unit including the third unit, and the third unit information regarding the processing result of the third unit being generated. A third unit information collecting step, a design information writing step for writing the collected third unit information to a design information database connected to the design processing unit and holding the design information, and a third unit information based on the written third unit information. It is determined whether or not the third processed unit obtained by changing the unit of 3 includes the fourth processed unit obtained by changing the fourth unit, and the third processed unit is the third processed unit. Since it is configured to include a determination step for determining whether or not it is equivalent to a unit, continuous processing can be performed by full automation, and the processing time can be reduced, and thus the design period can be shortened. Hierarchical design can be easily realized, and hierarchical design of large-scale circuits can be performed very efficiently.

  (23) The program of the present invention reads out information about a circuit from a circuit information database and designs a circuit for each unit to be processed, as well as circuit element specific information obtained by the design and history of circuit changes. Since the design information including the change history information representing the circuit information and the terminal load / drive capability information of the circuit is held in the design information database, an environment for designing a large-scale circuit can be easily constructed.

  (24) The program according to the present invention causes the design processing unit to generate a first unit information related to the processing result of the first unit in the computer, a change history information being generated, and a terminal load / drive of the circuit A design information collecting step for collecting design information including capability information, a design information writing step for writing the collected design information for each unit to be processed in the design information database, and a second based on the written design information. Based on the obtained reference relationship, a reference step for referring to the design information related to the first unit, a recognition step for recognizing the reference relationship for the design information related to the referenced first unit to process the unit Circuit information database reference step for referring to unit information related to the position and processing result held in the information database, and design processing Since the is operable to execute a circuit information database writes updating circuit data, whether or not the first unit is already processing is automatically recognized in the case of for example contained.

  (25) A program according to the present invention reads out information relating to a circuit from a circuit information database to a computer, and a first processing step of processing a fourth unit including the third unit in a design processing unit; A third unit information collecting step for collecting third unit information relating to the processing result of the third unit, a design information writing step for writing the collected third unit information in the design information database, and the written third unit Based on the information, it is determined whether the third processed unit obtained by changing the third unit includes the fourth processed unit obtained by changing the fourth unit, and the third processed unit Since the function to execute the determination step for determining whether the unit is equal to the third unit or not, continuous processing is possible by full automation, reducing the processing time and consequently the design period. It can be shortened.

  (26) The timing distribution creating unit is configured as an agent having a hierarchy entity provided corresponding to each of a plurality of design hierarchies and program data for processing design information, and It may be configured as a manager that is connected to the timing distribution creation unit as an agent and transmits / receives information on timing distribution values to / from each of a plurality of design hierarchies. Communication is possible via the cooperation manager.

  (27) A timing distribution creating unit holds a logic / constraint information holding unit that holds delay element information, a floor plan unit that distributes timing based on a floor plan and performs temporary wiring, and holds timing information that holds netlist information And a distribution manager that outputs a delay value based on the netlist information. In this way, a flexible design change is possible.

  (28) a layout processing unit that presents a portion that can be improved and modified based on slack from the constraint information with respect to the distribution value as attribute information, and that stores the layout information resulting from the delay element information; Real wiring / temporary wiring execution unit for linking to temporary wiring and temporary wiring and outputting wiring information, wiring information holding unit for holding wiring information, delay value per unit length and load capacity per unit length A physical technology information holding unit that holds physical technology information, and a conversion unit that converts the wiring information into a delay value based on the delay length and the load capacity, and outputs it. For example, the delay value can be easily calculated from the wiring length.

(29) The actual wiring / temporary wiring execution unit may be configured to perform wiring using both the actual wiring that requires a long calculation time and the temporary wiring that has a short calculation time, and extract a timing distribution value. In this way, the designer can examine the timing specifications by provisional wiring and change the timing distribution based on the result obtained by the examination to perform actual wiring.
(30) An actual wiring / temporary wiring execution unit, a Manhattan length temporary wiring unit for temporary wiring of Manhattan length for both PCB and LSI, and an oblique Manhattan length temporary wiring unit for temporary wiring using diagonal wiring for diagonal wiring The printed circuit board and the large-scale integrated circuit may be provided with an actual wiring link unit for wiring, and in this way, the efficiency of wiring work is improved.

(31) The actual wiring / temporary wiring execution unit may be configured to perform temporary wiring based on the Manhattan long temporary wiring, the oblique Manhattan long temporary wiring, and the actual wiring. Accuracy is improved even in dense places.
(32) The real wiring / provisional wiring execution unit is configured to read the delay value and the load capacity for the selected hierarchy from the physical technology information holding unit, and distribute the variable while changing the delay time per unit wiring length. In this way, the efficiency of the wiring work is improved.

(33) The actual wiring / provisional wiring execution unit may be configured to perform actual wiring based on the margin calculated for the timing distribution value obtained by the temporary wiring and the wiring congestion degree indicating the wiring density. By doing so, since the temporary wiring or the actual wiring is automatically switched according to the degree of wiring congestion, the trade-off can be effectively utilized, and the effort of the designer can be reduced.
(34) The real wiring / provisional wiring execution unit is configured to output information for analysis related to information lacking in the actual wiring so as to be linked with a design apparatus that supports other computers capable of performing only actual wiring. In this way, the designer is notified of information that is insufficient when actual wiring is performed, and the designer creates information necessary for analysis based on the information, and sends the information to the layout CAD device dedicated to actual wiring. Can be sent and wired.

(35) The actual wiring / temporary wiring execution unit may be configured to perform temporary wiring and actual wiring based on the wiring prohibition area and the wiring congestion degree. Detailed actual wiring depending on the target circuit block can be mixed and wired, and the timing distribution value can be extracted.
(36) The real wiring / provisional wiring execution unit determines whether it can be reached within the time that must be reached based on the clock frequency used as the constraint condition. It may be configured to instruct insertion of buffers and flip-flops with respect to the list information. In this way, a buffer or the like is inserted only when the virtual pin cannot be reached. Can be met effectively.

(37) The actual wiring / provisional wiring execution unit may be configured to arrange the terminals included in the circuit block based on the restriction information, and in this way, the arrangement becomes simple.
(38) The inter-layer cooperation manager may be configured to extract a circuit block lacking timing information data from the timing information database and notify the designer of the missing circuit block. In this way, the work efficiency of the designer is improved.

(39) The floor plan unit may be configured such that the wiring width in the circuit block can be changed while the actual wiring and the temporary wiring are being performed. In this way, the wiring width can be changed, so that the circuit Can be designed flexibly.
(40) The inter-tier cooperation manager may be configured to change the combination of a plurality of distribution managers, and in this way, it can be freely and dynamically changed according to the design object.

(41) The timing distribution creation unit may be configured to include a waveform analysis information creation unit that generates information for PCB waveform analysis from I / O buffer information of the LSI layer. Waveform can be easily analyzed.
(42) The timing distribution creation unit may be configured to output a timing distribution value based on other preset timing specifications and the timing distributed by the floor plan unit. For example, the designer can refer to the distribution report describing the distribution value.

(43) The floor plan unit may be configured such that the scale or shape of the circuit block can be changed while the actual wiring and the temporary wiring are being performed. In this way, a flexible layout design is possible.
(44) The timing allocation creating unit may be configured to read the timing allocation value back-annotated from the logic design or layout examination using the source code. In this way, the designer can easily Can simulate.

(45) The timing distribution creation unit may be configured to include an annotator that writes information resulting from the timing distribution value into the source code. In this way, a user interface between the designer and the circuit design device is provided. Get closer.
(46) The annotator may be configured to write netlist information relating to the wiring form in the source code. In this way, the distributed value is back-annotated in the source code, and the delay value is automatically set. Set or changed.

(47) The physical technology information holding unit may be configured to hold the wiring length, the delay value per unit length, and the load capacity per unit length in association with each other. A delay value is calculated from the wiring length.
(48) The inter-layer cooperation manager receives the timing distribution specification change request transmitted by one of the plurality of timing information databases, extracts other timing information databases that can be affected by the timing distribution specification change, The timing information database may be inquired as to whether or not the timing distribution value can be changed. In this way, the timing specification change is promptly notified.

(49) When the inter-layer cooperation manager receives the change of the timing distribution value from another timing information database, it may be configured to output the change possibility to the desired timing information database. As a result, the timing specification can be quickly changed.
(50) When the timing distribution value is changed, the inter-layer cooperation manager may be configured such that a hierarchical entity higher than the changed hierarchy is updated. Specification changes are quicker.

  (51) A database in which a distribution manager is connected to a logic / constraint information holding unit and connected to a distribution editor for timing distribution, a distribution editor, a logic / constraint information holding unit, and a timing information holding unit, and outputs netlist information A reference registration unit, a self-hierarchy TDB output / other-hierarchy TDB automatic reflection unit for inputting / outputting timing distribution information of its own layer and timing distribution information of another layer, and an arbitration control unit that performs arbitration are configured. In this way, the distribution value is efficiently reflected.

(52) The distribution manager may be configured to calculate the skew on the basis of a wiring path other than the common wiring path among the wiring paths of the netlist information relating to the wiring form. Calculations with variations removed can be performed automatically.
(53) The distribution manager may be configured to give the wiring path a name representing the wiring form as the sub-signal name. In this way, the layout becomes unnecessary and the number of wiring layers is known. This also reduces man-hours for allocation.

(54) The distribution manager may be configured to name the sub-signal name and the fan-out number in association with each other. In this way, since the attribute is given to each pin and each wiring, the man-hour is also reduced. Reduce.
(55) The distribution manager may be configured to display a gradation according to the value of the constraint information on the operation screen with respect to the wired portion, so that variations in the common portion can be removed. Can do.

(56) The distribution manager may be configured to display a timing distribution value and a range of values capable of timing distribution on the diagram showing the circuit block, and in this way, the designer can select a highly reliable circuit. Can design.
(57) When the hierarchical design is performed by the program of the present invention, since the computer functions as a plurality of timing distribution creation units and inter-layer cooperation managers, for example, terminal boundary information and terminal design information are automatically Is automatically determined from the processing history, and the design information contained in the non-processing part is automatically extracted and used for processing the part currently being designed. it can. For the critical portion, the wiring form can be designated before the layout, so that highly reliable wiring after the actual layout is possible. Detailed examination can be performed using an existing PCB layout CAD device or LSI layout CAD device, and the design can be directly connected to the implementation. Therefore, the design can be performed without changing the existing design flow. In addition, since the PCB can be analyzed by the waveform analysis information before the LSI is completed, the parallel design of the LSI and the PCB is facilitated.

  In addition, since the floor plan information that does not depend on technology can be reused, existing layout assets can be used effectively. Furthermore, it becomes possible to design a timing that integrates PCB and LSI, which are components of a high-speed system that will become increasingly important in the future. In the architecture design, a part having a critical and important timing specification at the time of implementation can be grasped in advance by distributed examination, so that the development period can be greatly shortened and a highly reliable design can be achieved.

1 is a configuration diagram of a circuit design device according to a first embodiment of the present invention. It is a block diagram of the unique process part which concerns on 1st Embodiment of this invention. 2 is a block diagram of a test circuit generation processing unit according to the first embodiment of the present invention. FIG. It is a block diagram of the load adjustment process part which concerns on 1st Embodiment of this invention. It is a conceptual diagram of the HDL conversion which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the unique process based on 1st Embodiment of this invention. (A)-(d) is a figure for demonstrating the specificization process in the ECO design which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the circuit change in the ECO design which concerns on 1st Embodiment of this invention. (A), (b) is a figure for demonstrating the test circuit generation process in the hierarchical design based on 1st Embodiment of this invention. (A)-(d) is a figure for demonstrating the test circuit production | generation process in the ECO design which concerns on 1st Embodiment of this invention. (A)-(d) is a figure for demonstrating the load adjustment process in the hierarchical design which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the flow of the circuit data which concerns on 1st Embodiment of this invention. It is a figure which shows the data image of the semiconductor circuit which concerns on 1st Embodiment of this invention. It is a flowchart for demonstrating the hierarchical design which concerns on 1st Embodiment of this invention. It is a figure which shows the data image of the other semiconductor circuit which concerns on 1st Embodiment of this invention. (A), (b) is a flowchart for demonstrating the ECO process which concerns on 1st Embodiment of this invention. It is a figure which shows the process of the circuit design which concerns on 2nd Embodiment of this invention. It is a figure which shows the process of the block division | segmentation design which concerns on 2nd Embodiment of this invention. It is a block diagram of the circuit design apparatus which concerns on 2nd Embodiment of this invention. It is a block diagram of the timing distribution apparatus which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating transmission / reception of the distribution value between the hierarchies which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating transmission / reception of the distribution value between the upper hierarchy based on 2nd Embodiment of this invention, and a lower hierarchy. It is a figure for demonstrating the hierarchy entity which concerns on 2nd Embodiment of this invention. It is a block diagram of the timing distribution preparation part which concerns on 2nd Embodiment of this invention. It is a block diagram of the floor plan part concerning a 2nd embodiment of the present invention. It is a figure for demonstrating the diagonal Manhattan length temporary wiring which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the algorithm for extracting the wiring congestion degree which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the algorithm for extracting the wiring congestion degree which concerns on 2nd Embodiment of this invention. It is a figure which shows typically expansion of the arrangement | positioning area | region which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the timing distribution inside LSI which concerns on 2nd Embodiment of this invention. It is a block diagram of the distribution manager which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the skew calculation which concerns on 2nd Embodiment of this invention. (A)-(c) is a figure for demonstrating the netlist expression which concerns on 2nd Embodiment of this invention. It is a figure which shows the process of the block design which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating the timing distribution which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating a part of timing distribution which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating a part of timing distribution which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating a part of timing distribution which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the timing distribution preparation part which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the floor plan part which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the distribution manager which concerns on 2nd Embodiment of this invention. It is a flowchart for demonstrating operation | movement of the allocation manager which concerns on 2nd Embodiment of this invention. It is a conceptual diagram of hierarchical design. It is a block diagram of a semiconductor circuit design device. (A), (b) is a figure for demonstrating an individualization process, respectively. (A)-(c) is a figure for demonstrating ECO design, respectively. It is a figure for demonstrating timing allocation. It is a flowchart for demonstrating the outline of apparatus design. It is a flowchart for demonstrating timing design. It is a figure for demonstrating Manhattan length.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Semiconductor circuit design apparatus 2 Circuit information database 3 Automatic design processing part 4 Calculation processing part 5 Design information database 3a HDL language reading part 3b Parameter input part 3c Processing result output part 3d Test circuit rule input part 4a HDL conversion processing part 4b Unique processing unit 4c Test circuit generation processing unit 4d Load adjustment processing unit 4e HDL output processing unit 6a Design information reading control unit 6b Design information reading unit 7a Processing target determination unit 7b Processing data acquisition unit 8a Multiple reference analysis control unit 8b Multiple reference Analysis unit 8c Circuit analysis control unit 8d Circuit analysis unit 8e Terminal load / driving capability setting control unit 8f Terminal load / driving capability setting unit 9a Specific name assignment rule setting unit 9b Specific name generation unit 9c Test circuit generation control unit 9d Test circuit generation Section 9e Load analysis control section 9f Load analysis section 10a Circuit Data replication control unit 10b Circuit data replication unit 10c Hierarchy consistency restoration control unit 10d Hierarchy consistency restoration unit 10e Circuit adjustment control unit 10f Circuit adjustment unit 11a Circuit information write control unit 11b Circuit information write unit 12a Design information write control unit 12b Design Information writing unit 40a, 40b, 40c Source code 41a, 41b, 41c, 41d, 41e Data image 42a, 42b Circuit module image 43, 43a, 43b, 45, 61a-61e Circuit module 50d Distribution report creation unit 51 Timing distribution device 52a , 52c Layout CAD device 52b Waveform analysis CAD device 53 Inter-layer cooperation manager 54a-54e Timing distribution creation unit 55a-55e Floor plan unit 56a-56e Distribution manager 57a-57e T B
58b Constraint condition holding unit 58c Structural partial netlist holding unit 58e HDL annotator 58f HDL compiler 58h Waveform analysis information creating unit 58i Waveform analysis information holding unit 59a Placement support unit 59b Placement information holding unit 59c Physical technology information holding unit 59d Wiring information Holding unit 59e Conversion unit 59f Placement processing unit 60 Real wiring / temporary wiring execution unit 60a Manhattan length temporary wiring unit 60b Diagonal Manhattan length temporary wiring unit 60c, 60d Real wiring cooperation unit 60e Extraction unit 60f Name assignment unit 61, 63, 80- 83 chip 61f critical net 61g flip-flop 62, 62a net list 63a distribution editor unit 63b TDB registration unit 63c TDB reference unit 63d own layer TDB output / other layer TDB automatic reflection unit 63e database reference registration unit 63 f Arbitration control unit 64a to 64e Logical / constraint information holding unit 65b to 65e Timing information holding unit 66 Buffer 90a to 90c Hierarchical entity 100a, 101a, 102a Control unit 100b, 101b, 102b Processing unit

Claims (2)

In hierarchical design,
Block information related to the function of the circuit is input from a plurality of timing information databases having netlist information related to the wiring form provided corresponding to each of the plurality of design hierarchies, and delay values generated by delay elements of the circuit are allocated. A plurality of timing distribution generation units capable of outputting the obtained timing distribution values;
A connection between the plurality of timing distribution creation units is dynamically changed, and an inter-layer cooperation manager is provided that transmits and receives correction information related to the timing distribution value between each of the plurality of timing distribution creation units. A timing distribution device, characterized by being configured. The timing distribution creation unit is configured as an agent having a hierarchy entity having design information provided corresponding to each of the plurality of design hierarchies and program data for processing the design information,
The inter-layer cooperation manager is configured as a manager that is connected to the timing distribution creation unit as the agent and transmits / receives information on the timing distribution value with each of the plurality of design layers. The timing distribution device described.

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