JP2007156728A - Logic verification method and logic verification system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can verify a logic circuit including a plurality of bus interfaces by using a model for verification of a unified form on a computer system. <P>SOLUTION: Operation of a verification target logic circuit 111 is verified by logic simulation while information of a verification model 110 in a unified form about the verification target logic circuit 111 comprising a plurality of bus interface signal group 160 is created on a computer system 10. The verification model 110 comprises a plurality of protocol processing sections 150 corresponding to a plurality of bus interface signal group 160 and an instruction processing section 120 which controls the whole including them. A test instruction string 101 including a protocol processing section selection instruction is inputted to an instruction processing section 120. By this processing, processing of the instruction concerned is executed by a selected protocol processing section 150, and a comparison result 104 is obtained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a logic verification / test technique based on a logic simulation using a verification model for a logic circuit or a logic device including a logic circuit on a computer (electronic computer) system. In particular, creation (generation / construction) of a verification model for generating a processor bus interface (abbreviated as bus I / F) signal of a logic circuit including a CPU processor that realizes a logic operation by a specific instruction word; The present invention also relates to a logic verification or test processing method by a logic simulation means using the verification model.

  Conventionally, in a logic simulation using a verification model for a logic circuit, for example, the following method is used. First, the logic simulator directly uses the initial state setting data for checking the operation of the processor, the input test data created at the processor-specific instruction level, and the signal change in the operation status of the logic circuit as the output result as the expected value. A test vector that is input to a logic simulation is created by means of conversion to a format such as readable text or binary.

  In the execution stage of the logic simulation, the processor verification model reads the instruction level input data expanded into the test vector. Then, the processor verification model gives test vector data corresponding to each time according to the bus I / F operation to the verification target logic circuit together with the initial state setting expanded to the test vector, and sets the target logic. Make it work. Thereafter, a method is used in which the output value of the logic circuit to be verified is read by a processor verification model, and a logic operation error is reported when the output value does not match an expected value prepared in advance.

  Details of the logic simulation technique using the verification model are also described in Japanese Patent Application Laid-Open No. 10-212410 (Patent Document 1).

In the conventional logic verification method and system based on logic simulation, when the verification target logic circuit includes bus I / Fs of a plurality of processors, a plurality of verifications corresponding to the bus I / Fs of the plurality of processors are performed. A method is used in which a pattern is generated for input models (protocol processing units) using input parameters and the like, and the patterns are read by individual verification models and given to the verification target logic circuit.
JP 10-22214 A

  In general, different processors have different instruction formats (in other words, protocols) and processor bus operation specifications (bus I / F).

  In the conventional technique, when different processor buses are provided on the same logical configuration of the logic circuit to be verified, it is necessary to create a verification model in accordance with the operation specifications (bus I / F) of each processor bus. Since each processor has a different instruction format, it is necessary to prepare and provide an instruction sequence for each processor when creating verification / test data (instructions) for realizing one verification / test case. When creating a verification model (protocol processing unit) that matches the specifications of each processor, the number of steps for creating and managing this verification model has increased. In other words, the protocol processing unit is a module that logically simulates a processor such as a CPU.

  In addition, in order to perform verification / test such as competition between a plurality of processor buses, it is necessary to control operations between the plurality of processors. However, the method of controlling the operation between the processors is complicated because it has to correspond to each processor and bus I / F as described above. Therefore, the number of man-hours for creation and management for verification / testing such as competition between the processor buses in the logic simulation is enormous.

  Conventionally, there has been no logic simulation and logic verification / testing technique for handling a unified verification model corresponding to a plurality of processors and bus I / Fs. Even in the prior art, it was possible to verify / test multiple target processors in parallel for each verification model, but it was particularly difficult to verify / test contention between multiple processor buses. .

  The present invention has been made in view of the above problems, and an object thereof is to realize verification / test of a target logic circuit / logic device by executing a logic simulation on a computer system using a verification model. An object of the present invention is to provide a technology capable of realizing a logic verification / test processing operation of a target circuit / device including a plurality of bus I / Fs by using a verification model and instructions in one unified format. It is. In particular, by operating the verification model with a single instruction sequence and enabling verification of multiple target circuits / devices, verification model creation and management man-hours can be reduced, and data creation between processors. It is an object of the present invention to provide a technique capable of performing efficient logic simulation of a bus I / F signal by facilitating verification / testing of competition between processor buses.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In order to achieve the above object, the technique of the present invention is to verify / test a target logic circuit / logic device by executing a logic simulation using a model for verification on a computer system (hardware including a processor and a memory), and The verification model is created (generated / constructed), and includes the following technical means. This logic verification method is a data / information processing method having processing steps to be described later executed by a computer (processor). The logical verification system is a computer system / information processing system that executes processing according to the logical verification method.

  (1) The technique of the present invention relates to a logic circuit to be verified in which a plurality of bus I / Fs corresponding to a plurality of processors (processing devices such as CPUs) exist on a computer used by a verification / test operator. The operation of the logic circuit to be verified including a plurality of bus I / Fs using the verification model and the corresponding instruction format in the environment / state in which the verification model in a unified format is created This verification / test is performed by a logic simulation method. The logic model is executed by operating the verification model in a form in which a program or the like in a memory is processed by a processor or the like on the computer.

  In this logic verification method and system, the verification model has a protocol processing function (in other words, a bus I / F processing function) for controlling and operating a processor-dependent bus I / F signal (signal data input to and output from the processor bus). A plurality of protocol processing units (first to Nth protocol processing units) having a plurality of protocol processing units, and a first control unit including one or more instructions for verification / test It is divided into an instruction processing unit that performs verification / test processing of the operation of the logic circuit by processing of an instruction sequence (test / verification instruction) and outputs a result of the processing.

  The operator inputs a first instruction sequence (data / information in a format such as text or binary by conversion thereof) to the instruction processing unit for verification / testing. Through processing such as decoding of the first instruction sequence in the instruction processing section, one or more instructions (commands and data for controlling the bus I / F signal) are given to the protocol processing section, and the instructions are The corresponding protocol process is executed. That is, a control operation such as input / output of a bus I / F signal to the verification target logic circuit is executed by the protocol processing unit. Then, the instruction processing unit compares the data value of the processing result of the protocol processing unit (input data from the logic circuit to be verified, etc.) with the expected value (E) and acquires the comparison result as information. Output.

  In the logic verification method and system, the first instruction sequence is selected, designated, determined, etc., to which protocol processing unit among the plurality (first to Nth) of the corresponding instruction. Processing steps and means for adding identification information for use. For example, the operator describes the dedicated instruction (protocol processing unit selection instruction) in the first instruction sequence. Alternatively, a code corresponding to the dedicated instruction is described in the first instruction string by converting the instruction string by a program. The instruction processing unit selects an arbitrary protocol processing unit identified by the identification information by reading the input first instruction sequence and referring / decoding the identification information. Processing steps and means (protocol processing selection means) for executing processing and obtaining the result are provided.

  (2) Further, in the logic verification method and system according to the above (1), the verification model (or one of them) further includes the plurality of protocol processing units connected to the logic circuit to be verified on the computer system. Processing steps and means (protocol setting means). This creation is performed by setting the protocol processing function of the protocol processing unit by inputting parameter data. Then, during the execution of the logic simulation after the creation (initial setting), the time / timing of the bus I / F operation of any of the plurality of protocol processing units connected to the logic circuit to be verified, It has processing steps and means (operation timing setting means) that are arbitrarily changed (or changed) by inputting an instruction to the instruction processing unit or resetting the protocol processing function.

  (3) Further, in the logic verification method and system according to the above (1), a plurality of protocols and bus I / Fs connected to the logic circuit to be verified are the same and different in operation speed on the computer system. It has processing steps and means (protocol setting means) for creating the verification model including the protocol processing unit (or including some modules / information thereof). Then, during execution of the logic simulation after the creation, the protocol processing function of an arbitrary protocol processing unit among the plurality of protocol processing units having different operation speeds, etc., is input to the instruction processing unit, or the protocol It includes processing steps and means for arbitrarily changing the setting by resetting the processing function.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the present invention, it is possible to realize a logic verification / test processing operation of a target circuit / device including a plurality of bus I / Fs using a verification model and instructions in one unified format. In particular, by operating the verification model with a single instruction sequence and enabling verification of multiple target circuits / devices, verification model creation and management man-hours can be reduced, and data creation between processors. By facilitating verification / testing of competition between processor buses, it is possible to perform efficient logic simulation of bus I / F signals.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. 1 to 11 are for illustrating the present embodiment, and FIG. 12 is for illustrating the prior art.

  In the present embodiment, as a feature, a protocol automatic selection function in a verification model is provided. That is, a protocol processing unit that describes a dedicated command (protocol processing unit selection command) in the test command sequence, decodes the command by the command processing unit of the verification model, and processes and operates the corresponding command in the test command sequence; The bus I / F is selected and processed.

  FIG. 1 shows a configuration example and a processing image of a computer system 10 serving as a processing execution environment corresponding to the logic verification system and method according to the embodiment of the present invention. FIG. 2 shows a conceptual configuration (schematic configuration including characteristic functions) of the present logic verification system corresponding to FIG. FIG. 3 shows a specific configuration of the logic simulator 100 included in the logic verification system of FIG.

  1 and 2, the present logic verification system is a system that executes processing related to logic verification / test of a target logic circuit (or logic device) in accordance with the logic verification method of the embodiment of the present invention. In this logic verification system, processing related to this logic verification / test is realized by logic simulation by the logic simulator 100. The computer system 10 has the logic simulator 100 software. This software includes a program (each processing unit) for performing a logic verification process and related information. An operator who performs a logic verification / test operation on the computer system 10 executes the software, generates / constructs a verification model 110 while performing an input / output operation of information as necessary, and performs a verification model. 110 is used to perform logic verification / test by logic simulation of the logic circuit 111 to be verified.

  In FIG. 1, in a computer system 10, a logic verification system including software of the logic simulator 100 shown in FIG. 2 is constructed on a computer such as a PC or a workstation. On the computer system 10, data / information such as test data 11 and a verification target logic circuit (logic circuit description information) 13 is input / created by an operator. Based on the input / created information, logic verification / test processing by logic simulation is executed, and as a result, a file 12 is created / output.

  In the operation verification by the logic simulation for the verification target logic circuit 13 in the computer system 10, the verification target logic circuit 13 is a text level (worker readable) such as a circuit description language (hardware description language). Level) uses a file (data / information) in which the function is described. In addition, in order to apply a signal value to the verification target logic circuit 13, the signal value given at each execution time is sequentially described for each signal line on the verification target logic circuit 13, and the operation result is observed. Test data 11 for instructing signal line names to be created is created. In this logic simulation, the verification target logic circuit 13 and the test data 11 are read, the change state of the logic signal up to a predetermined time is sequentially calculated, and the result is output to the result file 12. For example, in the execution of the logic simulation in FIG. 1, input signal values (SIG1, SIG2) are given to terminals of a circuit (AND circuit), an output value (SIGO) of the circuit is calculated, and the result is output. The signal value is described by the signal level H / L and its duration, such as “L20 H20 L20”.

  2, the computer system 10 includes a CPU 21, a memory 22, an input device 23 such as a keyboard, an output device 24 such as a display, and the like. The CPU 21 executes the software of the logic simulator 100. In addition, related data such as the test instruction sequence 101, the comparison result 102, and the parameter data 105 are stored on the memory 22.

  The logic simulator 100 generates / constructs a verification target logic circuit 111 and a corresponding verification model 110 for logic verification / test (hereinafter also simply referred to as verification or test) by logic simulation. The verification target logic circuit 111 (corresponding to 13) and the bus I / F signal group (bus I / F signal line) 160 are described in a predetermined information format by the circuit description language or the like, and are generated on the computer system 10. / Build process. As illustrated in FIG. 11 to be described later, the verification target logic circuit 111 performs control processing when the operations of the bus I / Fs of a plurality of processors (corresponding one-to-one with the plurality of protocol processing units 150) compete. The circuit which performs is included. The verification model 110 is also referred to as information (simulation module) similar to the verification target logic circuit 111, a pseudo program realized in a program language, or the like. The verification model 110 includes a plurality of protocol processing units 150 and a command processing unit 120 that controls the whole of the verification model 110 including the plurality of protocol processing units 150. A plurality (N) of protocol processing units 150 {150A, 150B,..., 150N} correspond to a plurality of bus I / F signal lines 160 {160A, 160B,. Connected. For example, the first (A) protocol processing unit 150A has a processing function for controlling the first (A) bus I / F signal group 160A.

  The instruction processing unit 120 receives a test instruction sequence 101, performs instruction processing on the protocol processing unit 150, and outputs a comparison result 104 with an expected value (E). It supports various functions such as operation timing setting and protocol setting. In the protocol processing selection, an arbitrary protocol processing unit 150 is selected from a plurality of commands by a dedicated command (protocol processing unit selection command), and command processing is performed. The operation timing setting is to change the operation timing / time of an instruction to be executed by an arbitrary protocol processing unit 150 at any time. In the protocol setting, the protocol setting (definition) of an arbitrary protocol processing unit 150 can be changed at any time after the verification model 110 is generated (at the time of initial setting).

  Note that the conventional logic verification system has only one protocol processing unit corresponding to one bus I / F. For this reason, it has been difficult to verify / test the conflicting operations of a plurality of processors and the bus I / F.

  3, the logic simulator 100 includes an input parameter processing unit 140, a command processing unit 120, a data bus control unit 130, and a protocol processing unit 150 as the configuration of the verification model 110 for the verification target logic circuit 111. The protocol processing unit (A) 150A and the protocol processing unit (B) 150B} are mainly classified into four functional blocks. In this example, a description will be given using an example in which two (A, B) protocol processing units 150 are provided. For this reason, FIG. 3 shows a protocol processing unit (A) 150A and a protocol processing unit (B) 150B.

  The test instruction sequence 101 is text description data in a specific assembler instruction format that is input and created by an operator for logic verification and given to the logic simulator 100, and may be paraphrased as a verification instruction. Specific examples of the test instruction sequence 101 are shown in FIGS. Of the one or more instructions constituting the test instruction sequence 101, instructions to be executed by a single protocol processing unit 150 are shown in the same manner as in the prior art format (FIG. 12). FIG. 5 shows an example of an instruction newly added to the format of the test instruction sequence 101 in the system of the present embodiment.

  A bus I / F signal group (bus I / F signal line) 160 is a signal group such as a command, an address, and data, and a corresponding signal line. For example, when a read (RD) command is output from the instruction processing unit 120 to the protocol processing unit 150A, the corresponding signal is transmitted from the protocol processing unit 150A to the verification target logic circuit 111 through the corresponding bus I / F signal group 160A. The response read data and the like are received and input to the instruction processing unit 120. In the bus I / F signal group 160, the direction from the protocol processing unit 150 to the verification target logic circuit 111 is described as the output direction, and the opposite is the input direction.

  The instruction conversion program (P) unit 102 is a program unit that converts the code of the test instruction sequence 101 into a format that can be read by the verification model 110. The instruction conversion program unit 102 reads an assembler instruction description described as the test data 11, converts it into a binary format, and creates binary data 103 as input data for the verification model 110. The instruction processing unit 120 receives the binary data 103, processes it, and outputs the comparison result 104. The instruction conversion program unit 102 is also provided on the computer system 10.

  The input parameter processing unit 140 reads the parameter data (protocol setting information) 105 defining the functions of the plurality of protocol processing units 150 by the parameter input unit 141, and determines the protocol according to the parameter data corresponding to each protocol processing unit (150A, 150B). The setting unit 142 sets the protocol and bus I / F processing function of each protocol processing unit (150A, 150B). That is, function settings such as the transmission order, transmission timing, and data width of the bus I / F signal group 160 of each protocol processing unit 150 are performed.

  The instruction processing unit 120 reads the binary data 103 corresponding to the test instruction sequence 101 by the data reading unit 121 and stores it in the built-in memory unit 122. The built-in memory unit 122 stores verification data (command), expected value (E), and the like.

  The instruction decoding processing unit 123 sequentially reads instructions (that is, codes included in the binary data 103) from the built-in memory unit 122 and decodes the contents of the instructions, and also includes a data processing unit 124 and an expected value checking unit 125. And the data bus control unit 130 (transaction monitoring mechanism unit 131 and protocol selection data input / output unit 132) are instructed to operate according to the command. The command processing unit 120 and the command decoding processing unit 123 are also characteristic parts and have a function of decoding a dedicated command, particularly a Req setting command 311 which is a protocol processing unit selection command.

  The data processing unit 124 controls the output data buffer 127, and sequentially reads data (commands) from the built-in memory unit 122 and sends them to the output data buffer 127 in accordance with instructions from the command decoding processing unit 123. The output data buffer 127 outputs data (command) to the data bus with the protocol processing unit 150. Further, the input data buffer 126 inputs data (command) from the data bus with the protocol processing unit 150.

  The expected value check unit 125, according to an instruction from the instruction decode processing unit 123, the contents of the input data buffer 126 that stores the input data read from the verification target logic circuit 111 through the protocol processing unit 150, and the expected value (E) And the comparison result 104 is output.

  The data bus control unit 130 includes a transaction monitoring mechanism unit 131 and a protocol selection / data input / output unit 132. The data bus control unit 130 controls transactions on the data bus between the instruction processing unit 120 and the plurality of protocol processing units 150. The transaction monitoring mechanism unit 131 controls data transmission / reception among the instruction processing unit 120, the input parameter processing unit 140, and the protocol processing unit 150. The protocol selection / data input / output unit 132 performs selection of the protocol processing unit 150 and input / output control of data and addresses.

  The protocol processing unit 150 includes an instruction decoding unit 151, a transaction processing unit 152, a timing control unit 153, an address / data input / output buffer 154, a data input / output unit 155, and the like. The transaction processing unit 152 has functions such as input / output control and bus I / F signal control.

  In the protocol processing unit 150, in response to designation (parameter data input) from the protocol setting unit 142 of the input parameter processing unit 140, the instruction decoding unit 151 performs the bus I / F signal of the verification target logic circuit 111 for the protocol to be processed by itself. The output order and output timing of the group 160 are set. In addition, the data sent from the instruction processing unit 120 is read into the instruction decoding unit 151, and an operation according to an individual instruction included in the data is instructed to the transaction processing unit 152. The transaction processing unit 152 sends the operation of the bus I / F signal group 160 to be executed by the designated instruction to the data input / output unit 155. Then, a command, an address, and data are transmitted from the data input / output unit 155 to the bus I / F signal line (160) of the verification target logic circuit 111. The address / data input / output buffer 154 stores addresses, data, and the like input / output to / from the bus I / F signal line (160). The timing control unit 153 controls the input / output timing of the address / data input / output buffer 154 in accordance with the control from the instruction decoding unit 151.

  When the command is a READ instruction system that receives data from the logic circuit 111 to be verified, the signal value of the bus I / F signal line 160 is read by the data input / output unit 155 at a predetermined time and stored in the address / data input / output buffer 154. The contents are stored, and the data bus control unit 130 is notified that reading data has been fetched. The data bus control unit 130 causes the data stored in the address / data input / output buffer 154 to be input to the input data buffer 126 through the data bus.

  With the above configuration, the protocol processing unit 150 has a function capable of realizing a plurality of types of protocol operations (protocol processing unit 150) with a type of verification model 110 in accordance with the designation of the parameter data 105. .

  FIG. 12A shows an example test instruction sequence 200 in the conventional technique format for comparison with the present embodiment. FIG. 12B shows an instruction code classification 210 in the test instruction sequence 200. FIG. 12C shows a format example of the binary data 220 corresponding to the test instruction sequence 200.

  As shown in the instruction code classification 210, the test instruction sequence 200 is divided into an instruction code indicating a command 201 and an operand 202 indicating its data. In this example indicated by the underline, in the command 201 “MVL”, an operation using data in which the first operand is “R0”, the second operand is “R1”, and the third operand is “0x0200” is performed. It is shown that. Specifically, the test instruction sequence 200 is an instruction sequence for transferring 512 bytes continuously from the data content existing at the address indicated by “R1” to the address indicated by “R0”. For example, when the instruction code (command 201 and operand 202) is converted into binary format, 4-byte binary machine language data indicated by binary data 220 is generated. In this binary data 220, “MVL” 221 of the command 201 is indicated by the first 1 byte “11100101” (0xE5), the next 1 byte “00000001” indicates the contents of the first operand and the second operand, The second byte data “00000010 00000000” indicates the data of the third operand.

  On the other hand, FIG. 4 shows an example of a test instruction sequence 300 (corresponding to 101) applied in the present embodiment, and FIG. 5 shows a Req which is a protocol processor selection instruction as a newly added instruction code classification 310. The (request) setting command 311 will be described.

  In the system using the conventional test instruction sequence 200, it is impossible to perform any of a plurality of protocol processes with one instruction code in the verification model. Therefore, in the present embodiment, as a means (protocol process selection function) for selecting a process of a plurality of arbitrary protocol processing units 150 by a single instruction code, a selection of the protocol processing unit 150 to process an instruction is selected. Instruction codes (301, 302) are added. “@RQSET” 301 is a Req setting command 311, and “@RQSETE” 302 is a termination command corresponding to the Req setting command 311.

  In this new format test instruction sequence 300, when it is desired to arbitrarily select from a plurality of protocol processing units 150 and process an instruction for the bus I / F signal line 160, the protocol processing unit selection command “@RQSET “301” is described at the beginning of the target test instruction sequence 300 (101), and “@RQSETE” 302 corresponding to “@RQSET” 301 is described at the end. Information for identifying the protocol processing unit 150 is added to “@RQSET” 301. “V0”, “V1”, and the like correspond to a device number 501 described later, and are information for identifying the protocol processing unit 150. Then, in the range between “@RQSET” 301 and “@RQSETE” 302, one or more instructions to be executed by the designated protocol processing unit 150 are described. As a result, the protocol processing unit 150 that executes the corresponding instruction within the range is selected and executed.

  In FIG. 5, “@RQSET” 301 corresponding to the Req setting command 311 has a Req transmission destination 312 (corresponding to the device number 501) as the first operand, a Req transmission time 313 as the second operand, and a Req as the third operand. This is a format for describing the transmission frequency 314. In this example, “@RQSET” 301 sets “V0” to the Req destination 312 in the first operand, “T030”, that is, “after 48 cycles” as the Req transmission time 313, and the Req transmission frequency 314 “AC02”, that is, “transmission every two cycles” is set and described. Therefore, the instruction sequence in the range from “@RQSET” 301 to “@RQSETE” 302 is executed by the protocol processing unit 150A identified by “V0”, and the first instruction start time is 48 cycles of instruction detection. It is defined that the data is started later and the transmission data from the protocol processing unit 150A is continuous every two cycles.

  In FIG. 4, “V0 EQU 0x0001” or the like indicates the definition of “V0” or the like that is the Req destination 312. “T010 EQU 0x0010” or the like indicates the definition of “execute after 16 cycles” or the like as the Req transmission time 313. “AC01 EQU 0x0030” or the like indicates the definition of “executed every cycle” that is the Req transmission frequency 314. The format of the instruction sequence in FIGS. 4 and 5 is an example, and for example, the setting of the Req transmission frequency 314 may be an option.

  Thus, the operator prepares the test instruction sequence 300 according to the selection of the protocol processing unit 150, creates the binary data 103, and loads the binary data 103 into the verification model 110 of the logic simulator 100. As a result, the instruction processing unit 120 can automatically perform the decoding process, and the selected protocol processing unit 150 can perform the processing operation to obtain the comparison result 104. That is, verification of an arbitrary protocol processing unit 150, particularly verification when a plurality of protocol processing units 150 operate in association with each other can be realized.

  Next, FIG. 6 shows the timing of sending data (command) from the output data buffer 127 in the command processing unit 120 (Req transmission time 313), the association of the protocol processing unit 150 that executes the data (command), and the management method therefor Is shown. In the logic simulator 100, the time wheel 400, the execution management table 410, and the output data buffer 420 (corresponding to 127) are managed in association with each other. The time wheel 400 indicates a relative time from the current simulation time (t) 401. The execution management table 410 includes records with an address (link pointer) 411, a device number (Req transmission destination) 412, ReqData (request data) 413, an output data section link 414, and the like. The output data buffer 420 can hold a plurality of output data portions (data records) 421. The output data unit 421 stores commands to be executed and data to be output to the protocol processing unit 150.

  The time wheel 400 stores the address 402 of the execution management table 410 to be executed at the next time (t + 1). In the execution management table 410, the Req transmission destination device number 412, the ReqData 413 having data defined by the Req setting command 311, the address of the output data buffer 420 storing the command and data to be executed at that time (t + 1) ( It has a record having an output data part link 414) and the like. Thus, time control of commands and data to be executed at each time is performed.

  In the verification model 110, when the Req setting command 311 in the binary data 103 is read by the instruction decoding processing unit 123, “@RQSET” 301 to “@RQSETE” 302 are stored in the output data unit 421 of the output data buffer 420. Write binary data (instruction sequence equivalent code). Also, the Req destination 312 defined by “@RQSET” 301 is set in the device number 412 of the record in the execution management table 410. In addition, Req transmission frequency 314 and the like, which are other control data, are set in ReqData 413 of the same record. Then, the address 411 of the corresponding record is registered in the address 402 of the relative time of the time wheel 400 corresponding to the Req transmission time 313 that is the execution time of the corresponding record.

  For example, the table structure shown in FIG. 6 is a case where there is an instruction sequence for accessing the protocol processing unit 150A identified by “V0” at time (t + 1). When the corresponding time reaches (t + 1) during the logic simulation execution, the corresponding record of the execution management table 410 indicated by the address 402 and the corresponding output data part 421 of the output data buffer 420 are read and the Req transmission destination device number 412 is used. An output data unit 421 including commands and data is sent to the protocol processing unit 150A shown. At this time, if the address 411 is other than zero, the data to be processed still remains as a record, and the contents of the relative record indicated by the address 411 (in this example, to the protocol processing unit 150B identified by “V1”). Access) is handled in the same way.

  FIG. 7 shows an example of the contents of the parameter data 105 for performing protocol setting (definition) such as initial setting and occasional setting of the protocol processing unit 150. The parameter data 105 includes elements such as a device number 501, a protocol type 502, a data issue cycle 503, a data pulse width 504, and a continuous access wait 505.

  The device number 501 defines a code for identifying a plurality of devices, that is, the protocol processing unit 150, and may be called a protocol processing unit ID. The protocol type 502 defines the type of operation (protocol) of the bus I / F signal group 160 of the corresponding protocol processing unit 150. Further, the operation in the corresponding bus I / F signal group 160 is finely defined by a data issue cycle 503, a data pulse width (size) 504, a continuous access wait 505, and the like. Data is a command and data unit. For example, for the protocol processor 150A having the device number 501 “V0” and the protocol type 502 “CPU1”, the Data issue cycle 503 is “2” (2 cycles), and the Data pulse width 504 is “1” (1 cycle). ) And continuous access Wait 505 is “1” (one cycle unit). Also, for example, even when “CPU1” which is the protocol processing unit 150 of the same protocol type 502 is included, a plurality of protocol processing units 150 in which the access time is changed by changing the operation time / timing setting by 503 to 505 etc. are defined. Can be verified. FIG. 10 also shows the operation timing of the instruction.

  In particular, the Req transmission frequency 314 in FIG. 4 relates to the operation timing setting function in FIG. 2 and also corresponds to the setting by the continuous access Wait 505 in the parameter data 105 in FIG.

  Next, FIG. 8 shows an execution flow of a logic verification process using the protocol automatic selection function in the present embodiment. Prior to the start of logic simulation execution in the logic simulator 100 of the computer system 10, it is assumed that the generation / construction of the verification target logic circuit 111 in the logic simulator 100 has been completed. That is, reading and creation of necessary information and initial setting of each bus I / F signal line 160 and registers are performed.

  The operator creates parameter data 105 that becomes necessary initial setting data of the protocol processing unit 150 before executing the logic simulation. In addition, binary data 103 converted by using a test instruction sequence 101 additionally describing a verification instruction sequence and selection instructions (301, 302) of the protocol processing unit 150 is prepared. When the logic simulation is executed in the logic simulator 100, the target protocol control is realized by advancing the processing according to FIG.

  First, in S600 (hereinafter, S represents a processing step), at the start of a logical simulation, the parameter input unit 141 of the input parameter processing unit 140 reads the contents of the parameter data 105, selects one protocol processing unit 150, The protocol processing unit 150 selected according to the parameter data 105 is set.

  In step S <b> 601, when the logic simulation is started, the data reading unit 121 of the instruction processing unit 120 reads the binary data 103 of the test instruction sequence 101 and writes the contents to the built-in memory unit 122. A logic simulation is started according to the code of the written binary data 103.

  In step S602, the instruction decoding processing unit 123 sequentially reads and decodes the contents of the built-in memory unit 122 one instruction at a time. As a result, the designated data is read by the data processing unit 124 and stored in the output data buffer 127. In the instruction decode processing unit 123, when the Req setting command 311 (“@RQSET” 301) appears in the read instruction, the data processing unit 124 causes the time wheel 400, the execution management table 410, and the output data buffer 420 in FIG. Create and set each record.

  Further, in the instruction decoding processing unit 123, when a result comparison instruction (expected value comparison instruction), that is, an instruction for determining a comparison point based on an expected value (E) in a plurality of instruction processes in an instruction sequence appears in the read instruction, The expected value (E) of the instruction processing output result is sent from the built-in memory unit 122 to the expected value check unit 125 and stored in a predetermined buffer.

  Next, in S603, if the address 411 of the execution management table 410 is registered at the logic simulation time indicated by the time wheel 400, it indicates that there is a command and data to be executed at that time, and the data bus The control unit 130 sequentially sends commands and data (output data unit 421) from the corresponding data record in the output data buffer 420 to the protocol processing unit 150 indicated by the device number 412 via the data bus.

  Next, in step S604, the target protocol processing unit 150 reads the command and data (output data unit 421) sent from the data bus control unit 130, and the protocol and bus set in the parameter data 105 at the start of the logic simulation. Commands and data are transmitted to the bus I / F signal line 160 of the verification target logic circuit 111 in accordance with the I / F processing function. Further, the target protocol processing unit 150 reads input data from the bus I / F signal line 160 of the verification target logic circuit 111, assigns its own device number 501, and sends it to the data bus control unit 130 as input data.

  While the target protocol processing unit 150 is processing, the instruction decoding processing unit 123 and the data bus control unit 130 are on standby after confirming the expected value (E) and the presence of input data.

  In step S <b> 605, the data bus control unit 130 writes the input data sent from the protocol processing unit 150 to the input data buffer 126 in units of device numbers 501, and completes the setting of the input data to the expected value check unit 125. Report.

  Next, in S606, when the instruction stored in the internal memory unit 122 includes the result comparison instruction, the expected value check unit 125 follows the instruction from the instruction decoding processing unit 123 in accordance with the expected value ( The data of E) and the input data of the input data buffer 126 are compared and checked, and the result is output as the comparison result 104.

  Next, in S607, the instruction processing unit 120 confirms whether or not all instruction processing of each instruction in the binary data 103 of the test instruction sequence 101 is completed, and until all are completed (S607-N), from S602 to S606. This process is repeated, and when all the read instruction sequences are executed and all the processes are completed (S607-Y), the logic simulation is terminated. The information of the comparison result 104 indicates the result of verification / test by logic simulation. When another verification / test is performed, the same processing is executed by another test instruction sequence 101.

  Through the above procedure, a verification environment of the protocol processing unit 150, which is a plurality of bus I / F (160) connection parts, can be constructed using the verification model 110 and the test instruction sequence 101 in one unified format, Various verification / tests can be efficiently realized by selecting an arbitrary protocol processing unit 150. Further, the operation timing of the bus I / F (160) of each protocol processing unit 150 can be controlled by the test instruction sequence 101 and the parameter data 105. Further, by the expansion (protocol setting) of the protocol processing unit 150 by the parameter data 105, the configuration of the bus I / F (160) of the protocol processing unit 150 can be changed and verified / tested arbitrarily and at any time. Therefore, verification / test of competition between the bus I / Fs (160) of each protocol processing unit 150 can be easily realized.

  FIG. 9 shows an example test instruction sequence 900 (corresponding to 101) corresponding to the case where the verification / test of the conflict between the plurality of bus I / Fs (160) is executed. In this case, in the test instruction sequence 900, any of a plurality of instruction sequences (901, 902) having the same format as “@RQSET” 301 to “@RQSETE” 302 in the test instruction sequence 300 of FIG. The protocol processing units 150 are sequentially selected and processed. In this example, the instruction sequence 901 performs the selection operation of the protocol processing unit 150A, and the instruction sequence 902 performs the selection operation of the protocol processing unit 150B.

  FIG. 10 shows the operation timing of each instruction sequence corresponding to the test instruction sequence 900 of FIG. Each "@RQSET" 301 (Req setting command 311) unit instruction sequence (901, 902) is executed in accordance with an execution time instruction (313, 314). By decoding and executing the instruction sequence (901, 902), the protocol processing unit 150A of “V0” is activated after 10 cycles indicated by “T010”, and the corresponding instruction sequence {SET, SET, SET, RD, WR} is sequentially processed. Further, after 14 cycles indicated by “T020”, the protocol processing unit 150B of “V1” is activated and the corresponding instruction sequence {RD, WR, RD, WR} is sequentially processed. “RE” corresponds to “@RQSETE” 302. The process waits for the end of processing of all RQSET unit instruction sequences (901, 902), and at the end point, issues and executes the next RQSET unit instruction sequence.

  FIG. 11 is a configuration example of the logic circuit 112 corresponding to the logic circuit 111 to be verified, corresponding to the case where the verification / test of competition between the bus I / Fs (160) is executed. The control of Data Read (data reading) from the DEV (input / output device) in the logic circuit 112 (illustrated in six steps) is illustrated. The processors CPU # 1 and CPU # 2 are associated with the protocol processing unit 150A and the protocol processing unit 150B, respectively. The logic circuit 112 is connected to the CPUs # 1 and # 2 via the bus I / Fs # 1 and # 2, and controls the data transfer control unit that arbitrates the operations of the buses I / F # 1 and # 2 of the CPUs # 1 and # 2. The circuit includes 113 and the like.

  The contention operation between the bus I / Fs # 1 and # 2 is as follows when, for example, the CPU # 1 plays the role of I / O control and the DEV data is read from the CPU # 2. First, the data transfer control unit 113 receives a data read request (command) from the CPU # 2. Second, the data transfer control unit 113 informs the CPU # 1 of that fact. Third, data is read from the CPU # 1 to the DEV via the IOC (I / O control unit). Fourth, data is read from the DEV to the data transfer control unit 113 and stored in the memory via the memory control unit. Fifth, the data transfer control unit 113 notifies the CPU # 2 that data has been read out to the memory. Sixth, CPU # 2 reads data from the memory. The competing operation as in the above example can be executed by the above-described logic simulation process in the logic simulator 100, and can be verified efficiently.

  As described above, according to the present embodiment, it is possible to realize logic verification / test by efficient logic simulation for a logic circuit including a plurality of processors and a bus I / F, and development and creation of the verification model 110 and the logic simulator 100 , Change, management and other man-hours can be reduced. In particular, the protocol processing selection, operation timing setting, and protocol setting functions facilitate the verification / testing of competition between the bus I / Fs (160), and facilitate the creation of test data.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used in a system for performing logic verification / test of a logic circuit / logic device, particularly a technology for logic verification of a system LSI chip having a plurality of processor buses and a peripheral circuit using the chip.

It is a figure which shows the structural example and process image of a computer system used as the process execution environment corresponding to the logic verification system which is one embodiment of this invention. It is a figure which shows the notional structure of the logic verification system which is one embodiment of this invention. It is a figure which shows the structure of a logic simulator as a more concrete structure of the logic verification system which is one embodiment of this invention. It is a figure which shows an example of the test instruction sequence applied with the logic verification system which is one embodiment of this invention. It is a figure which shows about the Req (request) setting command which is a protocol process part selection command as a command code classification | category in the test command sequence applied with the logic verification system which is one embodiment of this invention. In the logic verification system which is one embodiment of the present invention, the timing of sending data (command) from the output data buffer in the instruction processing unit, the association of the protocol processing unit for executing the data (command), and the management method thereof It is a figure. It is a figure which shows the example of the content of the parameter data for performing protocol setting (definition), such as an initial setting of a protocol processing part, and an arbitrary setting in the logic verification system which is one embodiment of this invention. It is a figure which shows the execution flow of the logic verification process using the protocol automatic selection function in the logic verification system and method which is one embodiment of this invention. It is a figure which shows an example of a test instruction sequence corresponding to the case where the verification / test of the competition between several bus I / F is performed in the logic verification system which is one embodiment of this invention. FIG. 10 is a diagram illustrating operation timing of each instruction sequence corresponding to the test instruction sequence of FIG. 9 in the logic verification system according to the embodiment of the present invention. It is a figure which shows the structural example of the logic circuit corresponded to the case where the verification / test of the competition between bus | bowl I / F is performed in the logic verification system which is one embodiment of this invention. . For comparison with the present embodiment, in the prior art, (a) an example test instruction sequence, (b) an instruction code classification in the test instruction sequence, and (c) binary data corresponding to the test instruction sequence It is a figure which shows the example of a format.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Computer system, 11 ... Test data, 12 ... Result file, 13 ... Verification target logic circuit (logic circuit description information), 21 ... CPU, 22 ... Memory, 23 ... Input device, 24 ... Output device, 100 ... Logic simulator , 101 ... Test instruction sequence, 102 ... Instruction conversion program part, 103 ... Binary data, 104 ... Comparison result, 105 ... Parameter data, 110 ... Model for verification, 111 ... Logic circuit to be verified, 112 ... Logic circuit, 113 ... Data Transfer control unit, 120 ... instruction processing unit, 121 ... data reading unit, 122 ... built-in memory unit, 123 ... instruction decoding processing unit, 124 ... data processing unit, 125 ... expected value check unit, 126 ... input data buffer, 127 ... Output data buffer, 130 ... data bus control unit, 131 ... transaction monitoring mechanism unit 132 ... Protocol selection data input / output unit, 140 ... Input parameter processing unit, 141 ... Parameter input unit, 142 ... Protocol setting unit, 150, 150A, 150B ... Protocol processing unit, 151 ... Instruction decoding unit, 152 ... Transaction processing unit, 153: Timing control unit, 154: Address / data input / output buffer, 155 ... Data input / output unit, 160, 160A, 160B ... Bus I / F signal group (bus I / F signal line), 200, 300, 900 ... Test Instruction sequence, 201 ... command, 202 ... operand, 210, 310 ... instruction code classification, 220 ... binary data, 301 ... "@RQSET", 302 ... "@RQSETE", 311 ... Req (request) setting command, 312 ... Req Destination, 313 ... Req sending time, 314 ... Req sending frequency, 400 ... Time wheel, 41 ... execution management table, 420 ... output data buffer, 421 ... output data unit, 901, 902 ... instruction sequence.

Claims (4)

A logic verification method for verifying the operation of a logic circuit to be verified by logic simulation using a verification model on a computer system,
In a state where a verification model in a unified format for a logic circuit to be verified having a plurality of processor bus interfaces is created on a computer used by an operator, a logic simulation using the verification model and instructions is performed. Verifying the operation of the logic circuit to be verified;
The verification model controls a whole including a plurality of protocol processing units each having a protocol processing function for controlling and operating a signal of the processor bus interface, and the plurality of protocol processing units, and the processor bus for the verification A command processing unit that performs verification processing of the operation of the logic circuit by processing a first command sequence including one or more commands related to the control operation of the interface signal, and outputs the result.
Based on the operation of the operator, the first instruction sequence to which the identification information of the protocol processing unit to be executed of the corresponding instruction in the first instruction sequence is added is input to the instruction processing unit. Processing steps;
The instruction processing unit performs processing of the corresponding instruction in the first instruction sequence by processing of the identification information in the first instruction sequence, by the protocol processing unit to be executed among the plurality of instructions. And a logic verification method using a verification model, characterized by comprising a processing step of executing and obtaining the result data. In the logic verification method using the verification model according to claim 1,
On the computer system, a processing step for creating the verification model including the protocol processing unit connected to the logic circuit to be verified by setting the protocol processing function of the protocol processing unit by inputting parameter data; ,
The processor bus of the protocol processing unit is set by inputting an instruction to the instruction processing unit or setting the protocol processing function by inputting the parameter data during execution of the logic simulation after the creation of the verification model. A logic verification method using a verification model, comprising: a processing step of arbitrarily changing a timing of a control operation of an interface signal. In the logic verification method using the verification model according to claim 1,
On the computer system, a processing step of creating the verification model including the plurality of protocol processing units connected to the logic circuit to be verified and having the same processor bus interface and different operation speeds;
A plurality of protocols having different operation speeds by inputting an instruction to the instruction processing unit or setting the protocol processing function by inputting the parameter data during execution of the logic simulation after the creation of the verification model A logic verification method using a verification model, comprising a processing step of setting an arbitrary protocol processing function of a processing unit. A logic verification system for verifying the operation of a logic circuit to be verified by a logic simulation using a verification model on a computer system,
In a state where a verification model in a unified format for a logic circuit to be verified having a plurality of processor bus interfaces is created on a computer used by an operator, a logic simulation using the verification model and instructions is performed. Verifying the operation of the logic circuit to be verified;
The verification model controls a whole including a plurality of protocol processing units each having a protocol processing function for controlling and operating a signal of the processor bus interface, and the plurality of protocol processing units, and the processor bus for the verification A command processing unit that performs verification processing of the operation of the logic circuit by processing a first command sequence including one or more commands related to the control operation of the interface signal, and outputs the result.
The first instruction sequence to which the identification information of the protocol processing unit to be executed of the corresponding instruction in the first instruction sequence is added based on the operation of the operator is input to the instruction processing unit,
The instruction processing unit performs processing of the corresponding instruction in the first instruction sequence by processing of the identification information in the first instruction sequence, by the protocol processing unit to be executed among the plurality of instructions. A logic verification system using a model for verification, characterized by performing a process of executing and obtaining the result data.

Images