JP2007151322A - Power circuit and dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent output during unstable operation of a level shift circuit, a drive circuit, or the like until an output voltage is started immediately after power supply or startup by a control signal. <P>SOLUTION: This power circuit includes: an internal power circuit 30 for generating an internal power supply voltage by receiving an input dc voltage; internal circuits operated by the internal power supply voltage generated by the internal power circuit; and a level shift circuit 25 for converting the level of signals output from the internal circuits 22 to 24 by receiving the internal power supply voltage and input dc voltage for output. In addition, a delay circuit 26 is installed at the post-stage of the level shift circuit so as to inhibit the output of output signals from the level shift circuit until a predetermined time elapses after the internal power supply voltage reaches the predetermined potential by monitoring the internal power supply voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a power supply device that generates a DC power supply voltage, and further to a DC-DC converter that converts a DC voltage. For example, a switching regulator and a series regulator that generates the operation power supply voltage are provided, and an operation state is controlled by an external control signal. The present invention relates to a technique that is effective when used for a power source semiconductor integrated circuit constituting a DC-DC converter.

There is a DC-DC converter as a circuit for converting an input DC voltage and outputting DC voltages of different potentials. 2. Description of the Related Art In recent years, DC-DC converters are used in devices that operate on batteries, such as portable electronic devices, in order to convert a power supply voltage from the battery to a voltage suitable for a circuit constituting the system. In a device incorporating such a DC-DC converter, the operation of the DC-DC converter is stopped when the standby mode is entered and the normal operation mode is restored from the standby mode in order to reduce power consumption during standby. Some have a function of restarting a DC-DC converter. As an invention relating to a DC power supply having a function of starting / stopping such a circuit, there is an invention described in Patent Document 1, for example.
JP 2004-096869 A

  The present applicant has developed a DC-DC converter having a configuration as shown in FIG. 1 as a circuit for converting an input DC voltage and outputting a DC voltage having a potential different from the input DC voltage. This DC-DC converter is a circuit that converts an input DC voltage Vdd1 from the DC power supply 10 by a switching regulator 20 and outputs a DC voltage Vdd2 having a different potential.

  In this DC-DC converter, in order to ensure the operation of the switching regulator 20, the input DC voltage Vin from the DC power supply 10 is stepped down by the series regulator 30 and supplied to the switching regulator 20 as an internal power supply voltage Vddi (eg, 2.2V). It is configured as follows. Then, an operation control signal EN is given to the series regulator 30 and the switching regulator 20 from the outside, and the regulator is set to an operating state or a non-operating state according to the state of the signal.

  The inventors have examined the DC-DC converter of FIG. 1 and found that when the control signal EN is changed to an effective level to operate the regulator, the series regulator 30 is activated and the output voltage rises somewhat. Since it takes time, the operations of the level shift circuit 25 and the drive circuit 27 become unstable until the output voltage rises. When these operations become unstable, a through current flows through the output transistors SW1 and SW2, for example. It became clear that there was a defect.

  The present invention has been made paying attention to the problems as described above, and an object of the present invention is to provide a power supply semiconductor configured to generate an operation voltage of an internal circuit in an internal power supply circuit such as a series regulator. In an integrated circuit, an output when an operation of a level shift circuit, a drive circuit, or the like becomes unstable until the output voltage rises immediately after power-on or activation by a control signal is to be prevented. If these operations become unstable, problems such as a through current flowing in the output transistor occur.

  In order to achieve the above object, the present invention provides an internal power supply circuit (30) that receives an input DC voltage to generate an internal power supply voltage, an internal circuit that operates by the internal power supply voltage generated by the internal power supply circuit, A power supply circuit comprising a level shift circuit (25) that receives an internal power supply voltage and the input DC voltage and outputs a level-converted signal output from the internal circuit (22-24). A delay circuit (26) for monitoring the internal power supply voltage and preventing the output signal of the level shift circuit from being output until a predetermined time elapses after the internal power supply voltage reaches a predetermined potential is provided at a subsequent stage. It is what has been.

  According to the power supply circuit having the above-described configuration, since the output signal of the level shift circuit is delayed by the delay circuit, the level shift circuit until the output voltage rises immediately after the input DC voltage is input. It becomes possible to prevent the output when the operation of the drive circuit or the like becomes unstable. If these operations become unstable, problems such as a through current flowing in the output transistor occur. Further, when the internal power supply circuit and the internal circuit are set to an operating state or a non-operating state by a state control signal supplied from the outside, the internal circuit is set to an operating state by the state control signal. Immediately after that, until the output voltage rises, it becomes possible to prevent the output when the operation of the level shift circuit or the drive circuit becomes unstable. If these operations become unstable, problems such as a through current flowing in the output transistor occur.

  Here, preferably, a series regulator is used as an internal power supply circuit for generating an internal power supply voltage. The series regulator eliminates the need for an external coil and simplifies the control circuit. This reduces the number of components and reduces the chip size and power costs when the power supply circuit is integrated. Can be achieved.

  In addition, a switching element that constitutes a switching regulator and a drive circuit that generates a drive signal for the switching element are provided, and the internal circuit is a control circuit that generates a control signal for controlling on / off of the switching element, The output signal of the level shift circuit is configured to be supplied to the drive circuit. By using a switching regulator, a DC-DC converter with high power efficiency can be realized.

  Further, the power supply circuit includes a first external terminal to which the input DC voltage is applied, a second external terminal to which an inductance element through which a current flows by an on / off operation of the switching element, and the inductance A third external terminal to which the voltage of the other terminal of the element is input and a fourth external terminal to which the state control signal is input are provided. By providing the third external terminal to which the voltage of the other terminal of the inductance element is input, the output voltage can be accurately controlled.

  Further, a reference voltage circuit for generating a reference voltage and a resistance voltage dividing circuit for dividing the voltage input to the third external terminal are provided, and the control circuit includes a reference voltage circuit generated by the reference voltage circuit. An error amplifying circuit that compares a voltage and a voltage divided by the resistance voltage dividing circuit and outputs a voltage corresponding to the potential difference, an oscillation circuit that generates a signal (triangular wave) of a predetermined frequency, and the oscillation circuit A comparator for generating a pulse signal (rectangular wave) by comparing the generated signal and the output of the error amplifier circuit. Thereby, PWM control of a switching regulator is attained.

  Furthermore, a first switching element connected between the first external terminal and the second external terminal, and a second switching connected between the second external terminal and a ground potential point. The drive circuit is configured to generate and output a drive signal for complementary on / off control of the first and second switching elements. Thereby, a synchronous rectification control type switching regulator can be realized.

  As described above, according to the present invention, in the power supply circuit configured to generate the operating voltage of the internal circuit in the internal power supply circuit such as the series regulator, the output voltage is immediately after turning on the power or starting up by the control signal. Until the signal rises, there is an effect that the output when the operation of the level shift circuit or the drive circuit becomes unstable can be prevented. If these operations become unstable, problems such as a through current flowing in the output transistor occur.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Preferred embodiments of the invention will be described below with reference to the drawings.
FIG. 2 shows an embodiment of a DC-DC converter to which the present invention is applied.
The DC-DC converter according to this embodiment converts the DC voltage Vdd1 from the DC power supply 10 to generate a DC voltage Vdd2 having a potential different from Vdd1, and steps down the DC voltage Vdd1 from the DC power supply 10. The series regulator 30 that generates the operating voltage (internal power supply voltage Vddi) of each circuit of the control unit of the switching regulator 20, the reference voltage circuit 40 that generates the reference voltage Vref necessary for the operation of the switching regulator 20 and the series regulator 30, etc. It is composed of

  The switching regulator 20 includes a coil L1 as an inductance element, a smoothing capacitor C1 connected between the other terminal of the coil L1 and a grounding point, and a P-channel MOSFET (insulated gate type) for flowing a drive current toward the coil L1. A switching transistor SW1 on the power supply voltage side composed of a field effect transistor), a switching transistor SW2 on the ground side composed of an N-channel MOSFET that draws current from the coil L1, and a switching control circuit 21 that controls on and off of these switching transistors SW1 and SW2. Is provided. Among the elements constituting the switching regulator 20, elements other than the coil L1 and the smoothing capacitor C1 are configured as a semiconductor integrated circuit (IC) on a semiconductor chip, and the coil L1 is connected to an external terminal P2 provided in the IC. It is connected as an attachment element.

  The switching control circuit 21 divides the output DC voltage Vdd2 fed back to the external terminal P3 by a predetermined resistance ratio to generate an output monitor voltage, and a resistance voltage dividing circuit including series resistors R1 and R2, and the divided voltage And a reference voltage Vref and output a voltage corresponding to the potential difference, an error amplifier (error amplifier circuit) 22, an oscillation circuit 23 that generates a triangular wave signal of a predetermined frequency, the generated triangular wave signal and the error amplifier The PWM comparator 24 that generates a PWM control pulse by comparing the output voltage 22 with the output voltage, the level shift circuit 25 that converts the output signal of the comparator 24 into a signal having a larger amplitude, and level shifted by the level shift circuit 25. A delay circuit 26 that delays the change timing of the signal by a predetermined time (for example, several tens of microseconds), and the output of the delay circuit 26 And a like drive circuit 27 for generating a gate drive signal of the switching transistors Q1, Q2 by the signal.

  The DC voltage Vdd1 from the DC power supply 10 is supplied to the delay circuit 26, the drive circuit 27, and the source terminal of the switching transistor SW1 among the circuits constituting the switching control circuit 21, and the error amplifier 22, the oscillation circuit 23, and the PWM comparator 24 are supplied. The internal power supply voltage Vddi stepped down by the series regulator 30 is supplied. The series regulator 30 and the reference voltage circuit 40 are supplied with the DC voltage Vdd1 from the DC power supply 10. A front-stage circuit (for example, a CMOS inverter) in which the level shift circuit 25 discriminates the level of the output signal of the comparator 24 that operates at the internal power supply voltage Vddi, and a rear-stage circuit that outputs a signal of the DC voltage Vdd1 level according to the discrimination result of the front stage circuit. (For example, a flip-flop circuit). Therefore, the internal power supply voltage Vddi stepped down by the series regulator 30 is supplied to the preceding circuit of the level shift circuit 25, and the DC voltage Vdd1 from the DC power supply 10 is supplied to the subsequent circuit.

  The PWM comparator 24 operates to widen the pulse width of the PWM pulse that turns on and off the transistor SW1 when the output DC voltage Vdd2 decreases, and conversely narrows the pulse width of the PWM pulse when the output voltage Vdd2 increases. That is, the duty ratio of the PWM pulse changes according to the level of the output DC voltage Vdd2, and when the output DC voltage Vdd2 decreases, the ON time of the transistor SW1 is lengthened, and when the output DC voltage Vdd2 increases, the OFF time of the transistor SW1 is shortened. Then, feedback control is performed to keep the output DC voltage Vdd2 constant by the PWM method. Instead of changing the pulse width, for example, the output voltage may be controlled by changing the frequency while keeping the pulse width constant.

  The switching control circuit 21 performs synchronous rectification control to turn on the ground-side transistor SW2 and reduce loss while the power-supply voltage (Vdd1) -side transistor SW1 is turned off. Since the PWM drive and synchronous rectification control as described above are known methods, a detailed description of the configuration and operation is omitted. Further, the switching control circuit 21 is configured to have a backflow prevention function that detects that a reverse current flows through the coil at a light load and turns off the ground-side transistor SW2 during a period during which the ground-side transistor SW2 is to be turned on. Can do. The series regulator 30 includes a control transistor connected between input and output terminals, and a control circuit such as an error amplifier that generates a voltage for controlling the on-resistance of the control transistor so that the output voltage becomes a target voltage. The general circuit may be used.

  In the DC-DC converter of this embodiment, a control signal (hereinafter referred to as an enable signal EN) for instructing an operation state input from the external terminal P4 is a reference voltage circuit 40, a series regulator 30, an error amplifier 22, an oscillation circuit. 23, supplied to the PWM comparator 24, etc., when the enable signal EN is set to high level, these circuits are operated to generate a voltage Vdd2 obtained by converting Vdd1, and when the enable signal EN is set to low level, these circuits are operated. The operation of the circuit is stopped and the generation of Vdd2 is stopped. Specifically, when the current source of the operational amplifier provided in the reference voltage circuit 40, the series regulator 30, and the switching regulator 20 is turned on / off by the enable signal EN, these circuits are in an operating state, It becomes inactive.

FIG. 3 shows an example of a specific circuit of the delay circuit 26.
The delay circuit 26 of this embodiment includes a resistance voltage dividing circuit 28 including series resistors R3 and R4 that divide the internal power supply voltage Vddi, such as 2.2 V, stepped down by the series regulator 30 with a predetermined resistance ratio, MOSFET Q1 that receives the compressed voltage Vc at its gate terminal, constant current source I1 connected in series with Q1, MOSFET Q2 that receives the potential of the connection node N1 between MOSFET Q1 and constant current source I1 at its gate terminal, and series with Q2 The constant current source I2 connected to the capacitor, the capacitor C2 connected between the connection node N2 of the MOSFET Q2 and the constant current source I2 and the ground point, and the potential of the connection node of the MOSFET Q2 and the constant current source I2 are input. NOR circuit that receives the inverter circuit G1, the output signal of the inverter circuit G1, and the output signal of the level shift circuit 25 as input signals It is composed of a chromatography preparative circuit G2.

Here, the operation of the delay circuit 26 will be described with reference to the timing chart of FIG.
First, when the enable signal EN is at a low level and the circuit is in a non-operating state, the internal power supply voltage Vddi that is the output of the series regulator 30 is 0 V, so that the MOSFET Q1 is turned off, and the potential Vn1 of the connection node N1. Is set to the high level (Vdd1), whereby the MOSFET Q2 is turned on, and the potential Vn2 of the connection node N2 is 0 V which is the ground potential (period T1 in FIG. 4). Therefore, the output Vcnt of the subsequent inverter G1 is set to the high level, and the output of the NOR gate circuit G2 is fixed to the low level regardless of the output of the level shift circuit 25.

  When the enable signal EN is changed to a high level at timing t1 from this state, the reference voltage circuit 40, the series regulator 30, the error amplifier 22, the oscillation circuit 23, and the comparator 24 are activated, and the reference voltage Vref first rises. Subsequently, the internal power supply voltage Vddi that is the output of the series regulator 30 starts to gradually increase. Then, Q1 changes from off to on at timing t2 when the voltage Vc divided by the resistance voltage dividing circuit 28 exceeds the threshold voltage Vth (eg, 0.6 V) of the MOSFET Q1. Then, the potential Vn1 of the connection node N1 is changed to a low level (0V), whereby the MOSFET Q2 is turned off, and the capacitor C2 is charged by the current of the constant current source I2, so that the potential Vn2 of the connection node N2 is constant. Start climbing at speed. When the potential Vn2 of the connection node N2 exceeds the logic threshold value VLT of the subsequent inverter G1 at timing t3, the output of the inverter G1 changes to low level, and the output of the NOR gate circuit G2 is the output of the level shift circuit 25. It will change according to.

  The delay circuit 26 of the present embodiment is configured so that the current value of the constant current source I2 is such that the time T2 from when the enable signal EN changes to high level to when the output Vcnt of the inverter G1 changes to low level is several tens of microseconds. And the value of the capacity C2. Further, while the output of the NOR gate circuit G2 is fixed, the drive circuit 27 is configured to output a drive signal that turns off the switching transistors SW1 and SW2. As a result, the operation immediately after the start of the operation in which the operation of the switching regulator 20 is not stable, that is, the output level of the comparator 24 is unstable is supplied to the drive circuit 27, and the operations of the level shift circuit 25 and the drive circuit 27 are unstable. Therefore, the output switching transistor can be prevented from being driven by the unstable output. When the output switching transistor is driven by an unstable output, a problem such as a through current flowing through the output transistors SW1 and SW2 occurs.

  Further, in the circuit of FIG. 3, instead of inputting the voltage Vc obtained by resistance-dividing the internal power supply voltage Vddi generated by the series regulator 30 to the gate terminal of the MOSFET Q1, an enable signal EN supplied from the outside is input and a constant value is set. Even if the time constant composed of the current source I2 and the capacitor C2 is increased, the timing of the signal output from the level shift circuit 25 can be delayed. However, since the rise time of the output voltage of the series regulator varies in this way, it is necessary to determine the time constant according to the maximum variation. There is a risk of being late. On the other hand, the internal power supply voltage Vddi is monitored by the delay circuit 26 as in the embodiment, and after the internal power supply voltage reaches a predetermined potential, the output signal of the level shift circuit is output until the predetermined time elapses. By configuring so that it is not supplied to the drive circuit 27, even if there is a variation in the rise time of the output voltage of the series regulator, it can be output at an optimal timing according to the variation.

  Further, in the circuit of FIG. 3, the constants of the respective elements are set so that the MOSFET Q2 is turned on before the input DC voltage Vdd1 is input and the potential Vn2 of the node N2 reaches the logic threshold voltage VLT of the inverter G1 in the subsequent stage. If set, the circuit of FIG. 3 automatically operates in response to the rising of the input DC voltage Vdd1 without the enable signal EN as in the embodiment, and the PWM signal from the level shift circuit 25 is used for driving. It is possible to prevent the transistors SW1 and SW2 from being supplied.

  Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments. For example, the delay circuit of FIG. 3 is an example, and is not limited to the circuit having such a configuration. The constant current source I1 connected in series with the MOSFET Q1 may be a resistance element or a MOSFET acting as a load. Good. The delay circuit is not limited to an analog circuit as shown in FIG. 3, and may be a counter circuit that counts a signal output from the oscillation circuit 23 or an externally supplied clock signal. Is possible.

  Further, in the above-described embodiment, the transistors SW1 and SW2 constituting the switching regulator are formed in the IC chip. However, since a relatively large current flows through these transistors, as the external elements, You may comprise so that it may connect. The same applies to the control transistor constituting the series regulator 30. In addition, the transistor on the ground side of the switching transistors SW1 and SW2 can be replaced with a diode.

  In the embodiment, the resistors R1 and R2 that divide the output voltage Vdd2 are provided inside the chip. However, an external resistor is provided and the voltage divided outside the chip is supplied from the external terminal P4 to the error amplifier 22. It is also possible to make it input. Further, a power supply rise detection circuit for detecting the rise of the input DC voltage Vdd1 is provided instead of providing the enable signal EN from outside, and the series regulator 30, the reference voltage circuit 40, the error amplifier 22, and the oscillation circuit are provided with the output as an enable signal. 23, may be configured to be supplied to the PWM comparator 24 or the like.

  In the above description, the example in which the present invention is applied to a DC-DC converter has been described. However, the present invention is not limited to the present invention. For example, a regulator such as a charging device that charges a storage battery such as a lithium ion battery is used. A circuit that operates with a power supply voltage from the regulator is built in, and can be used for a device that is activated or deactivated by an external control signal.

FIG. 1 is a block diagram showing an example of a DC-DC converter studied prior to the present invention. FIG. 2 is a block diagram showing an embodiment of a DC-DC converter to which the present invention is applied. FIG. 3 is a block diagram showing an example of a specific circuit of the delay circuit constituting the DC-DC converter of the embodiment. FIG. 4 is a timing chart showing changes in signals and potentials at various parts immediately after the operation of the DC-DC converter according to the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 DC power supply 20 Switching regulator 21 Switching control circuit 22 Error amplifier 23 Oscillation circuit 24 PWM comparator 25 Level shift circuit 26 Delay circuit 27 Drive circuit 30 Series regulator 40 Reference voltage circuit L1 Coil (inductance element)
C1 Smoothing capacitor SW1, SW2 Coil driving switching transistor

Claims (10)

An internal power supply circuit that receives an input DC voltage and generates an internal power supply voltage; an internal circuit that operates according to the internal power supply voltage generated by the internal power supply circuit; and the internal circuit that receives the internal power supply voltage and the input DC voltage In a power supply circuit provided with a level shift circuit that performs level conversion on the output signal and outputs it,
A delay circuit that monitors the internal power supply voltage after the level shift circuit and prevents the output signal of the level shift circuit from being output until a predetermined time elapses after the internal power supply voltage reaches a predetermined potential. A power supply circuit is provided.   2. The power supply circuit according to claim 1, wherein the internal power supply circuit and the internal circuit are configured to be set to an operating state or a non-operating state by a state control signal supplied from the outside.   The power supply circuit according to claim 1, wherein the internal power supply circuit is a series regulator.   A switching circuit that constitutes a switching regulator; and a drive circuit that generates a drive signal for the switching element, wherein the internal circuit is a control circuit that generates a control signal for controlling on / off of the switching element, and The power supply circuit according to claim 1, wherein an output signal of the level shift circuit is configured to be supplied to the drive circuit.   A first external terminal to which the input DC voltage is applied, a second external terminal to which an inductance element through which a current flows by an on / off operation of the switching element, and an output voltage of the switching regulator or the equivalent The power supply circuit according to claim 4, further comprising a third external terminal to which a voltage is input and a fourth external terminal to which the state control signal is input.   A reference voltage circuit that generates a reference voltage; and a resistor voltage dividing circuit that divides the voltage input to the third external terminal, wherein the control circuit includes a reference voltage generated by the reference voltage circuit; An error amplifying circuit that compares the voltage divided by the resistance voltage dividing circuit and outputs a voltage corresponding to a potential difference; an oscillation circuit that generates a signal of a predetermined frequency; a signal generated by the oscillation circuit; 6. The power supply circuit according to claim 5, further comprising a comparator that compares the output of the error amplifier circuit with each other to generate a pulse signal.   A first switching element connected between the first external terminal and the second external terminal; a second switching element connected between the second external terminal and a ground potential point; The power supply circuit according to claim 6, wherein the drive circuit generates and outputs a drive signal for complementary on / off control of the first and second switching elements. .   8. A power supply circuit according to claim 1, wherein the power supply circuit according to claim 1 is a semiconductor integrated circuit.   A power supply circuit according to any one of claims 5 to 7, an inductance element connected to the second external terminal, and a smoothing connected between the other terminal of the inductance element and a ground potential point A DC-DC converter comprising: a capacitive element, wherein a potential at a connection point between the inductance element and the smoothing capacitive element is input to the third external terminal.   10. A DC-DC converter, wherein the power supply circuit according to claim 9 is a semiconductor integrated circuit.

Images