JP2007142059A - Method of manufacturing display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a display device equipped with a low-cost thin-film transistor and with uniform characteristics. <P>SOLUTION: This is a method of manufacturing a display device, having a thin-film transistor that uses a polycrystalline semiconductor layer on an insulating substrate. The method includes an amorphous semiconductor layer forming process wherein an amorphous semiconductor layer is formed on the insulating substrate; a metal layer forming process, wherein a metal layer is so formed as to coat the amorphous semiconductor layer, later than the amorphous semiconductor layer forming process; and a crystallization process, wherein by conducting ramp anealing on the amorphous semiconductor layer and on the metal layer, before patterning the metal layer, the amorphous semiconductor layer is crystallized into the polycrystalline semiconductor layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  For example, in an active matrix type display device, pixels arranged in a matrix are formed on the liquid crystal side surface of each substrate opposed to each other via a liquid crystal. A pixel group composed of each provided pixel is sequentially selected, and a signal (video signal) is supplied to each pixel in accordance with the selection timing.

Here, the pixel group is selected by providing a switching element for each pixel and turning on each of these switching elements in common.
The video signal is supplied to the corresponding pixel through each of the turned on switching elements by being applied to one of the pair of electrodes.

  Further, as the switching element, one using polycrystalline silicon (a-Si) has been known, and this polycrystalline silicon first forms amorphous silicon, and then annealed using, for example, laser light. By applying, it is made to crystallize into polycrystalline silicon. A technique for crystallizing amorphous silicon into polycrystalline silicon is described in detail, for example, in the following patent documents.

  A signal for turning on the switching element of each pixel or a video signal to be supplied to each pixel is supplied from a circuit formed on the substrate surface and outside the display unit including the set of pixels. These circuits are configured to include a large number of transistors.

  The transistor included in this circuit is formed by a so-called thin film transistor having substantially the same structure as the switching element, and the semiconductor layer is usually formed by the polycrystalline silicon. This is because each transistor is formed in parallel.

JP 2000-260710 A Japanese Patent Laid-Open No. 9-246555 JP-A-4-139728

However, in the formation of thin film transistors, annealing when crystallizing amorphous silicon into polycrystalline silicon is due to laser light irradiation, and the apparatus and running cost are high, and improvement has been desired.
Further, it is relatively difficult to maintain the oscillation of the laser beam in the apparatus in a stable state, and further uniformization of the characteristics of the thin film transistor has been desired in the mass production process.
The present invention has been made based on such circumstances, and an object of the present invention is to provide a method for manufacturing a display device including a thin film transistor which is inexpensive and has uniform characteristics.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1)
A method for manufacturing a display device according to the present invention is, for example, a method for manufacturing a display device having a thin film transistor using a polycrystalline semiconductor layer on an insulating substrate,
An amorphous semiconductor layer forming step of forming an amorphous semiconductor layer on the insulating substrate;
A metal layer forming step of forming a metal layer covering the amorphous semiconductor layer after the amorphous semiconductor layer forming step;
And crystallization step of crystallizing the amorphous semiconductor layer into the polycrystalline semiconductor layer by lamp annealing the amorphous semiconductor layer and the metal layer before patterning the metal layer. To do.

(2)
The display device manufacturing method according to the present invention is, for example, on the premise of the configuration (1), wherein the metal layer is a metal layer used for a gate electrode of the thin film transistor.

(3)
The display device manufacturing method according to the present invention is, for example, on the premise of the configuration (1), wherein the metal layer is a metal layer used for a source electrode and a drain electrode of the thin film transistor.

(4)
The display device manufacturing method according to the present invention is based on, for example, any one of the constitutions (1) to (3), and the amorphous material is formed between the amorphous semiconductor layer forming step and the metal layer forming step. And an amorphous semiconductor layer patterning step of patterning the porous semiconductor layer.

(5)
The display device manufacturing method according to the present invention is based on, for example, any one of the constitutions (1) to (3), and the amorphous material is formed between the amorphous semiconductor layer forming step and the metal layer forming step. And a doping step of injecting impurities into the porous semiconductor layer.

  In addition, this invention is not limited to the above structure, A various change is possible in the range which does not deviate from the technical idea of this invention.

Embodiments of a method for manufacturing a display device according to the present invention will be described below with reference to the drawings.
<Pixel configuration>
FIG. 6 is a block diagram showing the configuration of, for example, a pixel of a liquid crystal display device to be manufactured by the manufacturing method according to the present invention. Of the pixel having a rectangular shape, a portion on the upper right side where a thin film transistor TFT is formed. FIG. FIG. 7 is a cross-sectional view taken along line AA ′ of FIG.

For example, a base layer GW made of a laminate of a silicon nitride film (SiN) and a silicon oxide film (SiO ₂ ) is formed on the upper surface (surface on the liquid crystal side) of the transparent substrate SUB1 made of glass. This underlayer GW is provided in order to avoid that ionic impurities contained in the substrate SUB1 affect the thin film transistor TFT described later.

  A polycrystalline semiconductor layer PS made of, for example, a polysilicon layer is formed on the surface of the base layer GW. The polycrystalline semiconductor layer PS is obtained by polycrystallizing an amorphous silicon layer (amorphous semiconductor layer) by lamp annealing, and uniformity is ensured in the crystallization.

  This polycrystalline semiconductor layer PS is formed as a semiconductor layer of a thin film transistor TFT described later. Not only that, but in this embodiment, the first electrode CT1 of the capacitive element Cstg connected to the source region SD2 as it is is constituted.

  For this reason, the polycrystalline semiconductor layer PS is formed along a portion formed directly below the drain signal line DL, which will be described later, and partly along the drain signal line DL, and then bent to form a gate signal line GL, which will be described later. A portion that runs close to and in parallel and a portion that extends partially in the pixel region are integrally formed.

A first insulating film GI (see FIG. 7) made of, for example, SiO 2 or SiN is formed on the surface of the transparent substrate SUB1 on which the polycrystalline semiconductor layer PS is formed in this manner, covering the semiconductor layer PS. Yes.
The first insulating film GI functions as a gate insulating film of the thin film transistor TFT and functions as a dielectric film of a capacitive element Cstg described later.

  A gate signal line GL extending in the x direction in the drawing is formed on the upper surface of the first insulating film GI, and is arranged so as to cross a part of the semiconductor layer PS. The gate signal line GL surrounds the pixel region with a gate signal line (not shown) formed to extend in the x direction in the figure on the lower side in the figure.

  A part of the gate signal line GL extends slightly in the pixel region, and the extended part intersects a part of the semiconductor layer PS. This extending portion is formed as the gate electrode GT of the thin film transistor TFT.

  Here, the gate electrode GT of the thin film transistor TFT has a structure formed not only in the extending portion (GT1) but also in a portion (GT2) where the gate signal line GL itself crosses the semiconductor layer PS.

  After the formation of the gate signal line GL, impurities are ion-implanted through the first insulating film GI, and the region of the semiconductor layer PS except for the region immediately below the gate electrode GT is made conductive, so that the thin film transistor TFT Source electrode SD2 and drain electrode SD1 are formed, and the first electrode CT1 of the capacitive element Cstg is formed.

  Here, the thin film transistor TFT includes a region having a relatively small impurity amount in a region from the region (channel region) immediately below the gate electrodes GT1 and GT2 to the source electrode SD2 or the drain electrode SD1 in the polycrystalline semiconductor layer PS, that is, LDD. A (Lightly Doped Drain) region LD is formed. This is to avoid electric field concentration between the gate electrode GT and the source electrode SD2 or the drain electrode SD1.

  In addition, on the upper surface of the first insulating film GI, a capacitive signal line CL formed of the same material and in the same layer as the gate signal line GL is formed in parallel with the gate signal line GL. The capacitive signal line CL is formed so as to intersect the portion of the first electrode CT1 of the capacitive element Cstg, and a portion having a relatively large area is formed so as to sufficiently overlap the portion of the electrode CT1. It is formed as a pattern. This relatively wide area constitutes the second electrode CT2 of the capacitive element Cstg, and the capacitive element is formed between the first electrode CT1 and the second electrode CT2. The dielectric film is the first insulating film GI.

A second insulating film IN (see FIG. 6) is formed of, for example, SiO ₂ or SiN on the upper surface of the first insulating film GI, covering the gate signal line GL and the capacitance signal line CL (capacitance electrode CT2). .

  A drain signal line DL extending in the y direction in the figure is formed on the upper surface of the second insulating film IN. The drain signal line DL surrounds the pixel region with a drain signal line DL (not shown) that is formed to extend in the y direction in the drawing on the left side in the drawing.

  Although not shown in the figure, the drain signal line DL is composed of a conductive layer having a three-layer structure including a barrier metal layer, an aluminum (Al) layer, and a cap metal layer, for example.

  The drain signal line DL is arranged so as to overlap the drain electrode SD of the semiconductor layer PS, and a contact formed through the second insulating film IN and the first insulating film GI at the drain electrode SD. The drain electrode SD is connected through the hole CH1.

  Further, in forming the contact hole CH1, in order to expose the source electrode SD2 of the thin film transistor TFT, the contact hole CH2 formed through the second insulating film IN and the first insulating film GI is also formed. It is like that. The contact hole CH2 is provided to connect the third electrode CT3 of the capacitive element Cstg formed on the second insulating film IN to the source electrode SD2.

The third electrode CT3 of the capacitive element Cstg is formed so as to overlap with the second electrode CT2, and forms a capacitance with the second electrode CT2. The dielectric film is the second insulating film IN.
Therefore, the capacitive element Cstg is composed of two stacked capacitive elements, and a large capacity can be secured without increasing the occupation area.

  Although not shown in FIG. 5, a protective film is formed on the upper surface of the second insulating film IN so as to cover the drain signal line DL and the third electrode CT3, and the protective film is formed on the upper surface of the protective film. A pixel electrode connected to the third electrode CT3 through a contact hole formed in the film is formed.

  This pixel electrode is formed so as to occupy most of the pixel region, and is formed between the transparent substrate SUB1 and the counter electrode formed on the liquid crystal side surface of the other transparent substrate positioned opposite to the liquid crystal. An electric field for driving the liquid crystal is generated.

  In the pixel configured as described above, the video signal from the drain signal line DL is supplied to the pixel electrode via the thin film transistor TFT driven by the scanning signal from the gate signal line GL. In this case, the video signal is stored in the pixel electrode for a relatively long time by the capacitive element Cstg.

"Production method"
1 to 5 are process diagrams showing an embodiment of a method for manufacturing a display device according to the present invention. In particular, FIG. 1 to FIG.
Here, the thin film transistor TFT shown in FIGS. 1 to 5 does not show the electrode CT3 of the capacitive element connected to the source electrode SD2. However, when the pixels of the display device shown in FIGS. 6 and 7 are manufactured as they are, the electrode CT3 may be formed at the same time as, for example, the formation of the drain signal line DL.

  Although not shown in FIGS. 6 and 7, the protective film PAS is shown in FIGS. The protective film PAS functions as a thin film transistor TFT positioned below the protective film PAS in order to avoid direct contact with the liquid crystal.

  Further, FIG. 1 to FIG. 5 are drawn with two thin film transistors TFT physically separated. For example, when the thin film transistor TFT shown in FIGS. Should be understood as being physically connected. Also, it should be understood that one of the two separated thin film transistors TFT shown in FIGS. 1 to 5 is formed in the pixel region and the other is formed outside the display region.

Hereinafter, a method of manufacturing the display device shown in FIGS. 1 to 5 will be described in the order of steps.
Step 1.
As shown in FIG. 1 (1), a transparent substrate SUB1 is prepared, and a silicon nitride film (SiN), a silicon oxide film (surface) is formed on the main surface (surface on the liquid crystal side) of the transparent substrate SUB1 using a plasma CVD method. SiO ₂ ) and an amorphous silicon film (amorphous Si: a-Si) AS are sequentially stacked. In this case, an increase in the number of manufacturing steps can be avoided by forming them in the same chamber.
Here, the silicon nitride film (SiN) and the silicon oxide film (SiO ₂ ) function as the base layer GW.

Step 2.
As shown in FIG. 1 (2), the amorphous silicon film AS, which is the uppermost layer among the laminated films, is formed in a predetermined pattern using a selective etching method using a photolithography technique. As a result, the silicon oxide film is exposed in a region other than the region where the remaining amorphous silicon film AS is formed.

In general, the selective etching method using the photolithography technique is performed through the following steps. That is, a photoresist film is formed on the upper surface of a material layer to be formed in a predetermined pattern, and the photoresist film is selectively exposed using, for example, a photomask on which a light shielding film corresponding to the pattern is formed. Thereafter, the photoresist film is developed to remove the selectively exposed portion and leave the other portion of the photoresist film. Then, using the remaining photoresist film as a mask, the material layer exposed from the mask is etched using an appropriate etching solution.
In the following description of the steps, the selective etching method using the photolithography technique may be simply referred to as a selective etching method.

Step 3.
As shown in FIG. 1C, the first insulating film GI is formed by, for example, a plasma CVD method so as to cover the amorphous silicon film AS on the upper surface of the silicon oxide film. The first insulating film GI is formed of, for example, a silicon oxide film (SiO ₂ ) or the like and functions as a gate insulating film of the thin film transistor TFT.

Step 4.
As shown in FIG. 1 (4), a dopant is implanted into the amorphous silicon film AS from above the first insulating film GI through the first insulating film GI. As this dopant, for example, low-concentration boron (B) is used. This is for controlling the threshold value of the thin film transistor TFT.
In addition, the arrow in a figure has shown the irradiation direction of the dopant.

Step 5.
As shown in FIG. 2 (5), a metal layer MT is formed over the entire upper surface of the first insulating film GI by, for example, a sputtering method. This metal layer MT will be formed as a gate signal line or a capacitance signal line in a later process, but it is not formed in a predetermined pattern at this stage.

Step 6.
As shown in FIG. 2 (6), the amorphous silicon film AS is annealed through the metal layer MT. In this case, annealing is performed using so-called lamp annealing. This is because lamp annealing is inexpensive, and as a result, the manufacturing cost of the display device can be reduced. However, regardless of this, the annealing of the amorphous silicon film AS has the effect that the heat treatment can be made uniform over the entire region and the reliability of the annealing can be improved.

  That is, the light irradiated from the lamp is absorbed by the amorphous silicon film AS and the metal layer MT so that the temperature rises. In this case, heat conduction becomes steep in the metal layer MT, and the amorphous silicon film MT is heated. This is because a uniform heat treatment can be secured over the entire area of the film AS.

As a result, the dopant doped in the amorphous silicon film AS in the step 4 is uniformly activated over the entire area of the amorphous silicon film AS. In this case, the first insulating film GI is also heat-treated at the same time, and an effect of modifying the first insulating film GI is obtained.
In FIG. 2 (6), the heat source for lamp annealing is indicated by HT.

Step 7.
As shown in FIG. 2 (7), the amorphous silicon film AS is uniformly crystallized by the lamp annealing to form a polycrystalline semiconductor layer (silicon film) PS. In this case, the polycrystalline silicon film PS can be obtained with a uniform crystal structure by making the annealing uniform.

Step 8.
As shown in FIG. 2 (8), the metal layer MT is formed in a predetermined pattern by a selective etching method. As described above, the metal layer MT is formed as a gate signal line and a capacitance signal line. In FIG. 2 (8), the metal layer MT is shown as the gate electrode GT of the thin film transistor TFT formed integrally with the gate signal line. Has been.
In this step, the photoresist film PR used as a mask in the selective etching method is left without being removed.

The gate electrode GT existing below the photoresist film PR is formed such that the peripheral side surface thereof is positioned relatively larger inside than that of the photoresist film PR. In the pattern formation of the gate electrode GT, the above-described configuration can be obtained by performing selective etching so that so-called side etching is performed.
This is because a so-called LDD (Lightly Doped Drain) region is formed in the thin film transistor TFT, as will be described later.

Step 9.
As shown in FIG. 3 (9), a high concentration impurity made of, for example, phosphorus (P) is implanted into the polycrystalline silicon from above the photoresist film PR.
In this case, the photoresist film PR functions as a mask at the time of implantation, and the impurity is doped into the polycrystalline silicon film PS that protrudes from the region under the photoresist film PR. That is, the region under the photoresist film PR is not doped with impurities.
In addition, the arrow in a figure has shown the irradiation direction of the dopant.

Step 10.
As shown in FIG. 3 (10), the photoresist film PR is removed. As a result, the gate electrode GT (gate signal line) positioned under the photoresist film PR is exposed.

Step 11.
As shown in FIG. 3 (11), a low-concentration impurity made of, for example, phosphorus (P) is implanted into the polycrystalline silicon film PS from above the gate electrode.
In this case, the gate electrode GT functions as a mask at the time of implantation, and the impurity is doped into the polycrystalline silicon film PS protruding from a region under the gate electrode GT. That is, the region under the photoresist film is not doped with impurities.
In addition, the arrow in a figure has shown the irradiation direction of the dopant.

Step 12.
As shown in FIG. 3 (12), in the polycrystalline silicon film PS, a region immediately below the gate electrode GT, a region slightly extending outward from this region, and the region further extending outward from this region. The region up to the periphery is divided into a region not doped with impurities, a region doped with some impurities, and a region doped with a relatively large amount of impurities.

Thus, in the polycrystalline silicon film PS, the respective regions are formed as the channel region CD, the LDD region LDD, the source electrode or the drain electrode SD, respectively.
The LDD region LDD is provided in order to avoid electric field concentration that is likely to occur between the gate electrode GT and the source or drain electrode SD due to the relatively low concentration layer.

Step 13.
As shown in FIG. 4 (13), the second insulating film IN is formed on the upper surface of the gate electrode GT so as to cover the gate electrode GT by, for example, a plasma CVD method.
Thereafter, annealing is performed to activate the impurities doped in the step 11 in the polycrystalline silicon film PS.
In FIG. 4 (13), the heat source for lamp annealing is indicated by HT.

Step 14.
As shown in FIG. 4 (14), the second insulating film IN and the first insulating film GI therebelow are formed by selective etching, and the source electrode and the drain electrode SD of the polycrystalline silicon film PS are respectively formed. A contact hole CH that exposes a part is formed.

Step 15.
As shown in FIG. 4 (15), a conductive layer CNL is formed on the second insulating film IN so as to cover the contact hole CH. The conductive layer CNL is for forming a wiring layer connected to the source electrode or drain electrode SD by selective etching.
The conductive layer CNL has a three-layer structure formed by, for example, a sputtering method, and is composed of a laminated body of a barrier metal layer BM, an aluminum (Al) layer AL, and a cap metal layer CM.

Step 16.
As shown in FIG. 4 (16), the conductive layer CNL is selectively etched to form a wiring layer having a predetermined pattern. These wiring layers are electrically connected to the source electrode or drain electrode SD of the thin film transistor TFT through the contact hole CH.

Step 17.
As shown in FIG. 5 (17), the protective film PAS is formed on the second insulating film IN so as to cover the wiring layer. The protective film PAS is a film that avoids direct contact with the liquid crystal of the thin film transistor TFT, and an organic material may be used in addition to the inorganic material.

Step 18.
As shown in FIG. 5 (18), the protective film PAS is formed by selective etching to form a contact hole CH that exposes a part of the wiring layer.

Step 19.
As shown in FIG. 5 (19), a light-transmitting conductive film TC such as ITO is formed on the upper surface of the protective film PAS so as to cover the contact hole CH, and is formed in a predetermined pattern by a selective etching method.
This translucent conductive film TC constitutes one electrode (pixel electrode) of a pair of electrodes provided in each pixel of the display device.
In FIG. 5 (19), the light-transmitting conductive film may be used as a wiring layer for electrically connecting the thin film transistors TFT.

  FIGS. 8 to 13 are process diagrams showing another embodiment of the method for manufacturing a display device according to the present invention and correspond to the views shown in FIGS.

Step 1.
As shown in FIG. 8 (1), a transparent substrate SUB1 is prepared, and a silicon nitride film (SiN), a silicon oxide film (surface) is formed on the main surface (surface on the liquid crystal side) of the transparent substrate SUB1 using a plasma CVD method. SiO2) and an amorphous silicon film (amorphous Si: a-Si) AS are sequentially stacked. In this case, an increase in the number of manufacturing steps can be avoided by forming them in the same chamber.
Here, the silicon nitride film (SiN) and the silicon oxide film (SiO ₂ ) function as the base layer GW.

Step 2.
As shown in FIG. 8B, the amorphous silicon film AS, which is the uppermost layer of the stacked films, is formed in a predetermined pattern using a selective etching method using a photolithography technique. As a result, the silicon oxide film is exposed in a region other than the region where the remaining amorphous silicon film AS is formed.

Step 3.
As shown in FIG. 8C, the first insulating film GI is formed by, for example, a plasma CVD method so as to cover the amorphous silicon film AS on the upper surface of the silicon oxide film. The first insulating film GI is formed of, for example, a silicon oxide film (SiO ₂ ) or the like and functions as a gate insulating film of the thin film transistor TFT.

Step 4.
As shown in FIG. 8D, a dopant is implanted into the amorphous silicon film AS from above the first insulating film GI through the first insulating film GI. As this dopant, for example, low-concentration boron (B) is used. This is for controlling the threshold value of the thin film transistor TFT.
In addition, the arrow in a figure has shown the irradiation direction of the dopant.

Step 5.
As shown in FIG. 9 (5), a metal layer MT is formed over the entire upper surface of the first insulating film GI by, for example, a sputtering method.

Step 6.
As shown in FIG. 9 (6), the metal layer MT is formed in a predetermined pattern by a selective etching method. The metal layer MT is formed as a gate signal line and a capacitance signal line. In FIG. 9 (6), the metal layer MT is shown as the gate electrode GT of the thin film transistor TFT formed integrally with the gate signal line.

In this step, the photoresist film PR used as a mask in the selective etching method is left without being removed.
The gate electrode GT existing below the photoresist film PR is formed such that the peripheral side surface thereof is positioned relatively larger inside than that of the photoresist film PR.

In the pattern formation of the gate electrode GT, the above-described configuration can be obtained by performing selective etching so that so-called side etching is performed.
This is to form an LDD region in the thin film transistor TFT.

Step 7.
As shown in FIG. 9 (7), a high concentration impurity made of, for example, phosphorus (P) is implanted into the polycrystalline silicon from above the photoresist film PR.
In this case, the photoresist film PR functions as a mask at the time of implantation, and the impurity is doped into the amorphous silicon film AS that protrudes from the region under the photoresist film PR. That is, the region under the photoresist film PR is not doped with impurities.
In addition, the arrow in a figure has shown the irradiation direction of the dopant.

Step 8.
As shown in FIG. 9 (8), the photoresist film PR is removed. As a result, the gate electrode GT (gate signal line) positioned under the photoresist film PR is exposed.
In addition, in the amorphous silicon film AS, a conductive source electrode or drain electrode SD is formed from a position slightly away from a region immediately below the gate electrode GT to the periphery.

Step 9.
As shown in FIG. 10 (9), a low-concentration impurity made of, for example, phosphorus (P) is implanted into the polycrystalline silicon from above the gate electrode GT.
In this case, the gate electrode GT functions as a mask at the time of implantation, and the impurity is doped into the amorphous silicon film AS protruding from the region under the gate electrode GT. That is, the region under the gate electrode GT is not doped with impurities.
In addition, the arrow in a figure has shown the irradiation direction of the dopant.

Step 10.
As shown in FIG. 10 (10), in the amorphous silicon film AS, a region immediately below the gate electrode GT, a region slightly extending outward from this region, and an amorphous region extending further outward from this region. The region up to the periphery of the silicon film AS is divided into a region not doped with impurities, a region doped with some impurities, and a region doped with a relatively large amount of impurities.
Thus, in the amorphous silicon film AS, the respective regions are formed as the channel region CD, the LDD region LDD, the source electrode or the drain electrode SD, respectively.

Step 11.
As shown in FIG. 10 (11), the second insulating film IN is formed on the upper surface of the first insulating film GI so as to cover the gate electrode GT by, for example, a plasma CVD method.

Step 12.
As shown in FIG. 10 (12), the second insulating film IN and the first insulating film GI therebelow are formed by selective etching, and the source electrode and the drain electrode SD of the amorphous silicon film AS are respectively formed. A contact hole CH that exposes a part of the contact hole CH is formed.

Step 13.
As shown in FIG. 11 (13), a conductive film BM is formed on the upper surface of the second insulating film IN so as to cover the contact hole CH.
The conductive film BM is for forming a wiring layer connected to the source electrode or the drain electrode SD by selective etching, and is a barrier metal layer (hereinafter referred to as the lowermost layer) having a three-layer structure. The conductive layer BM is referred to as a barrier metal layer BM).

As described above, in the formation of the wiring layer having the three-layer structure, the barrier metal layer BM is formed by separating the other two layers from each other in addition to the original function of the barrier metal layer BM with high reliability. This is to have a function to perform.
For this reason, a material having a good thermal conductivity is selected as the material of the barrier metal layer BM.

Step 14.
As shown in FIG. 11 (14), the amorphous silicon film AS is annealed through the barrier metal layer BM. In this case, annealing is performed using so-called lamp annealing. This is because lamp annealing is inexpensive, and as a result, the manufacturing cost of the display device can be reduced. However, regardless of this, the annealing of the amorphous silicon film AS has the effect that the heat treatment can be made uniform over the entire region and the reliability of the annealing can be improved.

  That is, the light emitted from the lamp is absorbed by the amorphous silicon film AS and the barrier metal layer BM, and the temperature rises. In this case, the barrier metal layer BM has a sharp heat conduction and is amorphous. This is because a uniform temperature can be secured over the entire area of the quality silicon film AS.

As a result, the dopant doped in the amorphous silicon film AS in the steps 7 and 9 is uniformly activated over the entire area of the amorphous silicon film AS, and the amorphous silicon film AS is polycrystalline. A silicon film PS is formed. In this case, the first insulating film GI and the second insulating film IN are also heat-treated at the same time, and an effect of modifying the insulating films GI and IN is exhibited.
In FIG. 2 (6), the heat source for lamp annealing is indicated by HT.

Step 15.
As shown in FIG. 11 (15), two other conductive layers made of different materials are formed on the upper surface of the conductive layer by, for example, sputtering.
As a result, a multilayer structure PL including the conductive layer is formed. This multilayer structure PL is used to form a wiring layer connected to the source electrode or the drain electrode by selective etching. It is.
The multilayer body PL is configured by sequentially laminating an aluminum (Al) layer AL and a cap metal layer CM including the barrier metal layer BM.

Step 16.
As shown in FIG. 12 (16), the laminated body PL is selectively etched to form a wiring layer having a predetermined pattern. These wiring layers are electrically connected to the source electrode or drain electrode SD of the thin film transistor TFT through the contact hole CH.

Step 17.
As shown in FIG. 12 (17), a protective film PAS is formed on the upper surface of the second insulating film IN so as to cover the wiring layer. The protective film PAS is a film that avoids direct contact with the liquid crystal of the thin film transistor TFT, and an organic material may be used in addition to the inorganic material.

Step 18.
As shown in FIG. 12 (18), the protective film PAS is formed by selective etching to form a contact hole CH that exposes a part of the wiring layer.

Step 19.
As shown in FIG. 13 (19), a light-transmitting conductive film TC such as ITO is formed on the upper surface of the protective film PAS so as to cover the contact hole CH, and is formed into a predetermined pattern by a selective etching method.
This translucent conductive film TC constitutes one electrode (pixel electrode) of a pair of electrodes provided in each pixel of the display device.

    Each of the embodiments described above may be used alone or in combination. This is because the effects of the respective embodiments can be achieved independently or synergistically.

FIG. 6 is a process chart showing an embodiment of a method for manufacturing a display device according to the present invention, and shows one manufacturing method together with FIGS. FIG. 5 is a process diagram showing an embodiment of a method for manufacturing a display device according to the present invention, and shows one manufacturing method together with FIGS. FIG. 6 is a process diagram showing an embodiment of a method for manufacturing a display device according to the present invention, and shows one manufacturing method together with FIGS. 1 to 2 and FIGS. FIG. 6 is a process diagram showing an embodiment of a manufacturing method of a display device according to the present invention, and shows one manufacturing method together with FIGS. FIG. 6 is a process diagram showing an embodiment of a method for manufacturing a display device according to the present invention, and shows one manufacturing method together with FIGS. It is a top view which shows one Example of the pixel of the display apparatus used as the object of the manufacturing method of the display apparatus by this invention. It is a figure which shows the cross section in the A-A 'line | wire of FIG. FIG. 9 is a process diagram showing another embodiment of the manufacturing method of the display device according to the present invention, and shows one manufacturing method together with FIGS. FIG. 10 is a process diagram showing another embodiment of a method for manufacturing a display device according to the present invention, and shows one manufacturing method together with FIGS. 8 and 10 to 13. FIGS. 8 to 9 and FIGS. 11 to 13 are process diagrams showing another embodiment of the manufacturing method of the display device according to the present invention, and show one manufacturing method together with FIGS. FIGS. 8A to 10C and FIGS. 12 to 13 are process diagrams showing another embodiment of a method for manufacturing a display device according to the present invention, and show one manufacturing method together with FIGS. FIG. 10 is a process diagram showing another embodiment of the display device manufacturing method according to the present invention, and shows one manufacturing method together with FIGS. FIG. 9 is a process chart showing another embodiment of the manufacturing method of the display device according to the present invention, and shows one manufacturing method together with FIGS.

Explanation of symbols

SUB1 ... transparent substrate, GL ... gate signal line, DL ... drain signal line, PS ... polycrystalline silicon film, AS ... amorphous silicon film, CD ... channel region, LDD ... LDD region, TFT ... Thin film transistor, GT ... Gate electrode, SD ... Source electrode and / or drain electrode, GI ... First insulating film, IN ... Second insulating film, BM ... Barrier metal layer, CM ... Cap metal layer , PAS ... Protective film.

Claims (5)

A method of manufacturing a display device having a thin film transistor using a polycrystalline semiconductor layer on an insulating substrate,
An amorphous semiconductor layer forming step of forming an amorphous semiconductor layer on the insulating substrate;
A metal layer forming step of forming a metal layer covering the amorphous semiconductor layer after the amorphous semiconductor layer forming step;
And crystallization step of crystallizing the amorphous semiconductor layer into the polycrystalline semiconductor layer by lamp annealing the amorphous semiconductor layer and the metal layer before patterning the metal layer. A method for manufacturing a display device. 2. The method for manufacturing a display device according to claim 1, wherein the metal layer is a metal layer used for a gate electrode of the thin film transistor. 2. The method for manufacturing a display device according to claim 1, wherein the metal layer is a metal layer used for a source electrode and a drain electrode of the thin film transistor. 4. The method according to claim 1, further comprising an amorphous semiconductor layer patterning step of patterning the amorphous semiconductor layer between the amorphous semiconductor layer forming step and the metal layer forming step. 5. The manufacturing method of the display apparatus as described in any one of. 5. The method according to claim 1, further comprising a doping step of injecting impurities into the amorphous semiconductor layer between the amorphous semiconductor layer forming step and the metal layer forming step. Manufacturing method of display device.

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