JP2007141139A - Information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus that enables reliable debugging even if a CPU having a debugging function is difficult to connect to an external device. <P>SOLUTION: A communication channel setting part 211 of a second CPU unit 2 switches a communication channel to a PC if determining that the PC is connected to the second CPU unit 2, and switches the communication channel to a first CPU unit 1 if determining that no PC is connected to the second CPU unit 2. A debugging data extraction part 213 extracts data to be debugged. If the communication channel is switched to the PC, a debugging data transmission part 253 transmits the extracted data to the PC. If the communication channel is switched to the first CPU unit 1, a debugging data transmission part 226 transmits the extracted data to the first CPU unit 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing apparatus in which a plurality of CPU units including a CPU that executes a program and a memory that stores the program are connected to be communicable with each other.

  In information processing apparatuses such as printer apparatuses, copiers, and facsimile apparatuses that are already widely used, a plurality of CPUs are frequently operated in recent years to control the apparatuses. These CPUs are usually connected by a bus or a serial interface. In order to debug firmware operating on each of these CPUs, generally, hardware resources for debugging are mounted on each CPU. For this purpose, for example, it is common to use a CPU having an on-chip debugging function for each CPU, or to provide a socket for connecting an ICE (in-circuit emulator), which is a debugging device, to each CPU. In addition, a means for communicating with an external device is provided in each CPU.

  Also, a memory that can be read from and written to by the CPU is provided for each CPU, data transfer between the memories is performed by DMA (direct memory access), and a control unit controlled by one CPU is monitored from a control unit controlled by the other CPU. A method has also been proposed.

  For example, Patent Document 1 discloses a controller unit including a first memory for both reading and writing, a control unit that controls a control target based on data in the first memory, and a first communication unit for monitoring. A monitoring unit including a second memory for both reading and writing, a monitoring unit for monitoring data in the second memory, and a second communication unit for monitoring; a direct memory access unit provided in the controller unit; A monitoring device for a controller unit having The monitoring device of the controller unit transfers the data in the first memory of the controller unit to the first communication unit by the direct memory access unit, and transfers the data from the first communication unit to the second communication unit. Further, the data is transferred to the second memory of the monitoring unit, the monitoring unit monitors the temporal change of the data in the first memory based on the transferred data, and the second memory is based on the monitoring result. The updated data is updated, the updated data is transferred from the second communication unit to the first communication unit, and further transferred from the first communication unit to the first memory by the direct memory access unit.

  Further, when the debugging function is provided in each CPU as described above, hardware resources for debugging are required. Therefore, the hardware resources are surely reflected in the cost, and this cost is particularly high in the information processing apparatus targeted for the low end. The increase is unacceptable. Accordingly, it is conceivable that the first CPU of the plurality of CPUs is provided with a debugging function, and the second CPU is not provided with a debugging function. In this case, the debugging means for debugging the firmware of the second CPU is limited to the ICE, but it is necessary to prepare an expensive socket in order to use the ICE, and it is not possible to equip a socket for each of a plurality of mass production boards. It was difficult in terms of cost. If there is no such debugging means, it takes a lot of time to find out the true cause even if a problem occurs during design, manufacturing, or user use, which is a disadvantage for both manufacturers and users. There was a problem.

  Therefore, an information processing system including a plurality of CPUs including a first CPU having a debugging function and a second CPU not having a debugging function, and the first CPU and the second CPU cooperatively operate by communication. In the apparatus, a remote debugging method has been proposed in which a communication protocol for debugging a second CPU is included in the communication protocol, and the second CPU is debugged using the debugging function of the first CPU.

Further, in the information processing apparatus having the above hardware configuration, the communication protocol includes information for directly executing a subroutine of a firmware operating on the second CPU in the communication protocol for debugging the second CPU having no debugging function. Remote debugging methods have been proposed.
Japanese Patent No. 3027062

  However, according to the above remote debugging method, even if the information processing device has a debugging function in the second CPU, the second CPU on the board is disposed at a position where it is difficult to connect the debugger. There is. Considering the debugging situation for failure analysis, it is assumed that a debugger is not necessarily connected to the second CPU. In many cases, the debugger of the first CPU can be connected to the connector without turning off the power, and it is difficult for the debugger of the second CPU to connect the connector later without turning off the power. In many cases. If it is possible to acquire internal information without disconnecting the power supply even when a failure is low at the customer's failure analysis, it is effective for failure analysis with a low recall. When shipped as a product, the connector for connecting the debugger of the first CPU exists on the board, but the connector for connecting the debugger of the second CPU is often deleted for cost reduction. .

  The present invention has been made in order to solve the above-described problem, and is capable of reliably performing debugging even when it is difficult to connect a CPU having a debugging function to an external device. The object is to provide an apparatus.

  An information processing apparatus according to the present invention is an information processing apparatus in which a plurality of CPU units including a CPU that executes a program and a memory that stores the program are connected to be communicable with each other, and each of the plurality of CPU units includes A first CPU unit having a debugging function for debugging a program executed by the CPU; and a second CPU unit having a debugging function for debugging a program executed by its own CPU. The CPU unit determines whether or not an external device is connected to the second CPU unit, and when the determination unit determines that the external device is connected to the second CPU unit , Switching the communication channel to the external device, and the second CPU by the determination means When it is determined that an external device is not connected to the knit, the switching means for switching the communication channel to the first CPU unit, the extraction means for extracting data used for debugging, and the communication channel is connected to the external channel by the switching means. When switched to a device, the data extracted by the extracting means is transmitted to the external device, and when the communication channel is switched to the first CPU unit by the switching means, the data extracted by the extracting means Data transmitting means for transmitting data to the first CPU unit, wherein the first CPU unit is received by the data receiving means for receiving data transmitted by the data transmitting means and the data receiving means. Execution means for executing the debugging function using the collected data Provided.

  According to this configuration, the information processing apparatus debugs the first CPU unit having a debugging function for debugging the program executed by each CPU included in the plurality of CPU units and the program executed by the CPU of itself. And a second CPU unit having a debugging function. In the second CPU unit, it is determined whether or not an external device is connected to the second CPU unit, and if it is determined that an external device is connected to the second CPU unit, the communication channel is the external device. When it is determined that no external device is connected to the second CPU unit, the communication channel is switched to the first CPU unit. When data used for debugging is extracted and the communication channel is switched to the external device, the extracted data is transmitted to the external device, and when the communication channel is switched to the first CPU unit, the extracted data Is transmitted to the first CPU unit. In the first CPU unit, the data transmitted by the second CPU unit is received, and the debugging function is executed using the received data.

  Therefore, when it is determined whether or not an external device is connected to the second CPU unit, and it is determined that no external device is connected to the second CPU unit, the communication channel is switched to the first CPU unit. Therefore, even if it is difficult to connect a CPU having a debugging function (CPU provided in the second CPU unit) and an external device, another CPU (CPU provided in the first CPU unit) can be used. Can be surely debugged.

  In the information processing apparatus, when the communication channel is switched to the first CPU unit by the switching unit, the first CPU unit transfers the data extracted by the extracting unit to the first CPU. Receiving means for accepting selection by the user as to whether or not to transmit to the unit, and the data transmitting means, when the accepting means accepts not to transmit data to the first CPU unit, the extracting means It is preferable not to transmit the data extracted by the first CPU unit.

  According to this configuration, when the communication channel is switched to the first CPU unit in the first CPU unit, a selection by the user as to whether or not to transmit the extracted data to the first CPU unit is accepted. . When it is accepted that data is not transmitted to the first CPU unit, the extracted data is not transmitted to the first CPU unit. Therefore, even if the communication channel is switched to the first CPU unit, if it is accepted that the data used for debugging is not transmitted to the first CPU unit, the data is not transmitted. Debug data can be output from the second CPU unit.

  Further, in the information processing apparatus, the second CPU unit includes a connection confirmation signal transmitting unit that transmits a connection confirmation signal for confirming whether or not the external apparatus is connected to the external apparatus, Response signal receiving means for receiving a response signal to the connection confirmation signal transmitted by an external device, and the determination means, when the response signal is received by the response signal receiving means, the second CPU It is preferable to determine that an external device is connected to the unit.

  According to this configuration, in the second CPU unit, a connection confirmation signal for confirming whether or not the external device is connected is transmitted to the external device, and a response signal for the connection confirmation signal transmitted by the external device is received. Since it is received, it can be reliably detected that the external device is connected to the second CPU unit based on the presence or absence of the response signal.

  In the information processing apparatus, the second CPU unit further includes voltage detection means for detecting a voltage applied to a communication line connecting the second CPU unit and the external device, and the determination Preferably, the means determines that an external device is connected to the second CPU unit when a voltage is detected by the voltage detection means. In this case, the information processing apparatus does not include the connection confirmation signal transmission unit and the response signal reception unit, but further includes a voltage detection unit.

  According to this configuration, since the voltage applied to the communication line connecting the second CPU unit and the external device is detected in the second CPU unit, the second CPU unit is based on the presence or absence of this voltage. It is possible to reliably detect that an external device is connected to.

  In the above information processing apparatus, the information processing apparatus is an image forming apparatus that forms an image, and the first CPU unit includes a control unit that controls the entire image forming apparatus, and the second CPU The CPU unit preferably includes an engine control unit that controls a drive source built in the image forming apparatus.

  According to this configuration, even if the CPU unit is built in the apparatus like an engine control unit that controls a drive source built in the image forming apparatus and is difficult to directly debug by connecting an external device. Debugging can be performed via a control unit that controls the entire image forming apparatus that can be easily connected to an external device.

  According to the present invention, if it is determined whether or not an external device is connected to the second CPU unit, and if it is determined that no external device is connected to the second CPU unit, the communication channel is the first Since switching to a CPU unit is possible, even if it is difficult to connect a CPU having a debugging function (a CPU included in the second CPU unit) and an external device to another CPU (the first CPU unit is Debugging can be surely performed via the CPU provided.

  Hereinafter, an information processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an outline of the hardware configuration of an image forming apparatus which is an example of an information processing apparatus according to the present invention and a PC (personal computer) connected thereto. The image forming apparatus 10 is, for example, a printer, a copier, a facsimile machine, or the like. In the present embodiment, the image forming apparatus 10 is described as an example of an information processing apparatus. However, the present invention is not particularly limited thereto, and can be applied to an information processing apparatus other than the image forming apparatus 10.

  The image forming apparatus 10 is an embedded apparatus that is controlled by two CPUs (Central Processing Units) 11 and 21 that are connected by communication and operate in cooperation. The image forming apparatus 10 includes a first CPU unit 1 and a second CPU unit 2. The first CPU unit 1 includes a CPU 11, a ROM (read only memory) 12, a RAM (random access memory) 13, an operation panel unit 14, a communication unit 15, and a communication unit 16. The CPU 11, ROM 12, RAM 13, operation panel unit 14, communication unit 15 and communication unit 16 are connected by a local bus. The second CPU unit 2 includes a CPU 21, a communication unit 22, a ROM 23, a RAM 24, and a communication unit 25. The CPU 21, the communication unit 22, the ROM 23, the RAM 24, and the communication unit 25 are connected by a local bus.

  The first CPU unit 1 and the second CPU unit 2 are communicably connected by connecting the communication unit 15 and the communication unit 22. These communication units 15 and 22 are, for example, serial communication interfaces, and communicate by serial communication. This may be a bus connection, for example. In addition to the first and second CPU units 1 and 2, the image forming apparatus 10 includes a group of components that are connected to the CPU units 1 and 2 and controlled by the CPUs 11 and 21 to execute an image forming function (for example, a copy function). Here, it is not shown and description is omitted.

  When the information processing apparatus is an image forming apparatus, the first CPU unit 1 is a controller (control unit) that controls the entire image forming apparatus, for example, and the second CPU unit 2 is controlled by the first CPU unit 1, for example. An engine control unit that controls a motor (drive source) that drives a roller, a clutch, and the like built in the image forming apparatus. In this case, even if it is a CPU unit that is difficult to debug directly by connecting a PC, such as an engine control unit that controls a drive source built in the image forming apparatus, the PC is connected. It is possible to debug through the control unit that controls the entire image forming apparatus that is relatively easy to do. The second CPU unit 2 may be a post-processing device that is controlled by, for example, the first CPU unit 1 and performs post-processing (sorting processing, stapling processing, etc.) of paper on which images have been formed.

  A PC 3 is connected to the image forming apparatus 10 via a communication unit 16 as a terminal for a user to operate a debugging function. The PC 3 mainly includes a CPU 31, a communication unit 32, a RAM 33, an HDD 34, a display device 35, and an input device 36. Hereinafter, the components of the first and second CPU units 1 and 2 and the PC 3 will be described.

  The CPU 11 executes a program stored in the ROM 12 and controls the image forming apparatus 10 in cooperation with the CPU 21 to perform image formation and the like. The communication unit 16 is for connecting the PC 3 and is, for example, a serial communication interface. The ROM 12 is a memory for storing a program executed by the CPU 11. This program includes firmware for controlling the image forming apparatus 10 and a debugger program for providing a debugging function. The RAM 13 is a memory for giving a temporary work area or the like to the CPU 11. The operation panel unit 14 is used by a user to input an operation instruction to the image forming apparatus 10, and includes a display unit such as a liquid crystal display and operation key units such as a numeric keypad and a start key. Instead of the PC 3, the operation panel unit 14 may be used for the debugging function. The communication unit 15 is for connecting to the communication unit 22 of the second CPU unit 2, for transmitting and receiving inter-processor communication messages between the CPU units 1 and 2, and for the CPU 11 and CPU 21 to operate in cooperation, etc. Used for. The communication unit 16 is, for example, a serial communication interface for connecting to the communication unit 32 of the PC 3.

  The CPU 21 executes a program stored in the ROM 23 and controls the image forming apparatus 10 in cooperation with the CPU 11 to perform image formation. The communication unit 22 is connected to the communication unit 15 and is used for transmitting and receiving inter-processor communication messages between the CPU units 1 and 2 and for the CPU 11 and the CPU 21 to operate in cooperation. The ROM 23 is a memory for storing a program executed by the CPU 21. This program includes firmware for controlling the second CPU unit 2 and a debugger program for providing a debugging function. The RAM 24 is a memory for providing a temporary work area or the like to the CPU 21. The RAM 24 includes a transmission buffer and a change status buffer which will be described later. The communication unit 25 is, for example, a serial communication interface for connecting to a communication unit 32 of the PC 3 ′ described later.

  The CPU 31 executes a program in the RAM 33. The communication unit 32 is, for example, a serial communication interface for connecting to the communication unit 16 of the first CPU unit 1. Through this communication interface, a debug command is transmitted from the PC 3 to the first CPU unit 1 and a reply to the debug command is performed in the reverse path. The debug command includes an instruction to execute a predetermined function included in the firmware, an instruction to read data from the memory, an instruction to rewrite data to the memory, and the like. The CPU 11 performs debugging based on the instruction by the debug command. Execute. The RAM 33 is a main storage device for temporarily storing a part executed by the CPU 31 among programs stored in the HDD 34. An HDD (Hard Disk Drive Device) 34 is an external storage device that stores programs executed by the CPU 31. The display device 35 is composed of a liquid crystal display device, for example, and is used as a display user interface of the PC 3. The input device 36 includes, for example, a keyboard and a mouse, and is used as an input interface for the PC 3.

  In the present embodiment, the second CPU unit 2 may be connected to a PC. That is, the second CPU unit 2 is connected to the PC 3 ′ via the communication unit 25 provided in the second CPU unit 2. The configuration of PC3 'is the same as PC3. In this case, the debug command is transmitted from the PC 3 'to the second CPU unit 2, and the CPU 21 executes debugging based on an instruction by the debug command. In the present embodiment, the second CPU unit 2 and the PC 3 may be connected via the communication unit 25.

  Here, programs executed by the CPU 11 of the first CPU unit 1, the CPU 21 of the second CPU unit 2, and the CPU 31 of the PC 3 will be described. Programs executed by the CPU 31 are mainly a PC-side debugger program and an OS (operating system). The OS is software that mediates between application software (including a PC-side debugger program) executed on the PC 3 by basic software of the PC 3 and hardware of the PC 3. The PC-side debugger program is application software that runs on the PC 3, and is activated / terminated by the user using the input device 36 and operated. The user designates a debug command as an operation of the PC-side debugger program. Further, the user can check the execution result of the debug command displayed on the display device 35. The program executed by the CPU 31 of the PC 3 'is the same as described above.

  The programs executed by the CPU 11 are first CPU unit side firmware and first CPU unit side debugger program. The first CPU unit side firmware is a program for controlling the image forming apparatus 10, that is, the first CPU unit 1 and the second CPU unit 2, and is a program to be debugged (program to be debugged). The first CPU unit side debugger program is a program that performs processing for debugging the first CPU unit side firmware executed by the CPU 11 and the second CPU unit side firmware executed by the CPU 21. When the image forming apparatus 10 is activated, the first CPU unit side debugger program is activated. The first CPU unit-side debugger program activates the first CPU unit-side firmware as necessary.

  The programs executed by the CPU 21 are second CPU unit side firmware and second CPU unit side debugger program. The second CPU unit side firmware is a program for controlling the second CPU unit 2 and is a program to be debugged. The second CPU unit side debugger program is a program that performs processing for debugging the second CPU unit side firmware executed by the CPU 21.

  The debug command instructed to be executed by the user in the PC-side debugger program is transmitted as a debug command transmission character string to the first CPU unit-side debugger program (second CPU unit-side debugger program) via the OS. A reply to the received debug command is sent to the PC-side debugger program through the reverse route of transmission.

  Transmission / reception of inter-processor communication messages in inter-processor communication between the first CPU unit-side firmware and the second CPU unit-side firmware is performed via the first CPU unit-side debugger program and the second CPU unit-side firmware. An inter-processor communication message from the first CPU unit side firmware to the second CPU unit side firmware is sent from the first CPU unit side debugger program to the second CPU unit side firmware in a predetermined communication frame (unit of data transmitted and received in communication). Transmission of the communication frame from the second CPU unit side firmware to the first CPU unit side firmware takes the reverse path.

  The predetermined communication frame (format) used in the inter-processor communication message is also used when a debug command and its reply are transmitted and received between the first CPU unit-side debugger program and the second CPU unit-side debugger program.

  FIG. 2 is a block diagram showing a functional configuration of the first CPU unit 1 and the second CPU unit 2. The first CPU unit 1 includes a CPU 11 and a communication unit 15. The CPU 11 includes a communication channel setting unit 111, a transmission setting reception unit 112, and a debug execution unit 113. The communication channel setting unit 111 sets a communication channel with the second CPU unit 2 when a connection request is received by the connection request receiving unit 151.

  Whether the second CPU unit 2 transmits data for debugging (debug data) to the first CPU unit 1 when the communication channel is switched to the first CPU unit 1 by the second CPU unit 2. The selection by the user is accepted. Note that transmission setting information indicating whether or not the second CPU unit 2 transmits debug data to the first CPU unit 1 is input by the user using the input device 36 or the operation panel unit 14 of the PC 3.

  When the debug target is the first CPU unit 1, the debug execution unit 113 executes debugging of firmware stored in the first CPU unit 1. Further, when the debug target is the second CPU unit 2, the debug executing unit 113 executes debugging using the debug data received by the debug data receiving unit 156.

  The communication unit 15 includes a connection request reception unit 151, a connection response transmission unit 152, a transmission setting information transmission unit 153, an interrupt signal reception unit 154, a data request signal transmission unit 155, and a debug data reception unit 156.

  The connection request receiving unit 151 receives the connection request transmitted by the second CPU unit 2. The connection response transmission unit 152 transmits a connection response that is a response signal to the connection request received by the connection request reception unit 151 to the second CPU unit 2. The transmission setting information transmission unit 153 transmits the transmission setting information received by the transmission setting reception unit 112. The transmission setting information includes transmission permission information indicating that the second CPU unit 2 transmits debug data to the first CPU unit 1, and transmission indicating that the second CPU unit 2 does not transmit debug data to the first CPU unit 1. And rejection information. The interrupt signal receiving unit 154 receives the interrupt signal transmitted by the second CPU unit 2.

  When the interrupt signal receiving unit 154 receives the interrupt signal, the data request signal transmitting unit 155 transmits a data request signal for requesting debug data to the second CPU unit 2. The debug data receiving unit 156 receives the debug data transmitted by the second CPU unit 2.

  The second CPU unit 2 includes a CPU 21, a communication unit 22, a RAM 24, and a communication unit 25. The communication unit 22 includes a connection request transmission unit 221, a connection response reception unit 222, a transmission setting information reception unit 223, an interrupt signal transmission unit 224, a data request signal reception unit 225, and a debug data transmission unit 226. The CPU 21 includes a communication channel setting unit 211, a transmission setting unit 212, a debug data extraction unit 213, a determination unit 214, and a debug data reading unit 215. The communication unit 25 includes a connection confirmation request transmission unit 251, a connection confirmation response reception unit 252, and a debug data transmission unit 253.

  The communication channel setting unit 211 determines whether or not the PC 3 ′ is connected to the second CPU unit 2, and when it is determined that the PC 3 ′ is connected to the second CPU unit 2, the communication channel is switched to the PC 3 ′. At the same time, when it is determined that the PC 3 ′ is not connected to the second CPU unit 2, the communication channel is switched to the first CPU unit 1.

  The communication channel setting unit 211 outputs a connection confirmation request for confirming whether the PC 3 ′ is connected to the connection confirmation request transmission unit 251. The connection confirmation request transmission unit 251 transmits the connection confirmation request output by the communication channel setting unit 211 to the PC 3 ′. The connection confirmation response receiving unit 252 receives a response signal (connection confirmation response) to the connection confirmation request transmitted by the PC 3 ′ and outputs the response signal to the communication channel setting unit 211.

  The communication channel setting unit 211 determines that the PC 3 ′ is connected to the second CPU unit 2 when the connection confirmation response is received by the connection confirmation response receiving unit 252. If the connection confirmation response receiving unit 252 does not receive a connection confirmation response even after a predetermined time has elapsed, the communication channel setting unit 211 determines that the PC 3 ′ is not connected to the second CPU unit 2.

  When the communication channel setting unit 211 determines that the PC 3 ′ is not connected to the second CPU unit 2, the communication channel setting unit 211 outputs a connection request for requesting connection to the first CPU unit 1 to the connection request transmission unit 221. The connection request transmission unit 221 transmits the connection request output by the communication channel setting unit 211 to the first CPU unit 1. The connection response receiving unit 222 receives the connection response transmitted by the first CPU unit 1. The connection response receiving unit 222 outputs the received connection response to the communication channel setting unit 211. The communication channel setting unit 211 is connected to the communication channel with the first CPU unit 1 by receiving a connection response.

  The transmission setting information receiving unit 223 receives the transmission setting information transmitted by the first CPU unit 1 and outputs it to the transmission setting unit 212. When the transmission setting information received by the transmission setting information receiving unit 223 includes transmission rejection information indicating that debug data is not transmitted to the first CPU unit 1, the transmission setting unit 212 stores the debug data in the first CPU unit. The debug data transmission unit 226 is set so as not to be transmitted to 1.

  The debug data extracting unit 213 executes the firmware stored in the second CPU unit 2 and extracts debug data used for debugging. The debug data extraction unit 213 monitors data contents stored in the transmission buffer 241 and the change status buffer 242, outputs the extracted debug data to the transmission buffer 241, and outputs debug data from the transmission buffer 241 to the change status buffer 242. Output.

  The determination unit 214 determines whether debug data is stored in the change status buffer 242. The interrupt signal transmission unit 224 transmits an interrupt signal to the first CPU unit 1 when the determination unit 214 determines that the debug data is stored in the change status buffer 242. The data request signal receiving unit 225 receives the data request signal transmitted by the first CPU unit 1.

  The debug data reading unit 215 reads debug data from the change status buffer 242 when the data request signal is received by the data request signal receiving unit 225. When the PC 3 ′ is not connected to the second CPU unit 2, the debug data transmitting unit 226 transmits the debug data read by the debug data reading unit 215 to the first CPU unit 1. When the PC 3 ′ is connected to the second CPU unit 2, the debug data transmission unit 253 transmits the debug data read by the debug data reading unit 215 to the PC 3 ′.

  The RAM 24 includes a transmission buffer 241 and a change status buffer 242. The transmission buffer 241 stores the debug data extracted by the debug data extraction unit 213. Note that the debug data stored in the transmission buffer 241 is composed of, for example, a plurality of characters. The change status buffer 242 stores state change information of the second CPU unit 2 and stores debug data output from the transmission buffer 241. Note that the transmission buffer 241 sequentially outputs a plurality of characters to the change status buffer 242 one by one. The debug data stored in the change status buffer 242 stores, for example, a plurality of characters one by one.

  Note that the state change information of the second CPU unit 2 stored in the change status buffer 242 is, for example, information indicating that the side cover is open when the second CPU unit 2 is a post-processing device. That is, the state change information is information for voluntarily notifying the first CPU unit 1 of the changed state when the state of the second CPU unit 2 changes.

  In the present embodiment, the image forming apparatus 10 corresponds to an example of an information processing apparatus, the first CPU unit 1 corresponds to an example of a first CPU unit, and the second CPU unit 2 corresponds to an example of a second CPU unit. The PC 3 ′ corresponds to an example of an external device, the communication channel setting unit 211 corresponds to an example of a determination unit, the communication channel setting unit 211 corresponds to an example of a switching unit, and the debug data extraction unit 213 serves as an extraction unit. The debug data transmission unit 226 and the debug data transmission unit 253 correspond to an example of a data transmission unit, the debug data reception unit 156 corresponds to an example of a data reception unit, and the debug execution unit 113 corresponds to an example of an execution unit. It corresponds to. The transmission setting reception unit 112 corresponds to an example of a reception unit, the connection confirmation request transmission unit 251 corresponds to an example of a connection confirmation signal transmission unit, and the connection confirmation response reception unit 252 corresponds to an example of a response signal reception unit. .

  Next, the debugging operation by the first CPU unit 1 and the second CPU unit 2 will be described. 3 to 5 are flowcharts for explaining the debugging operation by the first CPU unit 1 and the second CPU unit 2 shown in FIG.

  First, when the image forming apparatus 10 is turned on, the communication channel setting unit 211 outputs a connection confirmation request to the connection confirmation request transmission unit 251. The connection confirmation request transmission unit 251 transmits the connection confirmation request output by the communication channel setting unit 211 to the PC 3 '(step S1). When the PC 3 ′ is connected to the second CPU unit 2, a connection confirmation response that is a response signal to the connection confirmation request is transmitted to the second CPU unit 2 by the PC 3 ′. On the other hand, when the PC 3 ′ is not connected to the second CPU unit 2, the connection confirmation response is not transmitted.

  Next, the communication channel setting unit 211 determines whether or not a connection confirmation response has been received by the connection confirmation response reception unit 252 (step S2). When the connection confirmation response is received (YES in step S2), since the PC 3 ′ is connected to the second CPU unit 2, the communication channel setting unit 211 switches the communication channel to the PC 3 ′ (communication unit 25) (step) S3). By switching the communication channel to PC3 ', subsequent data transmission / reception is performed with PC3'.

  Next, the debug data extraction unit 213 executes the firmware stored in the ROM 23, extracts debug data (debug data) (step S4), and outputs the extracted debug data to the transmission buffer 241 (step S4). S5). The debug data is extracted when the debug data extraction unit 213 executes an output function for outputting debug data included in the firmware. As this output function, for example, a printf function which is a general-purpose output function of C language is used.

  Thus, since the data used for debugging is extracted by executing the output function for outputting the data used for debugging from the program, by executing the output function described in advance in the program, Data used for debugging can be easily extracted. In this embodiment, the printf function, which is a general-purpose output function in C language, is used. However, the present invention is not particularly limited to this, and output functions in other languages may be used.

  Next, the debug data extraction unit 213 monitors the storage contents of the transmission buffer 241 and determines whether debug data is stored in the transmission buffer 241 (step S6). If it is determined that debug data is not stored in the transmission buffer 241 (NO in step S6), the process returns to step S4 to execute a process of extracting debug data.

  On the other hand, when it is determined that debug data is stored in the transmission buffer 241 (YES in step S6), the debug data extraction unit 213 outputs the debug data stored in the transmission buffer 241 to the change status buffer 242. (Step S7). At this time, when debug data composed of a plurality of characters is stored in the transmission buffer 241, the debug data extraction unit 213 extracts the characters from the transmission buffer 241 one by one in order from the first character, and sends them to the change status buffer 242. Output.

  Next, the determination unit 214 monitors the stored contents of the change status buffer 242 and determines whether or not the change status buffer 242 is empty (step S8). If it is determined that the change status buffer 242 is empty (YES in step S8), the determination unit 214 repeatedly executes the determination in step S8 at predetermined intervals until debug data is stored in the change status buffer 242. To do.

  On the other hand, when it is determined that the change status buffer 242 is not empty (NO in step S8), the debug data reading unit 215 reads the debug data stored in the change status buffer 242 (step S9). The debug data reading unit 215 outputs the read debug data to the debug data transmission unit 253.

  Next, the debug data transmitting unit 253 transmits the debug data read from the change status buffer 242 by the debug data reading unit 215 to the PC 3 '(Step S10). Then, after the debug data is transmitted to the PC 3 ′, the process returns to the process of step S 6, it is determined whether there is debug data in the transmission buffer 241, and the subsequent processes are executed. The communication unit 32 of the PC 3 ′ receives the debug data transmitted by the second CPU unit 2 and outputs it to the display device 35. The display device 35 displays debug data received by the communication unit 32.

  On the other hand, when the connection confirmation response is not received (NO in step S2), the communication channel setting unit 211 determines whether or not a predetermined time has elapsed since the connection confirmation request was transmitted (step S11). When the connection confirmation request is transmitted, the communication channel setting unit 211 starts timing by a timer (not shown). If it is determined that a predetermined time has not elapsed since the connection confirmation request was transmitted (NO in step S11), the process returns to step S2, and the connection confirmation response receiving unit 252 has received a connection confirmation response. It is determined whether or not.

  On the other hand, if it is determined that a predetermined time has elapsed since the connection confirmation request was transmitted (YES in step S11), since the PC 3 ′ is not connected to the second CPU unit 2, the communication channel setting unit 211 sets the communication channel. Switch to the first CPU unit 1 (communication unit 22) (step S12).

  Next, the communication channel setting unit 211 outputs a connection request for requesting connection to the first CPU unit 1 to the connection request transmission unit 221. The connection request transmission unit 221 transmits the connection request output by the communication channel setting unit 211 to the first CPU unit 1 (step S13).

  Next, the connection request receiving unit 151 of the first CPU unit 1 receives the connection request transmitted by the second CPU unit 2 and outputs it to the communication channel setting unit 111 (step S31). When the connection request is received by the connection request receiver 151, the communication channel setting unit 111 outputs a response signal (connection response) to the connection request to the connection response transmitter 152. The connection response transmission unit 152 transmits the connection response output by the communication channel setting unit 111 to the second CPU unit 2 (step S32).

  Next, the connection response receiving unit 222 receives the connection response transmitted by the first CPU unit 1 and outputs it to the communication channel setting unit 211 (step S14). By outputting the connection response to the communication channel setting unit 211, subsequent data transmission / reception is performed with the PC 3 via the first CPU unit 1.

  In step S32, after the connection response is transmitted to the second CPU unit 2 by the connection response transmission unit 152, the transmission setting reception unit 112 determines whether or not the second CPU unit 2 transmits the debug data to the first CPU unit 1. Is selected by the user, and the received transmission setting information is output to the transmission setting information transmitting unit 153 (step S33). Specifically, the transmission setting reception unit 112 displays a screen for receiving transmission setting information on the display device 35 of the PC 3 or the operation panel unit 14 of the first CPU unit 1. The input device 36 of the PC 3 or the operation panel unit 14 of the first CPU unit 1 accepts input of transmission setting information by the user, and outputs the inputted transmission setting information to the transmission setting acceptance unit 112.

  Next, the transmission setting information transmission unit 153 transmits the transmission setting information output by the transmission setting reception unit 112 to the second CPU unit 2 (step S34). Next, the transmission setting information receiving unit 223 of the second CPU unit 2 receives the transmission setting information transmitted by the first CPU unit 1 and outputs it to the transmission setting unit 212 (step S15).

  Next, the transmission setting unit 212 determines whether or not the transmission setting information received by the transmission setting information receiving unit 223 includes transmission rejection information indicating that debug data is not transmitted to the first CPU unit 1. (Step S16). Here, when it is determined that the transmission setting information includes the transmission rejection information (YES in step S16), the transmission setting unit 212 transmits the debug data to the first CPU unit 1 to the debug data transmission unit 226. It sets so that it may not (step S17).

  When it is determined that the transmission rejection information is not included in the transmission setting information, that is, when transmission permission information indicating that the debug data is transmitted to the first CPU unit 1 is included in the transmission setting information (in step S16). NO), or when transmission rejection setting is performed by the transmission setting unit 212, the debug data extracting unit 213 executes the firmware stored in the ROM 23 and extracts debug data (debug data) (step) S18).

  In addition, since the process from step S18 to S22 is the same as the process from step S4 to S8, the description is omitted.

  If it is determined in step S22 that the change status buffer 242 is not empty (NO in step S22), the determination unit 214 outputs an interrupt signal to the interrupt signal transmission unit 224 so as to generate an interrupt process in the first CPU unit 1. . Next, the interrupt signal transmission unit 224 transmits an interrupt signal to the first CPU unit 1 (step S23).

  Next, the interrupt signal receiver 154 of the first CPU unit 1 receives the interrupt signal transmitted by the second CPU unit 2 (step S35). When the interrupt signal is received by the interrupt signal receiving unit 154, the data request signal transmitting unit 155 transmits a data request signal for requesting transmission of debug data to the second CPU unit 2 (step S36).

  Next, the data request signal receiving unit 225 of the second CPU unit 2 receives the data request signal transmitted by the first CPU unit 1 (step S24). Next, when the data request signal is received by the data request signal receiving unit 225, the debug data reading unit 215 reads the debug data stored in the change status buffer 242 (step S25). The debug data reading unit 215 outputs the read debug data to the debug data transmission unit 226.

  Next, the debug data transmitting unit 226 determines whether or not the transmission setting unit 212 is set not to transmit debug data to the first CPU unit 1 (step S26). If it is determined that the debug data is set not to be transmitted to the first CPU unit 1 (YES in step S26), the debug data transmitting unit 226 reads the change data from the change status buffer 242 by the debug data reading unit 215. The debug data is discarded (step S27).

  On the other hand, when it is determined that the debug data is set to be transmitted to the first CPU unit 1 (NO in step S26), the debug data transmitting unit 226 is read from the change status buffer 242 by the debug data reading unit 215. The debug data is transmitted to the first CPU unit 1 (step S28). Then, after the debug data is transmitted to the first CPU unit 1 or after the debug data is discarded, the process returns to step S20 to determine whether or not there is debug data in the transmission buffer 241, and the subsequent processes Is executed.

  Next, the debug data receiving unit 156 of the first CPU unit 1 receives the debug data transmitted by the second CPU unit 2 (step S37). The debug data reception unit 156 outputs the received debug data to the debug execution unit 113.

  Next, the debug executing unit 113 executes a debug function using the debug data received by the debug data receiving unit 156 (step S38). Specifically, the debug execution unit 113 outputs debug data to the PC 3 via the communication unit 16. The communication unit 32 of the PC 3 receives the debug data transmitted by the first CPU unit 1 and outputs it to the display device 35. The display device 35 displays debug data received by the communication unit 32.

  As described above, the image forming apparatus 10 includes a first CPU unit 1 having a debugging function for debugging a program executed by each CPU included in a plurality of CPU units, and a debug for debugging a program executed by its own CPU. And a second CPU unit 2 having a function. In the second CPU unit 2, it is determined whether or not the PC 3 ′ is connected to the second CPU unit 2. When it is determined that the PC 3 ′ is connected to the second CPU unit 2, the communication channel is switched to the PC 3 ′. At the same time, when it is determined that the PC 3 ′ is not connected to the second CPU unit 2, the communication channel is switched to the first CPU unit 1. When data used for debugging is extracted and the communication channel is switched to the PC 3 ′, the extracted data is transmitted to the PC 3 ′, and when the communication channel is switched to the first CPU unit 1, the extracted data is It is transmitted to the first CPU unit 1. In the first CPU unit 1, the data transmitted by the second CPU unit 2 is received, and the debugging function is executed using the received data.

  Therefore, if it is determined whether or not the PC 3 ′ is connected to the second CPU unit 2 and it is determined that the PC 3 ′ is not connected to the second CPU unit 2, the communication channel is switched to the first CPU unit 1. Even when it is difficult to connect the CPU 3 having a debugging function (CPU 21 provided in the second CPU unit 2) and the PC 3 ', debugging is surely performed through another CPU (CPU 11 provided in the first CPU unit 1). It can be performed.

  Further, the communication unit 16 of the first CPU unit 1 has a connector that can be connected to the PC 3 without cutting off the power source, and the communication unit 25 of the second CPU unit 2 cannot be connected to the PC 3 ′ unless the power source is cut off. When the connector is provided, the first CPU unit 1 can debug the program executed by the CPU 21 of the second CPU unit 2, and therefore, it is possible to analyze a problem with a low reproducibility without turning off the power.

  Further, even when the second CPU unit 2 is mounted inside the image forming apparatus 10 and disposed at a position where it is difficult to connect to the PC 3 ′, the program executed by the CPU 21 of the second CPU unit 2 by the first CPU unit 1. Can be debugged.

  In the first CPU unit 1, when the communication channel is switched to the first CPU unit 1, a selection by the user as to whether or not to transmit the extracted data to the first CPU unit 1 is accepted. When it is accepted that data is not transmitted to the first CPU unit 1, the extracted data is not transmitted to the first CPU unit 1. Therefore, even if the communication channel is switched to the first CPU unit 1, if it is accepted that the data used for debugging is not transmitted to the first CPU unit 1, the data is not transmitted. Data for debugging can be output from the unit 2.

  Further, in the second CPU unit 2, a connection confirmation request for confirming whether or not the PC 3 ′ is connected is transmitted to the PC 3 ′, and a response signal (connection confirmation response) to the connection confirmation request transmitted by the PC 3 ′ is received. Since it is received, it can be reliably detected that the PC 3 'is connected to the second CPU unit 2 based on the presence or absence of the response signal.

  In the present embodiment, when the second CPU unit 2 transmits a connection confirmation request to the PC 3 ′ and receives a connection confirmation response from the PC 3 ′, the PC 3 ′ is connected to the second CPU unit 2. However, the present invention is not particularly limited to this, and by detecting the presence or absence of a voltage applied to the communication line connecting the second CPU unit 2 and the PC 3 ', the PC 3' is connected to the second CPU unit 2. It may be determined whether or not it is connected.

  FIG. 6 is a block diagram showing a functional configuration of the first CPU unit 1 and the second CPU unit 2 when detecting a voltage applied to a communication line connecting the second CPU unit 2 and the PC 3 ′. In FIG. 6, the description of the same configuration as that of the first CPU unit 1 and the second CPU unit 2 shown in FIG. 2 is omitted, and only a different configuration is described.

  The second CPU unit 2 includes a CPU 21, a communication unit 22, a RAM 24, a communication unit 25, and a voltage detection unit 26. The voltage detection unit 26 detects the presence / absence of a voltage applied to a communication line connecting the communication unit 25 of the second CPU unit 2 and the communication unit 32 of the PC 3 ′, and transmits a detection signal indicating the presence / absence of the voltage to the communication channel setting unit. To 211. The communication unit 25 includes a debug data transmission unit 253.

  When the PC 3 ′ is connected to the second CPU unit 2, a constant voltage is applied to the communication line that connects the communication unit 25 of the second CPU unit 2 and the communication unit 32 of the PC 3 ′. Therefore, the communication channel setting unit 211 determines that the PC 3 ′ is connected to the second CPU unit 2 when the voltage is detected by the voltage detection unit 26, and if the voltage is not detected by the voltage detection unit 26, the second CPU It is determined that the PC 3 ′ is not connected to the unit 2.

  As described above, in the second CPU unit 2, the voltage applied to the communication line connecting the second CPU unit 2 and the PC 3 'is detected, so that the PC 3' is connected to the second CPU unit 2 based on the presence or absence of this voltage. Can be reliably detected.

1 is a block diagram illustrating an outline of a hardware configuration of an image forming apparatus which is an example of an information processing apparatus according to the present invention and a PC (personal computer) connected thereto. It is a block diagram which shows the function structure of a 1st CPU unit and a 2nd CPU unit. FIG. 3 is a first flowchart for explaining a debugging operation by a first CPU unit and a second CPU unit shown in FIG. 2. FIG. 3 is a second flowchart for explaining a debugging operation by the first CPU unit and the second CPU unit shown in FIG. 2. FIG. 6 is a third flowchart for explaining a debugging operation by the first CPU unit and the second CPU unit shown in FIG. 2. It is a block diagram which shows the function structure of the 1st CPU unit and the 2nd CPU unit in the case of detecting the voltage applied to the communication line which connects 2nd CPU unit and PC.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st CPU unit 2 2nd CPU unit 10 Image forming apparatus 11, 21, 31 CPU
12,23 ROM
13, 24, 33 RAM
14 Operation panel section 15, 16, 22, 25, 32 Communication section 34 HDD
35 display device 36 input device 111 communication channel setting unit 112 transmission setting reception unit 113 debug execution unit 151 connection request reception unit 152 connection response transmission unit 153 transmission setting information transmission unit 154 interrupt signal reception unit 155 data request signal transmission unit 156 debug data Receiving unit 211 Communication channel setting unit 212 Transmission setting unit 213 Debug data extraction unit 214 Judgment unit 215 Debug data reading unit 221 Connection request transmission unit 222 Connection response reception unit 223 Transmission setting information reception unit 224 Interrupt signal transmission unit 225 Data request signal reception Unit 226 debug data transmission unit 241 transmission buffer 242 change status buffer 251 connection confirmation request transmission unit 252 connection confirmation response reception unit 253 debug data transmission unit

Claims (5)

An information processing apparatus in which a plurality of CPU units including a CPU that executes a program and a memory that stores the program are connected to be communicable with each other,
A first CPU unit having a debugging function for debugging a program executed by each CPU included in the plurality of CPU units;
A second CPU unit having a debugging function for debugging a program executed by its own CPU;
The second CPU unit is
Determining means for determining whether an external device is connected to the second CPU unit;
When the determination means determines that an external device is connected to the second CPU unit, the communication channel is switched to the external device, and the external device is connected to the second CPU unit by the determination means. Switching means for switching the communication channel to the first CPU unit when it is determined that the communication channel is not
An extraction means for extracting data used for debugging;
When the communication channel is switched to the external device by the switching unit, the data extracted by the extraction unit is transmitted to the external device, and the communication channel is switched to the first CPU unit by the switching unit. A data transmission means for transmitting the data extracted by the extraction means to the first CPU unit;
The first CPU unit is
Data receiving means for receiving data transmitted by the data transmitting means;
An information processing apparatus comprising: execution means for executing a debugging function using data received by the data receiving means. The first CPU unit is
An accepting means for accepting selection by the user as to whether or not to transmit the data extracted by the extracting means to the first CPU unit when the communication channel is switched to the first CPU unit by the switching means; Prepared,
The data transmission unit does not transmit the data extracted by the extraction unit to the first CPU unit when the reception unit accepts that the data is not transmitted to the first CPU unit. The information processing apparatus according to claim 1. The second CPU unit is
A connection confirmation signal transmitting means for transmitting a connection confirmation signal for confirming whether or not the external device is connected to the external device;
Response signal receiving means for receiving a response signal for the connection confirmation signal transmitted by the external device;
3. The information according to claim 1, wherein the determination unit determines that an external device is connected to the second CPU unit when the response signal is received by the response signal reception unit. Processing equipment. The second CPU unit is
Voltage detection means for detecting a voltage applied to a communication line connecting the second CPU unit and the external device;
The information processing apparatus according to claim 1, wherein the determination unit determines that an external device is connected to the second CPU unit when a voltage is detected by the voltage detection unit. The information processing apparatus is an image forming apparatus that forms an image;
The first CPU unit includes a control unit that controls the entire image forming apparatus,
The information processing apparatus according to claim 1, wherein the second CPU unit includes an engine control unit that controls a drive source built in the image forming apparatus.

Images