JP2007124075A - Image processing apparatus and method, and image recording apparatus and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus and an image processing method capable of carrying out image compression processing in real time while suppressing an increase in the circuit scale and the power consumption. <P>SOLUTION: The image processing apparatus includes: a resolution conversion means that converts a resolution of input image data adopting the raster scan system, temporarily stores intermediate data for the resolution conversion processing to an image buffer memory, reads the intermediate data stored in the image buffer memory to apply prescribed processing to the data and obtaining final image data after the resolution conversion; a scan system conversion means that converts the image data after the resolution conversion from the image data adopting the raster scan system into image data adopting the block scan system; and an image compression means for applying compression processing to the image data adopting the block scan system from the scan system conversion means. The scan system conversion means includes a buffer memory and gives a control signal for stopping an output of the image data after the resolution conversion to the resolution conversion means in response to an acquisition request of the image data from the image compression means and a utilizing state of the buffer memory. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is an image processing apparatus, an image processing method, an imaging recording apparatus, and an imaging recording method that are suitable for application when, for example, imaged image data from an image sensor is compressed and stored in a storage unit such as a memory or a recording medium. About.

  For example, when storing captured image data of a moving image from an image sensor in a memory or recording medium, in order to effectively use the data capacity of the memory or recording medium, the captured image data is compressed, It is conceivable to store in a memory or a recording medium.

  In this case, the compression of image data is generally a combination of DCT (Discrete Cosine Transform) processing, quantization processing, and entropy coding with a certain block size, such as MPEG (Moving Picture Experts Group). These compression techniques are generally used.

  By the way, when image data such as captured image data having a predetermined frame rate or field rate (represented by the number of image frames or image field per second) input continuously is compressed in real time, a single still Unlike the case of compressing an image, it is not possible to temporarily store one piece of captured image data in a frame memory or a field memory and perform compression processing over time.

  By using real-time processing without using frame memory or field memory, raster image capture image data is converted into block-unit image data (block scan image data) suitable for DCT processing, for example, and sequentially processed. This method is described in Patent Document 1 (Japanese Patent Laid-Open No. 5-252522).

  Also, by using the frame memory or field memory, only the difference from the previous frame or field is compressed, thereby reducing the data size and shortening the processing time required for the compression processing, thereby performing real-time video compression. The method is described in Patent Document 2 (Japanese Patent Laid-Open No. 6-253251).

The above prior art documents are as follows.
JP-A-5-252522 JP-A-6-253251

  However, when the method of Patent Document 2 is used, an increase in circuit scale becomes a problem because a frame memory and a field memory are separately required. According to the method of Patent Document 1, a frame memory and a field memory are not required individually, but it is assumed that the compression circuit has a processing capability with a sufficient margin with respect to the signal processing rate.

  However, normally, in entropy encoding, since an encoding table (ROM (Read Only Memory), etc.) is referred to from a data value, it is difficult to configure by pipeline processing, and the processing time of the compression circuit is the maximum processing time. Redundant processing time considering time is required.

  In an actual natural image, there is almost no continuous operation in the maximum processing time, so in the case of the method of Patent Document 1, the compression circuit requires excessive specifications for the necessary processing capacity. Therefore, it is necessary to increase the power consumption by increasing the clock frequency and increase the circuit scale by performing parallel processing.

  For example, when imaging output is required at a frame rate of, for example, 240 fps, which is higher than a normal frame rate of 50 fps (frame per second) or 60 fps, the above problem is further increased. It becomes.

  In view of the above points, an object of the present invention is to provide an image processing apparatus and method capable of performing image compression processing in real time while suppressing an increase in circuit scale and power consumption.

In order to solve the above problems, the invention of claim 1
Image buffer memory,
Converting the resolution of raster-scan input image data that is continuously input at a rate at which the number of frames or fields per unit time is a predetermined number, the intermediate data of the resolution conversion process A resolution conversion means for temporarily storing in the image buffer memory, reading out the intermediate data stored in the image buffer memory, performing a predetermined process, and obtaining final resolution-converted image data;
Scan method conversion means for converting the image data after resolution conversion from the resolution conversion means from raster scan method to block scan image data;
Image compression means for receiving the block scan system image data from the scan system conversion means in units of a predetermined amount and performing image data compression processing;
Storage means for storing the image data compressed by the image compression means in a storage unit;
With
After the image compression processing for the block scan type image data of the predetermined amount unit obtained from the scan type conversion unit is completed, the image compression unit stores the block scan type image data in the scan type conversion circuit. Is a request for acquisition,
The scan method conversion unit includes a buffer memory that temporarily holds the raster scan method image data to perform processing for converting the scan method, the request for acquiring the image data from the image compression unit, and When it is determined that the compression processing in the image compression unit is not in time for the resolution-converted image data from the resolution conversion unit according to the use situation of the buffer memory, the resolution conversion unit Provided is an image processing apparatus characterized by supplying a control signal for stopping output of post-image data.

  In the image processing apparatus according to the first aspect, the resolution of the raster scan type input image data is converted to the resolution of the output image data. In this case, the resolution conversion means temporarily stores the intermediate data of the resolution conversion process in the image buffer memory. Then, the intermediate data stored in the image buffer memory is read out and subjected to predetermined processing to obtain final image data after resolution conversion.

  Then, for image data compression, the scan method conversion means converts the raster scan method into block scan image data, and the converted block scan image data is converted into image data from the image compression means in units of a predetermined amount. It is sent to the image compression means in response to a data acquisition request.

  The image compression means sends the image data acquisition request to the scan method conversion means when the compression processing of the predetermined amount of image data acquired from the scan method conversion means is completed.

  The scanning method conversion means includes a buffer memory, and performs image compression on the resolution-converted image data from the resolution conversion means in accordance with a request for acquisition of image data from the image compression means and the usage status of the buffer memory. When it is determined that the compression processing by the means is not in time, a control signal for stopping output of the image data after resolution conversion is supplied to the resolution conversion means.

  Receiving this, the resolution conversion means stops outputting the image data after resolution conversion. At this time, intermediate data for resolution conversion processing is stored in the image buffer memory. When the compression process in the image compression unit is finished and an image data acquisition request is generated, the scan method conversion unit stops supplying a control signal for stopping output of the image data after resolution conversion to the resolution conversion unit. Therefore, the data compression processing of the image data after resolution conversion from the resolution conversion means is resumed.

  As described above, in the first aspect of the invention, when the image compression processing in the image compression unit is not in time for the input of the image data, the output of the resolution-converted data from the resolution conversion unit is stopped, Intermediate data for resolution conversion processing is stored in the image buffer memory. Since the image buffer memory originally exists for resolution conversion processing, the circuit scale does not increase, and it is not necessary to increase the clock frequency, so that it is possible to prevent an increase in power consumption.

  According to the present invention, image compression processing can be performed in real time while suppressing an increase in circuit scale and power consumption.

  Embodiments of an image processing apparatus according to the present invention will be described below with reference to the drawings. In this embodiment, the image processing apparatus according to the present invention can record and play back captured image data at a normal frame rate of 50 fps or 60 fps or a normal field rate (hereinafter referred to as a normal rate), and at a normal rate. This is a case where the present invention is applied to an imaging recording / reproducing apparatus capable of recording and reproducing captured image data at a higher speed, for example, a high frame rate or a high field rate (hereinafter referred to as a high speed rate) of 240 fps.

  The imaging recording / reproducing apparatus of this example includes a normal rate shooting recording mode and a high rate shooting recording mode as imaging recording modes.

  In the normal rate shooting / recording mode, the captured image data of the captured subject image at the normal rate is recorded on a recording medium such as a magnetic tape or an optical disk.

  In the high-speed rate recording mode, in this embodiment, the high-rate imaging data of the captured subject image is compressed and temporarily recorded in the built-in large-capacity memory. The compressed image data is read from the memory at a normal rate and decompressed, and the decompressed normal rate image data is recorded on a recording medium such as a magnetic tape or an optical disk.

  That is, in the imaging recording / reproducing apparatus of this embodiment, in the same apparatus that performs imaging / recording at the normal rate, the image data at the high rate is temporarily stored in the memory, and then the current rate at the normal rate is obtained by slow reproduction. By outputting in the video output format, imaging recording and reproduction at two rates can coexist.

  In the high-speed shooting / recording mode, when the high-rate imaging data of the photographed subject image is compressed and temporarily recorded in the built-in large-capacity memory, in the following description, in the compressed recording in the high-speed shooting / recording mode Called. In the high-rate recording mode, after compression recording is completed, the compressed image data is read from the built-in large-capacity memory at the normal rate and expanded, and the expanded normal-rate image data is recorded on a recording medium such as a magnetic tape or optical disk In the following description, the recording is referred to as the medium recording in the high-rate shooting recording mode.

  FIG. 1 is a block diagram showing the system configuration of the imaging recording / reproducing apparatus of this embodiment. The imaging recording / reproducing apparatus of this embodiment includes a circuit block portion that is commonly used in the normal rate imaging recording mode and the high-speed imaging recording mode, and a circuit block portion that is used only in the high-rate imaging recording mode. .

  In FIG. 1, an image sensor unit 11, a camera signal processing circuit 12, a resolution conversion circuit 13, an image buffer / control circuit 14, a media recording processing unit 15, a display processing unit 16, and a media playback processing unit 17 Is a circuit block portion used in common in the normal rate imaging recording mode and the high-speed imaging recording mode. In this example, these circuit block portions are operated by the first clock signal CLK1.

  In addition, the system control unit 10 configured with a microcomputer, the user interface 21, the internal control signal generation circuit 22, and the clock signal generation circuit 23 are the entire system control of the imaging recording / reproducing apparatus of this embodiment. These are also circuit block portions that are commonly used in the normal rate imaging recording mode and the high-speed imaging recording mode.

  In this embodiment, a high-speed rate image compression / decompression storage processing unit 30 and a simple resolution conversion circuit 36 are provided as circuit block portions used only in the high-speed rate imaging / recording mode. The high-speed rate image compression / decompression storage processing unit 30 is provided between the output terminal and the input terminal of the resolution conversion circuit 13.

  The high-speed rate image compression / decompression storage processing unit 30 compresses image data, a scan method conversion circuit 31 having a function of performing mutual conversion between raster scan image data and block scan image data, and An image compression / decompression circuit 32 having a function of decompressing compressed image data, a large-capacity memory / control circuit 33 for storing the compressed image data, and a transfer from the first clock signal CLK1 to the second clock signal CLK2. And a clock transfer buffer circuit 35 for switching from the second clock signal CLK2 to the first clock signal CLK1.

  Each block of the high-speed rate image compression / decompression storage processing unit 30 is operated by the second clock signal CLK2 different from the first clock signal CLK1, and when the second clock signal CLK2 is not generated, Each block constituting the image compression / decompression storage processing unit 30 is in an operation stop state.

  In this embodiment, the simple resolution conversion circuit 36 is provided for displaying a monitor image at a normal rate on the electronic viewfinder in the high-speed image capturing / recording mode. The control signal from the control unit 10 is controlled so as to operate only at the time of compression recording in the high-speed imaging recording mode.

[Description of each block]
First, the control system will be described. Although not shown, the system control unit 10 is configured with a microcomputer, and includes a CPU (Central Processing Unit), a ROM storing a software processing program, a work area RAM (Random Access Memory), and others. It is supposed to include.

  The system control unit 10 generates a control signal for controlling the entire imaging recording / reproducing apparatus in accordance with a software program written in the ROM. As will be described later, the control by the system control unit 10 includes a data compression rate control process and a resolution change control process for image data during compression recording in the high-speed image capturing / recording mode.

  The system control unit 10 is connected to a user interface 21 that receives user operations for imaging and recording. Although not shown, the user interface 21 is provided with an imaging recording start / end key, a reproduction key, a mode switching key for switching the imaging recording mode, and other keys.

  When the mode switching key of the user interface 21 is operated by the user, the operation input information is notified to the system control unit 10. Upon receiving this mode switching operation input information, the system control unit 10 supplies the frame rate switching signal Ms corresponding to the imaging recording mode selected by the user operation input to the image sensor unit 11 and is selected by each unit. A control signal corresponding to the imaging recording mode is supplied.

  The internal control signal generation circuit 22 receives the control signal from the system control unit 10 and generates image data write enable signals WE_A and WE_B and read enable signals RE_A and RE_B to be described later to the image buffer / control circuit 14. In addition, various other control signals are generated.

  In this case, the internal control signal generation circuit 22 generates different write enable signals WE_A and WE_B and read enable signals RE_A and RE_B depending on the imaging recording mode. That is, the internal control signal generation circuit 22 generates and generates write enable signals WE_A and WE_B and read enable signals RE_A and RE_B corresponding to the normal rate in the normal rate imaging recording mode.

  Further, during compression recording in the high-rate imaging recording mode, the internal control signal generation circuit 22 generates and generates write enable signals WE_A and WE_B and read enable signals RE_A and RE_B corresponding to the high-speed rate, respectively. Further, at the time of media recording in the high-rate imaging recording mode, the internal control signal generation circuit 22 generates and generates write enable signals WE_A and WE_B and read enable signals RE_A and RE_B corresponding to the normal rate, respectively.

  In response to the control signal from the system control unit 10, the clock signal generation circuit 23 outputs only the clock signal CLK1 and does not output the clock signal CLK2 in the normal rate imaging recording mode. As a result, as described above, the clock signal CLK2 is not supplied to the high-speed rate image compression / decompression storage processing unit 30, so that each block of the high-speed rate image compression / decompression storage processing unit 30 does not operate.

  The clock signal generation circuit 23 receives the control signal from the system control unit 10 and outputs the clock signal CLK2 in addition to the clock signal CLK1 in the high-speed rate imaging recording mode. This is supplied to the image compression / decompression storage processing unit 30. As a result, the high-rate image compression / decompression storage processing unit 30 operates in the high-rate imaging / recording mode.

  Here, the clock signal CLK1 and the clock signal CLK2 may have the same frequency or may be different. When the frequencies are different, the frequency of the clock signal CLK2 may be higher or lower than the frequency of the clock signal CLK1. In short, the clock signal CLK2 supplied to each block of the high-speed rate image compression / decompression storage processing unit 30 is different from the clock signal CLK1 supplied to each unit other than the high-speed rate image compression / decompression storage processing unit 30, and as the clock signal CLK2 It is sufficient if a frequency suitable for the compression / expansion processing of the captured image data in this example can be set.

  Next, each block which is a processing block of captured image data will be described.

  In this example, the image sensor unit 11 includes an image sensor composed of a complementary metal oxide semiconductor (CMOS), and outputs digital image data of a captured subject image. Although not shown, a camera optical system is disposed at the front part of the image sensor unit 11.

  In this embodiment, the image sensor unit 11 outputs raster scan type captured image data at a normal rate in the normal rate shooting / recording mode according to the image rate switching signal Ms supplied thereto, and performs high-speed rate shooting / recording. In the mode, output rate switching control is performed so as to output at a high rate.

  In this embodiment, the image sensor unit 11 can be used in either case of outputting captured image data by an interlace method or a case of outputting captured image data by a non-interlace method.

  In this case, as shown in FIG. 2, in the image sensor of this example, a predetermined effective pixel area FLk of all effective pixel areas AFL is set as an effective pixel area for resolution conversion, and this effective pixel area FLk Output the image data.

  In this case, in the normal rate shooting / recording mode, the image sensor unit 11 reads and outputs image data from the effective pixel area FLk at a normal rate of 60 fps in this example, as shown in FIG. 3A. .

  On the other hand, in the high-rate shooting / recording mode, the image sensor unit 11 starts from the effective pixel area FLk in this example, as shown in FIG. 3B, N times the normal rate (N is an integer of 2 or more). For example, image data is read and output at a high speed of 240 fps, which is four times as high.

  In the case of this example, the same clock is used as a read clock for image data to the image sensor unit 11 at the normal rate and the high-speed rate. For this reason, one frame or one field of image data at a high-rate is used. The number of pixels (image data size) is 1 / N of the normal rate, for example, 1/4.

  As described above, the image rate switching signal Ms is supplied to the image sensor unit 11 from the system control unit 10 that controls the entire imaging and recording apparatus, and the image sensor unit 11 receives the received image rate switching signal Ms. Image data at the instructed rate is output and supplied to the camera signal processing circuit 12.

  The camera signal processing circuit 12 receives the captured image data from the image sensor unit 11, performs various corrections in the imaging signal processing system, and supplies the corrected image data to the resolution conversion circuit 13.

  In the normal rate imaging recording mode, the resolution conversion circuit 13 converts the normal rate image data from the camera signal processing circuit 12 into the resolution Rn of the output image data to be recorded on the recording medium 40 in this example. The resolution-converted image data is supplied to the media recording processing unit 15 and the display processing unit 16 through the image buffer of the image buffer / control circuit 14.

  The resolution conversion circuit 13 is also suitable for processing the high-rate image data from the camera signal processing circuit 12 at a high-speed rate during compression recording in the high-rate imaging recording mode (when temporarily storing in the built-in memory). The output image data to be recorded on the recording medium is converted to an arbitrary resolution Rh that does not necessarily match the resolution Rn, and the image data after the resolution conversion is supplied to the high-speed rate image compression / decompression storage processing unit 30 and the image buffer / The image data is supplied to the simple resolution conversion circuit 36 through the image buffer of the control circuit 14.

  Further, the resolution conversion circuit 13 further records from the large-capacity memory of the high-speed rate image compression / decompression storage processing unit 30 and the large-capacity memory of the control circuit 33 at the time of recording on the recording medium in the high-rate imaging mode. A process of converting the read and expanded image data into the resolution of the output image data SN recorded on the recording medium is also performed.

  In this embodiment, the resolution conversion circuit 13 executes this resolution conversion processing in cooperation with the image buffer / control circuit 14.

  That is, in this embodiment, the resolution conversion circuit 13 sequentially performs horizontal interpolation processing for generating one interpolation pixel from a plurality of pixels in the horizontal direction, and uses the processing result as intermediate data for the image buffer / control circuit 14. Store in image buffer. Then, the resolution conversion circuit 13 sequentially sequentially selects one interpolation pixel from a plurality of vertical directions in the image data as a result of the horizontal direction interpolation process read from the image buffer of the image buffer / control circuit 14. A vertical direction interpolation process is generated.

  In this embodiment, the horizontal direction interpolation process and the vertical direction interpolation process in the resolution conversion circuit 13 are performed using a horizontal digital FIR (Finite Impulse Response) filter and a vertical digital FIR filter.

  FIG. 4 is a block diagram illustrating a detailed configuration example of a portion including the resolution conversion circuit 13 and the image buffer / control circuit 14.

  As shown in FIG. 4, the resolution conversion circuit 13 includes an input selection circuit 131, a horizontal filter circuit 132 including a horizontal digital FIR filter for the horizontal direction interpolation process, and a filter supplied to the horizontal filter circuit 132. A filter coefficient arithmetic circuit 133 for outputting a coefficient, a vertical filter circuit 134 composed of a digital FIR filter in the vertical direction for the vertical direction interpolation process, and a filter coefficient arithmetic circuit for outputting a filter coefficient to be supplied to the vertical filter circuit 134 135.

  Image data from the camera signal processing circuit 12 is input to one input terminal of the input selection circuit 131 of the resolution conversion circuit 13, and a high-speed rate image compression / decompression storage processing unit is input to the other input terminal of the input selection circuit 131. Image data from 30 clock transfer buffer circuits 35 is input.

  The input selection circuit 131 is selected and controlled by a selection control signal SW generated in response to switching between the normal rate imaging recording mode and the high-speed imaging recording mode. The input selection circuit 131 receives the normal rate imaging recording. In the mode, the image data from the camera signal processing circuit 12 is output, and in the high-speed image capturing / recording mode, the image data from the clock transfer buffer circuit 35 is output and supplied to the horizontal filter circuit 132.

  Based on the mode switching control from the system control unit 10, the filter coefficient calculation circuit 133 corresponds to each of the normal rate imaging recording mode and the high-speed imaging recording mode, and in the horizontal direction. The filter coefficient corresponding to the resolution conversion is supplied to the horizontal filter circuit 132. The horizontal filter circuit 132 uses the filter coefficient sent from the filter coefficient calculation circuit 133 to execute horizontal interpolation processing according to the horizontal resolution, and the captured image data of the processing result is subjected to image buffer / control. Supply to circuit 14.

  The image buffer / control circuit 14 includes an image buffer memory 141 and an image buffer control circuit 142. In this example, the image buffer memory 141 is logically divided into a first memory area 141A and a second memory area 141B based on the address management of the image buffer control circuit 142, and is controlled by the image buffer control circuit 142. The captured image data of the processing result of the horizontal filter circuit 132 is written in the first memory area 141A.

  In this example, the first memory area 141A has a capacity corresponding to the number of lines equal to or greater than the number of taps of the vertical digital FIR filter constituting the vertical filter circuit 134.

  When image data capable of starting vertical interpolation processing is written in the first memory area 141A, the image data is read from the first memory area 141A under the control of the image buffer control circuit 142, and This is supplied to the vertical filter circuit 134.

  Based on the mode switching control from the system control unit 10, the filter coefficient calculation circuit 135 corresponds to each of the normal rate imaging recording mode and the high-speed imaging recording mode, and is in the vertical direction. The filter coefficient corresponding to the resolution conversion is supplied to the vertical filter circuit 134. The vertical filter circuit 134 uses the filter coefficient sent from the filter coefficient calculation circuit 133 to execute vertical interpolation processing according to the vertical resolution, and the resolution-converted image data of the processing result is converted into an image buffer. To the control circuit 14 and to the clock transfer buffer circuit 34 of the high-speed image compression / decompression storage processing unit 30.

  The resolution-converted image data from the vertical filter circuit 134 is written into the second memory area 141B of the image buffer 141 under the control of the image buffer control circuit 142. Then, under the control of the image buffer control circuit 142, the image data after resolution conversion is read from the second memory area 141B and supplied to the media recording processing unit 15, the display processing unit 16, and the simple resolution conversion circuit 36. .

  The storage capacity of the second memory area 141B of the image buffer 141 is desirably a capacity of one screen (one field or one frame) of the image data after resolution conversion.

  Although not shown in this embodiment, the media recording processing unit 15 is controlled by the system control unit 10 so as to operate in the normal rate imaging recording mode and in the media recording in the high rate imaging recording mode. Is done. Then, the media recording processing unit 15 performs recording modulation processing or the like for recording the resolution-converted image data at the normal rate on the recording medium 40 and then records it on the recording medium 40.

  The display processing unit 16 displays the image data after resolution conversion at the normal rate on the electronic viewfinder in order to display the recording monitor image at the time of imaging recording. In this embodiment, although not shown, the display processing unit 16 is controlled by the system control unit 10 to display an image buffer in the normal rate imaging recording mode and in the medium recording in the high rate imaging recording mode. / The resolution-converted image data output from the control circuit 14 is received as input data, converted into a display image signal, and output. In contrast, at the time of compression recording in the high-speed imaging recording mode, the image data from the simple resolution conversion circuit 36 is received as input data, converted into a display image signal, and output.

  The simple resolution conversion circuit 36 is controlled by the system control unit 10 so as to operate only during compression recording in the high-speed rate imaging recording mode (not shown). That is, at the time of compression recording in the high-speed image capturing / recording mode, the image data is obtained from the second memory area 141B of the image buffer 141 in this example at a four-times high-speed rate. Only one frame or one field out of the frames or four fields is extracted and stored in the built-in buffer to obtain the normal rate, and the extracted one frame or field is displayed at the normal rate to be displayed on the electronic viewfinder. The image data is converted into resolution image data and supplied to the display processing unit 16.

  The imaging recording / reproducing apparatus of this embodiment reads image data recorded on the recording medium 40 and supplies it to the reproduction processing unit 17 when the reproduction key of the user interface 21 is operated. The reproduction processing unit 17 demodulates the recording-modulated image data read from the recording medium 40 and supplies the demodulated image data to the display processing unit 16. The display processing unit 16 converts the demodulated image data received from the reproduction processing unit 17 into a display image signal and supplies the display image signal to a monitor display connected to the imaging recording / reproducing apparatus. Is output to the monitor output terminal.

  Next, each block constituting the high-speed rate image compression / decompression storage processing unit 30 will be described.

  The clock transfer buffer circuit 34 writes the high-rate resolution-converted image data from the resolution conversion circuit 13 to the built-in buffer by the clock signal CLK1, and the high-rate resolution-converted image data from the built-in buffer by the clock signal CLK2. Reading is performed, and clock transfer processing from the clock signal CLK1 to the clock signal CLK2 is performed. Then, the image data after resolution conversion at a high rate converted to the clock signal CLK 2 is supplied to the scan system conversion circuit 31.

  The clock transfer buffer circuit 35 writes the image data from the scan system conversion circuit 31 to the internal buffer by the clock signal CLK2, reads out the normal rate image data from the internal buffer by the clock signal CLK1, and outputs the clock signal CLK2. To the clock signal CLK1. Then, the normal rate image data changed to the clock signal CLK 1 is supplied to the resolution conversion circuit 13.

  In this case, the clock transfer buffer circuits 34 and 35 perform so-called Full / Empty control on the built-in buffer, and write / read data so that the built-in buffer is always empty. It has a mechanism to prevent the internal buffer from overflowing.

  The scan method conversion circuit 31 uses the built-in buffer memory 31M to convert raster scan image data from the resolution conversion circuit 13 into block scan image data during compression recording in the high-speed imaging recording mode. The image is output to the image compression / decompression circuit 32. The scan system conversion circuit 31 also converts the block scan system image data from the image compression / decompression circuit 32 into raster scan system image data during media recording in the high-rate imaging mode, and passes through the clock transfer buffer circuit 35. A function of supplying to the resolution conversion circuit 13 is provided.

  The scan method conversion circuit 31 has a built-in buffer memory 31M having a two-bank configuration of a bank A and a bank B, with one line of line memory as many as the number of lines necessary for block conversion of the image data size in the high-speed rate imaging recording mode. Only one of read / write operations is performed on one bank. That is, when data is written in one bank, data is read from the other bank, so that the scan method can be converted efficiently and in real time.

  For example, in the case of converting raster scan type image data into block scan type image data, as shown in FIG. 5C, a case where image compression processing is performed in units of blocks of 16 pixels × 8 lines is taken as an example. The data for 8 lines per bank is stored, and when the data for 8 lines are prepared, the image data writing bank and the reading bank are switched.

  In the case of this example, the image data writing operation to one bank of the built-in buffer memory 31M of the scan method conversion circuit 31 is performed by rasterizing data for 8 lines in units of lines as shown in FIG. This is done by writing in the scan method. Then, as shown in FIG. 5B, the scan method is converted from the raster scan method to the block scan method by reading each block of 16 pixels × 8 lines from the built-in buffer memory 31M.

  FIG. 6 is a diagram for explaining the state transition of the two banks A and B in the scan method conversion circuit 31. In FIG. In the example of FIG. 6, STG1 is in a state where the first 8 lines are processed. In this example, image data is written to bank A (the writing state is indicated as “Write” in FIG. 6), and bank B is read / written. It becomes an idle state (the idle state is denoted as “idle” in FIG. 6).

  In this state SGT1, when the image data for the first eight lines is written into the bank A, the state shifts to the state STG2, and the bank A reads the written image data (the read state is indicated as “Read” in FIG. 6). The bank B is switched from the idle state to the write state.

  Then, in this state STG2, when image data for 8 lines is written into the bank B, the process proceeds to the state STG3 on condition that all the image data has been read out from the bank A. The state is switched to the writing state, and the bank B is switched to the reading state of the written image data.

  In this state STG3, when 8 lines worth of image data is written to bank A, on the condition that all image data has been read from bank B, the state returns to state STG2, and bank A switches to the read state. Bank B is switched to the write state.

  The state STG2 and the state STG3 are alternately repeated every 8 lines until the last 8 lines of image data are processed.

  Then, when the writing of the image data for eight lines to the bank A is completed in the state STG3, when the subsequent processing lines become the last eight lines, the state shifts to the state STG4, and the bank A is switched to the reading state. Bank B is switched to the idle state. Then, when all the image data is read from the bank A, the process ends. When the next image processing starts, the above-described state transition is repeated from the first state STG1.

  Further, when the writing of the image data for eight lines to the bank B is completed in the state STG2, when the subsequent processing lines become the last eight lines, the state shifts to the state STG5, and the bank A is switched to the idle state. Bank B is switched to the read state. Then, when all the image data is read out from the bank B, the process ends. When the next image processing starts, the above-described state transition is repeated from the first state STG1.

  The state transition of FIG. 6 described above is not limited to the case where the scan method conversion circuit 31 converts raster scan image data into block scan image data, and the scan method conversion circuit 31 converts block scan image data. The same applies when converting to raster image data.

  As described above, the image compression / decompression circuit 32 compresses, for example, the MPEG system of the block unit image data from the scan system conversion circuit 31 during compression recording in the high-speed image capturing / recording mode. The image data is sent to the large capacity memory / control circuit 33 and temporarily stored in the large capacity memory.

  The image compression / decompression circuit 32 also decompresses the compressed image data read by the large-capacity memory / control circuit 33 and sends the compressed image data to the scan method conversion circuit 31 during media recording in the high-speed rate imaging / recording mode.

  In this case, the image compression / decompression circuit 32 is configured to compress the image data for each block when compressing the image data. When the compression of one block is completed, the data of the next block is processed. The acquisition request is output to the scan method conversion circuit 31.

  Here, the processing time required to compress one block varies depending on the correlation of the image data, so when the compression rate is low or when processing an image containing a lot of high frequency components, There are cases where the compression processing cannot be performed in time for the input image signal.

  Therefore, in this embodiment, at the time when data for 8 lines is written in the bank in the write state (Write) in the scan method conversion circuit 31, all the data in the bank in the read state (Read) is read. If not output, the scan method conversion circuit 31 outputs a stop signal ST for stopping the output of the resolution conversion circuit 13 to the resolution conversion circuit 13.

  Upon receiving this stop signal ST, the resolution conversion circuit 13 stops the operation of generating and outputting image data after resolution conversion by performing vertical interpolation processing, and the image buffer 141 of the image buffer / control circuit 14 Reading from one memory area 141A is stopped. However, the resolution conversion circuit 13 continues the process of interpolating the captured image data in the horizontal direction and storing it in the first memory area 141A of the image buffer 141. For this reason, the capacity of the first memory area 141A of the image buffer 141 takes into account the amount of operation for temporarily storing image data in this way.

  In the state transition of FIG. 6, states STG6 and STG7 shown with halftone dots indicate the states of the buffer memory 31M when the scan method conversion circuit 31 sends the stop signal ST to the resolution conversion circuit 13, as described above. Show.

  That is, as described above, in the state STG2, when the bank A is in the read state and the bank B is in the write state, when the write to the bank B is completed and the read from the bank A is completed, the state Transition to STG3 switches the write / read states of the two banks.

  However, when the writing to the bank B is completed in the state STG2, since the reading from the bank A is not completed, the image compression / decompression circuit 32 has not finished the compression processing of the previous image data. Therefore, when the scanning method conversion circuit 31 has not received the block data acquisition request from the image compression / decompression circuit 32, the two-bank writing state / reading state is switched as it is. Image data that has not yet been read will be overwritten.

  As described above, the scan system conversion circuit 31 of this embodiment, as described above, when the writing of the image data to one bank is completed and the reading of the image data from the other bank is not completed. Then, the stop signal ST is supplied to the resolution conversion circuit 13 to stop the input to the scan method conversion circuit 31. Then, the scan system conversion circuit 31 shifts from the state STG2 to the state STG6, the bank B for which writing has been completed is set to the idle state, and the bank A for which reading has not been completed continues the reading state.

  Then, after the reading of the image data from the bank A is completed, the scan method conversion circuit 31 shifts from the state STG6 to the state STG3, and switches the writing state / reading state of the two banks, and the resolution conversion circuit 13 The supply of the stop signal ST to is stopped.

  In the state STG3 in which the states of the two banks A and B are opposite to the state STG2, the scan system conversion circuit 31 performs the bank B when the writing to the bank A is completed in exactly the same manner as described above. When reading from is not completed, the stop signal ST is supplied to the resolution conversion circuit 13 to stop the input to the scan system conversion circuit 31. Then, the scan system conversion circuit 31 shifts from the state STG3 to the state STG7, the bank A for which writing has been completed is set to the idle state, and the bank B for which reading has not been completed continues the reading state.

  Then, after the reading of the image data from the bank A is completed, the scan method conversion circuit 31 shifts from the state STG7 to the state STG3 to switch between the writing state / reading state of the two banks and the resolution conversion circuit 13 The supply of the stop signal ST to is stopped.

  In the state STG6 or STG7, when there is no input image data to the scan method conversion circuit 31, the state transitions to the state STG5 or STG4, respectively.

  FIG. 7 is a timing chart showing the relationship between the read / write processing timing of the two banks A and B and the processing timing in the image compression / decompression circuit 32 during the compression recording described above.

  7A shows a horizontal synchronization signal, and FIG. 7B shows raster scan system captured image data sent from the resolution conversion circuit 13 to the scan system conversion circuit 31.

  As described above, in the bank A and the bank B, as shown in FIGS. 7C and 7E, the raster scan type captured image data is alternately written every 8 lines. The captured image data written in these banks A and B are alternately read out from the banks A and B as shown in FIGS. 7D and 7F, so that the block scan method is used. Is output as shown in FIG. 7I.

  At this time, as shown in FIGS. 7D and 7F, the reading from the bank A and the bank B changes according to the processing time in the image compression / decompression circuit 32, as described above. The image compression / decompression circuit 32 completes reading of the block scan type image data from one bank, and when the compression processing of the block data is completed, the next request signal as shown in FIG. Is output.

  Then, before the next request signal is generated, when writing from one bank in the writing state is completed, if reading from the bank in the other reading state is not completed, FIG. In this example, the resolution conversion circuit stop signal ST as shown in (K) becomes a high level, and this is supplied from the scan system conversion circuit 31 to the resolution conversion circuit 13, so that the resolution conversion circuit 13 has a resolution in the vertical direction. The vertical interpolation processing as the conversion processing is stopped so that the image data after resolution conversion is not output. However, since the horizontal interpolation process as the horizontal resolution conversion process does not stop, the horizontal interpolation process result is accumulated in the first memory area 141A of the image buffer 141.

  When the reading from the bank in the reading state is completed and the compression process is completed, the image compression / decompression circuit 32 outputs the next request signal as shown in FIG. As shown in FIG. 7K, the resolution conversion circuit stop signal ST becomes low level, and the resolution conversion circuit 13 starts vertical resolution conversion processing (vertical interpolation processing) and performs resolution conversion. The image data is sent to the scan system conversion circuit 31.

  Then, in the scanning method conversion circuit 31, the states of the bank A and the bank B are switched by the switching signal between the bank A and the bank B shown in FIG. 7 (L) as shown in FIGS. 7 (G) and (H). Then, conversion processing from raster scan image data to block scan image data is performed, and block scan image data is supplied to the image compression / decompression circuit 32.

  The image compression / decompression circuit 32 receives this block scan type image data, performs compression processing, and outputs image data of the compression result as shown in FIG. 7M, as shown in FIG. 7N. And stored in the large-capacity memory of the large-capacity memory / control circuit 33.

  Next, in this embodiment, the image compression / decompression circuit 32 is configured to change the compression rate in units of one frame or one field based on a change control instruction for the compression rate from the system control unit 10. Has been.

  For this reason, in this embodiment, the image compression / decompression circuit 32 sends the compressed image data size for one frame or one field to the system control unit 10 for each frame or one field. The system controller 10 receives the received 1 according to the capacity of the large capacity memory of the large capacity memory / control circuit 33, the number of image frames or fields to be recorded, and the amount of compressed data that can be continuously compressed. An operation is performed based on the compressed image data size for one frame or one field, and the compression ratio of the next image is obtained. Then, the system control unit 10 sends the obtained compression rate to the image compression / decompression circuit 32 so as to perform feedback control.

  In this embodiment, the system control unit 10 changes the resolution in the resolution conversion circuit 13 in units of one frame in addition to controlling the compression rate of the image compression / decompression circuit 32 during compression recording in the high-speed image capturing / recording mode. It is configured so that it can be controlled.

  That is, in this embodiment, image compression is performed according to the capacity of the large-capacity memory of the large-capacity memory / control circuit 33, the number of image frames or fields to be recorded, and the amount of compressed data that can be continuously compressed. In addition to rate change control, image data size change control is performed. Thus, in this embodiment, real-time recording of compressed image data at a high rate can be performed more satisfactorily.

  As described above, in this embodiment, the data compressed by the image compression / decompression circuit 32 is temporarily stored in the large-capacity memory / control circuit 33, but the compressed image data is included in the image. The size varies depending on the frequency component and the compression rate. For this reason, as shown in FIG. 8, the large-capacity memory includes the compressed image data PD, the start address, the end address, and the image compression rate for each frame or field. Header information HE including the above is recorded.

  The large-capacity memory / control circuit 33 compresses from the large-capacity memory in units of one frame or one field based on the start address and end address of the image data of the header information HE during medium recording in the high-speed imaging recording mode. Image data is read out and sent to the image compression / decompression circuit 32.

  The image compression / decompression circuit 32 performs decompression processing according to the compression rate of the image of the header information HE during media recording in the high-speed image capturing / recording mode, and sends the decompression processing result to the scan method conversion circuit 33.

[Description of Operation of Imaging Recording / Reproducing Device of Embodiment]
The operation of the imaging recording / reproducing apparatus according to the embodiment having the above-described configuration will be described below.

<Operation in normal rate imaging / recording mode>
First, the operation in the normal rate imaging / recording mode will be described. FIG. 9 is a block diagram of the imaging / recording / reproducing apparatus according to the embodiment of FIG. 1, in which the operating portion is indicated by a solid line and the non-operating portion is indicated by a broken line during imaging recording in the normal rate imaging / recording mode. FIG. 10 shows a timing chart at this time.

  That is, as described above, in the normal rate imaging / recording mode, the clock signal generation circuit 23 generates only the clock signal CLK1 by the control signal from the system control unit 10, and does not generate the clock signal CLK2. Therefore, as described above, each unit of the high-speed rate image compression / decompression storage processing unit 30 and the simple resolution conversion circuit 36 are in an inoperative state.

  When the user performs an imaging start operation when the normal rate imaging recording mode is selected, the captured image data is converted to a predetermined output resolution and recorded on the recording medium 40 as follows. The When the user completes the imaging operation, the imaging / recording operation stops.

  That is, when the user performs an imaging start operation through the user interface 21, normal-rate image data is output from the image sensor unit 11 and supplied to the camera signal processing circuit 12 as indicated by a solid line in FIG. 9. . The camera signal processing circuit 12 performs predetermined correction processing such as gamma correction on the received image data and supplies the image data to the resolution conversion circuit 13.

  In the resolution conversion circuit 13, the resolution conversion process is performed as described above so that the resolution is in accordance with the resolution specified at the normal rate from the system control unit 10.

  At this time, when the horizontal synchronizing signal of the input image data of the resolution conversion circuit 13 is as shown in FIG. 10A, the input image data as shown in FIG. , Horizontal resolution conversion is performed by horizontal interpolation processing, and image data WD_A (see FIG. 10C) as a result of the horizontal resolution conversion is an image buffer in the normal rate imaging mode from the internal control signal generation circuit 22. 141 is written into the first memory area 141A of the image buffer 141 by a write enable signal WE_A (see FIG. 10D) for the first memory area 141A of 141.

  When image data for a plurality of lines capable of starting vertical resolution conversion is written in the first memory area 141A of the image buffer 141, the image buffer 141 in the normal rate imaging mode from the internal control signal generation circuit 22 is written. By the read enable signal RE_A (see FIG. 10E) for the first memory area 141A, the image data of the horizontal resolution conversion results for a plurality of lines are simultaneously read from the first memory area 141A. Image data RD_A shown in FIG. 10F indicates image data of a horizontal resolution conversion result for a plurality of lines read at this time.

  The resolution conversion circuit 13 performs vertical resolution processing by using the image data of the horizontal resolution conversion result for the plurality of lines, thereby performing vertical resolution conversion. Then, the image data (image data after resolution conversion) WD_B (see FIG. 10G) of the vertical resolution conversion result is the second memory area of the image buffer 141 in the normal rate imaging mode from the internal control signal generation circuit 22. The data is written into the second memory area 141B of the image buffer 141 by a write enable signal WE_B (see FIG. 10H) for 141B.

  The image data of the vertical resolution conversion processing result written in the second memory area 141B is generated at the normal rate from the internal control signal generation circuit 22 that is generated in synchronization with the output horizontal synchronization signal (see FIG. 10I). The read-out enable signal RE_B (see FIG. 10K) for the second memory area 141B of the image buffer 141 in the mode is read out from the second memory area 141B and the resolution-converted image data RD_B (FIG. 10J )) Is output to the media recording processing unit 15 and the display processing unit 16.

  The media recording processing unit 15 performs recording modulation processing on the image data, and then records the image data on a recording medium such as an optical disk such as a magnetic tape or a DVD, a hard disk, or a semiconductor memory. The image data recorded at this time is converted by the display processing unit 16 into an image signal in a format for image display and supplied to the viewfinder. Thereby, the monitor image of the recorded image data is displayed on the viewfinder.

<Operation in high-speed image capturing / recording mode>
(1) <Operation during compression recording in high-speed imaging / recording mode>
FIG. 11 is a block diagram of the imaging recording / reproducing apparatus of the embodiment shown in FIG. 12 and 13 show timing charts at this time. FIG. 12 shows the horizontal synchronization timing, and FIG. 13 shows the vertical synchronization timing.

  When the high-speed rate imaging / recording mode is selected by a user operation through the user interface 21, the clock signal generation circuit 23 generates not only the clock signal CLK1 but also the clock signal CLK2 by the control signal from the system control unit 10, As described above, the respective units of the high-speed rate image compression / decompression storage processing unit 30 and the simple resolution conversion circuit 36 are in an operating state.

  If the user performs an imaging start operation through the user interface 21 while the high-speed imaging recording mode is selected, the imaging recording of this embodiment is performed until the user performs an imaging stop operation through the user interface 21. The playback device is in compression recording in the high-speed image capturing / recording mode. In this embodiment, when a user performs an imaging stop operation through the user interface 21, in this embodiment, an operation at the time of media recording in a high-speed imaging recording mode to be described later is automatically started and stored in a large-capacity memory during the compression recording. The recorded compressed image data is recorded on a recording medium (recording medium).

  At the time of compression recording in the high-speed imaging recording mode, the imaging recording / reproducing apparatus of this embodiment compresses the captured image data as follows, and the compressed image data is stored in the large-capacity memory / control circuit 33. Stored in large memory.

  That is, when a user performs an imaging start operation through the user interface 21, as shown by a solid line in FIG. 11, image data at a high rate is output from the image sensor unit 11 and supplied to the camera signal processing circuit 12. . At this time, as described above, the horizontal synchronization signal of the captured image data input to the camera signal processing circuit 12 is N times the frequency of the normal rate, and in this example, is 4 times the frequency. The camera signal processing circuit 12 performs predetermined correction processing such as gamma correction on the received image data and supplies the image data to the resolution conversion circuit 13.

  In the resolution conversion circuit 13, the resolution conversion process is performed as described above so that the resolution according to the initial setting value of the resolution at the high rate from the system control unit 10 is obtained.

  When this high-speed horizontal synchronizing signal is as shown in FIG. 12 (A) and the vertical synchronizing signal is as shown in FIG. 13 (A), FIG. 12 (B) and FIG. The input image data as shown in B) is subjected to horizontal resolution conversion by horizontal interpolation processing in the resolution conversion circuit 13, and the horizontal resolution conversion result image data WD_A (FIGS. 12C and 13C). ))) By the write enable signal WE_A (see FIGS. 12D and 13D) for the first memory area 141A of the image buffer 141 in the high-speed imaging mode from the internal control signal generation circuit 22. The data is written in the first memory area 141A of the buffer 141.

  Then, when image data for a plurality of lines capable of starting resolution conversion in the vertical direction is written in the first memory area 141A of the image buffer 141, the image buffer 141 in the high-speed imaging mode from the internal control signal generation circuit 22 is written. In response to a read enable signal RE_A (see FIGS. 12F and 13E) for the first memory area 141A, the image data of the horizontal resolution conversion results for a plurality of lines are simultaneously read from the first memory area 141A. Image data RD_A shown in FIGS. 12G and 13F shows image data of horizontal resolution conversion results for a plurality of lines read at this time.

  The resolution conversion circuit 13 performs vertical resolution processing by using the image data of the horizontal resolution conversion result for the plurality of lines, thereby performing vertical resolution conversion. Then, the image data (image data after resolution conversion) WD_B (see FIGS. 12H and 13G) of the vertical resolution conversion result is an image buffer in the high-speed rate imaging mode from the internal control signal generation circuit 22. 141 is written into the second memory area 141B of the image buffer 141 by a write enable signal WE_B (see FIGS. 12I and 13H) for the second memory area 141B of 141.

  At this time, as shown in FIG. 13 (H), at the vertical synchronization timing, the write enable signal WE_B is enabled only in one vertical cycle section of the four vertical cycle sections. For this reason, the second memory region 141B Are written at a rate of 1 (1 frame or 1 field) to 4 (4 frames or 4 fields) of the image data after resolution conversion.

  The image data of the vertical resolution conversion processing result written in the second memory area 141B has the same output horizontal synchronization signal (see FIG. 12J) and output vertical synchronization signal (FIG. 13I in the normal rate imaging recording mode). The read enable signal RE_B for the second memory area 141B of the image buffer 141 in the normal rate imaging mode from the internal control signal generation circuit 22 that is generated in synchronization with the internal control signal generation circuit 22 (see FIGS. 12L and 13K). Are read from the second memory area 141B and output to the simple resolution conversion circuit 36 as image data RD_B for compression recording monitoring (see FIGS. 12K and 13J).

  The simple resolution conversion circuit 36 converts the resolution of the image data input thereto so as to have the same resolution as the captured image signal at the normal rate, and supplies the converted image data to the display processing unit 16. This image data is converted into an image signal in a format for image display by the display processing unit 16 and supplied to the viewfinder. Thereby, the monitor image of the image data to be compressed and recorded is displayed on the viewfinder.

  At the time of compression recording in the high-speed image recording mode, the resolution-converted image data from the resolution conversion circuit 13 is supplied to the clock transfer buffer circuit 34 of the high-speed rate image compression / decompression storage processing unit 30. As described above, the resolution-converted image data supplied from the resolution conversion circuit 13 to the clock transfer buffer circuit 34 is output as the data sampling clock signal changed from the clock signal CLK1 to the clock CLK2. It is supplied to the conversion circuit 31.

  As described above, the scan method conversion circuit 31 uses two buffer memory banks to convert raster scan input image data into block scan image data while controlling the writing / reading state. Then, after waiting for an acquisition request from the image compression / decompression circuit 32, the block scan type image data is supplied to the image compression / decompression circuit 32.

  Then, as described above, when the writing to one memory bank is completed, the scanning method conversion circuit 31 does not complete the reading from the other memory bank, and the image compression / decompression circuit 32 receives the next request signal. When it has not arrived, the resolution conversion circuit stop signal ST (see FIG. 12E) is set to the high level for the resolution conversion circuit 13 to read out the image data after the horizontal resolution conversion from the first memory area 141A, and The vertical resolution conversion process is stopped, and the output of the image data after resolution conversion from the resolution conversion circuit 13 is stopped.

  As shown in FIGS. 12 (F) and 12 (I), during the period when the resolution conversion circuit stop signal ST is at a high level, the internal control signal generation circuit 22 sends image data from the first memory area. The read enable signal RE_A and the image data write enable signal WE_B to the second memory area are controlled so as not to be generated. For this reason, although not shown, the resolution conversion circuit stop signal ST is also supplied to the internal control signal generation circuit 22.

  Then, the image compression / decompression circuit 32 that has received the block scan type image data compresses the image data in units of blocks and sequentially stores it in the large capacity memory of the large capacity memory / control circuit 33. The image compression / decompression circuit 32 reports the image data amount (code amount) for one sheet to the system control unit 10 when the compression of the image data for one sheet (one frame or one filter) is completed. To do.

  Upon receiving this image data amount, the system control unit 10 determines whether or not the compression rate in the image compression / decompression circuit 32 is appropriate for continuing the real-time compression processing, and the compression rate determined according to the determination result Is sent to the image compression / decompression circuit 32. The image compression / decompression circuit 32 performs the next image data compression process at the compression rate designated by the system control unit 10.

  Further, when the system control unit 10 determines that the real-time compression process is not appropriately performed only by changing the compression rate, the image data size (image data amount) is appropriate for the resolution conversion circuit 13. A resolution change instruction for instructing to change to the resolution (specified by the system control unit 10) is sent.

  Thereafter, the resolution conversion circuit 13 performs resolution conversion on the input image data so that the resolution designated by the system control unit 10 is obtained.

  As described above, the high-speed rate image compression / decompression storage processing unit 30 controls the compression rate in the image compression / decompression circuit 32 or the resolution conversion circuit 13 so that high-speed rate image compression recording can be performed in real time. While controlling the resolution of the image data, compression of the captured image data and storage processing of the compressed captured image data in the large-capacity memory are executed. The image data is compressed and recorded until a high-speed recording stop instruction is issued by the user.

  14, 15, and 16 to 17 are flowcharts illustrating examples of operations of the scan method conversion circuit 31, the image compression / expansion circuit 32, and the system control unit 10 during compression recording in the high-speed image capturing / recording mode described above. .

  FIG. 14 is a flowchart for explaining an example of the operation of the scan method conversion circuit 31 at the time of compression recording in the high-rate imaging recording mode. As shown in FIG. 14, the scan system conversion circuit 31 first initializes a write bank and a read bank for two buffer memory banks (step S1).

  Next, raster scan type image data from the clock transfer buffer circuit 34 is written to the write bank, and the read bank is set in an idle state (step S2). Next, it is determined whether or not writing of raster scan image data to the writing bank is completed (step S3). If writing is not completed, the process returns to step S2 to continue writing. For the two buffer memory banks, the write bank and the read bank are alternated (step S4).

  Then, raster scan type image data from the clock transfer buffer circuit 34 is written to the write bank, and the written image data is read from the read bank as block scan type image data (step S5).

  Next, it is determined whether or not writing of raster scan type image data to the writing bank is completed (step S6). If writing to the writing bank is not completed, the process returns to step S5 to continue writing. If reading from the reading bank is not completed, reading of the image data is continued.

  If it is determined in step S6 that writing to the write bank is completed, it is determined whether or not an acquisition request (next request signal) for the next block data has been acquired from the image compression / decompression circuit 32 (step S7).

  In step S7, when it is determined that the next request signal has not been acquired, and therefore reading from the read bank is not completed, a resolution conversion circuit stop signal ST (high level signal) is sent to the resolution conversion circuit 13, During the high level period, the vertical resolution conversion process and the output of the image data after resolution conversion are stopped (step S8). At this time, the stop signal ST (high level signal) is also supplied to the internal control signal generation circuit 22, and during the high level period, the image data read enable signal RE_A from the first memory area and the second memory area are supplied. The image data write enable signal WE_B is controlled not to be generated.

  If it is determined in step S7 that the next request signal has been acquired, the image recording is completed based on the high-speed recording stop instruction from the user, and image data to be written from the clock transfer buffer circuit 34 is stored. It is determined whether or not it has disappeared (step S9). When it is determined that the imaging recording has not been completed yet and there is image data to be written, the process returns to the end step S4, and the write bank and the read bank are switched for the two buffer memory banks.

  If it is determined in step S9 that there is no more image data to be written, bank switching is performed to switch between the write bank and the read bank for the two buffer memory banks. However, since there is no image data to be written, The idle state is set, and the written image data is only read from the read bank (step S10).

  Then, it is determined whether or not the reading of the image data from the reading bank is completed (step S11). When it is determined that the reading is not completed, the process returns to step S10 and the reading of the image data is continued, and the reading is completed. When it is determined that the processing has been performed, the processing routine is terminated.

  Next, FIG. 15 is a flowchart for explaining an example of the operation of the image compression / decompression circuit 32 at the time of compression recording in the high-speed image capturing / recording mode.

  As shown in FIG. 15, the image compression / decompression circuit 32 acquires a block scan type image from the scan type conversion circuit 31, performs data compression, and converts the compressed image data into a large capacity memory / control circuit 33. Is stored in the large capacity memory (step S21).

  Next, the image compression / decompression circuit 32 determines whether or not the compression processing of the block data sent from the scan method conversion circuit 31 has been completed (step S22), and if not, returns to step S21, The compression process of the block data sent from the scan method conversion circuit 31 is continued.

  When it is determined in step S22 that the compression processing of the block data sent from the scan method conversion circuit 31 has been completed, a next request signal for image data is sent to the scan method conversion circuit 31 (step S23). Then, it is determined whether or not the image data compression processing for one image (one frame image) has been completed (step S24). If it is determined that the compression has not been completed, the process returns to step S21 to convert the scan method. The block scan type image data is received from the circuit 31, and the compression process is continued.

  When it is determined in step S24 that the compression processing for one frame of image data has been completed, the first address, the end address, and the compression rate at that time are used as header information HE for the 1 frame image data. The compressed image data of the frame is written into the large capacity memory (step S25; see FIG. 8).

  Then, it is determined whether or not the compression processing has ended by determining whether or not the image recording from the scan method conversion circuit 31 has been completed by the end of the imaging and recording (step S26). If so, this processing routine is terminated.

  If it is determined in step S26 that the compression process has not ended, the system control unit 10 is notified of the data size (code amount) of the compressed image data for one frame stored in the large-capacity memory (step S27). Then, the compression rate information for the image data of the next frame from the system control unit 10 is acquired (step S28), the process returns to step S21, and the processes after step S21 are repeated.

  Next, FIG. 16 and FIG. 17 that is a continuation thereof are flowcharts for explaining an example of a compression rate and resolution control operation by the system control unit 10 at the time of compression recording in the high-speed imaging recording mode.

  First, the system control unit 10 sets an initial value of the compression rate of image data in the image compression / decompression circuit 32 and sets an initial value of resolution in the resolution conversion circuit 13 (step S31).

  Next, the system control unit 10 receives the code amount from the image compression / decompression circuit 32 (step S32). Then, the code amount is analyzed, and it is determined whether or not the code amount exceeds a predetermined first value Th1 (step S33). The first predetermined value Th1 is a threshold value that determines that it is better to increase the compression rate and reduce the code amount because the code amount is too large.

  If it is determined in step S33 that the first predetermined value Th1 is exceeded, it is determined whether or not the state where the compression rate is high continues (step S34). When it is determined that the state where the compression rate is high does not continue, it is determined that the image data size (code amount) can be made lower than the first predetermined value Th1 by increasing the compression rate. A higher compression rate is set, and information on the set higher compression rate is sent to the image compression / decompression circuit 32 (step S35).

  Then, it is determined whether or not the compression processing in the high-speed rate imaging / recording mode has been completed (step S37), and if not completed, the process returns to step S32, and the processes in and after step S32 are repeated. The processing routine ends.

  Further, when it is determined in step S34 that the state where the compression ratio is high continues, if the compression ratio is further increased, the image quality is expected to deteriorate due to a compression error. Is instructed to set the resolution to reduce the image data size (step S36). This instruction may directly indicate the resolution value, or the system control unit 10 instructs the resolution conversion circuit 13 to decrease the resolution, and the resolution conversion circuit 13 decreases the resolution in accordance with the instruction. It may be.

  After step S36, the process proceeds to step S37, where it is determined whether or not the compression processing in the high-speed image capturing / recording mode has been completed. If not, the process returns to step S32, and the processes in and after step S32 are repeated. If completed, this processing routine is terminated.

  If it is determined in step S33 that the code amount does not exceed the first predetermined value Th1, it is determined whether the code amount is equal to or smaller than a second predetermined value Th2 (Th2 <Th1) (FIG. 17). Step S41). The second predetermined value Th2 is a threshold value that determines that the code amount can be increased by reducing the compression rate because the code amount is too small.

  If it is determined in step S41 that the code amount is not equal to or smaller than the second predetermined value Th2, information of the same compression rate as the current one is sent to the image compression / decompression circuit 32 (step S45), and then the step of FIG. The process jumps to S37, and the processes after step S37 are repeated.

  If it is determined in step S41 that the code amount is equal to or smaller than the second predetermined value Th2, it is determined whether or not the state where the compression rate is low continues (step S42). When it is determined that the state where the compression rate is low does not continue, it is determined that the image data size (code amount) can be made lower than the second predetermined value Th2 by reducing the compression rate. A lower compression rate is set, and information on the set lower compression rate is sent to the image compression / decompression circuit 32 (step S43).

  Then, the process jumps to step S37 in FIG. 16 to determine whether or not the compression processing in the high-speed image capturing / recording mode has been completed. If not, the process returns to step S32 to repeat the processes in and after step S32. If so, this processing routine is terminated.

  If it is determined in step S42 that the low compression rate continues, it is determined that it is better to increase the resolution in the resolution conversion circuit 13 rather than lowering the compression rate. The conversion circuit 13 is instructed to increase the resolution to increase the image data size (step S44). This instruction may directly indicate the resolution value, or the system control unit 10 instructs the resolution conversion circuit 13 to increase the resolution, and the resolution conversion circuit 13 increases the resolution according to the instruction. It may be.

  Then, after step S44, the process jumps to step S37 in FIG. 16 to determine whether or not the compression processing in the high-speed imaging recording mode has been completed. If not, the process returns to step S32, and this step S32 The subsequent processing is repeated, and if the processing is finished, this processing routine is finished.

(1) <Operations during media recording in high-speed imaging recording mode>
FIG. 18 shows, in the block of the imaging recording / playback apparatus of the embodiment of FIG. 1, a portion that operates during medium recording in the high-speed imaging recording mode, and a non-operating portion indicated by a broken line.

  When there is a high-speed imaging / recording stop instruction by the user, the system control unit 10 automatically shifts the imaging / recording / reproducing apparatus during the media recording from the compression recording in the high-rate imaging / recording mode. At this time, the system control unit 10 controls the internal control signal generation circuit 22 to output the write enable signals WE_A and WE_b and the read enable signals RE_A and RE_b corresponding to the normal rate image data. Therefore, compressed image data at a high rate is read out at a normal rate, which is equivalent to so-called slow reproduction.

  In response to a request from the image compression / decompression circuit 32, the large-capacity memory / control circuit 33 reads the compressed image data from the large-capacity memory in units of frames at a normal rate. At this time, the large-capacity memory / control circuit 33 first refers to the header HE to detect the start address and the end address of the compressed image data in the frame unit, and based on that, the compressed image data in the frame unit is detected. Is sent to the image compression / decompression circuit 32. The large capacity memory / control circuit 33 also sends the compression rate information included in the header HE to the image compression / decompression circuit 32.

  The image compression / decompression circuit 32 performs a process of decompressing and decoding the compressed image data received from the large-capacity memory / control circuit 33 according to the compression rate information received from the large-capacity memory / control circuit 33. The expanded image data is sequentially supplied to the scan method conversion circuit 31 as block scan image data.

  In the scan system conversion circuit 31, as in the case of compression recording, writing is performed to one of the two banks A and B, and reading is performed from the other, and the writing state of these two banks A and B Processing is performed by alternately switching the read state. For example, in this embodiment, as described above, since processing is performed in units of blocks each consisting of 16 pixels × 8 lines, image data for 8 lines is stored in one bank, and image data for 8 lines is prepared. At that time, the read / write bank is switched.

  Then, the scan method conversion circuit 31 writes the block scan type decompressed image data to the write state bank, and reads the image data from the read state bank by the raster scan method. Perform the conversion.

  By this scan method conversion, the decompressed image data converted to the raster scan method is supplied to the clock transfer buffer circuit 35, and the sampling clock of the image data is changed from the clock signal CLK2 to the clock signal CLK1.

  The expanded image data from the clock transfer buffer circuit 35 is supplied to the resolution conversion circuit 13. At this time, as shown in FIG. 4, the input selection circuit 131 of the resolution conversion circuit 13 receives a selection control signal SW from the internal control signal generation circuit 22 from the clock transfer buffer circuit 35 supplied to the other input terminal. The expanded image data is switched to the selected state. Accordingly, the decompressed image data from the clock transfer buffer circuit 35 is supplied to the horizontal filter circuit 131 of the resolution conversion circuit 13.

  At this time, the resolution conversion circuit 13 is supplied with resolution control information from the system control unit 10 so as to obtain the resolution at the time of media recording in the high-speed imaging recording mode. As a result, for the horizontal filter circuit 132 for horizontal resolution conversion in the resolution conversion circuit 13, a filter coefficient that has the same horizontal resolution as that of the normal-rate image data from the image data of the high-speed rate is converted to the filter coefficient arithmetic circuit. 133.

  The image data that has been subjected to the horizontal resolution conversion as a result of the interpolation processing in the horizontal filter circuit 131 is written in the first memory area 141A of the image buffer 141. The image data written in the first memory area 141A is read out and supplied to the vertical filter circuit 134 as a vertical resolution conversion circuit.

  Then, the vertical filter coefficient calculation circuit 135 supplies a filter coefficient that gives the same vertical resolution as the normal rate image data from the high-rate image data to the vertical filter circuit 134. Normal rate image data in the rate imaging recording mode is obtained and written into the second memory area 141B.

  In this example, the image data written in the second memory area 141B is read out with a delay of one frame, and is recorded on the recording medium 40 through the media recording processing unit 15. Also, the image data read from the second memory area 141B is supplied to the viewfinder through the display processing unit 16. The monitor display image at this time is a slow reproduction image, as described above, because a high-rate image is reproduced at a normal rate.

<Operation in playback mode>
The imaging recording / playback apparatus of this embodiment has a playback mode. When a user gives a playback instruction through the user interface 21, image data recorded on the recording medium 40 is read and supplied to the playback processing unit 17. The playback processing unit 17 performs playback processing as all normal rate image data, and supplies the playback processing image signal to the display processing unit 16.

  The display processing unit 16 supplies reproduced image data to the viewfinder and displays the reproduced image. Alternatively, the reproduced image data is supplied to an external monitor display device through an image output terminal and displayed on the display screen.

  At this time, the image data recorded in the normal rate imaging recording mode is reproduced at a normal speed, but the image data recorded in the high rate imaging recording mode is always a slow reproduction image.

[Other variations]
In the above embodiment, at the time of image compression recording in the high-speed rate recording mode, the system control unit 10 determines the image data compression rate and the resolution in the resolution conversion circuit 13 according to the code amount from the image compression / decompression circuit 32. However, it is of course possible to change only the compression rate or only the resolution.

  Further, the frequency of the clock signal CLK2 may be controlled instead of the compression rate and resolution of the image data. Further, the frequency control of the clock signal CLK2 and the compression rate and / or resolution control may be combined.

  Rather than controlling the compression rate, resolution, and frequency of the clock signal CLK2 according to the code amount from the image compression / decompression circuit 32, the image data is compressed according to the number of appearances of the resolution conversion circuit stop signal ST. The rate, resolution, and frequency of the clock signal CLK2 may be controlled. Further, the compression rate of image data, the resolution, and the frequency of the clock signal CLK2 may be controlled based on the combination of the code amount and the resolution conversion circuit stop signal ST.

  In the above-described embodiment, the present invention is applied to an imaging recording apparatus that assumes a case in which normal-rate image data and a high-rate image rate are output from the image sensor. It goes without saying that the image processing apparatus according to the invention is not limited to such image data from the image sensor, but can be applied to all cases where normal-rate image data and high-rate image rates are input.

It is a block diagram which shows the structural example of embodiment of the imaging recording device by this invention. It is a figure used in order to demonstrate the image sensor of embodiment of FIG. It is a figure used in order to demonstrate the image sensor of embodiment of FIG. It is a block diagram of the detailed structural example of the one part block of embodiment of FIG. It is a figure for demonstrating the scanning system conversion of image data. It is a figure for demonstrating the usage condition of the buffer memory in the scanning system conversion circuit of the imaging recording device of embodiment of FIG. FIG. 7 is a timing chart for explaining how the buffer memory is used in the scan method conversion circuit of FIG. 6. FIG. It is a figure for demonstrating the recording information of the compression image data in embodiment of FIG. It is a figure for demonstrating operation | movement of the normal rate imaging recording mode in the imaging recording device of embodiment of FIG. 3 is a timing chart for explaining the operation in a normal rate imaging / recording mode in the imaging / recording apparatus of the embodiment of FIG. 1. It is a figure for demonstrating the operation | movement at the time of the compression recording of the high-speed rate imaging recording mode in the imaging recording device of embodiment of FIG. 3 is a timing chart for explaining an operation at the time of compression recording in a high-speed image capturing / recording mode in the image capturing / recording apparatus of the embodiment of FIG. 1. 3 is a timing chart for explaining an operation at the time of compression recording in a high-speed image capturing / recording mode in the image capturing / recording apparatus of the embodiment of FIG. 1. 2 is a flowchart for explaining the operation of a main part during compression recording in a high-speed image capturing / recording mode in the image capturing / recording apparatus of the embodiment of FIG. 1. 2 is a flowchart for explaining the operation of a main part during compression recording in a high-speed image capturing / recording mode in the image capturing / recording apparatus of the embodiment of FIG. 1. 2 is a flowchart for explaining the operation of a main part during compression recording in a high-speed image capturing / recording mode in the image capturing / recording apparatus of the embodiment of FIG. 1. 2 is a flowchart for explaining the operation of a main part during compression recording in a high-speed image capturing / recording mode in the image capturing / recording apparatus of the embodiment of FIG. 1. It is a figure for demonstrating the operation | movement at the time of the medium recording of the high-speed imaging recording mode in the imaging recording device of embodiment of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Image sensor, 13 ... Resolution conversion circuit, 14 ... Image buffer / control circuit, 15 ... Media recording part, 16 ... Display processing part, 21 ... User interface, 22 ... Internal control signal generation circuit, 23 ... Clock signal generation circuit , 30: High-speed rate image compression / decompression storage processing unit, 31: Scan method conversion circuit, 32 ... Image compression / decompression circuit, 33 ... Large capacity memory / control circuit, 34, 35 ... Clock transfer buffer circuit, 40 ... Recording medium

Claims (14)

A first buffer memory;
Converting the resolution of raster-scan input image data that is continuously input at a rate at which the number of frames or fields per unit time is a predetermined number, the intermediate data of the resolution conversion process Resolution conversion means for temporarily storing in the first buffer memory, reading the intermediate data stored in the first buffer memory, performing a predetermined process, and obtaining final image data after resolution conversion;
Scan method conversion means for converting the image data after resolution conversion from the resolution conversion means from raster scan method to block scan image data;
Image compression means for receiving the block scan system image data from the scan system conversion means in units of a predetermined amount and performing image data compression processing;
Storage means for storing the image data compressed by the image compression means in a storage unit;
With
After the image compression processing for the block scan type image data of the predetermined amount unit obtained from the scan type conversion unit is completed, the image compression unit stores the block scan type image data in the scan type conversion circuit. Is a request for acquisition,
The scan method conversion unit includes a second buffer memory that temporarily holds the image data of the raster scan method in order to perform processing for converting the scan method, and requests for acquisition of the image data from the image compression unit And when it is determined that the compression processing in the image compression means is not in time for the resolution-converted image data from the resolution conversion means in accordance with the usage status of the second buffer memory. A control signal for stopping output of the image data after resolution conversion is supplied to the means. The image processing apparatus according to claim 1.
Clock conversion means for converting the image data after resolution conversion from the resolution conversion means into data of a second clock different from the first clock for the resolution conversion means;
The image processing apparatus, wherein the scan method conversion unit, the image compression unit, and the storage unit operate with the second clock. The image processing apparatus according to claim 1.
The image compression means performs compression with a variable amount of data after compression per predetermined amount of data, and a compression rate is variable, according to the data amount of the image data after compression, An image processing apparatus in which a compression rate is set. The image processing apparatus according to claim 3.
Image processing comprising: control means for receiving the information on the amount of data after compression from the image compression means, setting the compression ratio, and supplying the information on the set compression ratio to the image compression means apparatus. The image processing apparatus according to claim 1.
The image compression means performs compression with a variable amount of data after compression per predetermined data amount, and supplies the data amount of the image data after compression to the control means,
The control means sends a control signal for changing the resolution of the image data after resolution conversion to the resolution conversion means according to the data amount of the compressed image data from the image compression means. An image processing apparatus characterized by being supplied. The image processing apparatus according to claim 1.
The input image data includes image data of a first rate of a raster scan method in which the number of frames or fields per unit time is a first predetermined number, and the number of frames or fields per unit time is the first number. The image of the first rate according to the user selection from the image sensor that switches and outputs one of the second predetermined number of image data of the raster scan method that is larger than the predetermined number of 1 Data or image data of the second rate,
A third buffer memory for temporarily storing the resolution-converted image data from the resolution conversion means;
The scan method conversion unit, the image compression unit, and the storage unit are controlled to operate only when the image data of the second rate is output from the image sensor,
When the image data at the first rate is output from the image sensor, the image data after resolution conversion from the resolution conversion means is temporarily stored in the third buffer memory and then read and recorded. Data recorded on the medium,
When the image data of the second rate is output from the image sensor, the image data after the resolution conversion from the resolution conversion unit is converted from the raster scan type image data to the block scan type by the scan type conversion unit. An image processing apparatus, wherein the image data compression processing is performed by the image compression means, and is stored in the storage unit. The image processing apparatus according to claim 6.
When the image data of the second rate is output from the image sensor, the image data from the third buffer memory is converted into the image data of the first rate and output for monitoring. An image processing apparatus comprising: a resolution conversion unit. The image processing apparatus according to claim 6.
The compressed image data stored in the storage unit is read and decompressed at the first rate, and the decompressed image data is converted from the block scan image data to raster scan image data, The resolution conversion means includes means for inputting instead of the input image data,
The resolution conversion means converts the input image data instead of the input image data into the image data after resolution conversion, and then outputs the image data through the third buffer memory. Processing equipment. Image data of the first rate of the raster scan method in which the number of frames or fields per unit time is a first predetermined number, and the number of frames or fields per unit time is more than the first predetermined number An image sensor that switches and outputs one of the second predetermined number of image data of the raster scan method, which is a large second predetermined number, according to a user's switching selection;
Accepting a selection input of a first mode for outputting the image data of the first rate from the image sensor and a second mode for outputting the image data of the second rate, and according to the selection input Mode switching means for switching to the mode;
A first buffer memory and a second buffer memory for an image buffer;
Converting the resolution of the first rate image data or the second rate image data from the image sensor, temporarily storing intermediate data of the resolution conversion processing in the first buffer memory Resolution conversion means for reading the intermediate data stored in the first buffer memory, performing a predetermined process, obtaining final image data after resolution conversion, and storing the image data in the second buffer memory;
Recording means for recording the image data through the second buffer memory on a recording medium in the first mode;
A scan method that is controlled so as to operate only in the second mode, and that converts the image data after resolution conversion from the resolution conversion means from raster scan method to block scan method image data. Conversion means;
An image that is controlled so as to operate only in the second mode, and that receives image data of the block scan method from the scan method conversion means in units of a predetermined amount and performs image data compression processing Compression means;
A storage unit that is controlled to operate only in the second mode, and stores the image data compressed by the image compression unit in a storage unit;
With
After the image compression processing for the block scan type image data of the predetermined amount unit obtained from the scan type conversion circuit is completed, the image compression unit sends the block scan type image data to the scan type conversion unit. Is a request for acquisition,
The scan method conversion means includes a third buffer memory for temporarily storing the raster scan image data to perform processing for converting the scan method, and a request for acquiring the image data from the image compression means. And when it is determined that the compression processing in the image compression unit is not in time for the resolution-converted image data from the resolution conversion unit according to the usage status of the third buffer memory. A control signal for stopping output of the image data after resolution conversion is supplied to the means. The imaging recording apparatus according to claim 9, wherein
Clock conversion means for converting the image data after resolution conversion from the resolution conversion means into data of a second clock different from the first clock for the resolution conversion means;
The scan method conversion unit, the image compression unit, and the storage unit operate with the second clock,
In the first mode, the second clock is stopped, and the operations of the scan method conversion unit, the image compression unit, and the storage unit are stopped. The imaging recording apparatus according to claim 9, wherein
When the image data of the second rate is output from the image sensor, the image data from the second area of the image buffer memory is converted into the image data of the first rate for monitoring. An image recording apparatus comprising: a second resolution converting means for outputting as the above. The imaging recording apparatus according to claim 9, wherein
The compressed image data stored in the storage unit is read and decompressed at the first rate, converted from the block scan type image data to raster scan type image data, and sent to the resolution conversion unit. And means for inputting instead of the input image data,
The resolution conversion means converts the input image data instead of the input image data into the image data after resolution conversion, and then temporarily stores the image data after resolution conversion in the second buffer memory. Store and
The image recording apparatus, wherein the image data temporarily stored in the second buffer memory is output as a reproduced image or recorded on a recording medium. An image processing method in which raster scan type input image data, which is continuously input at a rate with a predetermined number of frames or fields per unit time, is compressed and stored in a storage means,
The resolution conversion means is a step of converting the resolution of the input image data, temporarily storing the intermediate data of the resolution conversion processing in the first buffer memory, and the intermediate data stored in the first buffer memory A resolution conversion step of reading and performing predetermined processing to obtain final resolution-converted image data;
A scan method conversion unit that converts the resolution-converted image data obtained in the resolution conversion step from raster scan method to block scan method image data,
The image compression means receives the block scan type image data obtained by the conversion in the scan type conversion step in a predetermined amount unit, performs an image data compression process, and the compressed image data is a compressed image data storage unit. A process of storing in
With
The image compression unit requests the scan method conversion unit to acquire the block scan type image data after the image compression process for the block scan type image data in the predetermined amount unit is completed. And
The scan method conversion unit temporarily stores the raster scan method image data in a second buffer memory to perform processing for converting the scan method, and requests acquisition of the image data from the image compression unit. And when it is determined that the compression processing in the image compression means is not in time for the resolution-converted image data from the resolution conversion means in accordance with the usage status of the second buffer memory. A control instruction for stopping output of the image data after the resolution conversion is supplied to the means. Image data of the first rate of the raster scan method in which the number of frames or fields per unit time is a first predetermined number, and the number of frames or fields per unit time is more than the first predetermined number An image sensor is provided that switches and outputs one of the second predetermined number of raster scan type image data, which is a large second predetermined number, according to a user's switching selection, and from the image sensor to the first rate. Mode switching means for receiving a selection input of the first mode for outputting the image data of the second and the second mode for outputting the image data of the second rate and switching the mode according to the selection input. In the imaging recording method in the imaging recording apparatus,
When the first mode is selected,
The resolution conversion means converts the resolution of the image data of the first rate image data from the image sensor into the resolution of the output image data to be recorded on the recording medium, and the intermediate data of the resolution conversion processing is converted into the first data. The resolution for temporarily storing in the first buffer memory, reading the intermediate data stored in the first buffer memory, performing predetermined processing, obtaining final resolution-converted image data, and storing it in the second buffer memory Conversion process;
A recording step in which recording means records the image data through the second buffer memory on the recording medium;
As well as
When the second mode is selected,
The resolution conversion unit converts the resolution of the image data of the second rate image data from the image sensor to a predetermined resolution, and temporarily stores the intermediate data of the resolution conversion process in the first buffer memory. The intermediate data stored in the first buffer memory is read and subjected to a predetermined process to obtain final image data after resolution conversion, and the image data after resolution conversion is converted into the second mode. A resolution conversion step for supplying to the scanning method conversion means controlled to operate only when,
The scan method conversion means converts the resolution-converted image data from the resolution conversion means from raster scan method to block scan image data, and converts the converted block scan image data to the second image data. A scanning method conversion step to be supplied to the image compression means controlled to operate only in the mode of
An image in which the image compression means receives the block scan type image data from the scan type conversion means in units of a predetermined amount, performs image data compression processing, and stores the compressed image data in a compressed image data storage unit A compression process;
Run
And in the second mode,
In the image compression step, after the image compression processing for the block scan type image data of the predetermined amount unit obtained from the scan type conversion unit is completed, the image compression unit sends the block to the scan type conversion unit. This is a request for acquisition of scan-type image data,
In the scan method conversion step, the scan method conversion means includes a third buffer memory that temporarily holds the raster scan image data in order to perform processing for converting the scan method, and from the image compression means Depending on the request for acquisition of the image data and the usage status of the third buffer memory, the compression processing in the image compression unit may not be in time for the image data after resolution conversion from the resolution conversion unit. A control signal for stopping output of the image data after resolution conversion is supplied to the resolution conversion means when it is determined.

Images