JP2007116677A - Cyclic redundancy check circuit, semiconductor device having cyclic redundancy check circuit, electronic device having the semiconductor device, and wireless communication system using the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CRC circuit with a simple configuration which is of low power consumption. <P>SOLUTION: The CRC circuit comprises a first shift register to a p-th shift register, a first EXOR to a (p-1)-th EXOR, and a switch circuit. A data signal, a select signal and an output of a final stage of the p-th shift register are inputted to the switch circuit, and it selects a first signal or a second signal according to the select signal and outputs the signal. An output of the switch circuit is inputted to a first stage of the first shift register. An output of a final stage of an r-th (r is a smaller natural number than p) shift register and the output of the switch circuit are inputted to an r-th EXOR. An output of the r-th EXOR is inputted to a first stage of an (r+1)-th shift register. The first signal is obtained by performing an exclusive-or operation between a data signal and an output of a final stage of the p-th shift register. The second signal is a logical value of "0". <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a cyclic redundancy check circuit. The present invention also relates to a semiconductor device having a cyclic redundancy check circuit. Furthermore, the present invention relates to an electronic device having the semiconductor device. The present invention also relates to a wireless communication system using the semiconductor device.

  There are semiconductor devices that transmit and receive data signals by wireless communication, such as wireless tags (IC tags, IC chips, RF (Radio Frequency) tags, RFID (Radio Frequency Identification) tags, electronic tags, and transponders). In a device that transmits and receives data signals, cyclic redundancy checking (CRC) is performed in order to check whether the data signals are correctly transmitted. In the cyclic redundancy check, a polynomial (referred to as a code polynomial) with each bit of the received data signal as a coefficient is divided by a predetermined generator polynomial, and a coefficient of a remainder polynomial (residue polynomial) (hereinafter referred to as a CRC code) is calculated. . By comparing the CRC code with a predetermined signal, it is determined whether the received data signal is correct.

  As a circuit for performing a cyclic redundancy check (cyclic redundancy check circuit), a configuration having a plurality of delay elements and a plurality of exclusive OR circuits has been proposed (see Patent Document 1).

  The configuration of this cyclic redundancy check circuit will be described with reference to FIG. In FIG. 12, the cyclic redundancy check circuit includes delay elements S0 to S15 and exclusive OR circuits EXOR0 to EXOR2 for calculating exclusive OR of two input signals.

  The delay elements S0 to S4 output signals that are sequentially shifted in synchronization with the clock signal 181. That is, the delay elements S0 to S4 constitute a first shift register (denoted as SR1 in FIG. 12). The delay elements S5 to S11 also output signals shifted in order in synchronization with the clock signal 181. That is, the delay elements S5 to S11 constitute a second shift register (denoted as SR2 in FIG. 12). The delay elements S12 to S15 also output signals that are sequentially shifted in synchronization with the clock signal 181. That is, the delay elements S12 to S15 constitute a third shift register (denoted as SR3 in FIG. 12). The output of the exclusive OR circuit EXOR0 is input to the delay element S0 of the first shift register SR1. The output of S4 of the first shift register and the output of the exclusive OR circuit EXOR0 are input to the exclusive OR circuit EXOR1. The output of the exclusive OR circuit EXOR1 is input to S5 of the second shift register. The output of S11 of the second shift register and the output of the exclusive OR circuit EXOR0 are input to the exclusive OR circuit EXOR2. The output of the exclusive OR circuit EXOR2 is input to S12 of the third shift register. The exclusive OR circuit EXOR0 receives the data signal 182 and the output of S15 of the third shift register.

The cyclic redundancy check circuit configured as described above calculates a 16-bit CRC code corresponding to the input data signal 182 and outputs the CRC code in parallel from out_1 to out_16.
JP-A-10-107650

  When a data signal is received, a CRC code corresponding to the data signal is calculated, the CRC code is output in parallel, and the received data signal is correct by comparing the CRC code with a predetermined signal. Or not. On the other hand, when transmitting a data signal, it is necessary to calculate a CRC code corresponding to the data signal and add the CRC code to the data signal serially.

  However, the conventional cyclic redundancy check circuit can only output the CRC code in parallel and cannot output it serially. This is because the signal changes when a signal is transmitted from a certain shift register to the next shift register via an exclusive OR circuit, so that the signals stored in the delay elements of all the shift registers are shifted and output. Because you can't.

  In the conventional cyclic redundancy check circuit, in order to serially output the CRC code stored in each delay element of the shift register, a circuit that temporarily holds the CRC code output in parallel and sequentially outputs it is necessary. For example, it is necessary to provide a shift register or the like separately from the shift register that calculates the CRC code. For this reason, the configuration of the cyclic redundancy check circuit is complicated, resulting in an increase in the size of the circuit. Furthermore, as the circuit becomes larger, power consumption increases.

  In view of the above situation, when a data signal is received, a CRC code corresponding to the data signal can be calculated, the CRC code can be output in parallel, and the CRC code can be compared with a predetermined signal. When transmitting a data signal, a cyclic redundancy check circuit capable of calculating a CRC code corresponding to the data signal and sequentially outputting the CRC code serially, with a simpler configuration and less power consumption It is an object to provide a cyclic redundancy check circuit.

  In order to solve the above-described problems, the following configuration is characterized.

  The cyclic redundancy check circuit includes a first shift register to a p-th shift register (p is a natural number greater than 1), a first exclusive-OR circuit to a (p−1) -exclusive OR circuit, And a switching circuit.

  Each of the first to p-th shift registers has one stage or a plurality of stages connected in cascade, and delays an input signal in synchronization with a clock signal and outputs the delayed signal from each stage. That is, each of the shift registers from the first shift register to the p-th shift register has one stage or a plurality of stages connected in cascade. Each of the one stage or the plurality of stages outputs the input signal after delaying the input signal. Output of signals from the one stage or the plurality of stages is performed in synchronization with a clock signal. The first exclusive OR circuit to the (p-1) th exclusive OR circuit calculate the exclusive OR of the two input signals. The switching circuit receives a data signal, a select signal, and an output of the last stage of the p-th shift register, and switches and outputs one of the first signal and the second signal according to the select signal. The output of the switching circuit is input to the first stage of the first shift register. In the first to p-th shift registers, the output of the last stage of the r-th shift register (r is a natural number smaller than p) and the output of the switching circuit are sent to the r-th exclusive OR circuit. Entered. The output of the rth exclusive OR circuit is input to the first stage of the (r + 1) th shift register.

  The first signal is an exclusive OR of the data signal and the output of the final stage of the p-th shift register. The second signal is “0”. Here, “0” indicates that the digital signal has a logical value of “0”. Note that when the second signal is input to the r-th exclusive OR circuit, the second signal is output from the r-th exclusive OR circuit as the output of the last stage of the r-th shift register. Any signal that equalizes may be used.

  Further, the cyclic redundancy check circuit may include a determination circuit and a first memory circuit. The first shift register to the p-th shift register each include s (s is a natural number greater than or equal to p) second storage circuits that store 1-bit signals. The signals stored in the s second storage circuits are input in parallel to the determination circuit as s-bit outputs. The determination circuit outputs a different signal depending on whether or not the s-bit output matches the predetermined signal stored in the first memory circuit.

  The cyclic redundancy check circuit configured as described above has a switching circuit to calculate a CRC code corresponding to a data signal without adding a new shift register or the like, and to output the CRC code in parallel. The CRC code corresponding to the signal can be calculated, and the case where the CRC code is serially output sequentially can be switched. Thus, it is possible to provide a cyclic redundancy check circuit with a simpler configuration and less power consumption.

  Therefore, a semiconductor device using the cyclic redundancy check circuit can be reduced in size and saved in power. Further, an electronic device using the semiconductor device can be reduced in size and power can be saved. In particular, in the case where the semiconductor device is a wireless chip, the chip can be reduced in size and power can be saved. Therefore, the types of objects on which the chip can be installed are increased, and application of a wireless communication system using the chip is applied. The range can be expanded.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numeral is used in different drawings. Further, in the present invention, being connected is synonymous with being electrically connected. Therefore, another element or the like may be disposed between them.
(Embodiment 1)

  In the first embodiment, the configuration and operation of the cyclic redundancy check circuit of the present invention will be described with reference to FIGS.

  FIG. 1 shows the configuration of a cyclic redundancy check circuit. The cyclic redundancy check circuit includes a first shift register (denoted as SR1 in FIG. 1) to a p-th shift register (p is a natural number greater than 1) (denoted as SRp in FIG. 1), a first exclusive register. A logical sum circuit (denoted as EXOR1 in FIG. 1) to (p-1) th exclusive OR circuit (denoted as EXOR (p-1) in FIG. 1) and a switching circuit 101 are included.

  Each of the first to p-th shift registers SR1 to SRp has one stage or a plurality of stages connected in cascade, and delays the input signal in synchronization with the clock signal and outputs it from each stage. To do. That is, each of the first shift register SR1 to the p-th shift register SRp has one stage or a plurality of stages connected in cascade. Each of the one stage or the plurality of stages outputs the input signal after delaying the input signal. Output of signals from the one stage or the plurality of stages is performed in synchronization with a clock signal.

  Here, a configuration example of each of the first shift register SR1 to the p-th shift register SRp will be described with reference to FIG. FIG. 5A is a diagram illustrating a configuration of any one shift register (indicated as SR in FIG. 5) among the first shift register SR1 to the p-th shift register SRp. The shift register SR has first to u-th (u is a natural number) stages, and an input signal 153 and a clock signal 152 are input thereto. The input signal 153 is input to the first stage, and the output of the previous stage is input to the subsequent stage. Cascade connection means that each stage is connected so that the output of the previous stage is input to the subsequent stage. Each of the first to u-th stages can be configured with a delay element having a 1-bit storage circuit. A D-type flip-flop circuit or the like can be used as the delay element.

  Note that in FIG. 5A, the shift register SR having a plurality of stages is shown; however, a shift register having only one stage may be used. That is, at least one of the first shift register SR1 to the p-th shift register SRp may be a shift register having only one stage.

  FIG. 5B shows a timing chart showing a method for driving the shift register having the structure shown in FIG. As shown in FIG. 5B, the shift register SR delays the input signal 153 in synchronization with the clock signal 152, and sequentially outputs the first to u-th stages. In FIG. 5, outputs from the respective stages are denoted by out_1 to out_u. Out_1 to out_u become the output 151 of the shift register SR. In the circuit illustrated in FIG. 5, an example is shown in which the signal output to the subsequent stage and the signal output from the shift register SR are equal at any stage, but the present invention is not limited to this. In any stage, the signal that is output from the shift register SR may be a signal that is inverted with respect to the signal that is output to the subsequent stage.

  Reference is again made to FIG. The first exclusive OR circuit EXOR1 to the (p−1) th exclusive OR circuit EXOR (p−1) calculate the exclusive OR of the two input signals. The switching circuit 101 receives the data signal 131, the select signal 132, and the output 103 of the final stage of the p-th shift register SRp, and switches one of the first signal and the second signal according to the select signal 132. Output as output 102. The output 102 of the switching circuit 101 is input to the first stage of the first shift register SR1. The output of the final stage of the r-th (r is a natural number smaller than p) shift register SRr and the output 102 of the switching circuit 101 are input to the r-th exclusive OR circuit EXORr. The output of the rth exclusive OR circuit EXORr is input to the first stage of the (r + 1) th shift register SR (r + 1).

  The first signal is an exclusive OR of the data signal 131 and the output 103 of the final stage of the p-th shift register SRp. The second signal is “0”. Here, “0” indicates that the digital signal has a logical value of “0”. Note that when the second signal is input to the r-th exclusive OR circuit EXORr, the second signal is output from the r-th exclusive OR circuit EXORr to the final stage of the r-th shift register SRr. Any signal may be used as long as it is equal to the output of.

  While the first signal is output from the output 102 of the switching circuit 101, the cyclic redundancy check circuit outputs the s-bit CRC code in parallel (the s-bit output 104 in FIG. 1). On the other hand, while the second signal is output from the output 102 of the switching circuit 101, the first shift register SR1 to the pth shift register SRp collectively operate as one shift register, and the cyclic redundancy check circuit. Outputs the s-bit CRC code as output 103 serially.

  A specific configuration example of the switching circuit 101 will be described with reference to FIG. The switching circuit 101 includes an exclusive OR circuit EXOR 111 and a selector 112. The exclusive OR circuit EXOR 111 receives the output 103 and the data signal 131, calculates the exclusive OR of the output 103 and the data signal 131, and inputs the exclusive OR to the selector 112. The selector 112 switches the output of the exclusive OR circuit EXOR 111 and the data signal 131 in accordance with the select signal 132 and outputs it as the output 102.

  The data signal 131 and the select signal 132 will be described with reference to FIG. In the description, FIG. 1 and FIG. 2 are also referred to. The selector 112 outputs a signal input to IN1 from Y when the select signal 132 input to S has a logical value of “1”, and a signal input to IN2 when the select signal 132 is “0”. Are output from Y.

  The data signal 131 includes a reception data signal, a transmission data signal, and a signal “0” when neither the reception data signal nor the transmission data signal exists.

  As shown in FIG. 3, the cyclic redundancy check circuit (CRC circuit) calculates a CRC code corresponding to the received data signal after a serial received data signal is input as the data signal 131 (in FIG. 3, (Period indicated by TC1). When the calculation of the CRC code is completed, the calculation result, that is, the obtained CRC code is output in parallel (period indicated by TO1 in FIG. 3). An error in the received data signal is checked using the CRC code output in parallel. In TC1 and TO1, the select signal 132 is “1”.

  Next, after a serial transmission data signal is input as a data signal, the cyclic redundancy check circuit (CRC circuit) calculates a CRC code corresponding to the transmission data signal (period indicated by TC2 in FIG. 3). When the calculation of the CRC code is completed, the calculation result, that is, the obtained CRC code is serially output (period indicated by TO2 in FIG. 3). The serially output CRC code is added to the transmission data signal. In TO2, the select signal 132 is “0”.

  In FIG. 3, the select signal 132 is set to “1” in all periods other than TO2, but the present invention is not limited to this. As long as the select signal 132 is “1” for TC1 and TO1 and “0” for TO2, the other period may be “1” or “0”.

  In this way, the cyclic redundancy check circuit (CRC circuit) calculates the CRC code corresponding to the received data signal, outputs the CRC code in parallel, calculates the CRC code corresponding to the transmission data signal, and calculates the CRC code. Can be switched between serial output and serial output.

  Further, as shown in FIG. 1, the cyclic redundancy check circuit can include a determination circuit 105. The first shift register SR1 to the p-th shift register SRp have a configuration in which s (s is a natural number greater than or equal to p) storage circuits that store 1-bit signals. Here, referring to FIG. 5, the total number of stages of the first shift register SR1 to the p-th shift register SRp corresponds to s. As shown in FIG. 1, signals stored in the s storage circuits are input in parallel to the determination circuit 105 as s-bit outputs 104. The s-bit output 104 is a CRC code corresponding to the received data signal. The determination circuit 105 outputs a different signal as the output 106 depending on whether or not the s-bit output matches the predetermined s-bit signal 144. The predetermined s-bit signal 144 is stored in a storage circuit different from the s storage circuits. For example, it is stored in a mask ROM or the like.

Thus, the cyclic redundancy check circuit (CRC circuit) calculates the CRC code corresponding to the received data signal, outputs the CRC code in parallel, and determines whether the CRC code matches a predetermined signal. Can do.
(Embodiment 2)

  In this embodiment, the configuration of the determination circuit 105 in FIG. 1 will be described more specifically with reference to FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

  4A to 4D and FIGS. 11A to 11D are configuration examples of the determination circuit 105. FIG.

  4A, the determination circuit 105 includes s matching circuits (indicated as EXNOR147 in FIG. 4) and an AND circuit (indicated as AND148 in FIG. 4). It is determined by the s matching circuits (EXNOR 147) whether or not the s-bit output 104 and the predetermined s-bit signal 144 match each bit. That is, one matching circuit (EXNOR 147) corresponds to the v-th bit (v is a natural number between 1 and s). The matching circuit (EXNOR 147) receives the v-th bit signal of the s-bit output 104 and the v-th bit signal of the predetermined s-bit signal 144. If the two input signals match, “1” is output, and if they do not match, a “0” signal is output. The outputs of the s matching circuits (EXNOR 147) are input to the AND circuit (AND 148). The AND circuit (AND 148) outputs “1” when all the outputs of the s matching circuits (EXNOR 147) are “1”, and outputs “0” otherwise. That is, the AND circuit (AND 148) outputs “1” when the s-bit output 104 and the predetermined s-bit signal 144 match, and outputs “0” otherwise. The output of the AND circuit (AND 148) becomes the output 106 of the determination circuit 105.

  The determination circuit 105 illustrated in FIG. 4B is different from the configuration illustrated in FIG. 4A in that the output of the AND circuit (AND 148) is output via the output control circuit 145. Other portions are the same as those in FIG. The output control circuit 145 receives the output of the AND circuit (AND 148) and the output control signal 146. The output control circuit 145 controls whether or not to output the output of the AND circuit (AND 148) as the output 106 by the output control signal 146. In this way, the output 106 can be prevented from being performed except when the determination result of the received data signal is output. Therefore, it is possible to eliminate the risk that the output 106 becomes “0” during the calculation of the CRC code and the circuit controlled using the determination result malfunctions.

  The determination circuit 105 illustrated in FIG. 4C is different from the structure illustrated in FIG. The output of the s number of matching circuits (EXNOR147) is input to the first NAND 149a and the second NAND 149b instead of the AND circuit (AND148), and the outputs of the first NAND 149a and the second NAND 149b are input to the NOR 150. . The output of NOR 150 is output 106. Other portions are the same as those in FIG. The first NAND 149a determines whether or not the first to qth (q is a natural number less than s) bits of the s-bit output 104 and the predetermined s-bit signal 144 all match. judge. If they match, “0” is output, and “1” is output otherwise. The second NAND 149b determines whether or not the (q + 1) th to sth bit signals all match in the s-bit output 104 and the predetermined s-bit signal 144. If they match, “0” is output, and “1” is output otherwise. In this way, the NOR 150 outputs “1” when the s-bit output 104 and the predetermined s-bit signal 144 match, and outputs “0” otherwise.

  In the configuration illustrated in FIG. 4C, the AND 148 illustrated in FIG. 4A includes a plurality of elements including a first NAND 149a, a second NAND 149b, and a NOR 150. Therefore, in the structure illustrated in FIG. 4C, the number of input terminals of each element can be reduced. Thus, the layout can be facilitated when the determination circuit 105 is actually manufactured.

  The configuration illustrated in FIG. 4D is different from the configuration illustrated in FIG. 4C in that the output of the NOR 150 is output via the output control circuit 145. Other portions are the same as those in FIG. The output of the NOR 150 and the output control signal 146 are input to the output control circuit 145. The output control circuit 145 controls whether or not to output the output of the NOR 150 as the output 106 by the output control signal 146. In this way, the output 106 can be prevented from being performed except when the determination result of the received data signal is output. Therefore, it is possible to eliminate the risk that the output 106 becomes “0” during the calculation of the CRC code and the circuit controlled using the determination result malfunctions.

  11A and 11B, the determination circuit 105 includes a logical product circuit (denoted as AND 148 in FIG. 11). The circuit shown in FIG. 11A corresponds to the case where s number of matching circuits (EXNOR147) are eliminated from the circuit shown in FIG.

  In general, when a received data signal is regarded as data including the CRC code and the CRC code is calculated, it is known that the obtained CRC code is a predetermined signal regardless of the received data signal. For example, FIG. 11A shows an example in which all bits of a predetermined s-bit signal 144 are “0”. At this time, if there is no error in the received data signal, all the bits of the calculated CRC code are “0”. Therefore, when there is no error in the received data signal, all signals obtained by inverting the signal of each bit of the calculated CRC code should be “1”. Therefore, by inputting the signal obtained by inverting the signal of each bit of the calculated CRC code to the AND 148 as the s-bit output 104, whether the calculated CRC code and each bit of the predetermined s-bit signal 144 match. It becomes possible to determine whether or not. If the calculated CRC code and each bit of the predetermined s-bit signal 144 match, “1” is output, and if they do not match, “0” is output.

  FIG. 11B shows an example in which the predetermined s-bit signal 144 is a 12-bit signal “111100000111” (described in the order of the 12th bit to the 1st bit). At this time, when there is no error in the received data signal, the calculated CRC code is “111100000111” (described from the 12th bit to the 1st bit). Therefore, when there is no error in the received data signal, a signal obtained by inverting only the signal of the 4th to 8th bits of the calculated CRC code (in FIG. 11B, the inverted signal is denoted as QB, All non-inverted signals are labeled Q) should be “1”. Therefore, by inputting a signal obtained by inverting only the 4th to 8th bits of the calculated CRC code to the AND 148 as an s-bit output 104, the calculated CRC code and a predetermined s-bit signal 144 are input. It is possible to determine whether or not each bit of the two matches. If the calculated CRC code and each bit of the predetermined s-bit signal 144 match, “1” is output, and if they do not match, “0” is output.

  FIG. 11C shows an example in which all bits of the predetermined s-bit signal 144 are “0”, as in FIG. 11A. A difference from FIG. 11A is that, similar to FIG. 4C, the AND 148 includes a plurality of elements including a first NAND 149a, a second NAND 149b, and a NOR 150.

  FIG. 11D illustrates an example in which the predetermined s-bit signal 144 is a 12-bit signal “111100000111” as in FIG. 11B. A difference from FIG. 11B is that, similar to FIG. 4C, the AND 148 includes a plurality of elements including a first NAND 149 a, a second NAND 149 b, and a NOR 150.

  11A to 11D, an output control circuit 145 may be provided at the output of the AND 148 as in FIGS. 4B and 4D.

This embodiment mode can be implemented freely combining with Embodiment Mode 1.
(Embodiment 3)

In this embodiment, a configuration corresponding to a CRC16-CCITT (also referred to as CRC-ITU-T) standard will be described. The CRC 16-CCITT standard generator polynomial is represented by ^{X 16 + X 12 + X 5} +1, CRC code is 16 bits. That is, in the above embodiment, this corresponds to the case where s is 16.

  A configuration example of a cyclic redundancy check circuit corresponding to the CRC16-CCITT standard will be described with reference to FIGS.

  As shown in FIG. 6, the cyclic redundancy check circuit includes a first shift register SR1, a second shift register SR2, a third shift register SR3, a first exclusive OR circuit EXOR1, The exclusive OR circuit EXOR2 and the switching circuit 101 are included.

    The first shift register SR1 has five stages connected in cascade, and delays the input signal in synchronization with the clock signal 152 and outputs the delayed signal from each stage. That is, each of the five stages connected in cascade outputs the input signal after delaying it. Output of signals from the five stages is performed in synchronization with the clock signal 152. The second shift register SR2 has seven stages connected in cascade, and delays the input signal in synchronization with the clock signal 152 and outputs the delayed signal from each stage. That is, each of the seven stages connected in cascade outputs the input signal after delaying it. Output of signals from the seven stages is performed in synchronization with the clock signal 152. The third shift register SR3 includes four stages connected in cascade, and delays the input signal in synchronization with the clock signal 152 and outputs the delayed signal from each stage. That is, each of the four stages connected in cascade outputs the input signal after delaying it. Output of signals from the four stages is performed in synchronization with the clock signal 152. Each of the first exclusive OR circuit EXOR1 and the second exclusive OR circuit EXOR2 has two input signals (corresponding to a signal input to A and a signal input to B in FIG. 6). Calculate exclusive OR. The switching circuit 101 receives the data signal 131, the select signal 132, and the output 103 of the fourth stage of the third shift register SR3, and switches one of the first signal and the second signal according to the select signal 132. Output. The output 102 of the switching circuit 101 is input to the first stage of the first shift register SR1. The output of the fifth stage of the first shift register SR1 and the output 102 of the switching circuit 101 are input to the first exclusive OR circuit EXOR1. The output of the first exclusive OR circuit EXOR1 (corresponding to the signal output from Y in FIG. 6) is input to the first stage of the second shift register SR2. The output of the seventh stage of the second shift register SR2 and the output 102 of the switching circuit 101 are input to the second exclusive OR circuit EXOR2. The output of the second exclusive OR circuit EXOR2 (corresponding to the signal output from Y in FIG. 6) is input to the first stage of the third shift register SR3.

  The first signal is an exclusive OR of the data signal 131 and the output of the fourth stage of the third shift register SR3, and the second signal is “0”. Note that when the second signal is input to the first exclusive OR circuit EXOR1, the second signal is output from the first exclusive OR circuit EXOR1 to the fifth stage of the first shift register SR1. When the second signal is input to the second exclusive OR circuit EXOR2, the output of the second exclusive OR circuit EXOR2 is equal to the output of the seventh stage of the second shift register SR2. As long as the signal is

  6 illustrates an example in which each of the plurality of stages included in each of the first shift register SR1 to the third shift register SR3 is configured using a set-type D-type flip-flop circuit (denoted as DFS in FIG. 6). . One set-type D-type flip-flop circuit DFS is a storage circuit that stores a 1-bit signal and corresponds to one stage. The output of the 16 set type D flip-flop circuits DFS becomes a 16-bit CRC code. The shift register reset signal 154 is input to set terminals (denoted as XS in FIG. 6) of the 16 set type D flip-flop circuits DFS. The information stored in the 16 set type D flip-flop circuits DFS can be initialized by the shift register reset signal 154 before the calculation of the CRC code is started.

  Since the configuration and operation of the switching circuit 101 are the same as those described in Embodiment 1 with reference to FIGS. 2 and 3, description thereof is omitted here.

  Thus, in response to the CRC16-CCITT standard, the cyclic redundancy check circuit (CRC circuit) calculates the CRC code corresponding to the received data signal, and outputs the CRC code in parallel and corresponds to the transmission data signal. It is possible to switch between the case where the CRC code is calculated and the CRC code is serially output sequentially.

  Further, the cyclic redundancy check circuit may have a determination circuit as shown in FIG. Signals stored in the first shift register SR1 to the third shift register SR3 in FIG. 6 are input in parallel to the determination circuit as a 16-bit output 104. The determination circuit outputs a different signal depending on whether or not the 16-bit output 104 matches a predetermined 16-bit signal 144.

  Here, when the received data signal is regarded as data including the CRC code and the CRC code is calculated, it is known that the obtained CRC code becomes a predetermined signal regardless of the received data signal. In the case of the CRC16-CCITT standard, the predetermined signal is “F0B8” in hexadecimal notation, that is, “1111 0000 1011 1000” in binary notation (described from the 16th bit to the 1st bit). It is known. Therefore, similarly to the configuration of the determination circuit shown in FIG. 11D, only the signals of the first to third bits, the seventh bit, and the ninth to twelfth bits of the calculated CRC code are used. Is input to the first NAND 149a and the second NAND 149b as an s-bit output 104. Therefore, as shown in FIG. 6, in the first shift register SR1 to the third shift register SR3, the first to third bits, the seventh bit, the ninth bit to the ninth bit of the calculated CRC code. In the stage corresponding to the 12th bit signal, the inverted output (QB) of DFS is output, and in the other stages, the non-inverted output (Q) of DFS is output. Thus, when the calculated CRC code and each bit of the predetermined s-bit signal 144 match, “1” is output, and when they do not match, “0” is output. Thereby, the error of the received data signal can be determined.

  In the determination circuit illustrated in FIG. 7, the output of the NOR 150 is input to the output control circuit 145. The output of the output control circuit 145 becomes the output 106 of the determination circuit. The configuration of the output control circuit 145 is basically the same as the configuration described in Embodiment 2 with reference to FIGS. 4B and 4D. The output control circuit 145 in FIG. 7 includes a reset type D flip-flop circuit (denoted as DFR in FIG. 7). An output reset signal 171 is input to a reset terminal (indicated as XR in FIG. 7) of the reset type D flip-flop circuit DFR. The output reset signal 171 can initialize the output of the determination circuit before the determination circuit outputs the result.

  In the present embodiment, the case corresponding to the CRC16-CCITT standard is shown as an example, but the present invention is not limited to this. It can be applied to a cyclic redundancy check circuit corresponding to an arbitrary standard.

This embodiment mode can be implemented by being freely combined with Embodiment Mode 1 or Embodiment Mode 2.
(Embodiment 4)

  In this embodiment, a more specific configuration of the selector 112 included in the switching circuit 101 in FIG. 2, the set type D flip-flop circuit DFS in FIG. 6, and the reset type D flip-flop circuit DFR in FIG. 7 will be described.

  The configuration of the selector 112 is shown in FIG. FIG. 8A shows a block diagram of the selector 112 and a circuit diagram corresponding to FIG. 8B. The selector 112 has two inverter circuits, six P-channel transistors, and six N-channel transistors.

  The configuration of the set type D flip-flop circuit DFS is shown in FIG. FIG. 9A shows a block diagram of the set-type D flip-flop circuit DFS, and a circuit diagram corresponding to FIG. 9B. The set-type D flip-flop circuit DFS has three inverter circuits and six NAND circuits.

  The configuration of the reset type D flip-flop circuit DFR is shown in FIG. FIG. 10A shows a block diagram of the reset type D flip-flop circuit DFR, and shows a circuit diagram corresponding to FIG. The reset type D flip-flop circuit DFR has two inverter circuits and six NAND circuits.

This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
(Embodiment 5)

  In this embodiment, a semiconductor device capable of communicating data by wireless communication (hereinafter also referred to as a wireless tag) and a wireless communication system using the semiconductor device include the cyclic redundancy described in Embodiments 1 to 4 above. A case where an inspection circuit is used will be described.

  FIG. 13A illustrates a configuration of a wireless communication system including a wireless tag 200 and a reader / writer 201 that performs data communication with the wireless tag 200 through wireless communication. The wireless tag 200 includes an antenna 202 and a circuit unit 203 that exchanges signals with the antenna 202. The reader / writer 201 includes an antenna 206 and a circuit unit 207 that exchanges signals with the antenna 206. The wireless tag 200 and the reader / writer 201 communicate data by transmitting and receiving a modulated carrier wave 190 (also referred to as a wireless signal) by the antenna 202 and the antenna 206. The circuit unit 203 includes an analog unit 204 and a digital unit 205. The analog unit 204 exchanges signals with the antenna 202. The digital unit 205 exchanges signals with the analog unit 204.

  FIG. 13B illustrates the structure of the analog portion 204 and the digital portion 205. The analog unit 204 includes a resonance capacitor 501, a band filter 502, a power supply circuit 503, a demodulation circuit 506, and a modulation circuit 507. The resonant capacitor 501 is provided so that the antenna 202 can easily receive a signal having a predetermined frequency. The digital unit 205 includes a code extraction circuit 301, a code determination circuit 302, a cyclic redundancy check circuit 303, a memory circuit 305, and a control circuit 304.

  A case where the wireless tag 200 receives data will be described. Noise from the modulated carrier wave input from the antenna 202 is removed by the band-pass filter 502 and input to the power supply circuit 503 and the demodulation circuit 506. The power supply circuit 503 includes a rectifier circuit and a storage capacitor. The modulated carrier wave input through the band-pass filter 502 is rectified by a rectifier circuit and further smoothed by a storage capacitor. Thus, the power supply circuit 503 generates a DC voltage. The DC voltage 191 generated in the power supply circuit 503 is supplied as a power supply voltage to each circuit in the circuit unit 203 included in the wireless tag 200. The modulated carrier wave input via the band filter 502 is demodulated by the demodulation circuit 506, and the demodulated signal is input to the digital unit 205. A signal input from the analog unit 204, that is, a signal obtained by demodulating a modulated carrier wave by the demodulation circuit 506 is input to the code extraction circuit 301, and a code included in the signal is extracted. The output of the code extraction circuit 301 is input to the code determination circuit 302, and the extracted code is analyzed. The analyzed code is input to the cyclic redundancy check circuit 303, and arithmetic processing for identifying a transmission error is performed. In this way, the cyclic redundancy check circuit 303 outputs a determination result 192 as to whether or not there is an error in the received data signal to the control circuit 304.

  Next, a case where the wireless tag 200 transmits data will be described. The memory circuit 305 outputs the stored unique identifier 193 (UID) to the control circuit 304 in accordance with the signal input from the code determination circuit 302. The cyclic redundancy check circuit 303 calculates a CRC code corresponding to the transmission data signal and outputs it to the control circuit 304. The control circuit 304 adds a CRC code to the transmission data signal. In addition, the control circuit 304 encodes data obtained by adding a CRC code to the transmission data signal. Further, the control circuit 304 converts the encoded information into a signal for modulating a carrier wave corresponding to a predetermined modulation method. The output of the control circuit 304 is input to the modulation circuit 507 of the analog unit 204. The modulation circuit 507 performs load modulation on the carrier wave according to the input signal and outputs the result to the antenna 202.

  Any method can be used for the carrier frequency, subcarrier frequency, data transmission rate, encoding method, and the like. For example, the frequency of the carrier wave is 300 GHz to 3 THz, which is a submillimeter wave, 30 GHz to less than 300 GHz, which is a millimeter wave, 3 GHz to less than 30 GHz, which is a microwave, 300 MHz to less than 3 GHz, which is an ultrashort wave, and 30 MHz to less than 300 MHz, which is an ultrashort wave. Any frequency of 3 MHz to less than 30 MHz as a short wave, 300 kHz to less than 3 MHz as a medium wave, 30 KHz to less than 300 KHz as a long wave, and 3 KHz to less than 30 KHz as a super long wave can be used.

  This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 4.

  In this embodiment, a specific structure of the semiconductor device of the present invention will be described with reference to FIGS.

  14A to 14D show structural examples of the antenna 202 in the semiconductor device of the present invention. The antenna 202 can be provided in two ways, and one (hereinafter referred to as a first antenna installation method) is shown in FIGS. 14 (A) and 14 (C). The other (hereinafter referred to as the second antenna installation method) is shown in FIGS. 14B and 14D. 14C corresponds to a cross-sectional view taken along lines A to A ′ in FIG. 14A, and FIG. 14D corresponds to a cross-sectional view taken along lines B to B ′ in FIG.

  In the first antenna installation method, the antenna 202 is provided over a substrate 600 over which a plurality of elements (hereinafter referred to as an element group 601) is provided (see FIGS. 14A and 14C). The element group 601 constitutes a circuit (circuit portion 203) other than the antenna of the semiconductor device of the present invention. The element group 601 includes a plurality of thin film transistors. In the structure illustrated, the conductive film functioning as the antenna 202 is provided in the same layer (on the same insulating surface) as the wiring connected to the source and drain of the thin film transistor included in the element group 601. However, the conductive film functioning as the antenna 202 may be provided in the same layer as the gate electrode 664 of the thin film transistor included in the element group 601, or an insulating film is provided over the insulating film so as to cover the element group 601. Also good.

  In the second antenna installation method, the terminal portion 602 is provided on the substrate 600 provided with the element group 601. Then, an antenna 202 provided over a substrate 610 different from the substrate 600 is connected so as to be connected to the terminal portion 602 (see FIGS. 14B and 14D). In the structure shown in the drawing, part of the wiring connected to the source and drain of the thin film transistor included in the element group 601 is used as the terminal portion 602. Then, the substrate 600 and the substrate 610 provided with the antenna 202 are attached to be connected to the terminal portion 602. Conductive particles 603 and a resin 604 are provided between the substrate 600 and the substrate 610. The antenna 202 and the terminal portion 602 are electrically connected by the conductive particles 603.

  A structure and a manufacturing method of the element group 601 will be described. If a plurality of element groups 601 are formed on a large-area substrate and then completed by being divided, an inexpensive device can be provided. As the substrate 600, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a semiconductor substrate having an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic may be used. The surface of the substrate may be planarized by polishing such as a CMP (Chemical Mechanical Polishing) method. Further, a glass substrate, a quartz substrate, or a substrate obtained by polishing and thinning a semiconductor substrate may be used.

As the base layer 661 provided over the substrate 600, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide (SiO _x N _y or SiN _x O _y where x> y) can be used. The base layer 661 can prevent alkali metal or alkaline earth metal such as Na contained in the substrate 600 from diffusing into the semiconductor layer 662 and adversely affecting the characteristics of the thin film transistor. In FIG. 14, the base layer 661 has a single-layer structure, but it may be formed of two or more layers. Note that the base layer 661 is not necessarily provided when diffusion of impurities such as a quartz substrate does not cause any problem.

Note that the surface of the substrate 600 may be directly processed by high-density plasma. The high density plasma is generated by using a high frequency, for example 2.45 GHz. As the high density plasma, one having an electron density of 10 ¹¹ to 10 ¹³ / cm ³ , an electron temperature of 2 eV or less, and an ion energy of 5 eV or less is used. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects than conventional plasma treatment. Plasma can be generated using a high-frequency excitation plasma processing apparatus using a radial slot antenna. The distance from the antenna that generates a high frequency to the substrate 600 is 20 to 80 mm (preferably 20 to 60 mm).

A nitriding atmosphere such as nitrogen (N) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, nitrogen, hydrogen (H), a rare gas atmosphere, or ammonia (NH ₃ ) In the rare gas atmosphere, the surface of the substrate 600 can be nitrided by performing the high-density plasma treatment. When glass, quartz, silicon wafer, or the like is used as the substrate 600, the nitride layer formed on the surface of the substrate 600 contains silicon nitride as a main component, so that it can be used as a blocking layer for impurities diffused from the substrate 600 side. can do. A silicon oxide film or a silicon oxynitride film may be formed over the nitride layer by a plasma CVD method to form the base layer 661.

  Further, by performing the same high-density plasma treatment on the surface of the base layer 661 made of silicon oxide, silicon oxynitride, or the like, the surface and the depth of 1 to 10 nm can be nitrided from the surface. This extremely thin silicon nitride layer is preferable because it functions as a blocking layer and is less affected by stress on the semiconductor layer 662 formed thereon.

  As the semiconductor layer 662, an island-shaped crystalline semiconductor film or an amorphous semiconductor film can be used. Further, an organic semiconductor film may be used. The crystalline semiconductor film can be obtained by crystallizing an amorphous semiconductor film. As a crystallization method, a laser crystallization method, a thermal crystallization method using RTA (Rapid Thermal Anneal) or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like can be used. The semiconductor layer 662 includes a channel formation region 662a and a pair of impurity regions 662b to which an impurity element imparting a conductivity type is added. Note that although the structure including the low-concentration impurity region 662c to which the impurity element is added at a lower concentration than the impurity region 662b is shown between the channel formation region 662a and the pair of impurity regions 662b, the invention is not limited thereto. A structure in which the low concentration impurity region 662c is not provided may be employed.

  Note that the wiring formed at the same time as the semiconductor layer 662 is preferably led so that corners are rounded when viewed from a direction perpendicular to the top surface of the substrate 600. FIG. 16 schematically shows the wiring routing method. In FIG. 16, a direction 3005 perpendicular to the upper surface of the substrate 600 is shown. A wiring formed simultaneously with the semiconductor layer is indicated by a wiring 3011 in the drawing. FIG. 16A shows a conventional wiring routing method. FIG. 16B shows a wiring routing method according to the present invention. The corner 1202a is round with respect to the conventional corner 1201a. By rounding the corner, it is possible to prevent dust and the like from remaining at the corner of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased.

  An impurity element imparting a conductivity type may be added to the channel formation region 662a of the thin film transistor. Thus, the threshold voltage of the thin film transistor can be controlled.

The first insulating layer 663 is formed using silicon oxide, silicon nitride, silicon nitride oxide (SiO _x N _y or SiN _x O _y where x> y), or the like by stacking a single layer or a plurality of films. Can do. In this case, the surface of the first insulating layer 663 may be densified by treatment with high-density plasma in an oxidizing atmosphere or a nitriding atmosphere, and oxidizing or nitriding treatment. As described above, the high-density plasma is generated by using a high frequency, for example, 2.45 GHz. As the high density plasma, one having an electron density of 10 ¹¹ to 10 ¹³ / cm ³ , an electron temperature of 2 eV or less, and an ion energy of 5 eV or less is used. Plasma can be generated using a high-frequency excitation plasma processing apparatus using a radial slot antenna. In the apparatus for generating high-density plasma, the distance from the antenna that generates high frequency to the substrate 600 is set to 20 to 80 mm (preferably 20 to 60 mm).

  Note that before the first insulating layer 663 is formed, the surface of the semiconductor layer 662 may be oxidized or nitrided by performing the above high-density plasma treatment. At this time, by performing treatment in an oxidizing atmosphere or a nitriding atmosphere at a temperature of the substrate 600 of 300 to 450 ° C., a favorable interface can be formed with the first insulating layer 663 deposited thereon.

The nitriding atmosphere may be a nitrogen (N) and rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, a nitrogen and hydrogen (H) and rare gas atmosphere, or ammonia (NH ₃ ) And a noble gas atmosphere. As the oxidizing atmosphere, an oxygen (O) and rare gas atmosphere, an oxygen and hydrogen (H) and rare gas atmosphere, or a dinitrogen monoxide (N ₂ O) and rare gas atmosphere can be used.

  As the gate electrode 664, one kind of element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy or compound containing a plurality of such elements can be used. In addition, a single layer or a stacked structure of these elements, alloys, and compounds can be used. In FIG. 14, a gate electrode 664 having a two-layer structure is shown. Note that the gate electrode 664 and the wiring formed at the same time as the gate electrode 664 are preferably led so that corners are rounded when viewed from a direction perpendicular to the top surface of the substrate 600. The routing method can be the same as the method shown in FIG. A wiring formed at the same time as the gate electrode 664 and the gate electrode 664 is indicated by a wiring 3012 in the drawing. By rounding the corner portion like the corner portion 1202b with respect to the corner portion 1201b, dust or the like can be prevented from remaining in the corner portion of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased.

  The thin film transistor includes a semiconductor layer 662, a gate electrode 664, and a first insulating layer 663 that functions as a gate insulating film between the semiconductor layer 662 and the gate electrode 664. In this embodiment, the thin film transistor is shown as a top gate type transistor, but it may be a bottom gate type transistor having a gate electrode below the semiconductor layer, or a dual gate type having gate electrodes above and below the semiconductor layer. This transistor may be used.

The second insulating layer 667 is preferably a barrier insulating film that blocks ionic impurities, such as a silicon nitride film. The second insulating layer 667 is formed using silicon nitride or silicon oxynitride. The second insulating layer 667 functions as a protective film that prevents contamination of the semiconductor layer 662. After the second insulating layer 667 is deposited, the second insulating layer 667 may be hydrogenated by introducing hydrogen gas and performing high-density plasma treatment as described above. Alternatively, the second insulating layer 667 may be nitrided and hydrogenated by introducing ammonia (NH ₃ ) gas. Alternatively, oxynitriding treatment and hydrogenation treatment may be performed by introducing oxygen, dinitrogen monoxide (N ₂ O) gas, or the like and hydrogen gas. By this method, the surface of the second insulating layer 667 can be densified by performing nitriding treatment, oxidation treatment, or oxynitridation treatment. Thus, the function of the second insulating layer 667 as a protective film can be enhanced. The hydrogen introduced into the second insulating layer 667 is then released by heat treatment at 400 to 450 ° C., so that the semiconductor layer 662 can be hydrogenated. Note that this hydrogenation treatment may be combined with a hydrogenation treatment using the first insulating layer 663.

  As the third insulating layer 665, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film formed by an SOG (Spin On Glass) method, or the like can be used. As an organic insulating film, polyimide, polyamide, BCB (benzoic acid) is used. A film such as cyclobutene), acrylic or positive photosensitive organic resin, or negative photosensitive organic resin can be used.

  Alternatively, the third insulating layer 665 can be formed using a material having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent of this material, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  As the wiring 666, one kind of element selected from Al, Ni, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements can be used. In addition, a single layer or a stacked structure of these elements and alloys can be used. FIG. 14 shows an example of a single layer structure. Note that the wiring 666 is preferably led so that corners are rounded when viewed from a direction perpendicular to the top surface of the substrate 600. The routing method can be the same as the method shown in FIG. A wiring 666 is indicated by a wiring 3013 in the drawing. By rounding the corner portion like the corner portion 1202c with respect to the corner portion 1201c, dust or the like can be prevented from remaining at the corner portion of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased. The wiring 3013 is connected to the wiring 3011 through the contact hole 3014. In the structures illustrated in FIGS. 14A and 14C, the wiring 666 serves as the antenna 202 and the wiring connected to the source and drain of the thin film transistor. In the structures illustrated in FIGS. 14B and 14D, the wiring 666 is a wiring connected to the source and drain of the thin film transistor and the terminal portion 602.

  Note that the antenna 202 can also be formed by a droplet discharge method using a conductive paste containing nanoparticles such as Au, Ag, or Cu. The droplet discharge method is a general term for a method of forming a pattern by discharging droplets, such as an inkjet method or a dispenser method, and has advantages such as improvement in material utilization efficiency.

  In the structure illustrated in FIGS. 14A and 14C, a fourth insulating layer 668 is formed over the wiring 666. As the fourth insulating layer 668, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. The fourth insulating layer 668 functions as a protective layer for the antenna 202.

  Alternatively, the element group 601 formed over the substrate 600 (see FIG. 15A) may be used as it is, but the element group 601 on the substrate 600 is peeled off (see FIG. 15B), The element group 601 may be attached to the flexible substrate 701 (see FIG. 15C). The flexible substrate 701 has flexibility, and for example, a plastic substrate such as polycarbonate, polyarylate, or polyether sulfone, or a ceramic substrate can be used.

  For peeling the element group 601 from the substrate 600, the following methods (A) to (C) can be used. (A) A method in which a peeling layer is provided in advance between the substrate 600 and the element group 601 and the peeling layer is removed with an etching agent. (B) A method in which the peeling layer is partially removed with an etching agent, and then the substrate 600 and the element group 601 are physically peeled off. (C) A method of separating the element group 601 by mechanically removing the substrate 600 having the element group 601 formed thereon or removing it by etching with a solution or gas. It should be noted that peeling by physical means means peeling by applying stress from the outside, for example, peeling by applying stress from the wind pressure of a gas blown from a nozzle or ultrasonic waves. .

  As a more specific method of the above (A) or (B), a metal oxide film is provided between the substrate 600 having high heat resistance and the element group 601, and the metal oxide film is weakened by crystallization, whereby the element A method for peeling the group 601 can be used. As another example of the more specific methods (A) and (B), an amorphous silicon film containing hydrogen is provided between the substrate 600 having high heat resistance and the element group 601, and laser light is emitted. A method for peeling the element group 601 can be used by removing the amorphous silicon film by irradiation or etching.

  The peeled element group 601 may be attached to the flexible substrate 701 using a commercially available adhesive, for example, an adhesive such as an epoxy resin adhesive or a resin additive.

  When the element group 601 is attached to a flexible substrate 701 on which an antenna is formed and is electrically connected to the antenna, the semiconductor device is completed which is thin, light, and difficult to break even when dropped (FIG. 15C). reference). When an inexpensive flexible substrate 701 is used, an inexpensive semiconductor device can be provided. Further, since the flexible substrate 701 has flexibility, the flexible substrate 701 can be bonded onto a curved surface or an irregular shape, thereby realizing a wide variety of uses. For example, the wireless tag 200 which is one embodiment of the semiconductor device of the present invention can be attached to a curved surface such as a medicine bottle (see FIG. 15D). Further, when the substrate 600 is reused, a semiconductor device can be manufactured at low cost.

  The element group 601 can be sealed by covering it with a film. The surface of the film may be coated with silicon dioxide (silica) powder. The coating can maintain waterproofness even in a high temperature and high humidity environment. That is, it can have a moisture resistance function. Further, the surface of the film may have an antistatic function. Further, the surface of the film may be coated with a material containing carbon as a main component (for example, diamond-like carbon). The coating increases the strength and can suppress deterioration and destruction of the semiconductor device. The film may be formed of a material obtained by mixing a base material (for example, resin) with silicon dioxide, a conductive material, or a material containing carbon as a main component. In addition, it is possible to impart an antistatic function to the film by forming the surfactant on the surface of the film or by kneading the surfactant directly into the film.

  This embodiment can be freely combined with the above embodiment modes.

  In this embodiment, an example in which the semiconductor device of the present invention is configured to be flexible will be described. FIG. 17 is used for the description. In FIG. 17A, a semiconductor device of the present invention includes a flexible protective layer 901, a flexible protective layer 903 including an antenna 902 (corresponding to the antenna 202), an element formed by a peeling process or thinning of a substrate. A group 904. The element group 904 can have a structure similar to the structure shown as the element group 601 in the first embodiment. An antenna 902 formed over the protective layer 903 is electrically connected to the element group 904. In FIG. 17, the antenna 902 is formed only on the protective layer 903; however, the present invention is not limited to this structure, and the antenna 902 may also be formed on the protective layer 901. Note that a barrier film formed of a silicon nitride film or the like is preferably formed between the element group 904 and the protective layer 901 and the protective layer 903. Then, a semiconductor device with improved reliability can be provided without the element group 904 being contaminated.

  The antenna 902 can be formed of Ag, Cu, or a metal plated with them. The element group 904 and the antenna 902 can be connected by performing an ultraviolet treatment or an ultrasonic treatment using an anisotropic conductive film. Note that the element group 904 and the antenna 902 may be bonded using a conductive paste or the like.

  A semiconductor device is completed by sandwiching the element group 904 between the protective layer 901 and the protective layer 903 (see arrows in FIG. 17A).

A cross-sectional structure of the semiconductor device thus formed is shown in FIG. A thickness 3003 of the sandwiched element group 904 may be 5 μm or less, preferably 0.1 μm to 3 μm. Further, when the thickness when the protective layer 901 and the protective layer 903 are overlapped is d, the thickness of the protective layer 901 and the protective layer 903 is preferably (d / 2) ± 30 μm, more preferably (d / 2) Set to ± 10 μm. The thickness of the protective layer 901 and the protective layer 903 is preferably 10 μm to 200 μm. Further, the area of the element group 904 is 10 mm square (100 mm ² ) or less, and preferably 0.3 mm square to 4 mm square (0.09 mm ^{2 to} 16 mm ² ).

  Since the protective layer 901 and the protective layer 903 are made of an organic resin material, they have a strong characteristic against bending. In addition, the element group 904 itself formed by a peeling process or thinning of the substrate also has a strong characteristic against bending compared to a single crystal semiconductor. Since the element group 904 and the protective layer 901 and the protective layer 903 can be in close contact with each other so that there is no gap, the completed semiconductor device itself has a strong characteristic against bending. The element group 904 surrounded by the protective layer 901 and the protective layer 903 may be arranged on the surface or inside of another solid object, or may be embedded in paper.

  A case where a semiconductor device including the element group 904 is attached to a substrate having a curved surface is described. FIG. 17C is used for the description. In the drawing, one transistor 981 selected from the element group 904 is shown. The transistor 981 flows current from one of the source and drain 905 to the other of the source and drain 906 in accordance with the potential of the gate electrode 907. The transistor 981 is arranged so that a direction 3004 in which the current of the transistor 981 flows (carrier movement direction) and a direction in which the substrate 980 draws an arc are orthogonal to each other. With such an arrangement, even when the substrate 980 is bent so as to draw an arc, the influence of stress applied to the transistor 981 is small, and variation in characteristics of the transistor 981 included in the element group 904 can be suppressed.

  This embodiment can be freely combined with the above embodiment mode and Embodiment 1.

  In this embodiment, a structural example of a transistor included in a circuit included in the semiconductor device of the present invention is shown. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 20 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 20 illustrates an N-channel transistor 2001, an N-channel transistor 2002, a capacitor element 2004, a resistor element 2005, and a P-channel transistor 2003. Each transistor includes a semiconductor layer 4405, a gate insulating layer 4408, and a gate electrode 4409. The gate electrode 4409 has a stacked structure of a first conductive layer 4403 and a second conductive layer 4402. FIG. 21A is a top view corresponding to the N-channel transistor 2001 illustrated in FIG. FIG. 21B is a top view corresponding to the N-channel transistor 2002 illustrated in FIG. FIG. 21C is a top view corresponding to the capacitor 2004 shown in FIG. FIG. 21D is a top view corresponding to the resistance element 2005 illustrated in FIG. FIG. 21E is a top view corresponding to the P-channel transistor 2003 illustrated in FIG. FIG. 21 can be referred to in conjunction with FIG.

  In FIG. 20, an N-channel transistor 2001 includes a low concentration drain (LDD) region on both sides of a channel formation region in the semiconductor layer 4405. The LDD region is an impurity region 4407 and is doped with an impurity imparting N-type at a lower concentration than the impurity concentration of a source region and a drain region (impurity region 4406) that form a contact with the wiring 4404. In the case where the N-channel transistor 2001 is formed, phosphorus or the like is added to the impurity region 4406 and the impurity region 4407 as an impurity imparting N-type conductivity. The LDD region is formed as a means for suppressing hot electron degradation and the short channel effect.

  As shown in FIG. 21A, in the gate electrode 4409 of the N-channel transistor 2001, the first conductive layer 4403 is formed so as to spread on both sides of the second conductive layer 4402. In this case, the first conductive layer 4403 is thinner than the second conductive layer 4402. The first conductive layer 4403 is formed to have a thickness that allows ionic species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 4407 is formed so as to overlap with the first conductive layer 4403 of the gate electrode 4409. That is, an LDD region overlapping with the gate electrode 4409 is formed. The impurity region 4407 is formed in a self-aligned manner by adding one conductivity type impurity to the semiconductor layer 4405 through the first conductive layer 4403 using the second conductive layer 4402 as a mask. That is, the LDD region overlapping with the gate electrode is formed in a self-aligning manner.

  A transistor having an LDD region on both sides of a channel formation region in a semiconductor layer is applied to a transistor forming a transmission gate (also referred to as an analog switch) or a transistor used in a rectifier circuit in the power supply circuit 503 in FIG. In these transistors, since positive and negative voltages are applied to the source electrode and the drain electrode, it is preferable to provide LDD regions on both sides of the channel formation region in the semiconductor layer.

  In FIG. 20, an N-channel transistor 2002 has an impurity region 4407 formed on one side of a channel formation region in the semiconductor layer 4405. The impurity region 4407 is doped with an impurity element imparting conductivity type at a lower concentration than the impurity concentration of the impurity region 4406. As shown in FIG. 21B, in the gate electrode 4409 of the N-channel transistor 2002, the first conductive layer 4403 is formed so as to spread on one side of the second conductive layer 4402. In this case as well, an LDD region can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 4403 using the second conductive layer 4402 as a mask.

  A transistor having an LDD region on one side of a channel formation region in a semiconductor layer may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between a source electrode and a drain electrode. Specifically, transistors that constitute logic gates such as inverter circuits, NAND, NOR, and latch circuits, transistors that constitute analog circuits such as sense amplifiers, constant voltage generation circuits, and VCOs (Voltage Controlled Oscillators). Apply.

  In FIG. 20, the capacitor 2004 is formed with a gate insulating layer 4408 sandwiched between a first conductive layer 4403 and a semiconductor layer 4405. A semiconductor layer 4405 that forms the capacitor 2004 includes an impurity region 4410 and an impurity region 4411. The impurity region 4411 is formed in the semiconductor layer 4405 so as to overlap with the first conductive layer 4403. In addition, the impurity region 4410 forms a contact with the wiring 4404. Since the impurity region 4411 can be doped with one conductivity type impurity through the first conductive layer 4403, the impurity concentration in the impurity region 4410 and the impurity region 4411 can be the same or can be different. It is. In any case, since the semiconductor layer 4405 functions as an electrode in the capacitor 2004, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as illustrated in FIG. 21C, the first conductive layer 4403 can function sufficiently as an electrode by using the second conductive layer 4402 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 4403 and the second conductive layer 4402 are combined, the capacitor element 2004 can be formed in a self-aligning manner.

  The capacitor 2004 can be used as a storage capacitor of the power supply circuit 503 illustrated in FIG. 13 or a capacitor included in the resonance capacitor 501 and the demodulation circuit 506. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor 501 needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

  In FIG. 20, the resistance element 2005 is formed of the first conductive layer 4403 (see also FIG. 21D). Since the first conductive layer 4403 is formed to a thickness of about 30 to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element can be used as a resistance load included in the modulation circuit 507 illustrated in FIG. Further, it can also be used as a resistance element included in the demodulation circuit 506 shown in FIG. Further, it may be used as a load for controlling current with a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 20, a P-channel transistor 2003 includes an impurity region 4412 in a semiconductor layer 4405. This impurity region 4412 functions as a source region and a drain region that form a contact with the wiring 4404. The gate electrode 4409 has a structure in which the first conductive layer 4403 and the second conductive layer 4402 overlap with each other (see also FIG. 21E). The P-channel transistor 2003 is a single drain transistor without an LDD region. In the case of forming the P-channel transistor 2003, boron or the like is added to the impurity region 4412 as an impurity imparting P-type conductivity. On the other hand, if phosphorus is added to the impurity region 4412, an N-channel transistor having a single drain structure can be obtained.

  One or both of the semiconductor layer 4405 and the gate insulating layer 4408 may be oxidized or nitrided by high density plasma treatment. This process can be performed in the same manner as in the first embodiment.

  Through the above treatment, the defect level at the interface between the semiconductor layer 4405 and the gate insulating layer 4408 can be reduced. By performing this treatment on the gate insulating layer 4408, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 4408. In the case where the driving voltage of the transistor is 3 V or more, a gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 4405 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 4408 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor element 2004. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor element 2004 having a large charge capacity can be formed.

  As described with reference to FIGS. 20 and 21, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 21A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  20 and 21, the first conductive layer is mainly composed of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride or molybdenum (Mo), or a refractory metal. The alloy or compound to be formed is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride, or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. It is formed to a thickness of 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, tantalum nitride can be used as the first conductive layer, and tungsten can be used as the second conductive layer.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same process using a photomask or reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be divided. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  This embodiment can be freely combined with the above embodiment mode, Embodiment 1 and Embodiment 2.

  In this embodiment, an example of a static RAM (SRAM) that can be used as a memory (such as the memory circuit 305 in FIG. 13) of the semiconductor device of the present invention will be described with reference to FIGS.

  The semiconductor layer 10 and the semiconductor layer 11 illustrated in FIG. 22A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, island-shaped semiconductor layers 10 and 11 having a specific shape including a source region and a drain region of the transistor and a channel formation region are formed. The shapes of the semiconductor layer 10 and the semiconductor layer 11 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layer 10 and the semiconductor layer 11 shown in FIG. 22A includes a mask pattern 2000 shown in FIG. The mask pattern 2000 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, a mask pattern 2000 shown in FIG. 22B is manufactured as a light shielding portion. The mask pattern 2000 has a shape in which a polygonal convex portion A is chamfered. Moreover, in the recessed part B, it becomes the shape bent so that the corner | angular part may not become a right angle.

  The shape of the mask pattern 2000 illustrated in FIG. 22B is reflected in the semiconductor layer 10 and the semiconductor layer 11 illustrated in FIG. In that case, a shape similar to the mask pattern 2000 may be transferred, but it may be transferred so that the corners of the mask pattern 2000 are further rounded. That is, you may provide the round part which made the pattern shape smoother than the mask pattern 2000 further.

  An insulating layer containing at least part of silicon oxide or silicon nitride is formed over the semiconductor layer 10 and the semiconductor layer 11. One purpose of forming this insulating layer is a gate insulating layer. Then, as illustrated in FIG. 23A, the gate wiring 12, the gate wiring 13, and the gate wiring 14 are formed so as to partially overlap the semiconductor layer. The gate wiring 12 is formed corresponding to the semiconductor layer 10. The gate wiring 13 is formed corresponding to the semiconductor layer 10 and the semiconductor layer 11. The gate wiring 14 is formed corresponding to the semiconductor layer 10 and the semiconductor layer 11. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

  A photomask for forming this gate wiring is provided with a mask pattern 2100 shown in FIG. The mask pattern 2100 has a shape that bends so that the corners do not form a right angle. The shape of the mask pattern 2100 illustrated in FIG. 23B is reflected in the gate wiring 12, the gate wiring 13, and the gate wiring 14 illustrated in FIG. In that case, a shape similar to the mask pattern 2100 may be transferred, or the corner of the mask pattern 2100 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 2100 may be provided. By rounding the corners, the rounded convex part suppresses the generation of fine powder due to abnormal discharge during plasma dry etching, and the rounded concave part, even if it is fine powder made during cleaning Can wash away, it is easy to gather in the corner. As a result, the yield can be improved.

  The interlayer insulating layer is a layer formed next to the gate wiring 12, the gate wiring 13, and the gate wiring 14. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material such as polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wiring 12, the gate wiring 13, and the gate wiring 14. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities such as exogenous metal ions and moisture that are not good for the transistor.

  An opening is formed at a predetermined position in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 24A, the wiring 15, the wiring 16, the wiring 17, the wiring 18, the wiring 19, and the wiring 20 are formed so as to partially overlap the semiconductor layer 10 and the semiconductor layer 11. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 15 to 20 includes a mask pattern 2200 shown in FIG. The mask pattern 2200 is also bent so that the corners do not become a right angle. In this way, the corners are rounded. Such a wiring suppresses the generation of fine powder due to abnormal discharge at the time of dry etching by plasma at the rounded convex part, and even at the rounded concave part, even if it is fine powder produced at the time of cleaning, it is a corner. It is possible to wash away what is easy to gather in. As a result, the yield can be improved. Electrical conduction can be realized by rounding the corners of the wiring. In addition, when a plurality of wirings having a bent part or a part whose width changes are provided in parallel, dust or the like is particularly likely to collect when the corners of the wiring are at right angles. Therefore, it is extremely convenient to round the corners. is there.

  FIG. 24A shows an N-channel transistor 21, an N-channel transistor 22, an N-channel transistor 23, an N-channel transistor 24, a P-channel transistor 25, and a P-channel transistor 26. Is formed. The N-channel transistor 23 and the P-channel transistor 25 constitute an inverter 27, and the N-channel transistor 24 and the P-channel transistor 26 constitute an inverter 28. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

  This embodiment can be freely combined with the above embodiment mode and Embodiments 1 to 3.

  One embodiment of the semiconductor device of the present invention is shown in FIG. FIG. 25A is a development view of the semiconductor device, and FIG. 25B is a cross-sectional view taken along a line AB in FIG. In this embodiment, a structure of a semiconductor device including a plurality of antennas, particularly an antenna formed over a layer including a thin film transistor and a patch antenna will be described.

  In a manner similar to the method for manufacturing the element group 601 described in Embodiment 1, a layer 7102 including a thin film transistor is formed over the insulating substrate 7101. An interlayer insulating layer 7182 is formed over the layer 7102 having a thin film transistor. A first antenna 7181 is formed over the interlayer insulating layer 7182. An insulating layer 7183 is formed over the first antenna 7181, and a connection terminal 7184 is formed on the surface of the insulating layer 7183.

  An insulating layer 7183 in which the connection terminal 7184 is partially exposed and a patch antenna 7103 which is a second antenna are fixed by an anisotropic conductive adhesive 7104. Further, the connection terminal 7184 and the power supply layer 7113 of the patch antenna are electrically connected with conductive particles dispersed in the anisotropic conductive adhesive. The connection terminal 7184 and the first thin film transistor 7185 formed in the thin film transistor layer 7102 are electrically connected. In addition, the second thin film transistor 7186 formed in the layer 7102 having a thin film transistor is connected to the first antenna 7181. Note that a conductive layer obtained by curing a conductive paste may be used instead of the anisotropic conductive adhesive.

  The first antenna 7181 is formed using a metal material containing aluminum, copper, or silver. For example, a copper or silver paste composition can be formed by screen printing, offset printing, or an ink jet printing method. Alternatively, an aluminum film may be formed by sputtering or the like and formed by etching. In addition, you may form using an electroplating method and an electroless-plating method.

  Note that the first antenna 7181 can be omitted.

  Here, the first antenna 7181 has a rectangular coil shape as shown in FIG.

  The shape of the first antenna 7181 will be described with reference to FIG. FIG. 26 is a top view showing the interlayer insulating layer 7182 and the antenna formed thereon. In this embodiment, as shown in FIGS. 25A and 26A, the first antenna 7181 has a rectangular coil shape 7181a, but is not limited to this shape. It may be a circular coil. Further, as shown in FIG. 26B, a square loop antenna 7181b can be obtained. Moreover, it can be set as a circular loop antenna. Further, as shown in FIG. 26C, a linear dipole-shaped antenna 7181c can be obtained. Moreover, it can be set as a curved dipole antenna.

  By providing a plurality of antennas in this way, a multiband semiconductor device capable of receiving radio waves of different frequencies with one semiconductor device can be formed.

  This embodiment can be freely combined with the above embodiment mode and Embodiments 1 to 4.

  In this embodiment, the application of the semiconductor device of the present invention (corresponding to the wireless tag 200 in FIG. 13) will be described with reference to FIGS. The wireless tag 200 can be used by being provided, for example, on banknotes, coins, securities, bearer bonds, certificate documents (driver's license, resident's card, etc., see FIG. 19A). Or packaging containers (wrapping paper, bottles, etc., see FIG. 19B), DVD software, recording media such as CDs and videotapes (see FIG. 19C), vehicles such as cars, motorcycles, bicycles, etc. (See FIG. 19D), personal items such as bags and glasses (see FIG. 19E), foods, clothing, daily necessities, electronic devices, and the like. Electronic devices refer to liquid crystal display devices, EL (electroluminescence) display devices, television devices (also simply referred to as televisions or television receivers), cellular phones, and the like.

  The wireless tag 200 can be fixed to an article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing the wireless tag 200 on bills, coins, securities, bearer bonds, certificates, and the like. Further, by providing the wireless tag 200 in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. . In addition, forgery and theft can be prevented by providing the wireless tag 200 in vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a wireless tag in a living creature such as livestock, it is possible to easily identify the year of birth, sex, type, or the like.

  As described above, the wireless tag 200 of the present invention can be provided and used for any article (including a living thing).

  The wireless tag 200 has various advantages such as that it can transmit and receive data by wireless communication, can be processed into various shapes, and has a wide directivity and a wide recognition range depending on the selected frequency. .

  Next, one mode of a system using the wireless tag 200 will be described with reference to FIG. A reader / writer 9520 (corresponding to the reader / writer 201 in FIG. 13) is provided on the side surface of the portable terminal including the display portion 9521, and the semiconductor device 9523 of the present invention (the wireless tag 200 in FIG. 13) is provided on the side surface of the article A 9522. ), And the semiconductor device 9531 of the present invention is provided over the top surface of the article B 9532 (see FIG. 18A). When the reader / writer 9520 is held over the semiconductor device 9523 included in the article A 9522, information about the article such as the raw material and origin of the article A 9522, the inspection result for each production process, the history of distribution process, and the explanation of the article is displayed on the display unit 9521. The When the reader / writer 9520 is held over the semiconductor device 9531 included in the article B 9532, information on the product such as the raw material and the place of origin of the article B 9532, the inspection result for each production process, the history of the distribution process, and the description of the product is displayed on the display unit 9521. The

  An example of a business model using the system shown in FIG. The flowchart in FIG. 18B is used for the description. In the portable terminal, allergy information is input (first step 8001). The allergy information is information on pharmaceuticals or components thereof that cause a predetermined person to cause an allergic reaction. Information on the article A 9522 is acquired by the reader / writer 9520 provided in the portable terminal as described above (second step 8002). Here, it is assumed that the article A 9522 is a medicine. Information on the article A 9522 includes information such as a component of the article A 9522. The allergy information is compared with the acquired information such as the component of the article A9522 to determine whether or not they match (third step 8003). If they match, it is determined that the predetermined person has a risk of causing an allergic reaction to the article A, and the user of the mobile terminal is called for attention (fourth step 8004). If they do not match, it is determined that the predetermined person is less likely to cause an allergic reaction to the article A, and the user of the portable terminal is notified of this (safe step) (fifth step 8005). In the fourth step 8004 and the fifth step 8005, the method of notifying the user of the mobile terminal of information may be a method of displaying on the display unit 9521 of the mobile terminal, or sounding an alarm of the mobile terminal. It may be a method.

  An example of another business model is shown in FIG. Information on a combination of dangerous pharmaceuticals that are dangerous when used at the same time or combinations of components of pharmaceuticals that are dangerous when used at the same time (hereinafter referred to as combination information) is input to the terminal (first step 8011). The information on the article A is acquired by the reader / writer provided in the terminal as described above (second step 8012a). Here, it is assumed that the article A is a medicine. The information on the article A includes information such as the components of the article A. Next, the information on the article B is acquired by the reader / writer provided in the terminal as described above (third step 8012b). Here, it is assumed that the article B is also a medicine. The information on the article B includes information such as the component of the article B. Thus, information on a plurality of medicines is acquired. The combination information is compared with the acquired information of the plurality of articles, and it is determined whether or not they match, that is, whether or not there is a combination of components of pharmaceuticals that are dangerous when used simultaneously (fourth step 8013). If they match, the user of the terminal is alerted (fifth step 8014). If they do not match, the terminal user is informed of that fact (safe) (sixth step 8015). In the fifth step and the sixth step, the method of informing the user of the terminal may be a method of displaying on the display unit of the terminal or a method of sounding an alarm of the portable terminal. good.

  In this manner, by utilizing the semiconductor device of the present invention for the system, information can be easily acquired, and a system that realizes high functionality and high added value can be provided.

  This embodiment can be freely combined with the above embodiment mode and Embodiments 1 to 5.

FIG. 3 illustrates a configuration of Embodiment 1; FIG. 3 illustrates a configuration of Embodiment 1; FIG. 3 illustrates a configuration of Embodiment 1; FIG. 6 illustrates a configuration of a second embodiment. FIG. 3 illustrates a configuration of Embodiment 1; FIG. 6 illustrates a configuration of a third embodiment. FIG. 6 illustrates a configuration of a third embodiment. FIG. 6 illustrates a configuration of a fourth embodiment. FIG. 6 illustrates a configuration of a fourth embodiment. FIG. 6 illustrates a configuration of a fourth embodiment. FIG. 6 illustrates a configuration of a second embodiment. The figure which shows the conventional structure. FIG. 6 shows a configuration of a fifth embodiment. FIG. 3 is a diagram illustrating Example 1; FIG. 3 is a diagram illustrating Example 1; FIG. 3 is a diagram illustrating Example 1; FIG. FIG. 6 shows a sixth embodiment. FIG. 6 shows a sixth embodiment. FIG. FIG. FIG. FIG. FIG. FIG. 6 shows a fifth embodiment. FIG. 6 shows a fifth embodiment.

Explanation of symbols

10 semiconductor layer 11 semiconductor layer 12 gate wiring 13 gate wiring 14 gate wiring 15 wiring 16 wiring 17 wiring 18 wiring 19 wiring 20 wiring 21 transistor 22 transistor 23 transistor 24 transistor 25 transistor 26 transistor 27 inverter 28 inverter 101 switching circuit 102 output 103 output 104 Output 105 Judgment circuit 106 Output 111 EXOR
112 selector 131 data signal 132 select signal 144 signal 145 output control circuit 146 output control signal 147 EXNOR
148 AND
149a first NAND
149b second NAND
150 NOR
151 output 152 clock signal 153 input signal 154 shift register reset signal 171 output reset signal 181 clock signal 182 data signal 190 modulated carrier wave 191 DC voltage 192 determination result 193 unique identifier 200 wireless tag 201 reader / writer 202 antenna 203 circuit unit 204 Analog unit 205 Digital unit 206 Antenna 207 Circuit unit 301 Code extraction circuit 302 Code determination circuit 303 Cyclic redundancy check circuit 304 Control circuit 305 Memory circuit 501 Resonance capacitor 502 Band filter 503 Power supply circuit 506 Demodulation circuit 507 Modulation circuit 600 Substrate 601 Element group 602 Terminal portion 603 Conductive particle 604 Resin 610 Substrate 661 Underlayer 662 Semiconductor layer 662a Channel formation region 662b Impurity region 662c Low concentration impurity region Region 663 First insulating layer 664 Gate electrode 665 Third insulating layer 666 Wiring 667 Second insulating layer 668 Fourth insulating layer 701 Flexible substrate 901 Protective layer 902 Antenna 903 Protective layer 904 Element group 905 One of source and drain 906 The other of the source and drain 907 Gate electrode 980 Substrate 981 Transistor 1201a Corner 1201b Corner 1201c Corner 1202a Corner 1202b Corner 1202c Corner 2000 Mask pattern 2001 Transistor 2002 Transistor 2003 Transistor 2004 Capacitance element 2005 Resistance element 2100 Mask pattern 2200 Mask pattern 3003 Thickness 3004 Direction 3005 Direction 3011 Wiring 3012 Wiring 3013 Wiring 3014 Contact hole 4402 Second conductive layer 4403 1 conductive layer 4404 wiring 4405 semiconductor layer 4406 impurity region 4407 impurity region 4408 gate insulating layer 4409 gate electrode 4410 impurity region 4411 impurity region 4412 insulating region 7101 insulating substrate 7102 layer 7103 patch antenna 7104 anisotropic conductive adhesive 7113 feeder layer 7181 First antenna 7181a Square coil shape 7181b Square loop shape 7181c Linear dipole shape 7182 Interlayer insulating layer 7183 Insulating layer 7184 Connection terminal 7185 First thin film transistor 7186 Second thin film transistor 8001 First step 8002 Second step 8003 Second 3rd step 8004 4th step 8005 5th step 8011 1st step 8012a 2nd step 8012b 3rd step 8013 Fourth step 8014 Fifth step 8015 Sixth step 9520 Reader / writer 9521 Display unit 9522 Article A
9523 Semiconductor device 9531 Semiconductor device 9532 Article B

Claims (11)

Each of the first shift register to the pth (p is 1), each having one stage or a plurality of cascaded stages, and delaying the input signal in synchronization with the clock signal and outputting from each stage A large natural number) shift register,
A first exclusive OR circuit to a (p-1) th exclusive OR circuit for calculating an exclusive OR of two input signals;
A switching circuit for inputting a data signal, a select signal, and an output of the last stage of the p-th shift register, and switching and outputting one of the first signal and the second signal according to the select signal; ,
The output of the switching circuit is input to the first stage of the first shift register,
In the first to p-th shift registers, the output of the last stage of the r-th (r is a natural number smaller than p) shift register and the output of the switching circuit are the r-th exclusive logic. Input to the sum circuit, and the output of the r-th exclusive OR circuit is input to the first stage of the (r + 1) th shift register,
The first signal is an exclusive OR of the data signal and the output of the final stage of the p-th shift register,
The cyclic redundancy check circuit, wherein the second signal is a logical value of “0”. Each of the first shift register to the pth (p is 1), each having one stage or a plurality of cascaded stages, and delaying the input signal in synchronization with the clock signal and outputting from each stage A large natural number) shift register,
A first exclusive OR circuit to a (p-1) th exclusive OR circuit for calculating an exclusive OR of two input signals;
A switching circuit for inputting a data signal, a select signal, and an output of the last stage of the p-th shift register, and switching and outputting one of the first signal and the second signal according to the select signal; ,
The output of the switching circuit is input to the first stage of the first shift register,
In the first to p-th shift registers, the output of the last stage of the r-th (r is a natural number smaller than p) shift register and the output of the switching circuit are the r-th exclusive logic. Input to the sum circuit, and the output of the r-th exclusive OR circuit is input to the first stage of the (r + 1) th shift register,
The first signal is an exclusive OR of the data signal and the output of the final stage of the p-th shift register,
When the second signal is input to the r-th exclusive OR circuit, the second signal is output from the r-th exclusive OR circuit to the final stage of the r-th shift register. A cyclic redundancy check circuit characterized by being a signal equal to an output. In claim 1 or claim 2,
A determination circuit and a first memory circuit;
The first to p-th shift registers each have s (s is a natural number greater than or equal to p) second storage circuits that store 1-bit signals.
The signals stored in the s second storage circuits are input in parallel to the determination circuit as s-bit outputs,
The cyclic redundancy check circuit according to claim 1, wherein the determination circuit outputs a different signal depending on whether or not the output of the s bits matches a predetermined signal stored in the first storage circuit. A first shift register having five stages connected in cascade, and delaying an input signal in synchronization with a clock signal and outputting from each stage;
A second shift register having seven stages connected in cascade, and delaying an input signal in synchronization with a clock signal and outputting from each stage;
A third shift register having four stages connected in cascade, delaying the input signal in synchronization with the clock signal and outputting from each stage;
A first exclusive OR circuit and a second exclusive OR circuit for calculating an exclusive OR of two input signals;
A switching circuit for inputting a data signal, a select signal, and an output of the fourth stage of the third shift register, and switching and outputting one of the first signal and the second signal according to the select signal; And
The output of the switching circuit is input to the first stage of the first shift register,
The output of the fifth stage of the first shift register and the output of the switching circuit are input to the first exclusive OR circuit, and the output of the first exclusive OR circuit is the second output. Input to the first stage of the shift register,
The output of the seventh stage of the second shift register and the output of the switching circuit are input to the second exclusive OR circuit, and the output of the second exclusive OR circuit is the third output. Input to the first stage of the shift register,
The first signal is an exclusive OR of the data signal and the output of the fourth stage of the third shift register,
The cyclic redundancy check circuit, wherein the second signal is a logical value of “0”. A first shift register having five stages connected in cascade, and delaying an input signal in synchronization with a clock signal and outputting from each stage;
A second shift register having seven stages connected in cascade, and delaying an input signal in synchronization with a clock signal and outputting from each stage;
A third shift register having four stages connected in cascade, delaying the input signal in synchronization with the clock signal and outputting from each stage;
A first exclusive OR circuit and a second exclusive OR circuit for calculating an exclusive OR of two input signals;
A switching circuit for inputting a data signal, a select signal, and an output of the fourth stage of the third shift register, and switching and outputting one of the first signal and the second signal according to the select signal; And
The output of the switching circuit is input to the first stage of the first shift register,
The output of the fifth stage of the first shift register and the output of the switching circuit are input to the first exclusive OR circuit, and the output of the first exclusive OR circuit is the second output. Input to the first stage of the shift register,
The output of the seventh stage of the second shift register and the output of the switching circuit are input to the second exclusive OR circuit, and the output of the second exclusive OR circuit is the third output. Input to the first stage of the shift register,
The first signal is an exclusive OR of the data signal and the output of the fourth stage of the third shift register,
When the second signal is input to the first exclusive OR circuit, the second signal is output from the first exclusive OR circuit to the fifth stage of the first shift register. When the second signal is input to the second exclusive OR circuit, the output of the second exclusive OR circuit is output to the seventh stage of the second shift register. A cyclic redundancy check circuit characterized by being a signal equal to an output. In claim 4 or claim 5,
A determination circuit and a first memory circuit;
Each of the 16 stages included in the first shift register to the third shift register includes a second memory circuit that stores a 1-bit signal;
The signals stored in the first shift register to the third shift register are input to the determination circuit in parallel as a 16-bit output,
The determination circuit outputs a different signal depending on whether or not the 16-bit output matches a predetermined 16-bit signal stored in the first storage circuit. .   A semiconductor device comprising the cyclic redundancy check circuit according to claim 1.   A semiconductor device comprising the cyclic redundancy check circuit according to claim 1, wherein information is transmitted and received wirelessly.   9. The semiconductor device according to claim 8, wherein the semiconductor device is a wireless chip.   An electronic apparatus using the semiconductor device according to claim 7.   A wireless communication system using the semiconductor device according to claim 8.

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