JP2007116591A - Coder, decoder and coding/decoding system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a coder, a decoder and a coding/decoding system which can improve decoding characteristics of an information bit sequence. <P>SOLUTION: Reference bit inserting devices 5-4 and 5-5 insert a plurality of known reference bits into the information bit sequence so that the reference bits may be dispersed in the information bit sequence, thereby generating data after reference bit insertion. Element coders 5-1 and 5-2 generate a parity bit sequence to be added to the information bit sequence from the data after reference bit insertion. On decoding, the reference bits are used as known information about likelihood to decode the coded data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an encoding device, a decoding device, and an encoding / decoding system that realize a low encoding rate with excellent encoding gain.

  The turbo code is an error correction code that can realize transmission characteristics close to the Shannon limit by realistic processing, and is also used in existing cellular systems such as W-CDMA and cdma2000 (for example, Non-Patent Documents 1 and 2). reference). Block diagrams of the turbo code encoder and decoder are shown in FIGS. 9 and 10, respectively. In the encoder shown in FIG. 9, the information bit sequence is input to the element encoder 1-1, and a parity bit sequence 1 is created. At the same time, the information bit sequence is rearranged by a turbo interleaver 1-3 (indicated by π in the figure) and input to the other element encoder 1-2 to create a parity bit sequence 2. The two parity bit sequences are simply multiplexed according to a desired coding rate, or multiplexed after being punctured and multiplexed with the original information bit sequence into the communication channel. Sent out. The configuration of the two element encoders may be the same or different.

  In the decoder shown in FIG. 10, an element decoder 2-1 corresponding to the element encoder 1-1 receives the received bit sequence, performs decoding processing, and outputs reliability information of each information symbol as an external value. The element decoder 2-2 relies on the reliability information output from the element decoder 2-1 (the order is rearranged by the turbo interleaver 2-3) for the received bit sequence whose order is rearranged by the turbo interleaver 2-4. Then, a decoding process is performed using the element decoder 2-2 as a prior value), and a decoding result and reliability information of each information symbol are output.

The obtained reliability information is returned to the original order by the turbo deinterleaver 2-5 (denoted by π-1 in the figure) and then sent to the element decoder 2-1. In the second and subsequent iterations, the element decoder 2-1 executes a decoding process on the received bit sequence using the reliability information from the element decoder 2-2. After the above processing is sufficiently repeated, the decoding result finally output from the element decoder 2-2 is hard-determined and output. As described above, in the turbo decoder, the two element decoders are connected by the bit interleaver, and the reliability information of the bit updated in each element decoder is fed back to the other element decoder. By having a loop, efficient MAP (Maximum A posteriori Probability) decoding is achieved.
3GPP, TS25.212 Version 5.1.0, “Multiplexing and channel coding (FDD),” June 2002. 3GPP2, C.S0024 Version 4.0, “cdma2000 High Rate Packet Data Air Interface Specification,” Oct. 2002.

  However, the above conventional method has the following problems. In order to guarantee the communication quality at the cell edge far away from the base station, it is necessary to reduce the received signal power to noise power ratio to achieve a predetermined error rate. It is conceivable to perform transmission at a conversion rate. A simple method for realizing a low coding rate is to transmit a part of the output sequence of a turbo coder with an original coding rate of 1/3 repeatedly according to a desired coding rate (repetition). (For example, see Non-Patent Document 1).

  FIG. 11 shows an example of a processing procedure when a code with a coding rate of 1/5 is configured using a turbo coder with an original coding rate of 1/3. Parity bit 1 and parity bit 2 as an error correction code are added to the 5-bit information bit sequence 4-1, and encoded data 4-2 is obtained. Parity bit 1 and parity bit 2 are further added to this encoded data 4-2 by repetition, resulting in encoded data 4-3. Although repetition can reduce the received signal power to noise power ratio to achieve a predetermined error rate, there is almost no improvement in characteristic gain due to simple processing of repeatedly transmitting the same bit. On the contrary, the ratio of received signal power to noise power per bit increases.

  The present invention has been made in view of the above-described problems, and provides an encoding device, a decoding device, and an encoding / decoding system capable of improving the decoding characteristics of an information bit sequence. Objective.

  The present invention has been made in order to solve the above-described problem, and first reference bit insertion for generating data after inserting a reference bit by inserting a known reference bit into an information bit sequence composed of a plurality of information bits. And an error correction code generating means for generating an error correction code to be added to the information bit sequence from the data after inserting the reference bits.

  Further, in the encoding device of the present invention, the first reference bit insertion means includes the reference so that one or more information bits exist between the first reference bit after insertion and the last reference bit. It is characterized by inserting a bit.

  In the encoding device of the present invention, when the number of the reference bits to be inserted is larger than the number of the information bits, the first reference bit insertion means prevents the information bits from being continuous. Is inserted.

  In the encoding device of the present invention, when the number of the reference bits to be inserted is equal to or less than the number of the information bits, the first reference bit insertion means prevents the reference bits from being continuous. Is inserted.

  Also, in the encoding device of the present invention, the first reference bit insertion means may perform the reference so that the number of consecutive information bits sandwiched between the reference bits is the same within the same information bit sequence. It is characterized by inserting a bit.

  Further, the present invention generates an error correction code from data after inserting a reference bit in which a known reference bit is inserted into an information bit sequence composed of a plurality of information bits, and adds the error correction code to the information bit sequence. A decoding apparatus for decoding generated encoded data, comprising decoding means for decoding the encoded data using the reference bits as known information on likelihood. It is a decoding device.

  The decoding apparatus of the present invention further comprises second reference bit insertion means for inserting the same reference bit as the known reference bit at the same position with respect to the encoded data, and the decoding means comprises: The encoded data is decoded using the reference bits inserted by the second reference bit insertion means as known information on likelihood.

  In the decoding device of the present invention, the second reference bit insertion means may include the reference so that one or more information bits exist between the first reference bit after insertion and the last reference bit. It is characterized by inserting a bit.

  In the decoding apparatus of the present invention, when the number of reference bits to be inserted is larger than the number of information bits, the second reference bit insertion means prevents the information bits from being continuous. Is inserted.

  In the decoding apparatus of the present invention, when the number of reference bits to be inserted is equal to or less than the number of information bits, the second reference bit insertion means prevents the reference bits from being continuous. Is inserted.

  Further, in the decoding apparatus of the present invention, the second reference bit insertion means may perform the reference so that the number of consecutive information bits sandwiched between the reference bits is the same within the same information bit sequence. It is characterized by inserting a bit.

  The present invention also provides an encoding / decoding system including the encoding device and the decoding device.

  According to the present invention, decoding is performed by inserting a known reference bit group into an information bit sequence and performing encoding, and using the reference bit as known information with a very high likelihood at the time of decoding. The effect that can be improved is obtained.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of a turbo code encoder (encoder) according to an embodiment of the present invention. Compared with the conventional turbo code encoder (FIG. 9), reference bit inserters (reference bit inserters 5-4 and 5-1-2) are provided immediately before each element encoder (element encoders 5-1 and 5-2). 5) is provided. A turbo interleaver 5-3 is provided in front of the reference bit inserter 5-5, and an information bit sequence input to the reference bit inserter 5-4 and information input to the reference bit inserter 5-5. The input order of bit sequences is different. In FIG. 1, the configuration of adding the parity bit sequence output from each element encoder to the information bit sequence is omitted as in FIG. 9, but can be configured by a known technique. .

  Hereinafter, the encoding procedure will be described with reference to FIGS. 3 and 5. FIG. 3 is a flowchart showing a processing procedure in the encoder (reference bit inserter and element encoder). First, a reference bit group is inserted at an arbitrary position in the information bit sequence by the reference bit inserter (step 8-1). Subsequently, the information bit sequence and the inserted reference bit group are collectively encoded by the element encoder, and a parity bit sequence corresponding to the input is generated (step 8-2). Only the information bit sequence and the parity bit sequence are actually transmitted to the communication path, and the reference bit group is removed before transmission (step 8-3).

  FIG. 5 shows an example of a processing procedure when a code with a coding rate of 1/5 is configured using a turbo coder with an original coding rate of 1/3. A reference bit group is inserted into the 5-bit information bit sequence 10-1, resulting in a bit sequence 10-2 (data after reference bit insertion). Parity bit 1 and parity bit 2 as error correction codes are added to this bit sequence 10-2 to become encoded data 10-3. The reference bit group is removed from the encoded data 10-3 to become encoded data 10-4. 3 and 5 show the procedure of adding the parity bit sequence to the data after inserting the reference bit and finally removing the reference bit. As shown in FIG. 1, the information bit sequence and the parity not including the reference bit are shown. The bit sequence may be output independently, and finally the parity bit sequence may be added to the information bit sequence.

  The reference bit inserted by the reference bit inserter may be “0” or “1”, but it is assumed that “0” or “1” is known. The number of reference bits to be inserted is determined according to a desired coding rate. If the information bit length is x, the encoding rate of the original encoder is R, and the desired encoding rate is R ′, the number of reference bits to be inserted is x · (R−R ′) / {R ′ (1 -R)}. For example, when using a turbo encoder with an original coding rate of 1/3 as shown in FIG. 5, if 5 reference bits are inserted for an information length of 5, a code with an encoding rate of 1/5 is constructed. Can do.

  In this embodiment, the reference bit inserter does not add the entire reference bit group before or after the information bit sequence, but inserts it in a distributed manner in the information bit sequence. A part of the reference bit group may be added before or after the information bit sequence and the rest may be inserted into the information bit sequence (see, for example, FIG. 5). When the number of reference bits to be inserted is larger than the number of information bits, the reference bit inserter ensures that the information bits are not consecutive (that is, the number of information bits sandwiched between the reference bits is only 1). Insert a reference bit. The reference bit inserter inserts the reference bits in a distributed manner so that the variation in the number of consecutive reference bits is within 50% (preferably within 20%). The variation in the number of bits is the difference between the maximum number of consecutive bits and the minimum number of bits, and the reference bit is inserted so that this is within 50% (preferably within 20%) of the maximum number of bits. . In particular, it is more desirable that the number of consecutive reference bits be the same within the same information bit sequence.

  When the number of reference bits to be inserted is equal to or less than the number of information bits, the reference bit inserter always ensures that the reference bits are not continuous (that is, the number of reference bits sandwiched between information bits is only 1). To) insert a reference bit. The reference bit inserter inserts information bits in a distributed manner so that the variation in the number of consecutive information bits is within 50% (preferably within 20%). The variation in the number of bits is the same as described above. If the above conditions are satisfied, the insertion position of the reference bits is arbitrary, but the information bits are equally spaced (that is, the number of consecutive information bits sandwiched between the reference bits is the same within the same information bit sequence) Is more desirable.

  FIG. 2 shows a configuration of a turbo code decoder (decoding device). Compared with a conventional turbo code decoder (FIG. 10), reference bit inserters (reference bit inserters 6-6 and 6-6) are provided immediately before each element decoder (element decoders 6-1 and 6-2). 7) is provided. However, the reference bit inserter 5-4 provided in front of the element encoder 5-1 and the reference bit inserter 6-6 provided in front of the element decoder 6-1 are the same. The reference bit inserter 5-5 provided before the encoder 5-2 and the reference bit inserter 6-7 provided before the element decoder 6-2 are the same. Here, the same means that the same number of the same bits are inserted at the same position in the inputted information bit series.

  In FIG. 2, encoded data that is encoded by generating an error correction code from data after reference bit insertion in which a known reference bit is inserted into an information bit sequence, and adding the error correction code to the original information bit sequence Are input to the decoder. Among these, the channel values of both the information bit sequence and the parity bit sequence 1 are input to the reference bit inserter 6-6. Further, the channel values of both the information bit sequence and the parity bit sequence 2 are input to the reference bit inserter 6-7 via the turbo interleaver 6-4. The reference bit inserter 6-6 inserts the same reference bit group as the reference bit group inserted by the element encoder 5-1 at the same insertion position, and outputs the same to the element decoder 6-1. Similarly, the reference bit inserter 6-7 inserts the same reference bit group as the reference bit group inserted by the element encoder 5-2 at the same insertion position, and outputs it to the element decoder 6-2.

  When the decoding process is first performed by the element decoder 6-1, the prior value of the information bits is set to “1/2” (log likelihood is 0). As a result, the external value and posterior value of the information bit sequence are calculated. However, generally, at this stage, only the external value is used for the next processing. The external values output from the element decoder 6-1 are rearranged in order by the turbo interleaver 6-3, and then input to the element decoder 6-2 as prior values.

  The element decoder 6-2 outputs an external value and a posterior value of the information bit sequence as a result of the decoding process. The external value output from the element decoder 6-2 is returned to the original order by the turbo deinterleaver 6-5, and then input to the element decoder 6-1 as a prior value. In the second and subsequent iterations, the element decoder 6-1 executes the received bit sequence decoding process using the prior value from the element decoder 6-2.

  FIG. 4 is a flowchart showing a processing procedure in the decoder (reference bit inserter and element encoder). In the decoder, the reference bit group inserted by the encoder is reinserted by the reference bit inserter with the insertion position and value already known (step 9-1). The element decoder uses each reference bit as known information with very high likelihood, and decodes the information bit sequence (step 9-2). After iterative decoding processing using a feedback loop between two element decoders is performed, bit determination is performed by hard decision, and a received information bit sequence is output (step 9-3).

Hereinafter, the decoding procedure in step 9-2 in FIG. 4 will be described with reference to FIG. Each element decoder estimates a received sequence based on the trellis diagram shown in FIG. FIG. 6 shows a case where the number of register states is 4, for example. In the state “x”, the branch metric r ⁱ _{x, y} when “y” is input as the i-th bit of the reception sequence is obtained from the channel value input from the demodulator and the other element decoder. It is calculated using a prior value to be fed back. The larger the value of r ⁱ _{x, y,} the higher the probability of going through that branch. When a normal information bit is received as the i-th bit, “0” or “1” may be input for each of the four states, so the element decoder is set as r ⁱ _{x, y} Eight values are calculated and used to calculate the likelihood of whether the i-th bit is “0” or “1”.

Assume that a reference bit “0” is input as the i + 1th bit. At this time, it is not necessary to consider the branch metric corresponding to bit “1”, and only the branch metric corresponding to bit “0” needs to be considered. For example, as a specific process, when calculating r ^{i + 1} _{x, 0} (y = 1,2,3,4), substitute a very large likelihood value ∞ as a channel value input from the demodulator. For example, only the branch corresponding to bit “0” survives as a candidate. Conversely, when the reference bit “1” is input, when calculating r ^{i + 1} _{x, 1} (y = 1, 2, 3, 4), the communication channel value input from the demodulator Is substituted with a large likelihood value ∞, leaving only the branch corresponding to bit “1” as a candidate. In this way, when reference bits are input, half of the branches need only be considered in comparison with normal information bits, the number of surviving effective paths when decoding the entire received sequence can be limited, and information bits The decoding characteristics of the sequence are improved. The decoding algorithm of the present embodiment is applicable to any of “Maximum A posteriori Probability (MAP) decoding”, “Log-MAP decoding”, and “Max Log-MAP decoding”.

  FIG. 7 shows the characteristics of the transmission error rate in OFDM transmission using turbo demodulation according to this embodiment. The simulation conditions are summarized in FIG. The original coding rate of the turbo encoder is 1/3, and codes of 1/4 and 1/5 are constructed using the method of repetition and the method of inserting reference bits, and each code per bit The frame error rate for the received signal power to noise power ratio was calculated. In the conventional repetition method, the characteristics are degraded as compared with the coding rate of 1/3. On the other hand, it is understood that the characteristics are improved by using the reference bit insertion method according to the present embodiment.

  According to the above-described embodiment, turbo coding is performed by inserting a known reference bit group into an information bit sequence, and at the time of decoding, a reference bit is used as known information having a very high likelihood, thereby generating an information bit. It can be expected that the decoding characteristics of the sequence are improved. Furthermore, since the reference bit group is not transmitted on the propagation path, and only the information bit sequence and the parity bit sequence are transmitted, a coding rate lower than the coding rate of the original encoder can be efficiently realized. As a result, the required signal-to-noise power ratio to achieve the desired frame error rate can be reduced under the poor signal-to-noise power ratio that must be transmitted at a low coding rate. High communication can be performed. In addition, the encoding device and the decoding device according to the present embodiment can be realized by adding a few functional means to the configuration of a conventional apparatus that handles turbo codes, and in order to realize a low coding rate. There is an advantage that a small circuit scale is required as compared with the case of introducing another new code.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and includes design changes and the like without departing from the gist of the present invention. . For example, an encoding / decoding system including the above-described encoding device and decoding device may be configured. As an example, the present invention can be applied to cellular systems such as W-CDMA and cdma2000.

It is a block diagram which shows the structure of the encoding apparatus by one Embodiment of this invention. It is a block diagram which shows the structure of the decoding apparatus by one Embodiment of this invention. It is a flowchart which shows the procedure of the encoding by one Embodiment of this invention. 5 is a flowchart illustrating a decoding procedure according to an embodiment of the present invention. It is a reference diagram for demonstrating the procedure of the encoding by one Embodiment of this invention. It is a reference figure for demonstrating the procedure of the decoding by one Embodiment of this invention. 5 is a graph showing transmission error rate characteristics according to turbo demodulation according to an embodiment of the present invention and conventional turbo demodulation. FIG. 8 is a reference diagram illustrating conditions for simulation performed to create FIG. 7. It is a block diagram which shows the structure of the conventional encoding apparatus. It is a block diagram which shows the structure of the conventional decoding apparatus. It is a reference figure for demonstrating the procedure of the conventional encoding.

Explanation of symbols

1-1, 1-2, 5-1, 5-2 ... element encoder, 1-3, 2-3, 2-4, 5-3, 6-3, 6-4 ... turbo interleaver 2-1, 2-2, 6-1, 6-2 ... element decoder, 2-5, 6-5 ... turbo deinterleaver, 5-4, 5-5, 6-6, 6 -7 ... Reference bit inserter

Claims (12)

First reference bit insertion means for generating data after inserting a reference bit by inserting a known reference bit into an information bit sequence composed of a plurality of information bits;
An error correction code generating means for generating an error correction code to be added to the information bit sequence from the data after inserting the reference bits;
An encoding device comprising:   The first reference bit insertion means inserts the reference bit so that one or more information bits exist between the first reference bit after insertion and the last reference bit. Item 4. The encoding device according to Item 1.   The first reference bit insertion means inserts the reference bits so that the information bits are not continuous when the number of the reference bits to be inserted is larger than the number of the information bits. The encoding device according to claim 1 or 2.   The first reference bit insertion unit inserts the reference bits so that the reference bits do not continue when the number of the reference bits to be inserted is equal to or less than the number of the information bits. The encoding device according to claim 1 or 2.   The first reference bit insertion means inserts the reference bits so that the number of consecutive information bits sandwiched between the reference bits is the same in the same information bit sequence. The encoding device according to any one of claims 1 to 4. Coded data generated by generating an error correction code from reference bit inserted data obtained by inserting a known reference bit into an information bit sequence composed of a plurality of information bits, and adding the error correction code to the information bit sequence A decryption device for decrypting
A decoding apparatus comprising: decoding means for decoding the encoded data using the reference bits as known information relating to likelihood. A second reference bit insertion means for inserting the same reference bit as the known reference bit at the same position with respect to the encoded data;
The decoding means decodes the encoded data using the reference bits inserted by the second reference bit insertion means as known information relating to likelihood. Decryption device.   The second reference bit insertion means inserts the reference bits so that one or more information bits exist between the first reference bit after insertion and the last reference bit. Item 8. The decoding device according to Item 7.   The second reference bit insertion means inserts the reference bits so that the information bits are not continuous when the number of the reference bits to be inserted is larger than the number of the information bits. The decoding device according to claim 7 or 8.   The second reference bit insertion unit inserts the reference bits so that the reference bits do not continue when the number of the reference bits to be inserted is equal to or less than the number of the information bits. The decoding device according to claim 7 or 8.   The second reference bit insertion means inserts the reference bits so that the number of consecutive information bits sandwiched between the reference bits is the same in the same information bit sequence. The decoding device according to any one of claims 8 to 10. An encoding device comprising: the encoding device according to any one of claims 1 to 5; and the decoding device according to any one of claims 6 to 11. Decryption system.

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