JP2007115809A - Wiring board - Google Patents

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JP2007115809A
JP2007115809A JP2005304092A JP2005304092A JP2007115809A JP 2007115809 A JP2007115809 A JP 2007115809A JP 2005304092 A JP2005304092 A JP 2005304092A JP 2005304092 A JP2005304092 A JP 2005304092A JP 2007115809 A JP2007115809 A JP 2007115809A
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foil
metal foil
wiring
wiring board
hole
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Norihiko Igai
憲彦 猪飼
Toshiya Asano
俊哉 浅野
Satoru Watanabe
渡辺  悟
Kazuhiro Takahashi
一弘 高橋
Tatsuya Hatano
達也 羽田野
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of easy microfabrication of a wiring pattern and prevention of curvature even in a case of using a thin-foil core board. <P>SOLUTION: Metallic foil 2 is inserted between foil core boards 5. Both core insulating layers 3 and 4 comprise a composite material impregnated with a synthetic resin for strengthening a substrate, such as a glass fiber. With such a structure, even if the thickness of the foil core board 5 is thin (0.2-0.6 mm), it is made possible to suppress the curvature of a wiring board 1 on the whole. Furthermore, wiring laminates L1 and L2 wherein a conductive layer and an insulating layer are laminated alternately are formed in both the main surfaces CP1 and CP2 of the foil core boards 5. Since a glass fiber or the like is not contained in this insulating layer, it is easy to form a fine via. It becomes easy to form a fine wiring pattern by using a semi additive method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、配線基板に関するものである。   The present invention relates to a wiring board.

近年、電子機器における高機能化並びに軽薄短小化の要求により、ICチップやLSI等の電子部品では高密度集積化が急速に進んでおり、これに伴い、電子部品を搭載するパッケージ基板には、従来にも増して高密度配線化及び多端子化が求められている。   In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

このようなパッケージ基板としては、ビルドアップ多層配線基板が採用されている。ビルドアップ多層配線基板とは、補強繊維に樹脂を含浸させた絶縁性のコア基板(FR−4等のガラスエポキシ基板)のリジッド性を利用し、その両主表面上に、高分子材料からなる絶縁体層と導体層とを交互に積層したものである。このようなビルドアップ多層配線基板では、ビルドアップ層において高密度配線化が実現されており、一方、コア基板は補強の役割を果たす。そのため、コア基板は、ビルドアップ層と比べて非常に厚く構成され、またその内部にはそれぞれの主表面に配されたビルドアップ層間の導通を図るための配線(スルーホール導体と呼ばれる)が厚さ方向に貫通形成されている。ところが、使用する信号周波数が1GHzを超える高周波帯域となってきた現在では、そのような厚いコア基板を貫通する配線は、大きなインダクタンスとして寄与してしまうという問題がある。   As such a package substrate, a build-up multilayer wiring substrate is employed. The build-up multilayer wiring board uses a rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and is made of a polymer material on both main surfaces thereof. Insulator layers and conductor layers are alternately laminated. In such a build-up multilayer wiring board, high-density wiring is realized in the build-up layer, while the core board plays a reinforcing role. For this reason, the core substrate is configured to be very thick compared to the build-up layer, and the wiring (called a through-hole conductor) for establishing electrical conduction between the build-up layers arranged on the respective main surfaces is thick inside the core substrate. It penetrates in the vertical direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring passing through such a thick core substrate contributes as a large inductance.

そこで、コア基板を薄くすることが考えられたが、薄すぎると剛性を確保できず、反りが発生して配線基板の製造が困難になる問題や、ICチップのアセンブリがしにくくなる問題が生じる。この問題を解決するために、例えば下記特許文献1に開示された配線基板では、厚さ100μm程度の銅板(金属板)をコア基板に用いている。金属板を使用することによって配線基板全体の剛性を確保でき、反りを低減できるようになる。
特開2000−101245号公報
Therefore, it has been considered to make the core substrate thin. However, if the core substrate is too thin, rigidity cannot be ensured, and there arises a problem that it becomes difficult to manufacture a wiring substrate due to warping and a problem that it is difficult to assemble an IC chip. . In order to solve this problem, for example, in the wiring substrate disclosed in Patent Document 1 below, a copper plate (metal plate) having a thickness of about 100 μm is used as the core substrate. By using a metal plate, the rigidity of the entire wiring board can be secured, and the warpage can be reduced.
JP 2000-101245 A

しかしながら上記配線基板では、配線積層部(ビルドアップ層)を構成する絶縁層として、連続多孔質PTFEやガラス繊維等にエポキシ樹脂を含浸させたプリプレグを用いているため、微細なビアを形成することが比較的困難であった。そのため、配線パターンの微細化が容易な配線基板が求められてきた。   However, in the above wiring board, a prepreg obtained by impregnating epoxy resin into continuous porous PTFE or glass fiber is used as the insulating layer constituting the wiring laminated portion (build-up layer), so that a fine via is formed. Was relatively difficult. Therefore, there has been a demand for a wiring board in which the wiring pattern can be easily miniaturized.

本発明は上述のような事情を背景になされたもので、特に、薄いコア基板を使用していても反りにくく、かつ配線パターンの微細化が容易な配線基板を提供することを課題とする。   The present invention has been made in the background as described above. In particular, it is an object of the present invention to provide a wiring board that is less likely to warp even when a thin core board is used and the wiring pattern can be easily miniaturized.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

この発明は、
金属箔と、その金属箔の両主表面に配置され、強化基材に合成樹脂を含浸させた複合材料から構成される第一コア絶縁層および第二コア絶縁層とを含む箔型コア基板と、
強化基材を含有しない非複合材料から構成される絶縁層と、導電性材料からなる導体層とを前記コア基板の両主表面に交互に積層して形成した第一配線積層部および第二配線積層部と、
を備えることを特徴とする配線基板である。
This invention
A foil-type core substrate including a metal foil, and a first core insulating layer and a second core insulating layer which are disposed on both main surfaces of the metal foil and are composed of a composite material in which a reinforced base material is impregnated with a synthetic resin; ,
A first wiring laminated portion and a second wiring formed by alternately laminating an insulating layer made of a non-composite material not containing a reinforced base material and a conductive layer made of a conductive material on both main surfaces of the core substrate A laminated part;
A wiring board comprising:

上記発明によると、金属箔(例えば厚さ25〜100μmの銅箔)を第一および第二コア絶縁層で挟み込んだ箔型コア基板が用いられる。第一および第二コア絶縁層は、ガラス繊維等の強化基材に合成樹脂を含浸させた複合材料から構成される。箔型コア基板の中心には金属箔が位置しているので、箔型コア基板全体の厚さが薄くても比較的高い剛性を確保でき、配線基板の反りを抑制できる。その結果、配線基板を製造しやすくなる。また、ICチップのアセンブリが容易になり、半田バンプの更なる狭ピッチ化に対応することができる。   According to the said invention, the foil type core board | substrate which pinched | interposed metal foil (for example, copper foil of thickness 25-100 micrometers) with the 1st and 2nd core insulating layer is used. The first and second core insulating layers are composed of a composite material obtained by impregnating a reinforcing resin such as glass fiber with a synthetic resin. Since the metal foil is located at the center of the foil-type core substrate, relatively high rigidity can be ensured even if the thickness of the entire foil-type core substrate is thin, and warping of the wiring board can be suppressed. As a result, it becomes easy to manufacture the wiring board. Further, the assembly of the IC chip is facilitated, and it is possible to cope with the further narrowing of the solder bumps.

一方、箔型コア基板の両主表面には、導体層および絶縁層が交互に積層された配線積層部が形成されるのであるが、この絶縁層はガラス繊維等を含まない非複合材料から構成される。そのため、この絶縁層に比較的微細なビアを形成することができ、また、配線積層部の形成工程において周知のセミアディティブ法を利用できるので、配線パターンの微細化が容易になる。   On the other hand, on both main surfaces of the foil-type core substrate, a wiring laminated portion in which conductor layers and insulating layers are alternately laminated is formed. This insulating layer is made of a non-composite material that does not contain glass fibers or the like. Is done. Therefore, relatively fine vias can be formed in this insulating layer, and a well-known semi-additive method can be used in the process of forming the wiring laminated portion, thereby facilitating the miniaturization of the wiring pattern.

従来の配線基板(例えば特許文献1)では、金属箔の両面に積層される絶縁層の全てが複合材料(ガラス繊維や連続多孔質PT等の強化基材に合成樹脂を含浸させたもの)から構成されていた。そのため配線基板全体としての剛性が高く、反りにくいものであった。しかしながら本発明のように、配線積層部を構成する絶縁層に強化基材が含まれていない場合は、全体の剛性が低いので、反り応力に弱い。そのため、金属箔を入れることによって箔型コア基板の剛性を高める効果が特に顕著に現れる。   In the conventional wiring board (for example, Patent Document 1), all of the insulating layers laminated on both surfaces of the metal foil are made of a composite material (a reinforced base material such as glass fiber or continuous porous PT impregnated with a synthetic resin). Was composed. Therefore, the rigidity of the entire wiring board is high, and it is difficult to warp. However, as in the present invention, when the insulating layer constituting the wiring laminated portion does not include a reinforced base material, the overall rigidity is low, so that it is vulnerable to warping stress. Therefore, the effect of increasing the rigidity of the foil-type core substrate by inserting the metal foil is particularly remarkable.

なお、箔型コア基板の厚さは0.2〜0.6mmとするとよい。その理由は、0.2mm未満だと薄すぎて、金属箔を入れたとしても反りが生じやすくなり、また、0.6mmを超えるとインダクタンスが高くなって高周波数に適さなくなるためである。より望ましい厚さは0.25〜0.55mmであり、更に望ましくは0.3〜0.5mmである。   Note that the thickness of the foil-type core substrate is preferably 0.2 to 0.6 mm. The reason is that if it is less than 0.2 mm, it is too thin, and even if a metal foil is inserted, warpage is likely to occur, and if it exceeds 0.6 mm, the inductance becomes high and becomes unsuitable for high frequencies. A more desirable thickness is 0.25 to 0.55 mm, and further desirably 0.3 to 0.5 mm.

一方、上記金属箔は、GNDに接続したり、電源供給部として利用したりできるのであるが、その場合、箔型コア基板に形成したスルーホール導体(第一、第二配線積層部を接続する導体)が金属箔に接触してしまう問題がある。この問題を解決するには、以下の構成を採用するとよい。すなわち、
前記金属箔の所定位置に形成された金属箔貫通孔と、
前記箔型コア基板に貫通形成され、前記第一配線積層部および第二配線積層部を電気的に接続するとともに、前記金属箔貫通孔の内側に位置して、前記金属箔から絶縁されているスルーホール導体と、
を備える配線基板。
On the other hand, the metal foil can be connected to GND or used as a power supply unit. In that case, the through-hole conductors formed on the foil-type core substrate (to connect the first and second wiring laminated portions). There is a problem that the conductor) contacts the metal foil. In order to solve this problem, the following configuration may be employed. That is,
A metal foil through hole formed in a predetermined position of the metal foil;
It is formed through the foil-type core substrate, electrically connects the first wiring laminated portion and the second wiring laminated portion, and is located inside the metal foil through hole and insulated from the metal foil. Through-hole conductors,
A wiring board comprising:

なお、本発明では、箔型コア基板が薄くても反りが生じにくいので、製造工程中でスルーホールを形成する際、複数枚の箔型コア基板を重ねてドリル等により一気に穿孔加工できる。そのため、製造コストを低減できる効果もある。   In the present invention, even if the foil-type core substrate is thin, warpage is unlikely to occur. Therefore, when forming a through hole in the manufacturing process, a plurality of foil-type core substrates can be stacked and drilled at once. Therefore, there is an effect that the manufacturing cost can be reduced.

また、前記金属箔の厚さは25〜100μmにするとよい。その理由は、金属箔の厚さが25μm未満になると反りが発生しやすくなり、100μmを超えると、後述する製造工程において上記金属箔貫通孔をエッチング形成しにくくなるためである。金属箔の厚さは、より好ましくは25〜75μmであり、更に好ましくは30〜50μmである。   The thickness of the metal foil is preferably 25 to 100 μm. The reason is that warpage is likely to occur when the thickness of the metal foil is less than 25 μm, and when the thickness exceeds 100 μm, it is difficult to etch the metal foil through-holes in the manufacturing process described later. The thickness of metal foil becomes like this. More preferably, it is 25-75 micrometers, More preferably, it is 30-50 micrometers.

本発明の実施形態を、図面を参照しながら以下に説明する。
図1に、本発明に係る配線基板1の模式断面図を示す。このように、配線基板1は金属箔2と、その金属箔2の両主表面MP1,MP2に配置された第一コア絶縁層3および第二コア絶縁層4を備え、これら金属箔2および第一、第二コア絶縁層3、4によって箔型コア基板5が構成されている。箔型コア基板5全体の厚さは0.2〜0.6mmとされ、金属箔2の厚さは25〜100μmにされている。金属箔2としては、銅箔が好適に用いられる。また、第一、第二コア絶縁層3、4はともに、ガラス繊維やPTFE(フッ素樹脂)、アラミド繊維などの強化基材に合成樹脂(例えばエポキシ樹脂)を含浸させた複合材料によって構成されている。
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a schematic cross-sectional view of a wiring board 1 according to the present invention. As described above, the wiring substrate 1 includes the metal foil 2 and the first core insulating layer 3 and the second core insulating layer 4 disposed on both main surfaces MP1 and MP2 of the metal foil 2, The foil-type core substrate 5 is constituted by the first and second core insulating layers 3 and 4. The entire thickness of the foil-type core substrate 5 is 0.2 to 0.6 mm, and the thickness of the metal foil 2 is 25 to 100 μm. As the metal foil 2, a copper foil is suitably used. The first and second core insulating layers 3 and 4 are both composed of a composite material obtained by impregnating a reinforced base material such as glass fiber, PTFE (fluorine resin), or aramid fiber with a synthetic resin (for example, epoxy resin). Yes.

一方、箔型コア基板5の第一主表面CP1には絶縁層V1,V2および導体層M1〜M3を交互に積層した第一配線積層部L1が形成され、第二主表面CP2には絶縁層V11,V12および導体層M11〜M13を交互に積層した第二配線積層部L2が形成されている。第一配線積層部L1の絶縁層V1,V2と、第二配線積層部L2の絶縁層V11,V12はともに、ガラス繊維などの強化基材を含まない合成樹脂(非複合材料)から構成されている。   On the other hand, the first main surface CP1 of the foil-type core substrate 5 is formed with a first wiring laminated portion L1 in which insulating layers V1 and V2 and conductor layers M1 to M3 are alternately laminated, and the second main surface CP2 has an insulating layer. A second wiring laminated portion L2 in which V11, V12 and conductor layers M11 to M13 are alternately laminated is formed. Both the insulating layers V1 and V2 of the first wiring laminated portion L1 and the insulating layers V11 and V12 of the second wiring laminated portion L2 are made of a synthetic resin (non-composite material) that does not include a reinforced base material such as glass fiber. Yes.

後述するように、配線基板1を製造する工程においては、箔型コア基板5の両主表面CP1,CP2に導体層および絶縁層を順次積層していくのであるが、この際に熱が加わるため、冷却した時に、第一配線積層部L1と第二配線積層部L2との間の配線密度の差によって熱収縮率の差が生じ、箔型コア基板5に反り応力が加わる。しかしながら本発明では箔型コア基板に金属箔2を挿入しているので、このような反り応力が生じたとしても、基板全体が反りにくくなるのである。そのため、製造工程において反った基板が他の装置に接触するなどの不具合を未然に防止できる。従来は、このような薄コア品を製造する場合には、反りが生じることを前提とした専用ライン(薄コア専用ライン)を利用せざるを得なかったが、本発明により、厚コア品のように反りが生じにくい製品を製造するライン(厚コア用ライン)を利用することも可能となり、従って、工場の稼動効率を上げることが可能となる。   As will be described later, in the process of manufacturing the wiring substrate 1, a conductor layer and an insulating layer are sequentially laminated on both main surfaces CP1 and CP2 of the foil-type core substrate 5, but heat is applied at this time. When cooled, a difference in thermal shrinkage occurs due to a difference in wiring density between the first wiring laminated portion L1 and the second wiring laminated portion L2, and warping stress is applied to the foil-type core substrate 5. However, in the present invention, since the metal foil 2 is inserted into the foil-type core substrate, even if such warping stress is generated, the entire substrate is hardly warped. Therefore, it is possible to prevent problems such as the substrate warped in the manufacturing process coming into contact with another device. Conventionally, when manufacturing such a thin core product, it has been necessary to use a dedicated line (thin core dedicated line) based on the assumption that warpage occurs. Thus, it is possible to use a line (thick core line) for producing a product that is unlikely to warp, and thus it is possible to increase the operating efficiency of the factory.

なお、従来の技術(例えば上記特許文献1)では絶縁層V1〜V12も複合材料を使用していたため、第一、第二配線積層部L1,L2の剛性が比較的高くされていた。しかしながら本発明では絶縁層V1〜V12を非複合材料としているため、第一、第二配線積層部L1,L2の剛性が比較的低く、従って、金属箔2を挿入する効果が特に顕著に現れる。   In the conventional technique (for example, Patent Document 1), since the insulating layers V1 to V12 also use composite materials, the rigidity of the first and second wiring laminated portions L1 and L2 is relatively high. However, since the insulating layers V1 to V12 are made of non-composite materials in the present invention, the rigidity of the first and second wiring laminated portions L1 and L2 is relatively low, and thus the effect of inserting the metal foil 2 is particularly noticeable.

上述したように、箔型コア基板5の全体の厚さは0.2〜0.6mmにされている。その理由は、0.2mm未満だと薄すぎて、金属箔2を入れていたとしても反りが生じやすくなり、また、0.6mmを超えるとインダクタンスが高くなるので、高周波数に適さなくなるためである。また、金属箔2の厚さは25〜100μmとされている。その理由は、25μm未満になると反りが発生しやすくなり、100μmを超えると、後述する製造工程において金属箔貫通孔13をエッチング形成しにくくなるからである。   As described above, the entire thickness of the foil-type core substrate 5 is set to 0.2 to 0.6 mm. The reason is that if it is less than 0.2 mm, it is too thin, and even if the metal foil 2 is inserted, warping is likely to occur, and if it exceeds 0.6 mm, the inductance becomes high, so it is not suitable for high frequencies. is there. Moreover, the thickness of the metal foil 2 is 25-100 micrometers. The reason is that warpage tends to occur when the thickness is less than 25 μm, and when the thickness exceeds 100 μm, it is difficult to form the metal foil through hole 13 by etching in the manufacturing process described later.

配線基板1の構造について更に詳細に説明する。箔型コア基板5にはドリルやレーザなどによりスルーホール6a,6bが貫通形成され、その内壁面にはコア導体層M1,M11を互いに導通させるスルーホール導体7a,7bが形成されている。より詳しくは、金属箔2には所定位置に金属箔貫通孔13が形成され、第一スルーホール6aはその金属箔貫通孔13が形成された位置に、箔型コア基板5を貫通するように形成されている。第一スルーホール6aの直径は金属箔貫通孔13の直径よりも小さくされており、第一スルーホール6aの内周面が金属箔貫通孔13の内周面に接触しないようになっている。これにより、第一スルーホール導体7aを金属箔2から絶縁することができる。一方、第二スルーホール導体7bは金属箔2と接続されている。すなわち、金属箔2をGNDに接続したり、電源供給部として使用したりできるのであるが、その場合、第二スルーホール導体7bは金属箔2と同電位に固定される。   The structure of the wiring board 1 will be described in more detail. Through-holes 6a and 6b are formed through the foil-type core substrate 5 by a drill, a laser, or the like, and through-hole conductors 7a and 7b for connecting the core conductor layers M1 and M11 to each other are formed on the inner wall surfaces thereof. More specifically, the metal foil 2 has a metal foil through hole 13 formed at a predetermined position, and the first through hole 6a passes through the foil core substrate 5 at the position where the metal foil through hole 13 is formed. Is formed. The diameter of the first through hole 6 a is smaller than the diameter of the metal foil through hole 13 so that the inner peripheral surface of the first through hole 6 a does not contact the inner peripheral surface of the metal foil through hole 13. Thereby, the first through-hole conductor 7a can be insulated from the metal foil 2. On the other hand, the second through-hole conductor 7 b is connected to the metal foil 2. That is, the metal foil 2 can be connected to GND or used as a power supply unit. In this case, the second through-hole conductor 7b is fixed at the same potential as the metal foil 2.

また、コア導体層M1,M11の上層には、非複合材料(例えばエポキシ樹脂)からなる第一絶縁層V1,V11がそれぞれ形成されている。さらに、その表面には配線パターンを構成する第一導体層M2,M12がCuメッキにより形成されている。コア導体層M1,M11と第一導体層M2,M12は、それぞれビア12により層間接続がなされている。ビア12は、ビアホール12hと、その内周面に設けられたビア導体12sと、底面側にてビア導体12sと導通するように設けられたビアパッド12pとを有している。   In addition, first insulating layers V1 and V11 made of a non-composite material (for example, epoxy resin) are formed on the core conductor layers M1 and M11, respectively. Further, first conductor layers M2 and M12 constituting a wiring pattern are formed on the surface by Cu plating. The core conductor layers M1 and M11 and the first conductor layers M2 and M12 are interconnected by vias 12, respectively. The via 12 has a via hole 12h, a via conductor 12s provided on the inner peripheral surface thereof, and a via pad 12p provided so as to be electrically connected to the via conductor 12s on the bottom surface side.

また、第一導体層M2,M12の上層には、非複合材料からなる第二絶縁層V2,V12が形成され、その表面には第二導体層M3,M13によってパッド9,11が形成されている。第二絶縁層V2,V12の表面はソルダーレジストSR1,SR11が被覆しており、各パッド9,11を個別に露出するための開口部17が形成されている。一方、パッド9には、ICチップ等との接続をするための半田バンプ10が形成されている。パッド11はマザーボード等にピングリッドアレイ(PGA)あるいはボールグリッドアレイ(BGA)により接続するために用いられる。パッド9,11は、図2A,Bに示すように、それぞれ格子状に配置されている。   In addition, second insulating layers V2 and V12 made of a non-composite material are formed on the first conductor layers M2 and M12, and pads 9 and 11 are formed on the surface by the second conductor layers M3 and M13. Yes. The surfaces of the second insulating layers V2 and V12 are covered with solder resists SR1 and SR11, and openings 17 for individually exposing the pads 9 and 11 are formed. On the other hand, solder bumps 10 for connection to an IC chip or the like are formed on the pads 9. The pad 11 is used for connecting to a motherboard or the like by a pin grid array (PGA) or a ball grid array (BGA). As shown in FIGS. 2A and 2B, the pads 9 and 11 are arranged in a grid pattern.

次に、本発明に係る配線基板1の製造方法を、図3〜図5の工程図を用いて説明する。まず、図3Aに示すように金属箔2を用意し、一方の主表面MP1にフォトレジスト14を塗布して所定パターンを形成するとともに、他方の主表面MP2に保護樹脂層15を塗布する(図3B)。その後、ウエットエッチングにより金属箔貫通孔13をエッチング形成し、フォトレジスト14および保護樹脂層15を除去する(図3C,D)。上述したように、金属箔2の厚さは100μm以下にされているので、無理なくエッチング処理できる。その後、ガラス繊維にエポキシ樹脂を含浸させた複合材料(プリプレグ)および銅箔を重ね、真空熱プレス機(図示しない)によって熱圧着することにより、第一、第二コア絶縁層3,4および銅箔Cu1,Cu2を形成する。金属箔貫通孔13の内部は、複合材料から染み出したエポキシ樹脂が充填される(図3E)。   Next, the manufacturing method of the wiring board 1 which concerns on this invention is demonstrated using process drawing of FIGS. First, as shown in FIG. 3A, a metal foil 2 is prepared, a photoresist 14 is applied to one main surface MP1 to form a predetermined pattern, and a protective resin layer 15 is applied to the other main surface MP2 (FIG. 3A). 3B). Thereafter, the metal foil through holes 13 are formed by wet etching, and the photoresist 14 and the protective resin layer 15 are removed (FIGS. 3C and 3D). As described above, since the thickness of the metal foil 2 is 100 μm or less, the etching process can be performed without difficulty. Thereafter, a composite material (prepreg) in which glass fiber is impregnated with an epoxy resin and a copper foil are stacked, and thermocompression bonded by a vacuum hot press machine (not shown), whereby the first and second core insulating layers 3 and 4 and copper The foils Cu1 and Cu2 are formed. The inside of the metal foil through-hole 13 is filled with an epoxy resin that has exuded from the composite material (FIG. 3E).

続いて、ドリルまたはレーザを用いて、箔型コア基板5の所定位置にスルーホール6a,6bを穿孔する(図3F)。スルーホール6aの直径は金属箔貫通孔13の直径よりも小さくされており、かつ、内周面から金属箔2が露出しないように、スルーホール6aの位置決めがされている。この工程では、箔型コア基板5の厚さが十分薄いので、複数枚(例えば2、3枚)の箔型コア基板5を重ね、まとめて穿孔することができる。その後、周知のサブトラクティブ法によりコア導体層M1,M11の導体パターンおよびスルーホール導体7a,7bを形成する(図4G)。すなわち、無電解銅めっき処理を行うことにより銅箔Cu1,Cu2およびスルーホール6a,6b内に無電解銅めっき層を形成し、その後、フォトレジストを塗布して所定パターンを露光形成する。そして、無電解銅めっき層を共通電極としてフォトレジストの開口部やスルーホール6内部に電解銅めっき処理を施して厚さを増し、その後、フォトレジストを除去して不要な無電解銅めっき層をエッチング除去する。この一連の工程により銅箔Cu1,Cu2は厚さが増してコア導体層M1,M2となる。   Subsequently, through holes 6a and 6b are drilled at predetermined positions of the foil-type core substrate 5 using a drill or a laser (FIG. 3F). The diameter of the through hole 6a is made smaller than the diameter of the metal foil through hole 13, and the through hole 6a is positioned so that the metal foil 2 is not exposed from the inner peripheral surface. In this step, since the thickness of the foil-type core substrate 5 is sufficiently thin, a plurality of (for example, two or three) foil-type core substrates 5 can be stacked and punched together. Thereafter, the conductor patterns of the core conductor layers M1 and M11 and the through-hole conductors 7a and 7b are formed by a known subtractive method (FIG. 4G). That is, an electroless copper plating process is performed to form an electroless copper plating layer in the copper foils Cu1, Cu2 and the through holes 6a, 6b, and then a photoresist is applied to form a predetermined pattern by exposure. Then, using the electroless copper plating layer as a common electrode, the opening of the photoresist and the inside of the through hole 6 are subjected to electrolytic copper plating to increase the thickness, and then the photoresist is removed to form an unnecessary electroless copper plating layer. Etch away. Through this series of steps, the copper foils Cu1 and Cu2 are increased in thickness to become the core conductor layers M1 and M2.

次に、スルーホール導体7a,7bの内部にエポキシ樹脂からなる充填材8を充填し、箔型コア基板5の両主表面MP1,MP2に、強化基材を含まないエポキシ樹脂(非複合材料)を塗布して第一絶縁層V1,V11を形成する(図4H)。その後、レーザにより所定位置にビアホール16を形成する(図5I)。この際、第一絶縁層V1,V11にガラス繊維等が含まれていると、レーザによってガラス繊維を切断するのに大きなエネルギーが必要となり、微細なビアホール16を形成しにくくなったり、ビアホール16の内面をきれいに仕上げるのが難しくなったりする。しかし本発明では、第一絶縁層V1,V11にガラス繊維等が含まれていないため、このような問題が生じにくい。   Next, the inside of the through-hole conductors 7a and 7b is filled with a filler 8 made of an epoxy resin, and the main surfaces MP1 and MP2 of the foil-type core substrate 5 are not filled with an epoxy resin (non-composite material). Is applied to form first insulating layers V1 and V11 (FIG. 4H). Thereafter, a via hole 16 is formed at a predetermined position by a laser (FIG. 5I). At this time, if glass fibers or the like are included in the first insulating layers V1 and V11, a large amount of energy is required to cut the glass fibers by the laser, and it becomes difficult to form the fine via holes 16, It may be difficult to finish the inner surface cleanly. However, in the present invention, since the first insulating layers V1 and V11 do not contain glass fiber or the like, such a problem hardly occurs.

次いで、周知のセミアディティブ法により導体層M2,M12の導体パターンおよびビア12を形成する(図5J)。すなわち、第一絶縁層V1,V11の表面およびビアホール16の内面を粗面化処理した後、無電解銅めっき処理を施して全体に無電解銅めっき層を形成する。そして、フォトレジストを塗布して所定パターンを露光形成する。その後、無電解銅めっき層を共通電極としてフォトレジストの開口やビアホール16の内面に電解銅めっき処理を施して厚さを増し、フォトレジストを除去して不要な無電解銅めっき層をクイックエッチング法により除去する。このようなセミアディティブ法はファインパターンに向いているので、配線の微細化が容易になる。   Next, the conductor patterns M2 and M12 and the vias 12 are formed by a known semi-additive method (FIG. 5J). That is, after the surface of the first insulating layers V1 and V11 and the inner surface of the via hole 16 are roughened, an electroless copper plating process is performed to form an electroless copper plating layer. Then, a photoresist is applied to form a predetermined pattern by exposure. After that, using the electroless copper plating layer as a common electrode, the opening of the photoresist and the inner surface of the via hole 16 are subjected to electrolytic copper plating to increase the thickness, and the photoresist is removed to remove the unnecessary electroless copper plating layer by a quick etching method. To remove. Since such a semi-additive method is suitable for a fine pattern, it is easy to miniaturize wiring.

その後、エポキシ樹脂等を塗布することにより第二絶縁層V2,V12を形成し、レーザを用いて所定位置にビアホールを穿孔した後、セミアディティブ法を再度用いて第二導体層M3,M13の導体パターンを形成する(図5K)。そして、ソルダーレジストS1,S12を塗布し、フォト工程を施して、パッド9,11を個別に露出させる開口部17を形成する。その後、パッド9に半田ペーストをスクリーン印刷し、リフローして半田バンプ10を形成する。このようにして、図1に示す配線基板1が製造される。   Thereafter, the second insulating layers V2 and V12 are formed by applying an epoxy resin or the like, a via hole is drilled at a predetermined position using a laser, and then the conductors of the second conductor layers M3 and M13 are again used by using the semi-additive method. A pattern is formed (FIG. 5K). And solder resist S1, S12 is apply | coated and a photo process is performed, and the opening part 17 which exposes the pads 9 and 11 separately is formed. Thereafter, a solder paste is screen-printed on the pad 9 and reflowed to form solder bumps 10. In this way, the wiring board 1 shown in FIG. 1 is manufactured.

本発明に係る配線基板1の模式断面図である。1 is a schematic cross-sectional view of a wiring board 1 according to the present invention. 配線基板1の(A)表面図(B)裏面図。The wiring board 1 (A) front view (B) back view. (A)〜(E)配線基板1の製造方法を示す図である。(A)-(E) It is a figure which shows the manufacturing method of the wiring board 1. FIG. (F)〜(H)図3に続く図。(F)-(H) The figure following FIG. (I)〜(K)図4に続く図。(I)-(K) The figure following FIG.

符号の説明Explanation of symbols

1 配線基板
2 金属箔
3 第一コア絶縁層
4 第二コア絶縁層
5 箔型コア基板
6 スルーホール
7a,7b スルーホール導体
8 樹脂製充填材
9 パッド
10 半田バンプ
DESCRIPTION OF SYMBOLS 1 Wiring board 2 Metal foil 3 1st core insulating layer 4 2nd core insulating layer 5 Foil type core board 6 Through-hole 7a, 7b Through-hole conductor 8 Resin filler 9 Pad 10 Solder bump

Claims (4)

金属箔と、その金属箔の両主表面に配置され、強化基材に合成樹脂を含浸させた複合材料から構成される第一コア絶縁層および第二コア絶縁層とを含む箔型コア基板と、
強化基材を含有しない非複合材料から構成される絶縁層と、導電性材料からなる導体層とを前記コア基板の両主表面に交互に積層して形成した第一配線積層部および第二配線積層部と、
を備えることを特徴とする配線基板。
A foil-type core substrate including a metal foil, and a first core insulating layer and a second core insulating layer which are disposed on both main surfaces of the metal foil and are composed of a composite material in which a reinforced base material is impregnated with a synthetic resin; ,
A first wiring laminated portion and a second wiring formed by alternately laminating an insulating layer made of a non-composite material not containing a reinforced base material and a conductive layer made of a conductive material on both main surfaces of the core substrate A laminated part;
A wiring board comprising:
前記箔型コア基板は全体の厚さが0.2〜0.6mmである請求項1記載の配線基板。 The wiring board according to claim 1, wherein the foil-type core substrate has an overall thickness of 0.2 to 0.6 mm. 前記金属箔の所定位置に形成された金属箔貫通孔と、
前記箔型コア基板に貫通形成され、前記第一配線積層部および第二配線積層部を電気的に接続するとともに、前記金属箔貫通孔の内側に位置して、前記金属箔から絶縁されているスルーホール導体と、
を備える請求項1または2記載の配線基板。
A metal foil through hole formed in a predetermined position of the metal foil;
It is formed through the foil-type core substrate, electrically connects the first wiring laminated portion and the second wiring laminated portion, and is located inside the metal foil through hole and insulated from the metal foil. Through-hole conductors,
The wiring board according to claim 1, further comprising:
前記金属箔の厚さは25〜100μmである請求項1ないし3のいずれか1項に記載の配線基板。 The wiring board according to claim 1, wherein the metal foil has a thickness of 25 to 100 μm.
JP2005304092A 2005-10-19 2005-10-19 Wiring board Pending JP2007115809A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212116A (en) * 2008-02-29 2009-09-17 Oki Printed Circuits Co Ltd Multilayer printed wiring board
JP2013135229A (en) * 2011-12-22 2013-07-08 Samsung Techwin Co Ltd Manufacturing method of multilayer circuit board and multilayer circuit board manufactured by the same
JP2014003266A (en) * 2012-06-14 2014-01-09 Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd Multilayer electronic support structure with integral metal core
JP2014086651A (en) * 2012-10-26 2014-05-12 Ibiden Co Ltd Printed wiring board and manufacturing method for printed wiring board
JP2016054188A (en) * 2014-09-03 2016-04-14 大日本印刷株式会社 Component build-in wiring board, manufacturing method of the same, and intermediate wiring layer for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261869A (en) * 1997-01-17 1998-09-29 Ibiden Co Ltd Multilayer printed wiring board
JP2002332544A (en) * 2001-05-08 2002-11-22 Hitachi Metals Ltd Metal sheet for metal core base material and its manufacturing method, metal core base material using the same, and build-up printed wiring board
JP2005183466A (en) * 2003-12-16 2005-07-07 Ibiden Co Ltd Multilayer printed wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10261869A (en) * 1997-01-17 1998-09-29 Ibiden Co Ltd Multilayer printed wiring board
JP2002332544A (en) * 2001-05-08 2002-11-22 Hitachi Metals Ltd Metal sheet for metal core base material and its manufacturing method, metal core base material using the same, and build-up printed wiring board
JP2005183466A (en) * 2003-12-16 2005-07-07 Ibiden Co Ltd Multilayer printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009212116A (en) * 2008-02-29 2009-09-17 Oki Printed Circuits Co Ltd Multilayer printed wiring board
JP2013135229A (en) * 2011-12-22 2013-07-08 Samsung Techwin Co Ltd Manufacturing method of multilayer circuit board and multilayer circuit board manufactured by the same
JP2014003266A (en) * 2012-06-14 2014-01-09 Zhuhai Advanced Chip Carriers & Electronic Substrates Solutions Technologies Co Ltd Multilayer electronic support structure with integral metal core
JP2014086651A (en) * 2012-10-26 2014-05-12 Ibiden Co Ltd Printed wiring board and manufacturing method for printed wiring board
JP2016054188A (en) * 2014-09-03 2016-04-14 大日本印刷株式会社 Component build-in wiring board, manufacturing method of the same, and intermediate wiring layer for manufacturing the same

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