JP2007109298A - Synchronization detection method and device, and optical information reproducing device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and a synchronization detection device capable of performing precise synchronization detection even when the recording quality of a synchronous pattern is poor, and to provide an optical information reproducing device using the synchronization detection device. <P>SOLUTION: When the synchronous detection is carried out, a synchronous patten added to an optical disk 501 is detected, and a fixed pattern included before/after the synchronous pattern is detected, then information signals are synchronized based on detected results of the synchronous pattern and the fixed pattern. When the synchronous pattern is detected, a mark having a length nearly equal to a predetermined synchronous pattern is detected. Thus, even when error factors such as a flaw or dusts are caused in the synchronous pattern part of the optical disk, the synchronous detection processing can surely be carried out. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method and apparatus for performing synchronization detection during data reproduction of an optical disk or the like, and an optical information reproduction apparatus using the same.

  Conventionally, information recording media such as CD, MO, and DVD have been widely used. Today, an information recording / reproducing apparatus using a high-density medium such as a Blu-ray Disc apparatus (hereinafter referred to as a BD apparatus) has been put into practical use due to an increase in the amount of information. There is a growing demand for higher speeds. In particular, it is indispensable to further improve the reproduction performance when reproducing a high-density recording medium.

  The technology and physical format used in the BD device are introduced in Royal Philips Electronics, “ODS Optical Data Storage 2003”, Sunday, May, 11, 2003 (Non-Patent Document 1).

  According to “ODS Optical Data Storage 2003”, BD records data in units called RUB (Recording Unit Block). FIG. 13 shows the configuration of the RUB. According to FIG. 13, RUB is comprised from Run-in, Physical Cluster, and Run-out.

  As shown in FIG. 14, Run-in mainly includes a fixed pattern that repeats 3T / 3T / 2T / 2T / 5T / 5T (where “T” indicates a channel clock period). This fixed pattern is a pattern used for the purpose of PLL synchronization processing and data protection. The repetitive fixed pattern includes synchronization signals FS4 and FS6 called frame sync (hereinafter abbreviated as FS). A fixed pattern that repeats twice is included.

  The Physical Cluster is a user data area, and FS0 exists at the head of the Physical Cluster, and a fixed pattern of 3T / 3T / 2T / 2T / 5T / 5T is included between FS6 and FS0. For example, in order to detect the start timing of Physical Cluster, the 9T / 9T synchronization pattern of FS4 and FS6 included in Run-in is detected. Thereafter, the FS detection window is opened, and the 9T / 9T synchronization pattern of FS0 included at the beginning of the Physical Cluster is detected, and data is reproduced.

  Generally, in an information recording / reproducing apparatus, a certain number of data is divided into frames at the time of modulation, and a synchronization pattern indicating a frame break is added to the head of each frame and recorded. At the time of reproduction, the head of the frame can be correctly detected by detecting the synchronization pattern added for each frame at the time of demodulation.

If a reproduction operation is performed without ensuring data synchronization, a read error causes a large burst error over the entire frame or the entire block. Such a large burst error cannot be corrected even by using an error correction technique, and the synchronization pattern detection performance greatly affects the reproduction performance of the optical information recording / reproducing apparatus.
Royal Philips Electronics, “ODS Optical Data Storage 2003”, Sunday, May, 11, 2003

  Since the above-mentioned FS is composed of a relatively simple pattern including 9T / 9T, if the recording quality of the 9T deteriorates due to a defect such as a scratch or dust on the 9T portion, the pseudo-synchronized pattern May be falsely detected. Therefore, there has been a problem that synchronization detection is impossible or synchronization detection accuracy is deteriorated.

  An object of the present invention is to provide a synchronization detection method and apparatus capable of accurately performing synchronization detection even when the recording quality of the synchronization pattern is poor, and an optical information reproducing apparatus using the same.

  In order to solve the above-described problem, the synchronization detection method of the present invention is a method for detecting synchronization of an information signal based on a synchronization pattern added to an information recording medium. At least one fixed pattern inserted later is detected, and the information signal is synchronized from the detection result of the fixed pattern and the detection result of the synchronization pattern.

  The synchronization detection device of the present invention is a device for detecting synchronization of an information signal based on a synchronization pattern added to an information recording medium, and is inserted before or after the synchronization pattern detecting means and the synchronization pattern. And a means for detecting at least one fixed pattern, and means for synchronizing the information signal from the detection result of the fixed pattern detection means and the detection result of the synchronization pattern detection means.

  In the present invention, the synchronization pattern added to the information recording medium at the time of performing synchronization detection is detected, the fixed patterns included before and after the synchronization pattern are detected, and information is detected from the detection results of these synchronization patterns and fixed patterns. Synchronize the signal. When detecting the synchronization pattern, a mark having a length close to a predetermined synchronization pattern is detected as the synchronization pattern.

  By doing so, for example, in the BD device, the synchronization timing of the synchronization pattern included in FS0 in the PhysicalCluster is detected. At the time of detecting synchronization other than FS0 in the Physical Cluster, the synchronization timing is detected using only the synchronization pattern in the FS.

  Therefore, even when the recording quality of 9T in the FS is poor, it is possible to reproduce more accurately than before by increasing the detection accuracy of the first synchronization pattern FS0 in the PhysicalCluster.

  According to the present invention, by performing synchronization detection from the detection result of the synchronization pattern and the fixed pattern, it is possible to accurately perform synchronization detection even when the recording quality of the synchronization pattern is poor. Therefore, even if an error factor such as a scratch or dust occurs in the synchronization pattern portion of the information recording medium, the synchronization detection process can be reliably performed, and the reliability of the information reproduction system can be improved.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing an embodiment of an optical information recording / reproducing apparatus according to the present invention. In the figure, reference numeral 501 denotes an optical disk as an information recording medium, 502 denotes an optical head for recording or reproducing information on the optical disk 501, and 503 denotes a spindle motor for rotating the optical disk 501. Reference numeral 504 denotes an RF preamplifier that amplifies the reproduction signal, 505 denotes an AGC filter, and 506 denotes an A / D conversion circuit that digitizes the reproduction signal.

  Further, reference numeral 507 denotes a waveform equalization circuit, 508 denotes a Viterbi decoder, 509 denotes a wobble detection unit, 510 denotes a data area detection unit, 511 denotes a data area control unit, 512 denotes first synchronization detection means, and 513 denotes second synchronization. Detection means 514 is a demodulation circuit. Note that a servo control circuit that performs focus control, tracking control, and the like is omitted.

  The optical disk 501 is rotated by the drive of the spindle motor 503, irradiates the optical disk 501 with laser light from a laser light source (not shown) from the optical head 502, and receives the return light again by an optical sensor (not shown) in the optical head. The reproduction signal from the optical sensor is amplified by the RF amplifier 504, and further, the AGC filter 505 performs gain control and band limitation to a predetermined level.

  The analog reproduction signal input in the A / D conversion circuit 506 is converted into a digital signal and input to the waveform equalization circuit 507. A waveform equalization circuit 507 performs signal waveform equalization. In addition, a clock component synchronized with the reproduction signal is generated by a PLL circuit (not shown). A signal from the waveform equalization circuit 507 is input to the Viterbi decoder 508, and the data binarized by the Viterbi decoder 508 is input to the first synchronization detection means 512, the second synchronization detection means 513, and the demodulation circuit 514. Entered.

  A wobble detection unit 509 detects a meandering component of the guide groove of the optical disc from a signal received by an optical sensor (not shown) in the optical head 502. Specifically, the reflected light from the optical disc 501 is detected by at least two light receiving elements divided along the guide groove of the optical disc 501. The difference signal between the two light receiving elements is called a push-pull signal, which is a signal reflecting the wobble component.

  In the BD, tracks for recording data are formed in advance as pregrooves, and the side walls of the pregroup meander with wobble signals obtained by modulating address information and the like. A wobble address can be read from wobble information obtained as reflected light information during recording or reproduction. In the BD, an address system called ADIP (Address in Pregroove) is adopted, and the side wall of the pregroove is wobbled corresponding to the address information so that data can be recorded or reproduced at a predetermined position.

  The data area detection unit 510 detects a wobble address from the wobble signal detected by the wobble detection unit 509, and counts the counter value of the ADIP unit and the wobble counter value in the ADIP unit that constitute the address information of the BD. Thereby, it is possible to detect the timing at which the Run-in area starts, and it is detected whether the reproduction part of the optical disc 501 is the Run-in area or the user data area. The area information from the data area detection unit 510 is output to the data area control unit 511.

  The data area control unit 511 switches between the first synchronization detection unit 512 and the second synchronization detection unit 513 based on the area information from the data area detection unit 510 and outputs one of the output signals to the demodulation circuit 514. The demodulated data of the demodulation circuit 514 is synchronized by a signal from the data area control unit 511.

  At this time, if the reproduction part of the optical disc 501 is the Run-in area, a signal from the first synchronization detection means 512 is output, and if it is outside the Run-in area, the second synchronization detection means 513 outputs. Is output.

  Hereinafter, when the reproduction signal is detected to be in the Run-in area and the processing of the first synchronization detection unit 512 is executed, and when the reproduction signal is detected to be outside the Run-in area, the second synchronization detection unit is detected. This will be described separately for the case where the process 513 is executed.

(Processing by the first synchronization detecting means 512)
FIG. 2 is a block diagram showing the configuration of the first synchronization detection means 512, and FIGS. 3 and 4 are timing charts of the synchronization detection by the first synchronization detection means 512. FIG. 3 and 4 correspond to those in FIG. 14.

  In the figure, reference numeral 901 is a synchronization pattern comparison unit, 902 is a fixed pattern comparison unit, 903 is a synchronization pattern determination unit, 904 is a fixed pattern detection window control unit, 905 is a fixed pattern determination unit, 906 is an AND circuit, and 907 is a fixed pattern detection counter. , 908 are cluster start signal generators. The fixed pattern detection counter 907 is initialized to 0 immediately before the processing of the first synchronization detection unit 512 is executed.

  Each time a clock signal is input, serial data is input to the synchronization pattern comparison unit 901 and the fixed pattern comparison unit 902 bit by bit.

  An example of the synchronization pattern comparison unit 901 is shown in FIG. The synchronization pattern comparison unit 901 has a function of comparing the input data with the 9T / 9T synchronization pattern and counting the number of error bits when the two are compared. The synchronization pattern comparison unit 901 includes input data storage registers A1 to A18 for storing input data, synchronization pattern storage registers B1 to B18, an X-OR circuit 1201, and an adder 1202, as shown in FIG.

  The input data storage registers A1 to A18 are shift registers, which fetch one bit of data into the least significant bit A1 at the timing when the clock signal rises, and simultaneously shift the data stored in the remaining registers to the upper side by one bit. Each time a clock signal is input, serial input data is stored bit by bit in the input data storage registers A1 to A18.

  In the synchronous pattern storage registers B1 to B18, a pattern “000000001000000001” in which 9T continues twice is stored in advance. Each time serial input data is input, each bit of the input data storage registers A1 to A18 and the synchronization pattern storage registers B1 to B18 is input to the X-OR circuit 1201 to check the pattern matching degree.

  The X-OR circuit 1201 outputs “0” if the input bits match, and outputs “1” if they do not match. The number of error bits is checked by adding “1” output from the X-OR circuit 1201 by the adder 1202, and the detected number of error bits is output to the synchronization pattern determination unit 903.

  If the number of errors is equal to or less than a predetermined value, the synchronization pattern determination unit 903 determines that a synchronization pattern included in the FS 4 is detected, and sends a synchronization pattern detection signal that is HIGH for one clock to the fixed pattern detection window control unit 904. Output (1001 in FIG. 3).

  At this time, if a 9T / 9T synchronization pattern or a pattern in which a signal such as 8T or 10T close to the length of 9T continues is detected, the synchronization pattern detection signal that becomes HIGH for one clock is controlled by a fixed pattern detection window. Output to the unit 904.

  Therefore, a place where a 9T / 9T pattern is detected is detected as a synchronization pattern even when an 8T / 10T or 10T / 8T pattern is detected. For example, if the number of errors is 2 or less in the synchronization pattern determination unit 903, the synchronization pattern detection signal is output to the fixed pattern detection window control unit 904 assuming that the synchronization pattern is detected. By doing so, patterns such as 8T / 10T and 10T / 8T are also detected as synchronization patterns.

  The fixed pattern detection window control unit 904 outputs a signal that makes the fixed pattern detection window HIGH for 60 clocks to the AND circuit 906 when the synchronous pattern detection signal is detected (1002 in FIG. 3).

  FIG. 6 is a block diagram illustrating a configuration of the fixed pattern comparison unit 902. The fixed pattern comparison unit 902 includes input data storage registers C1 to C20, fixed pattern storage registers D1 to D20, an X-OR circuit 1301, and an adder 1302. The input data storage registers C1 to C20 in the fixed pattern comparison unit 902 are shift registers. One bit of data is taken into the least significant bit C1 at the timing when the clock signal rises, and is simultaneously stored in the remaining registers. Shift data up one bit.

  Each time a clock signal is input, serial input data is stored bit by bit in the input data storage registers C1 to C20. The fixed pattern storage registers D1 to D20 store the fixed pattern “100100101010000100000” shown in FIG. 14 in advance. Each time one bit of serial input data is input, each bit of the input data storage registers C1 to C20 and the fixed pattern storage registers D1 to D20 is input to the X-OR circuit 1301 to check the pattern matching degree.

  The X-OR circuit 1301 outputs ‘0’ if the bits match, and ‘1’ if the bits do not match. The number of error bits is checked by adding ‘1’ output from the X-OR circuit 1301 by the adder 1302. The detected number of error bits is input to the fixed pattern determination unit 905. If the number of errors is 0 (all bits match), the fixed pattern detection signal 1 which becomes HIGH for one clock is detected as an AND circuit. It outputs to 906 (1003, 1005 in FIG. 3).

  The AND circuit 906 outputs the fixed pattern detection signal 2 when the fixed pattern detection window is HIGH (1002 in FIG. 3) and the fixed pattern detection signal 1 is detected (1003 and 1005 in FIG. 3). (1004, 1006 in FIG. 3). At this time, +1 is added every time the fixed pattern detection counter 907 detects the fixed pattern detection signal, and the number of fixed pattern detection counters becomes +2 at the timing of 1006 in FIG.

  Next, in order to detect the synchronization pattern of FS6, the synchronization pattern comparison unit 901 of FIG. 5 is used in the same manner as when the synchronization pattern of FS4 is detected. The synchronization pattern of FS6 is detected in the same manner as when the synchronization pattern of FS4 is detected. Every time a clock signal is input by the synchronization pattern comparison unit 901, the pattern matching degree between the input data and the synchronization pattern is obtained, and the number of detected error bits is input to the synchronization pattern determination unit 903. If the number of errors is less than or equal to a predetermined value, a synchronization pattern detection signal that is HIGH for one clock is output to the fixed pattern detection window control unit 904 (1007 in FIG. 3).

  After detecting the synchronization pattern of FS6, the fixed pattern detection window control unit 904 opens the fixed pattern detection window for 60 clocks (1101 of FIG. 4) when detecting the synchronization pattern of FS6 (1007 of FIG. 3). The fixed pattern comparison unit 902 checks the degree of coincidence of each bit of the input data storage registers C1 to C20 and the fixed pattern storage registers D1 to D20.

  The detected number of error bits is input to the fixed pattern determination unit 905. If the number of errors is 0 (all bits match), a fixed pattern is detected, and a fixed pattern detection signal that is HIGH for one clock when a fixed pattern is detected. 1 is output to the AND circuit 906 (1102 in FIG. 4). The AND circuit 906 outputs the fixed pattern detection signal 2 when the fixed pattern detection window is HIGH (1101 in FIG. 4) and the fixed pattern detection signal 1 is detected (1102 in FIG. 4) (FIG. 4). 4 of 1103). At this time, +1 is added to the fixed pattern detection counter 907, and the number of fixed pattern detection counters becomes +3.

  When the number of fixed pattern detection counters 907 reaches +3, it is assumed that the synchronization pattern of FS4 included in the Run-in area and the fixed pattern sandwiched between FS4 and FS6 are detected. Furthermore, it is assumed that a synchronous pattern of FS6 and a fixed pattern sandwiched between FS6 and the head of Physical Cluster are detected.

  Next, the first synchronization pattern of the Physical Cluster is detected. Therefore, the cluster start signal generation unit 908 generates a cluster start signal that becomes HIGH for one clock at the 23rd clock from the timing of 1103 in FIG. 4 when the counter number of the fixed pattern detection counter 907 becomes +3 (1105 in FIG. 4). ). Then, the cluster start signal is output to the data area control unit 511 as a synchronization pattern detection signal of FS0 which is the first FS in the Physical Cluster.

  The data area control unit 511 outputs the detection signal from the first synchronization detection unit 512 to the demodulation circuit 514 based on the area information from the data area detection unit 510. The demodulated data of the demodulation circuit 514 is synchronized by a signal from the data area control unit 511.

(Processing by the second synchronization detecting means)
FIG. 7 is a block diagram showing the configuration of the second synchronization detection means 513, and FIG. 8 shows an example of a timing chart of synchronization detection by the second synchronization means 513. FIG. 8 corresponds to the format in the Physical Cluster in FIGS. Here, FS6 is shown as an example of the synchronization signal.

  Each time a clock signal is input, serial data is input to the synchronization pattern comparison unit 1401 bit by bit. The configuration of the synchronization pattern comparison unit 1401 is the same as that shown in FIG.

  The synchronization pattern comparison unit 1401 uses the same circuit as the synchronization pattern comparison unit 901 used in the first synchronization detection unit 512, compares the input data with the 9T / 9T synchronization pattern, and compares the number of errors. Has a function of counting. As shown in FIG. 5, the synchronization pattern comparison unit 1401 includes input data storage registers A1 to A18 for storing input data, synchronization pattern storage registers B1 to B18, an X-OR circuit 1201, and an adder 1202.

  The input data storage registers A1 to A18 are shift registers, which fetch one bit of data into the least significant bit A1 at the timing when the clock signal rises, and simultaneously shift the data stored in the remaining registers to the upper side by one bit. Each time a clock signal is input, serial input data is stored bit by bit in the input data storage registers A1 to A18.

  In addition, a pattern “000000001000000001” in which 9T continues twice is stored in advance in the synchronization pattern storage registers B1 to B18. Each time one bit of serial input data is input, each bit of the input data storage registers A1 to A18 and the synchronization pattern storage registers B1 to B18 is input to the X-OR circuit 1201 to check the pattern matching degree. The X-OR circuit 1201 outputs “0” if the input bits match, and outputs “1” if they do not match.

  The number of error bits is checked by adding “1” output from the X-OR circuit 1201 by the adder 1202, and the detected number of errors is output to the synchronization pattern determination unit 1402. If the number of errors is 0 (all bits match), the synchronization pattern determination unit 1402 determines that the synchronization pattern included in the FS 6 in FIG. 8 is detected and outputs a synchronization pattern detection signal that becomes HIGH for one clock in the data area. It outputs to the control part 511 and performs a synchronous detection (1501 of FIG. 8). The data area control unit 511 outputs a detection signal from the second synchronization detection unit 513 to the demodulation circuit 514 based on the area information from the data area detection unit 510. The demodulated data of the demodulation circuit 514 is synchronized by a signal from the data area control unit 511.

  As described above, in the present embodiment, when the reproduction signal is the Run-in area, the synchronization pattern of FS4 and FS6 included in the Run-in area and the fixed pattern included in the periphery are detected. Thus, it is possible to improve the accuracy of detecting the synchronization pattern of FS0 that is the first FS of the user data area.

  In this embodiment, the sequence is to detect FS0 after detecting FS4 and FS6. However, based on the gist of the present invention, synchronous detection is performed from at least two types of patterns among FS4, FS6, and FS0. The detection accuracy can be increased by the sequence.

  Therefore, even when the recording / reproduction quality of 9T / 9T, which is the synchronization pattern in the FS, is poor, the detection position of the fixed pattern is detected by detecting the coincidence of all bits of the fixed pattern included in the Run-in area. Thus, it becomes possible to detect the synchronization pattern in the FS more accurately. In particular, by accurately detecting the initial synchronization pattern of the Physical Cluster and increasing the synchronization detection accuracy, a more accurate reproduction operation than before can be performed.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. The overall configuration of the second embodiment is the same as that in FIG. 1, and a description of common parts is omitted. In the present embodiment, the configuration of the first synchronization detection means 512 is different from that of the first embodiment. The configuration of the second synchronization detecting means 513 is the same as that of FIG. 7 of the first embodiment.

  Similarly, when the reproduction signal is detected as being in the Run-in area and the process of the first synchronization detection unit is executed, it is detected that the reproduction signal is outside the Run-in area, and the second synchronization detection is performed. This will be described separately for the case where the processing of the means is executed.

(Processing by the first synchronization detecting means)
FIG. 9 is a block diagram showing the configuration of the first synchronization detection means 512, and FIGS. 10 and 11 show timing charts of the synchronization detection by the first synchronization detection means 512. FIG. The synchronization patterns and fixed patterns in FIGS. 10 and 11 correspond to those in FIG.

  9, 1601 is a fixed pattern comparison unit, 1602 is a synchronization pattern comparison unit, 1603 is a fixed pattern determination unit, 1604 is a synchronization pattern detection window control unit, 1605 is a synchronization pattern determination unit, 1606 is an AND circuit, and 1607 is a synchronization pattern. It is a detection correction unit. Reference numeral 1608 denotes a synchronous pattern detection counter, 1609 denotes a cluster start signal generation unit, 1610 denotes a fixed pattern comparison unit, and 1611 denotes a fixed pattern determination unit. The synchronization pattern detection counter 1608 is initialized to 0 immediately before the processing of the first synchronization detection means 512 is executed.

  Each time a clock signal is input, serial data is input bit by bit to the fixed pattern comparison unit 1601, the synchronization pattern comparison unit 1602, and the fixed pattern comparison unit 1610. An example of the fixed pattern comparison unit 1601 is shown in FIG.

  As shown in FIG. 12, the fixed pattern comparison unit 1601 includes input data storage registers E1 to E40, fixed pattern storage registers F1 to F40, an X-OR circuit 1901, and an adder 1902.

  The input data storage registers E1 to E40 in the fixed pattern comparison unit 1601 are shift registers. One bit of data is taken into the least significant bit E1 at the timing when the clock signal rises, and is simultaneously stored in the remaining registers. The existing data is shifted up by 1 bit. Each time a clock signal is input, the input data storage registers E1 to E40 store serial input data bit by bit.

  Further, '1001001010100001000010010010101000010000', which is a pattern that repeats the fixed pattern shown in FIG. 14 twice, is stored in advance in the fixed pattern storage registers F1 to F40. Each time one bit of serial input data is input, each bit of the input data storage registers E1 to E40 and the fixed pattern storage registers F1 to F40 is input to the X-OR circuit 1901 to check the pattern matching degree.

  The X-OR circuit 1901 outputs “0” when the input bits match, and outputs “1” when they do not match. The number of errors is checked by adding ‘1’ output from the X-OR circuit 1901 by the adder 1902 and counting the number of error bits. The number of detected errors is input to the fixed pattern determination unit 1603. If the number of errors is 0 (all bits match), a fixed pattern detection signal 1 that is HIGH for one clock is output to the fixed pattern detection window control unit 1604, assuming that a pattern that repeats the fixed pattern twice is detected ( 1701 in FIG.

  The synchronization pattern detection window control unit 1604 outputs a signal that the synchronization pattern detection window becomes HIGH for 10 clocks to the AND circuit 1606 20 clocks after detecting the fixed pattern detection signal (1702 in FIG. 12). Then, every time a pattern that repeats the fixed pattern included in the Run-in area is detected twice, the operation of opening the synchronous pattern detection window by 10 clocks is repeated 20 clocks after detecting the fixed pattern. A pattern in which the fixed pattern is repeated twice is '10010010101000010000100100101010000100000'.

  Next, the detailed operation of the synchronization pattern comparison unit 1602 will be described. The synchronization pattern comparison unit 1602 has a function of comparing the input data with the 9T / 9T synchronization pattern and counting the number of errors when the two are compared. The synchronization pattern comparison unit 1602 can be realized by a circuit similar to the synchronization pattern comparison unit 901 shown in FIG. 5 of the first embodiment.

  The synchronization pattern comparison unit 1602 includes input data storage registers A1 to A18 for storing input data, synchronization pattern storage registers B1 to B18, an X-OR circuit 1201, and an adder 1202. The input data storage registers A1 to A18 are shift registers, which fetch one bit of data into the least significant bit A1 at the timing when the clock signal rises, and simultaneously shift the data stored in the remaining registers to the upper side by one bit.

  Each time a clock signal is input, serial input data is stored bit by bit in the input data storage registers A1 to A18. In addition, a pattern “000000001000000001” in which 9T continues twice is stored in advance in the synchronization pattern storage registers B1 to B18. Each time serial input data is input, each bit of the input data storage registers A1 to A18 and the synchronization pattern storage registers B1 to B18 is input to the X-OR circuit 1201 to check the pattern matching degree.

  The X-OR circuit 1201 outputs “0” if the input bits match, and outputs “1” if they do not match. The adder 1202 adds “1” output from the X-OR circuit 1201 to check the number of error bits, and outputs the detected number of errors to the synchronization pattern determination unit 1605.

  The synchronization pattern determination unit 1605 outputs to the AND circuit 1606 a synchronization pattern detection signal 1 that is HIGH for one clock, assuming that the synchronization pattern included in the FS4 is detected if the number of errors is equal to or less than a predetermined value ( 1703 in FIG. In this case, in addition to the 9T / 9T synchronization pattern, a pattern in which a signal such as 8T or 10T having a length of 9T continues twice is also detected as a synchronization pattern, as in the first embodiment.

  The AND circuit 1606 outputs the synchronization pattern detection signal 2 when the synchronization pattern detection window is HIGH (1704 in FIG. 10) and when the synchronization pattern detection signal 1 is detected (1703 in FIG. 10) ( 1705 in FIG. At this time, the synchronization pattern detection correction unit 1607 determines the absolute position of the synchronization pattern from the fixed pattern detection signal 1 (1706 in FIG. 10) and the synchronization pattern detection signal 2 (1705 in FIG. 10), and the timing of the synchronization pattern detection signal 2 Correct.

  At this time, as shown in FIG. 10, after 1706 of the fixed pattern detection signal 1 is detected, the timing of 1705 of the synchronization pattern detection signal 2 is corrected. A synchronous pattern correction signal that is HIGH for the clock is output. The 23rd bit from 1706 of the fixed pattern detection signal 1 is the absolute position of the synchronization pattern.

  This synchronization pattern correction signal is output to the synchronization pattern detection counter 1608 (1707 in FIG. 10). In the synchronization pattern detection counter 1608, the number of synchronization pattern detection counters is incremented by 1, and the counter value becomes +1.

  Next, an operation for detecting '10010010101000010000100100101010000100000', which is a pattern that repeats the fixed pattern following FS4 twice, will be described. The fixed pattern is detected by the same method as described above. That is, a fixed pattern detection signal 1 that is HIGH for one clock is detected to the synchronous pattern detection window control unit 1604 when detecting a pattern that repeats the fixed pattern following FS4 twice (1801 in FIG. 11). The synchronization pattern detection window control unit 1604 detects the fixed pattern detection signal 1 (1801 in FIG. 11), then opens the synchronization pattern detection window by 10 clocks after 20 clocks (1802 in FIG. 11), and outputs it to the AND circuit 1606. To do.

  Next, in order to detect the synchronization pattern of FS6, the synchronization pattern comparison unit 1602 of FIG. 5 is used in the same manner as when the synchronization pattern of FS4 is detected. It is possible to detect the synchronization pattern of FS6 in the same manner as the detection method of the synchronization pattern of FS4. If the number of errors is equal to or less than a predetermined value in the synchronization pattern determination unit 1605, the synchronization pattern detection signal 1 is output to the AND circuit 1606, assuming that the synchronization pattern of FS6 is detected (1803 in FIG. 11).

  The AND circuit 1606 outputs the synchronization pattern detection signal 2 when the synchronization pattern detection window is HIGH (1802 in FIG. 11) and the synchronization pattern detection signal 1 is detected (1803 in FIG. 11) ( 1804 in FIG. At this time, as described above, the synchronization pattern detection correction unit 1607 determines the absolute position of the synchronization pattern from the fixed pattern detection signal 1 (1801 in FIG. 11) and the synchronization pattern detection signal 2 (1804 in FIG. 11), and detects the synchronization pattern. The timing of signal 2 is corrected.

  The correction method in this case is the same as described above. That is, as shown in FIG. 11, after the 1801 of the fixed pattern detection signal 1 is output, the timing of the synchronization pattern detection signal 1804 is corrected. A synchronization pattern correction signal that becomes HIGH is output.

  This synchronization pattern correction signal is output to the synchronization pattern detection counter 1608 (1805 in FIG. 11). The synchronization pattern detection counter 1608 adds +1 to the number of synchronization pattern detection counters, and the counter value becomes +2.

  When the count of the synchronization pattern detection counter 1607 reaches +2, the pattern that repeats the fixed pattern included in the Run-in area twice, the synchronization pattern of FS4, and the fixed pattern sandwiched between FS4 and FS6 twice Assume that a repeated pattern is detected. Furthermore, it is assumed that all the synchronization patterns of FS6 have been detected. Next, the cluster start signal generation unit 1609 generates a timing signal of the synchronization pattern of FS0, which is the first FS in the Physical Cluster.

  Here, before generating the timing signal of the synchronization pattern of FS0, it is necessary to detect 20 bits of the fixed pattern existing between FS6 and FS0 in the fixed pattern comparison unit 1610. The fixed pattern comparison unit 1610 can be realized by a circuit similar to the fixed pattern comparison unit 902 shown in FIG. 6 of the first embodiment.

  The fixed pattern comparison unit 1610 includes input data storage registers C1 to C20, fixed pattern storage registers D1 to D20, an X-OR circuit 1301, and an adder 1302, and compares the input data with each bit of the fixed pattern 20 bits. It has a function. The input data storage registers C1 to C20 in the fixed pattern comparison unit 1610 are shift registers. One bit of data is taken into the least significant bit C1 at the timing when the clock signal rises, and is simultaneously stored in the remaining registers. Shift data up one bit.

  Each time a clock signal is input, serial input data is stored bit by bit in the input data storage registers C1 to C20. Fixed patterns ‘100100101010000100000’ shown in FIG. 14 are stored in advance in the fixed pattern storage registers D1 to D20. Each time one bit of serial input data is input, each bit of the input data storage registers C1 to C20 and the fixed pattern storage registers D1 to D20 is input to the X-OR circuit 1301 to check the pattern matching degree.

  The X-OR circuit 1301 outputs ‘0’ if the bits match, and ‘1’ if the bits do not match. The number of error bits is checked by adding ‘1’ output from the X-OR circuit 1301 by an adder 1302. The detected number of error bits is input to the fixed pattern determination unit 1611. If the number of errors is 0 (all bits match), the fixed pattern detection signal 2 that becomes HIGH for one clock is assumed to be clustered if the fixed pattern is detected. It outputs to the signal generation part 1609 (1806 of FIG. 11).

  The cluster start signal generation unit 1609 calculates the absolute position of the synchronization pattern included in FS0 when the number of synchronization pattern detection counters input from the synchronization pattern detection counter 1608 is +2 and the fixed pattern detection signal 2 is detected. Determine.

  Specifically, the cluster start signal generation unit 1609 has a built-in clock counter, and a cluster start detection signal that becomes HIGH for one clock 23 clocks after the detection of 1806 in FIG. 11 is sent to the data area control unit 511. Output. That is, a timing signal of the synchronization pattern of FS0, which is the first synchronization pattern in the Physical Cluster, is generated as the detection position of the synchronization pattern of FS0 (1807 in FIG. 11).

  In this embodiment, the number of detected fixed patterns is two. However, based on the gist of the present invention, the synchronization timing signal of FS0 may be generated using at least one fixed pattern.

(Processing by the second synchronization detecting means)
The processing by the second synchronization detecting means 513 is the same as the method described in the first embodiment. As described above, FIG. 7 is a block diagram of the second synchronization means 513, and FIG. 8 is a timing chart of synchronization detection by the second synchronization means.

  Each time a clock signal is input, serial data is input to the synchronization pattern comparison unit 1401 bit by bit. An example of the synchronization pattern comparison unit 1401 is shown in FIG. The synchronization pattern comparison unit 1401 uses a circuit similar to the synchronization pattern comparison unit 901 used in the first synchronization unit 512. The synchronization pattern comparison unit 1401 has a function of comparing the input data with the 9T / 9T synchronization pattern and counting the number of errors when the two are compared.

  The synchronization pattern comparison unit 901 includes input data storage registers A1 to A18 for storing input data, synchronization pattern storage registers B1 to B18, an X-OR circuit 1201, and an adder 1202. The input data storage registers A1 to A18 are shift registers. One bit of data is taken into the least significant bit A1 at the timing when the clock signal rises, and at the same time, the data stored in the remaining registers is shifted to the upper side by 1 bit. .

  Each time a clock signal is input, serial input data is stored bit by bit in the input data storage registers A1 to A18. In addition, a pattern “000000001000000001” in which 9T continues twice is stored in advance in the synchronization pattern storage registers B1 to B18. Each time one bit of serial input data is input, each bit of the input data storage registers A1 to A18 and the synchronization pattern storage registers B1 to B18 is input to the X-OR circuit 1201 to check the degree of pattern matching.

  The X-OR circuit 1201 outputs “0” if the input bits match, and outputs “1” if they do not match. The number of error bits can be checked by adding ‘1’ output from the X-OR circuit 1201 by the adder 1202. The number of detected error bits is output to the synchronization pattern determination unit 1402. If the number of errors in the synchronization pattern determination unit 1402 is 0 (all bits match), a synchronization pattern detection signal that is HIGH for one clock is detected in the data area control unit 511, assuming that the synchronization pattern included in the FS 6 is detected. Output and perform synchronization detection (1501 in FIG. 8).

  As described above, when the reproduction signal is in the Run-in area, the synchronization pattern of FS4 and FS6 included in the Run-in area and the fixed pattern included in the periphery are detected. Thereby, it is possible to improve the accuracy of detecting the synchronization pattern of FS0 that is the first frame of the user data area.

  That is, even when the recording / reproduction quality of the synchronization pattern 9T / 9T is poor, the synchronization pattern is detected using the detection of the fixed pattern 3T / 3T / 2T / 2T / 5T / 5T included in the Run-in area. By determining the absolute position, the synchronization pattern in the FS can be detected more accurately. In particular, by accurately detecting the initial synchronization pattern of the Physical Cluster and increasing the synchronization detection accuracy, a more accurate reproduction operation than before can be performed.

It is a block diagram which shows the 1st Embodiment of this invention. It is a block diagram which shows an example of the 1st synchronous detection means 512 of FIG. It is a timing chart of the synchronous detection by the 1st synchronous detection means. It is a timing chart of the synchronous detection by the 1st synchronous detection means. FIG. 3 is a circuit diagram illustrating an example of a synchronization pattern comparison unit 901 in FIG. 2. FIG. 3 is a circuit diagram illustrating an example of a fixed pattern comparison unit 902 in FIG. 2. It is a block diagram which shows an example of the 2nd synchronous detection means 513 of FIG. It is a timing chart of the synchronous detection by the 2nd synchronous detection means. It is a block diagram which shows an example of the 1st synchronous detection means 512 of the 2nd Embodiment of this invention. It is a timing chart of the synchronous detection by the 1st synchronous detection means of 2nd Embodiment. It is a timing chart of the synchronous detection by the 1st synchronous detection means of 2nd Embodiment. FIG. 10 is a circuit diagram illustrating an example of a fixed pattern comparison unit 1601 in FIG. 9. It is a figure which shows the structure of RUB (RecordingUnit Block). It is a figure which shows the detailed structure of Run-in.

Explanation of symbols

501 Optical disk 502 Optical head 503 Spindle motor 504 RF amplifier 505 AGC filter 506 A / D conversion circuit 507 Waveform equalization circuit 508 Viterbi decoder 509 Wobble detection unit 510 Data area detection unit 511 Data area control unit 512 First synchronization detection means 513 Second synchronization detection means 514 Demodulation circuit 901 Synchronization pattern comparison unit 902 Fixed pattern comparison unit 903 Synchronization pattern determination unit 904 Fixed pattern detection window control unit 905 Fixed pattern determination unit 906 AND circuit 907 Fixed pattern detection counter 908 Cluster start signal generation Unit 1201 X-OR circuit 1202 adder 1301 X-OR circuit 1302 adder 1401 synchronization pattern comparison unit 1402 synchronization pattern determination unit 1601 fixed pattern comparison 1602 Synchronization pattern comparison unit 1603 Fixed pattern determination unit 1604 Synchronization pattern detection window control unit 1605 Synchronization pattern determination unit 1606 AND circuit 1607 Synchronization pattern detection correction unit 1608 Synchronization pattern detection counter 1609 Cluster start signal generation unit 1610 Fixed pattern comparison unit 1611 Fixed pattern Determination unit 1901 X-OR circuit 1902 Adder A1 to A18 Input data storage register B1 to B18 Synchronization pattern storage register C1 to C20 Input data storage register D1 to D20 Fixed pattern storage register E1 to E40 Input data storage register F1 to F40 Fixed pattern Storage register

Claims (6)

In a method for detecting synchronization of an information signal based on a synchronization pattern added to an information recording medium, the synchronization pattern is detected, at least one fixed pattern inserted before or after the synchronization pattern is detected, and the fixed A synchronization detection method comprising synchronizing the information signal from a pattern detection result and a synchronization pattern detection result. When the information signal is synchronized, a window that allows detection of the fixed pattern is opened for a predetermined period when the synchronization pattern is detected, and the information is based on the detection result of the fixed pattern detected in the window. The synchronization detection method according to claim 1, wherein the signals are synchronized. 3. The synchronization detection method according to claim 1, wherein when detecting the synchronization pattern, a mark having a length close to a predetermined synchronization pattern is detected as a synchronization pattern. When synchronizing the information signal, a window that allows detection of the synchronization pattern is opened for a predetermined period when the fixed pattern is detected, and synchronization of the information signal is performed based on the synchronization pattern detected in the window. The synchronization detection method according to claim 1, wherein: In an apparatus for detecting synchronization of an information signal based on a synchronization pattern added to an information recording medium, means for detecting the synchronization pattern, and means for detecting at least one fixed pattern inserted before or after the synchronization pattern And a means for synchronizing the information signal from the detection result of the fixed pattern detection means and the detection result of the synchronization pattern detection means. 5. The optical information reproducing apparatus for reproducing an information signal recorded on an optical information recording medium by synchronizing the information signal based on a synchronization pattern added to the recording medium. 6. An optical information reproducing apparatus for reproducing an information signal recorded on the recording medium by using the synchronization detection method.

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