JP2007102399A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the processing efficiency of task switching of a data processor which executes a task by making software to be executed on a processor and hardware exclusive for specific processing cooperatively execute a task. <P>SOLUTION: This data processor is composed of: a CPU 101 for successively executing a plurality of tasks according to the priority of tasks; and an HW accelerator 103 for processing electronic data according to the instruction of the CPU 101. The HW accelerator 103 records an HW status showing the progress circumstances of processing to be executed in a status register 107, and the CPU 101 recognizes the recorded HW status, and successively executes tasks by switching the tasks. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing apparatus that processes electronic data for general use, and more particularly, to a data processing apparatus in which hardware and software operating on a processor jointly process data.

Currently, a data processing device having a configuration in which a hardware device that executes a specific process is controlled by a control device such as a processor is widely used. In such a data processing apparatus, one processor executes a plurality of tasks in accordance with the priority order, and requests a process having a relatively large load among the tasks in this process.
When processing is requested to the hardware, this processor interrupts the task related to this processing and executes the task to be executed next. When the execution of the requested process ends, the hardware notifies the processor of the end of the process. At this time, if the process being executed has a lower priority than the process requested to the hardware, the processor interrupts the process being executed. Then, the task that has been requested by the hardware and completed processing is continuously executed as necessary.

In the operations of the processor and hardware described above, an interrupt is generally used for notification of the end of processing performed from the hardware to the processor. Many conventional data processing apparatuses switch tasks by using an interrupt to a processor as a trigger. As such a conventional technique, for example, Patent Document 1 is cited.
JP-A-7-271344

However, in the invention described in Patent Document 1, since the processor switches a task using only an interrupt as a trigger, a process for interrupting a task being executed is started after an interrupt is made. The process for interrupting a task refers to a process for storing the processing content immediately before the interruption in preparation for the resumption of the process.
In the invention described in Patent Document 1, since tasks are sequentially executed unless an interrupt is made, a task with a lower priority is issued even immediately before the task processing is completed than the priority requested by the processor. The execution of is started. In such a case, in the invention described in Patent Document 1, there is a possibility that the execution start of a task with a higher priority is delayed due to the start of execution of a task with a lower priority.

Such Patent Document 1 has a large overhead due to task switching, and it is desired to further improve the task switching processing efficiency.
The present invention has been made in view of the above points, and the task switching processing efficiency of a data processing apparatus in which software executed on a processor and hardware dedicated to a specific process execute a task jointly The purpose is to further increase.

  In order to solve the above problems, a data processing apparatus according to the present invention includes a control unit that sequentially executes a plurality of tasks in accordance with the priority order of the tasks, and a data processing execution unit that processes electronic data in accordance with instructions from the control unit The data processing execution means includes progress information recording means for recording progress information indicating a progress status of processing of electronic data to be executed, and the control means includes the progress information. Progress status recognition means for recognizing the progress information recorded by the recording means is provided, and tasks are switched based on information including the progress information recognized by the progress status recognition means, and executed sequentially.

  According to such an invention, a plurality of tasks can be sequentially executed according to the priority order, and in this process, the data processing execution means can execute a part of the tasks. In addition, since the progress information indicating the progress status of the processing of the electronic data executed by the data processing execution means can be recorded and the control means can recognize the progress information, the data processing apparatus of the present embodiment has the control means The processing progress of the data processing execution means can be grasped, and tasks can be switched according to the situation.

Such an embodiment of the present invention can further improve the task switching processing efficiency of a data processing apparatus in which software executed on a processor and hardware dedicated to a specific process execute a task.
In the data processing apparatus of the present invention, the control means includes execution order setting means for setting an execution order of tasks, and the execution order setting means executes the execution according to the progress situation recognized by the progress situation recognition means. The execution order set by the order setting means is changed.

According to such an invention, the control means can set the task execution order, and the set execution order can be changed according to the progress situation recognized by the progress situation recognition means.
According to such an invention, it is possible to change the execution order of tasks once set according to the progress of processing in the data processing apparatus, and flexibly respond to the progress of processing, thereby improving the processing efficiency. High order can be set.

In the data processing apparatus of the present invention, the progress information recording means records progress information in a register in the data processing execution means, and the progress status recognition means is a memory map assigned to the progress information recording means. The progress information is recognized by referring to the corresponding address above.
According to such an invention, the progress information can be recorded in the register, and the recorded progress information can be recognized by referring to the address previously assigned to the register. For this reason, it is possible to reduce the procedure and time for referring to the progress information, and to easily refer to the changing progress information in real time.

In the data processing apparatus of the present invention, the progress information recording means records the number of cycles for the remaining data processing among the data processing in the data processing execution means as progress information.
According to such an invention, the progress status of the data processing can be grasped by the remaining time required for the data processing in the data processing execution means. For this reason, it is possible to easily determine whether the task should be executed according to the set execution order or whether the execution of the task should be resumed after waiting for the processing of the data processing execution means.

In the data processing apparatus of the present invention, the progress information recording unit determines whether or not the remaining data processing in the data processing execution unit is equal to or less than a threshold value that is a predetermined data processing amount, and a threshold value. When the value is less than or equal to the value, a flag indicating that the remaining data processing is less than or equal to the threshold value is recorded as progress information.
According to such an invention, it is possible to omit the determination based on the remaining amount of data processing and execute the task according to the set execution order, or wait for the processing of the data processing execution means to resume the execution of the task Judgment of what to do can be made easier.

The data processing apparatus of the present invention is characterized by comprising threshold recording means capable of recording the threshold and changing the recorded threshold.
According to such an invention, the criteria for determining whether the task should be executed according to the set execution order or whether the execution of the task should be resumed after waiting for the processing of the data processing execution means is determined based on the user needs and the data processing. It can be changed according to the contents.

Hereinafter, an embodiment of a data processing apparatus according to the present invention will be described with reference to the drawings.
FIG. 1 is a diagram for explaining the configuration of the data processing apparatus according to the present embodiment. The data processing apparatus according to the present embodiment includes a CPU (Central Processing Unit) 101 that sequentially executes a plurality of tasks according to the priority order of the tasks, and hardware (hereinafter simply referred to as data) that processes electronic data according to instructions from the CPU 101. HW) accelerator 103. The memory 102 shown in FIG. 1 has a configuration for storing instructions used for executing tasks of the data processing apparatus, tables and data used for executing the instructions, and the like.

  The CPU 101, the memory 102, and the HW accelerator 103 are connected to each other by a bus. Further, as illustrated in FIG. 1, the present embodiment is not limited to the one provided with one HW accelerator 103, and may include a plurality of HW accelerators 103. In such a case, one CPU 101 may control a plurality of HW accelerators 103, or a plurality of CPUs may be provided.

The CPU 101 includes a task management table 108 in order to properly execute a plurality of tasks sequentially. An example of the task management table 108 is shown in FIG.
The task management table 108 illustrated in FIG. 2 is a task management table for managing tasks including task A, task B, and task C. The task management table 108 includes a task name of each task, a program counter (PC) indicating the progress of each task, a processor state register (PSR) that records a processor state and condition at the time of task execution, and a stack position. A stack pointer (SP) indicating a state of a task, a state indicating a state of the task, a priority (priority), a processing content of a task being executed (register file), an HW accelerator being used when there are a plurality of HW accelerators, or Manage the use and non-use (HW) of the only HW accelerator.

  The CPU 101 uses such a task management table 108 to set the execution order of a plurality of tasks. The CPU 101 and the task management table 108 function as an execution order setting unit in the present embodiment. The execution order referred to in the present embodiment is represented by listing the task names of tasks that can be executed in a line from those that are executed earlier. This column is also referred to as a ready queue hereinafter.

On the other hand, the HW accelerator 103 is hardware for processing data with a relatively large load when executing a task. For this reason, the control part 104 which controls the calculating part 106 according to the instruction | indication of the calculating part 106 and CPU101 used for data processing is provided.
The control unit 104 includes a counter or a state machine. The counter of the present embodiment counts processing cycles. The state machine controls processing in the arithmetic unit 106 according to processing parameters and settings. The control unit 104 can indicate the number of cycles and the state of the process currently being executed by the calculation unit 106.

  The HW accelerator 103 also includes a status signal generation unit 105 and a status register 107. The status signal generation unit 105 generates a status signal indicating the number of remaining cycles of processing obtained by the HW accelerator 103. The status signal is a signal for writing information including the remaining number of cycles to the status register 107 as the HW status (progress_val). In the example illustrated in FIG. 1, the remaining number of cycles of the process executed by the HW accelerator 103 is 30.

The control unit 104, the status signal generation unit 105, and the status register 107 function as a progress information recording unit that records an HW status (progress information) indicating a progress status of processing of electronic data to be executed.
The CPU 101 recognizes the HW status written in the status register 107, switches tasks based on information including the recognized HW status, and executes them sequentially. The data processing apparatus according to this embodiment executes task switching by changing the execution order set in the task management table 108 according to the HW status. A specific operation for changing the execution order will be described later. The information including the HW status referred to in the present embodiment is information on the HW status and the priority order of each task.

  In the configuration described above, the CPU 101 kicks the HW accelerator 103 and instructs execution of one process (HW request process) included in the task. The HW accelerator 103 executes the instructed HW request process. At this time, in the present embodiment, the control unit 104 calculates the number of cycles required from the start to the end of the process based on the contents of the HW request process. The status signal generation unit 105 writes the set number of cycles in the status register 107 using the status signal. Further, the CPU 101 updates the number of cycles written by the HW accelerator 103 in accordance with the progress of the processing of the calculation unit 106.

Further, the CPU 101 can recognize the HW status recorded in the status register 107 (indicated by an arrow A). In this embodiment, the HW status is written in the status register 107, and the CPU 101 can recognize the HW status by referring to the status register 107 assigned to the memory map.
FIG. 3 is a diagram illustrating an example of a memory map referred to by the CPU 101. In the present embodiment, an address range in which the HW status is written in the memory map is set in advance. Then, every time the CPU 101 finishes the task, the CPU 101 recognizes the number of remaining cycles of processing by referring to the data written to the address within the set range of the memory map.

With such a configuration, the CPU 101 can relatively easily refer to the HW status and determine the status of the process being executed by the HW accelerator 103 at any time.
On the other hand, the HW accelerator 103 has an access line indicated by an arrow B, and can notify the CPU 101 of the completion of the instructed processing as an interrupt.
Next, the operation of the data processing apparatus of this embodiment described above will be described. In this description, it is assumed that the data processing apparatus executes three tasks, task A, task B, and task C. The priority order of task A, task B, and task C is task A> task B> task C.

  FIG. 4 is a diagram for explaining the operation of the data processing apparatus according to the present embodiment. The solid line indicates the operation of the data processing apparatus according to the present embodiment, and the broken line indicates the operation of the prior art described for comparison. Yes. In FIG. 4, vertical arrows indicated below the characters of task A, task B, and task C indicate the timing at which each task is executed. The vertical arrow line below the OS character indicates the timing at which the OS is operating in the CPU 101, and the vertical arrow line below the INT character indicates interrupts and interrupt-related processing. Timing is shown. Moreover, the horizontal arrow line shows the transition of each process.

Note that the deviation between the solid line and the broken line in the vertical direction of the arrow shown in FIG. 4 is for identifying and recognizing both, and there is no substantial difference between the two except for the parts described in particular. Absent.
Hereinafter, the operation of the data processing apparatus of the present embodiment will be described in comparison with the operation of the conventional configuration.

(Data processing apparatus of this embodiment)
In the data processing apparatus of the present embodiment, first, the CPU 101 starts execution of task A having the highest priority. During the execution of task A, the CPU 101 instructs the HW accelerator 103 to execute the HW request process (S401). For this reason, in the CPU 101, the task being executed is switched to the OS (Operating System) and the dispatcher is activated.

FIG. 5 is a diagram showing a task program that performs HW request processing during the execution of task A described above. In the HW request process, the CPU 101 calls the HW accelerator 103 during execution of task A. Then, a parameter necessary for the HW request process is passed to instruct execution of the process.
The CPU 101 refers to the task management table shown in FIG. 2 and confirms the usage status of the HW accelerator 103 (S402). If the HW accelerator 103 is usable, the OS operating on the CPU 101 instructs the HW accelerator 103 to execute the HW request process (S403). Task A is in a state where it cannot be executed until the HW request process is completed. Therefore, the CPU 101 removes task A from the ready queue (S404).

Since the task A cannot be executed, the CPU 101 starts the dispatcher to execute the next task (S405). Here, the data processing apparatus according to the present embodiment checks the HW status written in the status register 107 by the OS (S406).
The HW status of this embodiment is represented by the number of remaining cycles necessary for the HW request process. As a result of checking the HW status, the CPU 101 executes the next task B in the ready queue when the HW status indicates a predetermined number of cycles or more (S407).

When the execution of task B is completed in the CPU 101, the dispatcher is activated (S408), and the OS operates on the CPU 101. The OS confirms the HW status written in the status register 107 (S409). As a result of the confirmation, when the number of cycles indicated by the HW status is less than the predetermined number, the task A ends within a predetermined time or less.
When the number of cycles indicated by the HW status is less than the predetermined number, the CPU 101 compares the priority of the task C to be executed next to the task B in the ready queue with the priority of the task A. The priority of task A is higher than the priority of task C. Therefore, the CPU 101 changes the execution order set in the ready queue and adds task A to the head of the ready queue without executing task C (S410).

When the HW request process ends, the HW accelerator 103 notifies the CPU 101 of the end of the process by interruption (S411). In the data processing apparatus of this embodiment, when an interrupt occurs, a task has already been added to the ready queue, and the CPU 101 is not executing another task. For this reason, it is possible to immediately start the execution of the task A by performing a process associated with the interruption.
When the process associated with the interrupt is completed, the OS operates on the CPU 101 and the dispatcher is activated (S412). Next, the CPU 101 executes task A at the head of the ready queue (S413: the execution start timing is indicated as t1 in the figure).

(Conventional configuration)
The conventional data processing apparatus starts the dispatcher after removing the task A from the ready queue by requesting the HW accelerator 103 to execute part of the processing of the task A. Then, regardless of the processing status of the HW accelerator 103, task B and task C are sequentially executed along the ready queue.

  When completing the HW request process, the HW accelerator 103 notifies the CPU 101 of the end of the process by an interrupt. At this time, the CPU 101 determines that the task A is being executed and the task A having a higher priority than the task C is being executed. Therefore, task A is added to the head of the ready queue to start the dispatcher. The CPU 101 executes the task A instead of the task C by the dispatcher (execution start timing is indicated as t2 in the figure).

As described above, the data processing apparatus according to the present embodiment is different from the conventional configuration in that the number of remaining cycles of the HW request processing in the HW accelerator 103 is confirmed when the task is completed. Further, since the priority of task A including the HW request process is higher than that of task C, task A is added to the ready queue without executing task C.
According to such processing, the data processing apparatus of the present embodiment can change the task execution order and add task A to the ready queue prior to the interruption by the HW accelerator 103. In addition, even after an interrupt is made, the execution of task A can be quickly prepared without processing such as saving the data being processed in task C to a register file in order to interrupt the execution of task C. it can.

For this reason, in the present embodiment, the execution of the task A interrupted by requesting the HW accelerator 103 to execute a part of the processing is different from the conventional configuration in the difference d (timing t1 and timing t2 shown in the figure). Can be started earlier by the time of (difference).
Note that the data processing apparatus of the present embodiment is not limited to the configuration described above. That is, in the embodiment described above, the remaining number of cycles of the process executed by the HW accelerator 103 is written as progress information. However, the progress information is not limited to the number of remaining cycles, and for example, a flag or the like may be set based on the number of remaining cycles.

FIG. 6 is a diagram for explaining an example of a data processing apparatus that uses a flag as progress information for the HW status. Of the configurations shown in FIG. 6, the same configurations as those shown in FIG. Are given the same reference numerals, and a part of the explanation is omitted.
In the illustrated data processing apparatus, a parameter register in which a cycle number (threshold cycle number: pre_done_cfg) serving as a threshold for setting a flag is set instead of the status register 107 in which the remaining cycle number of processing is recorded. 608 is provided with a status register 607 into which a flag that is set when the number of remaining processes is equal to or less than the threshold cycle number is written.

  In the data processing apparatus shown in FIG. 6, the control unit 104 counts the number of cycles of the currently executing HW request process and calculates the number of remaining cycles. Further, the control unit 104 compares the calculated remaining cycle number with the threshold cycle number written in the parameter register 608. When the remaining number of cycles is equal to or less than the threshold number of cycles, the status signal generation unit 105 is instructed to cause the status register 607 to write a flag (pre_done_flag).

When the task is completed, the CPU 101 refers to the status register 607 and detects that the HW request process in the HW accelerator 103 is almost completed by setting the flag “1”. Then, the task execution order is changed according to the priority order of the task including the HW request process and the task set in the ready queue.
Also in the data processing apparatus shown in FIG. 6, the CPU 101 recognizes the HW status such as the threshold cycle number and flag by referring to the memory map.

FIG. 7 is an example of a memory map referred to by the CPU 101. In the present embodiment, an address range in which the HW status is written in the memory map is set in advance. Then, the CPU 101 recognizes the number of remaining cycles of processing by referring to data written to addresses in a set range of the memory map every time a task is completed.
Further, the data processing apparatus of the present embodiment can be configured such that the number of threshold cycles can be arbitrarily set. In such a configuration, for example, a desired setting value is written in the parameter register 608 at the time of shipment of a device including the data processing device according to the user's request, the type of data handled by the data processing device, and the processing content of the HW accelerator. Can be realized.

Alternatively, a plurality of predetermined threshold values may be set in advance, and the CPU 101 may change the setting according to a task parameter or the like.
In the above configuration, the parameter register 608 that can rewrite the value of the threshold cycle serves as the threshold recording means.

It is a figure for demonstrating the structure of the data processor of one Embodiment of this invention. It is the figure which showed an example of the task management table shown in FIG. It is the figure which showed an example of the memory map referred by CPU shown in FIG. It is a figure for demonstrating operation | movement of the data processor of one Embodiment of this invention. FIG. 5 is a diagram showing a task program that performs HW request processing during execution of task A shown in FIG. 4. It is a figure for demonstrating the other structure of the data processor of one Embodiment of this invention. It is the figure which showed an example of the memory map referred by CPU shown in FIG.

Explanation of symbols

101 CPU, 102 memory, 103 HW accelerator, 104 control unit 105 status signal generation unit, 106 operation unit, 107 status register, 108 task management table, 607 status register, 608 parameter register

Claims (6)

Control means for sequentially executing a plurality of tasks according to the priority order of the tasks;
A data processing device comprising: data processing execution means for processing electronic data according to an instruction from the control means;
The data processing execution means includes
A progress information recording means for recording progress information indicating a progress status of processing of electronic data to be executed;
The control means includes
Progress status recognition means for recognizing progress information recorded by the progress information recording means,
A data processing apparatus, wherein tasks are switched and executed sequentially based on information including progress information recognized by the progress status recognition means. The control means includes an execution order setting means for setting an execution order of tasks,
The data processing apparatus according to claim 1, wherein the execution order setting unit changes the execution order set by the execution order setting unit according to a progress situation recognized by the progress situation recognition unit.   The progress information recording means records progress information in a register in the data processing execution means, and the progress status recognition means refers to a corresponding address on the memory map assigned to the progress information recording means. The data processing apparatus according to claim 1 or 2, wherein information is recognized.   The data according to any one of claims 1 to 3, wherein the progress information recording means records the number of cycles for the remaining data processing among the data processing in the data processing execution means as progress information. Processing equipment.   The progress information recording means determines whether or not the remainder of the data processing in the data processing execution means is equal to or less than a threshold value that is a predetermined data processing amount. The data processing apparatus according to any one of claims 1 to 3, wherein a flag indicating that the remainder is equal to or less than a threshold is recorded as progress information.   6. The data processing apparatus according to claim 5, further comprising a threshold value recording unit capable of recording the threshold value and changing the recorded threshold value.

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