JP2007066381A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a signal of the object to be monitored inside a circuit can be detected by an existing output terminal. <P>SOLUTION: The device comprises: a mode register 110 in which when the device is set to the prescribed mode by a signal input from the outside, a first signal is output, when it is not set to the prescribed mode, a second signal being an inversion signal of the first signal is output; a control logic 104 in which the first signal is received, the first signal or the second signal is output to an output terminal, when the second signal is received, a signal in a high impedance state is output to the output terminal; and a logic circuit 20 which is connected between the mode register and the control logic and in which a test mode signal for detecting an internal signal is not input, a signal received from the mode register is sent to the control logic, when the internal signal and the test mode signal are input, the signal received from the mode register is reversed and sent to the control logic. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device capable of monitoring a signal inside a circuit.

  Conventionally, there is a DRAM (Dynamic Random Access Memory) as a kind of semiconductor memory device. Among the types of DRAMs, there is a synchronous DRAM (hereinafter referred to as SDRAM) that operates in synchronization with a clock signal having a fixed period. The SDRAM includes a DDR-SDRAM having a high-speed data transfer function called a DDR (Double Data Rate) mode, and a DDR2-SDRAM having higher performance than DDR and suppressing power consumption.

  On the other hand, the control signal inside the chip may not be as designed due to process variations and voltage dependence, so it is necessary to check whether the signal is as designed. For example, there is a method of monitoring from the outside by transmitting a signal for activating a sense to an existing output terminal in a test mode in order to check whether a control signal for determining a sense timing is as designed. An example of a method for monitoring a control signal inside a chip is disclosed in Patent Document 1. Hereinafter, the control signal inside the chip is referred to as an internal signal. A conventional method for monitoring internal signals in the DDR2-SDRAM will be described.

  FIG. 7 is a block diagram showing a configuration example of a conventional DDR2-SDRAM.

  As shown in FIG. 7, the semiconductor memory device includes a clock generator 100, a command decoder 102 to which an external signal is input, a mode register 110 for performing various settings by a user, and control signals corresponding to the various settings. Control logic 104, a row address buffer 106 for temporarily storing row addresses, a column address buffer 108 for temporarily storing column addresses, memory cell array regions 111A to 111D serving as storage regions, The data control logic 112 controls input / output and an input / output circuit 114 including an input / output buffer. A row decoder 116, a sense amplifier 118, and a column decoder 120 are provided in each of the memory cell array regions 111A to 111D. In the following, the input / output circuit 114 will be described mainly with respect to the function as an output circuit in relation to the method of monitoring internal signals at the output terminal.

  The input / output circuit 114 is provided with terminals for input / output signals DQ0 to DQk. However, k is an integer such as 3, 7, 15 or the like, and varies depending on the number of input / output terminals of the device. The output terminal for outputting the internal signal to be monitored may be set to any one of the plurality of input / output signals DQ0 to DQk, or may be set to all these terminals. Here, a terminal for monitoring the internal signal is referred to as a DQ terminal. The input / output circuit 114 is provided with a terminal for inputting / outputting DQS which is a signal for determining the timing of data transfer. DQS is an input / output signal added from the DDR specification, and is input / output in the same manner as DQ with a fixed logic. This DQS signal input / output terminal is referred to as a DQS terminal. The input / output circuit 114 is connected to a selector 130 for switching an output signal and an output control logic circuit 132 so that the user can monitor the internal signal.

  The selector 130 receives an internal signal to be monitored and internal memory data. The selector 130 normally sends internal memory data to the input / output circuit 114, and when an external test mode signal is input, sends an internal signal to the input / output circuit 114 instead of the internal memory data. When receiving the READ command signal, the output control logic circuit 132 outputs an OE (Output Enable) signal to the input / output circuit 114. When the input / output circuit 114 receives the OE signal from the output control logic circuit 132, the input / output circuit 114 sends a signal received from the selector 130 to a predetermined input / output terminal.

  Next, the operation for monitoring internal signals in the semiconductor memory device shown in FIG. 7 will be briefly described.

  Normally, when the input / output circuit 114 receives the OE signal from the output control logic circuit 132, the input / output circuit 114 sends the internal memory data received from the selector 130 to the terminals of the input / output signals DQ0 to DQk. As a result, internal data is output to the outside from these input / output terminals. On the other hand, when receiving the test mode signal, the selector 130 sends an internal signal to the input / output circuit 114 instead of the internal memory data. When the input / output circuit 114 receives the OE signal from the output control logic circuit 132, the input / output circuit 114 sends an internal signal to the DQ terminal. An internal signal is output to the DQ terminal instead of the internal memory data. In this way, in the test mode, it is possible to monitor the internal signal with the DQ terminal.

  As a method of monitoring a specific internal signal, a test mode called roll call is disclosed (see Patent Document 2). This roll call makes it possible to check which address is using redundancy by outputting a redundancy determination signal to the output terminal.

  On the other hand, the DDR2-SDRAM allows the user to set parameters such as Cas-Latency and Additive-Latency. The method will be briefly described below.

  The Cas-Latency setting is assigned to an MRS (Mode Register Set) code. The setting of Additive-Latency is assigned to the code of EMRS1 (Extended Mode Register Set-1). The user selects a code according to the parameters and sets the external signal as assigned to the code.

  FIG. 8 is a diagram schematically showing a command decoder circuit of EMRS1 in the mode register. The command decoder circuit 140 of the EMRS 1 sends a control signal to the control logic 104 when an external signal is set corresponding to the code at the address input terminal and the bank address input terminal. The command decoder 102 sends a control signal to the control logic 104 when the external signals / CS, / RAS, / CAS and / WE are set. When the control logic 104 receives control signals from the mode register 110 and the command decoder 102, the control logic 104 sends to the row address buffer 106, the column address buffer 108, the row decoder 116, the sense amplifier 118 and the input / output circuit 114 corresponding to the received control signal. Send control signal. In FIG. 7, the address inputs are A0 to A11, and the bank address inputs are BA0 and BA1, but the number of these input terminals varies depending on the size of the storage capacity.

  When Additive-Latency is set to “3”, for example, the user sets the external signals / CS, / RAS, / CAS and / WE to / CS, / RAS, / CAS, / WE = 0 (Low). In order to set the MRS mode to EMRS1, BA0 = 1 and BA1 = 0. Then, the external signals A3 to A5 are set to A3 = A4 = 1 and A5 = 0. Thereby, Additive-Latency is set to “3”.

  Further, the DDR2-SDRAM not only enables setting of various parameter values, but also has a standard specification OCD (Off Chip Driver) calibration function (hereinafter simply referred to as “OCD function”). This function allows the user to adjust the output impedance. The OCD function, which is the JEDEC standard specification in DDR2, will be briefly described below.

  The OCD function is assigned to the EMRS1 code. The logic is set in the command decoder circuit 140 of EMRS 1 in the mode register 110. As described above, when the control logic 104 receives a control signal from the command decoder circuit 140 of the EMRS 1 in the mode register 110 as described above, the control logic 104 sends a control signal to each unit, so that the DQ terminal of the input / output circuit 114 and A signal as described below is output from the DQS terminal.

  The user sets an external signal with reference to the OCD-Drive-Mode code in order to measure and adjust the output impedance. The modes include Drive (1) and Drive (0). In order to set the MRS mode to EMRS1, the external signals BA0 and BA1 are set to BA0 = 1 and BA1 = 0. When the drive (1) mode is set, the external signals A7 to A9 are set to A7 = 1 and A8 = A9 = 0. In the case of the Drive (0) mode, the external signals A7 to A9 are set to A7 = A9 = 0 and A8 = 1.

  FIG. 9A shows a waveform diagram of the Drive (1) mode, and FIG. 9B shows a waveform diagram of the Drive (0) mode.

In the case of the Drive (1) mode, as shown in FIG. 9A, when the Drive (1) mode is entered in the mode register 110, “H” is output from the DQ terminal and the DQS terminal of the input / output circuit 114. Although not shown in the figure, “L” is output from the output terminal of DQSB which is a signal having a phase opposite to that of the DQS signal. In the Drive (0) mode, as shown in FIG. 9B, “L” is output from the DQ terminal and the DQS terminal of the input / output circuit 114, as opposed to the Drive (1) mode. “H” is output from the output terminal of the DQSB. By entering Drive (1) or Drive (0) assigned to one of the mode register sets in the standard specification, the output of the DQ terminal and DQS terminal of the input / output circuit 114 is set to “H” or “L”. Thus, in the DDR2 product, the logic is set in the mode register 110.
Japanese Patent Laid-Open No. 61-66295 Japanese Patent Laid-Open No. 2000-231796

  When the test mode is incorporated in the chip design, the data of the internal output data path is transmitted to the output terminal. Therefore, it is necessary to add a selector for switching between the data path and the internal signal depending on the test mode. In this case, a side effect of access path delay occurs due to the test mode.

  In addition, in order to output data to the output terminal, the output control logic circuit requires a test mode logic. Normally, upon receipt of the READ command, the OE signal is activated and the output control logic circuit operates. However, logic for activating the OE is required also in the test mode. And because of the test mode, an extra load is added to the normal data path.

  The logic for activating the output circuit is created from the READ command, but the output control logic circuit in DDR is complicated due to specifications such as Cas-Latency and Additive-Latency. When adding a test mode to monitor, there was a problem that it became more complicated.

  The present invention has been made to solve the above-described problems of the prior art, and provides a semiconductor memory device capable of detecting a signal to be monitored in a circuit with an existing output terminal. The purpose is to do.

In order to achieve the above object, a semiconductor memory device of the present invention is a semiconductor memory device for detecting an internal signal to be monitored in a circuit at an output terminal,
When a predetermined mode is set by a signal input from the outside, a first signal is output, and when the predetermined mode is not set, a second signal that is an inverted signal of the first signal is output. A mode register;
When receiving the first signal, output the first signal or the second signal to the output terminal, and when receiving the second signal, output a signal in a high impedance state to the output terminal. Control logic,
When a test mode signal connected between the mode register and the control logic and detecting the internal signal is not input, a signal received from the mode register is sent to the control logic, and the internal signal and the test When a mode signal is input, a logic circuit that inverts a signal received from the mode register and sends it to the control logic;
It is the structure which has.

  In the present invention, after the mode register is set to the predetermined mode, the logic circuit is set to the test mode, and when the internal signal to be monitored is input to the logic circuit, the signal output from the output terminal is the first signal. Since the signal or the second signal transits to the high impedance state signal, the internal signal can be detected at the output terminal. In addition, if the time from when the internal signal is input to when the output of the output terminal transitions is measured, the time until activation of the internal signal can be measured.

  According to the present invention, since a logic that switches the output state according to the setting of the mode register is used, it is not necessary to add a large-scale circuit. By simply adding a small-scale logic circuit, it is possible not only to monitor the internal signal at the output terminal, but also to suppress the side effect of access path delay.

  The semiconductor memory device of the present invention includes a logic circuit for outputting an internal signal to be monitored to an output terminal in the middle of a predetermined circuit like the standard OCD function in DDR2-SDRAM. And

  The configuration of the semiconductor memory device of this embodiment will be described.

  FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device of this embodiment. In addition, about the structure similar to the conventional figure, the same code | symbol is attached | subjected and the detailed description is abbreviate | omitted.

  As shown in FIG. 1, a logic circuit 20 is connected to a mode register 110 in the semiconductor memory device of this embodiment. A signal line (not shown) through which an internal signal to be monitored is transmitted is branched and connected to the logic circuit 20. In addition to the signal from the mode register 110, an internal signal to be monitored is input to the logic circuit 20. The output of the logic circuit 20 becomes the output OUT2 of the mode register 110. In this embodiment, it is assumed that the OCD function is set to operate.

  FIG. 2 is a diagram showing the configuration of the logic circuit 20 of this embodiment.

  As shown in FIG. 2, the logic circuit 20 includes NANDs 21 and 22 of a negative logical product and an INV 23 of a negative gate. The NAND 21 receives an internal signal Sig-A and a test mode signal Sig-T that is a signal for enabling the test mode. The test mode signal Sig-T is set by an external signal, and becomes inactive when “0” (Low) and becomes active when “1” (High). The test mode signal Sig-T is supplied from the mode register 110 to the logic circuit 20. The NAND 22 receives the output signal OUT1 from the command decoder circuit 140 of the ERMS1 and the output signal of the NAND21. The INV 23 receives the output signal of the NAND 22 and sends the output signal to the control logic 104 as the output signal OUT 2 of the mode register 110.

  Next, the operation of the logic circuit 20 shown in FIG. 2 will be described.

  During normal operation, the test mode signal Sig-T is “L” (inactive), and OUT1 = OUT2. In this case, the user can perform OCD calibration and various parameter settings in the same manner as before.

  Next, a method for detecting an internal signal to be monitored will be described. 3 and 4 are waveform diagrams for explaining a method of detecting an internal signal to be monitored. FIG. 3 is a waveform diagram showing the case of the Drive (1) mode, and FIG. 4 is a waveform diagram showing the case of the Drive (0) mode.

  As shown in FIG. 3, when the test mode signal Sig-T is in the “L” state and the OCD-Drive (1) is entered, the DQ terminal and the DQS terminal are not electrically connected to each other according to the specification. From the Hi-Z state, the output is “H”. After entering the Drive mode, the test mode signal Sig-T = “H” is entered to enter the test mode. Here, for example, it is assumed that the internal signal Sig-A to be monitored is a signal output from the ACT command at a certain time.

  After entering the test mode, when an ACT command is input at a certain CK timing and Sig-A = “H”, the output of the NAND 21 becomes “L”. The NAND 22 outputs “H” because OUT 1 is “H” and “L” is input from the NAND 21. The INV 23 receives “H” and outputs “L”. As a result, the OUT2 of the Drive (1) mode signal changes from “H” to “L”, and the outputs of the DQ terminal and the DQS terminal change from “H” to “Hi-Z”. If this timing is detected using a tester or the like, the output terminals DQ and DQS can detect how long Sig-A is activated from the ACT command.

  The logic circuit 20 shown in FIG. 3 enters the test mode, and when OUT1 = “H” and OUT2 = “H”, when the internal signal to be monitored transitions from “L” to “H”, OUT2 = "L".

  On the other hand, when an internal signal is detected in the Drive (0) mode, the logic circuit 20 shown in FIG. 3 is connected to the output of OUT1 ′ different from the signal path of OUT1 shown in FIG. The output from the logic circuit 20 to the control logic 104 is OUT2 '. If the user designates the Drive (0) mode with the OCD function, the output from the DQ terminal and the DQS terminal of the input / output circuit 114 becomes “L” by the signal from OUT1 ′.

  In the case where the logic circuit 20 is incorporated in the logic of the Drive (0) mode, as shown in FIG. 4, the internal signal to be monitored is detected by detecting the transition of OUT2 from “L” to “Hi-Z”. The time to activation will be measured. Since the operation of the logic circuit 20 is the same as that described with reference to FIG. 3, detailed description thereof is omitted here.

  Note that the circuit configuration may be different from that of the present embodiment as long as the logic is the same, and even in this case, the logic circuit can be easily realized by adding a small number of logic elements.

  In the semiconductor memory device of this embodiment, when the logic circuit 20 is set to the test mode and an internal signal to be monitored is input to the logic circuit 20, the signal output from the output terminal is changed from “H” or “L”. Since the transition is made to Hi-Z, the internal signal can be detected at the output terminal. In addition, if the time from when the internal signal is input to when the output of the output terminal transitions is measured, the time until activation of the internal signal can be measured.

  The semiconductor memory device according to the present embodiment uses a logic represented by the OCD function of the DDR2-SDRAM so that the output state is switched according to the setting of the mode register. Therefore, it is not necessary to add a large-scale circuit. . As a result, it is possible to realize a test mode in which side effects of access path delay are suppressed and an internal signal is detected at the output terminal.

  In the first embodiment, a circuit is added to the logic of the Drive (0) mode or the Drive (1) mode of the OCD function. However, in this embodiment, a circuit is added to the logic of the Drive (0) mode and the Drive (1) mode. Thus, the transition of the internal signal is detected. The configuration of the present embodiment will be described below. Since the configuration other than the logic circuit is the same as that of the first embodiment, detailed description thereof is omitted. The same reference numerals are given to the same configurations as those in the first embodiment, and the detailed description thereof is omitted.

  FIG. 5 is a diagram showing a configuration example of the logic circuit of this embodiment. As shown in FIG. 5, the command decoder circuit 140 of EMRS1 outputs a signal OUT1 for outputting “H” to the DQ terminal and the DQS terminal in the Drive (1) mode, and in the Drive (0) mode. And a signal path for outputting a signal OUT3 for outputting “L” to the DQ terminal and the DQS terminal. Here, since the Drive (1) mode is set by an external signal, the Drive (1) mode signal of OUT1 is “H”, and the Drive (0) mode signal of OUT3 is “L”.

  In this embodiment, a logic circuit 30 is connected instead of the logic circuit 20 of the first embodiment. The logic circuit 30 includes NAND circuits 21 and 22 of negative logical products, INV 23 of negative gates, INVs 24 and 26, and NOR 25 of negative logical sums. The connections of the NANDs 21 and 22 and the INV 23 are the same as in the first embodiment. The output of the NAND 21 is input to the INV 24. The output of INV24 and OUT3 are input to NOR25. The INV 26 receives the output of the NOR 25 and sends an output signal to the control logic 104 as OUT4.

  Note that the signal line that outputs OUT2 becomes a signal path for outputting “H” to the DQ terminal and the DQS terminal in the Drive (1) mode, and the signal line that outputs OUT4 is the DQ terminal and DQS in the Drive (0) mode. This is a signal path for outputting "L" to the terminal.

  Next, the operation of the logic circuit 30 of this embodiment will be described.

  During normal operation, the test mode signal Sig-T is “L” (inactive), OUT1 = OUT2, and OUT3 = OUT4. In this case, the user can perform OCD calibration and various parameter settings in the same manner as before.

  Next, a method for outputting an internal signal to be monitored will be described. FIG. 6 is a waveform diagram for explaining the operation of the logic circuit of this embodiment.

  As shown in FIG. 6, when the test mode signal Sig-T is in the “L” state and OCD-Drive (1) is entered, OUT1 = OUT2 = “H”, and the DQ terminal and the DQS terminal are changed from Hi-Z. “H” output. Thereafter, when the test mode is entered, the test mode signal Sig-T = “H”. Assume that the internal signal Sig-A to be monitored is a signal that is output from the ACT command at a certain time. When an ACT command is input at a certain CK timing, the internal signal Sig-A changes from “L” to “H”, and OUT2 changes from “H” to “L” as in the first embodiment.

  On the other hand, when the internal signal Sig-A transitions from “L” to “H”, the output of the NAND 21 becomes “L” and the output of the INV 24 becomes “H”. The NOR 25 outputs the “L” signal to the INV 26 when the “H” signal of the INV 24 and the “L” signal of the OUT 3 are input. When receiving the “L” signal from the NOR 25, the INV 26 outputs the “H” signal. In this way, as shown in FIG. 6, OUT4 changes from “L” to “H”.

  As described above, OUT2 changes from “H” to “L” and the Drive (1) mode is deactivated, but OUT4 changes from “L” to “H” and the Drive (0) mode is activated. It becomes. Therefore, as shown in FIG. 6, the outputs of the DQ terminal and the DQS terminal are switched from “H” to “L”. If this timing is detected using a tester or the like, the output terminals DQ and DQS can detect how long Sig-A is activated from the ACT command.

  The logic circuit 30 shown in FIG. 5 enters the test mode, and when OUT1 = OUT2 = “H” and OUT3 = OUT4 = “L”, the internal signal to be monitored changes from “L” to “H”. When a transition is made, a logical configuration is adopted in which OUT2 transitions to “L” and OUT4 transitions to “H”.

  It should be noted that the detection of the internal signal at the output terminal can be switched from “L” to “H” by reversing the test mode logic added to Drive (1) and Drive (0). In this case, the Drive (0) mode signal is output to the signal path that is input to the NAND 22, and the Drive (1) mode signal is output to the signal path that is input to the NOR 25. The output from the INV 23 becomes a signal for the Drive (0) mode, and the output from the INV 26 becomes a signal for the Drive (1) mode and is input to the control logic 104, respectively.

  In the semiconductor memory device of this embodiment, even in a tester environment or an evaluation environment in which switching from “H” or “L” to “Hi-Z” is difficult to detect, the signal change of the detection target changes from “H” to “L”. Since it is a transition to ", detection becomes easier and the switching timing can be obtained more accurately. Further, the logic for the test mode of the present embodiment only requires addition of a small number of logic elements as shown in FIG. 5, and does not require addition of a large-scale circuit.

  Since the semiconductor memory device of the present invention uses logic such as the OCD function of DDR2-SDRAM that changes the output state by setting the mode register, it is necessary to add a large-scale circuit. Absent. As a result, it is possible to realize a test mode in which side effects of access path delay are suppressed and an internal signal is detected at the output terminal. Also, internal signals can be monitored from the outside simply by adding a small logic. Furthermore, it is possible to know at what timing the actual semiconductor is operating depending on the process and voltage, and timing adjustment and design accuracy can be improved.

  In the first and second embodiments, the change of the internal signal is detected by the DQ terminal and the DQS terminal. However, the present invention is not limited to the DQ terminal and the DQS terminal, and is set to one of the terminals in advance. Then, the change may be detected.

  In addition, the present invention can be applied not only to the OCD function of DDR2, but also to a semiconductor memory device provided with logic that switches the output state depending on the setting of the mode register.

1 is a block diagram illustrating a configuration example of a semiconductor memory device according to a first embodiment. 1 is a diagram illustrating a configuration example of a logic circuit according to a first embodiment. It is a wave form diagram for demonstrating the detection method of the internal signal used as monitoring object. It is a wave form diagram for demonstrating the detection method of the internal signal used as monitoring object. FIG. 6 is a diagram illustrating a configuration example of a logic circuit according to a second embodiment. FIG. 6 is a diagram for explaining the operation of the logic circuit shown in FIG. 5. It is a block diagram which shows the example of 1 structure of the conventional semiconductor memory device. It is a figure which shows typically the inside of a mode register. It is a wave form diagram for demonstrating an OCD function.

Explanation of symbols

20 logic circuit 104 control logic 110 mode register

Claims (5)

A semiconductor memory device for detecting an internal signal to be monitored in a circuit at an output terminal,
When a predetermined mode is set by a signal input from the outside, a first signal is output, and when the predetermined mode is not set, a second signal that is an inverted signal of the first signal is output. A mode register;
When receiving the first signal, output the first signal or the second signal to the output terminal, and when receiving the second signal, output a signal in a high impedance state to the output terminal. Control logic,
When the test mode signal connected between the mode register and the control logic and detecting the internal signal is not input, a signal received from the mode register is sent to the control logic, and the internal signal and the test logic are sent. When a mode signal is input, a logic circuit that inverts a signal received from the mode register and sends it to the control logic;
A semiconductor memory device. The mode register is
When the first mode of the predetermined modes is set, a first signal path for sending a signal to the logic circuit and a second of the predetermined modes different from the first mode And a second signal path for sending a signal to the logic circuit,
The logic circuit is:
Corresponding to a signal received via the first signal path, a third signal path for sending a signal to the control logic in response to a signal received via the first signal path, and a signal received via the second signal path The semiconductor memory device according to claim 1, further comprising a fourth signal path for transmitting a signal to the control logic. The mode register is
When set to the first mode, the first signal is sent to the logic circuit via the first signal path, and the second signal is sent to the logic circuit via the second signal path. To the circuit,
The control logic is
When the first signal is received via the third signal path, the first signal is output to the output terminal, and then the first signal is received via the fourth signal path. The semiconductor memory device according to claim 2, wherein the second signal is output to the output terminal. The mode register is
When the second mode is set, the second signal is sent to the logic circuit via the first signal path, and the first signal is sent to the logic circuit via the second signal path. To the circuit,
The control logic is
When the first signal is received via the fourth signal path, the second signal is output to the output terminal, and then the first signal is received via the third signal path. 3. The semiconductor memory device according to claim 2, wherein the first signal is output to the output terminal.   5. The device according to claim 2, wherein the first mode is a Drive (1) mode of an OCD function of the DDR2-SDRAM, and the second mode is a Drive (0) mode of the OCD function. 6. The semiconductor memory device described.

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