JP2007051936A - Method of specifying fault position in scan chain - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance precision for specifying a fault position while reducing the number of wires and design man-hours, in a method of specifying a fault position in a scan chain. <P>SOLUTION: This method of specifying a fault position in the scan chain SC2 includes a step for setting all the respective flip-flops FF1-FF10 to "0" by reset, so as to set initially all the respective outputs to "1", and a step for specifying the fault position on the scan chain, by comparing a bit sequence output from scan-out by a scan shift with an expected value bit sequence, using the scan chain SC2 constituted with all the plurality of flip-flops FF1-FF10 of an NQ output, allowing the reset, and constituted by connecting the flip-flops FF1-FF10 of the NQ output repeatedly such as "NQ output→NQ output→ → →" , as inspection object. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for identifying a fault location (defective flip-flop) in a scan chain.

  The serial scan chain will be briefly described. In the scan chain SC10 shown in FIG. 11A, three stages of flip-flops FF1 to FF3 are serially connected. As shown in FIG. 11B, a clock is applied to each flip-flop at the same timing. The flip-flop FF1 fetches data at the first clock, the flip-flop FF2 fetches data at the second clock, and the flip-flop FF3 fetches data at the third clock.

  However, as shown in FIG. 11C, the timing of the clock may be shifted due to a wiring delay or the like. In this example, there is a delay in the clock of the flip-flop FF2. Therefore, the flip-flop FF2 captures data at the first clock. As a result, the flip-flop FF2 does not perform a scan shift operation, and data passes through. Such a flip-flop is called a defective flip-flop.

  Scan design is a method for facilitating testing of logic circuits, and since it can efficiently generate a test pattern with a high failure detection rate, it has been increasingly used in recent years. A method for detecting a defective flip-flop in a conventional serial scan chain will be described with reference to FIGS.

  The scan chain shown in FIG. 12A is configured by serial connection of flip-flops FF1 to FF5. By applying a clock, the data of the previous flip-flop is fetched from the data input terminal D and output to the Q output terminal. Send to stage flip-flop. Each flip-flop FF1 to FF5 has a reset terminal R connected in common, and every other flip-flop FF2 and FF4 has a preset terminal S.

  In detecting a defective flip-flop, first, a pulse is applied to the reset terminal R to clear “0” in all the flip-flops FF1 to FF5. Next, a pulse is applied to the preset terminal S to set every other stage flip-flops FF2 and FF4 to "1". The set data string is “01010” in order from the first stage.

  Next, scan shift is performed, and the output bit string from the shift-out is compared with the expected value bit string (initial value bit string) “01010”. In the normal scan shift operation, the output bit string matches the expected value bit string as shown in FIG. If they do not match, there is a defective flip-flop in the scan chain. For example, when the second-stage flip-flop FF2 is defective as shown in FIG. 12B, the output bit string becomes “X0010” from the bottom to the top as shown in FIG. 13B. .

Output bit string: X 0 010
Expected value bit string: 0 1 010
It is. The three bits from the back (top) match with “010”, and the fourth bit does not match. The fourth bit that does not match is the second bit from the front (bottom), which corresponds to a defective flip-flop. Thus, since the output bit string is immobile with respect to the expected value bit string at the defective flip-flop, the second-stage flip-flop FF2 is identified as a defective flip-flop. Similarly, if the output bit string is “XX110” from bottom to top,
Output bit string: XX 1 10
Expected value bit string: 01 0 10
The flip-flop SS3 is identified as a defective flip-flop.
JP-A-6-230075 (page 2-3, FIG. 1-2)

  In the conventional configuration described above, the flip-flops constituting the scan chain must be configured to be preset in addition to reset, and there are problems such as an increase in wiring and a layout increase. In addition, the placement and wiring in which flip-flops having preset terminals every other stage are troublesome in the current EDA (Electronic Design Automation) tool, and the number of design steps is increased.

  The present invention solves the above-mentioned conventional problems, and aims to improve the accuracy of fault location while reducing the number of wirings and the design man-hours in the fault location specifying method in the scan chain. .

The fault location method in the scan chain according to the present invention is:
A plurality of flip-flops in the scan chain can output NQ, the NQ output terminal of the first stage flip-flop is connected to the data input terminal of the next stage flip-flop, and the NQ output terminal of the next stage flip-flop is connected to the third stage flip-flop. For example, a scan chain configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →...” Is connected to the data input terminal of the flip-flop.
Setting each flop flop to a predetermined initial value by a system reset; and
Next, the step of identifying a failure position on the scan chain by comparing the bit string output from the scan-out by the scan shift with the expected value bit string is included. This is a flip-flop that can cope with a flip-flop with a reset terminal without a preset terminal and a flip-flop with a preset terminal without a reset terminal in any order.

  According to this, since the serial connection state of the plurality of flip-flops constituting the scan chain is the NQ output repetitive connection, the expected value bit string that is the output bit string from the scan-out when there is no defective flip-flop is the initial output In the bit string, the logic is inverted every other bit. If there is a defective flip-flop, the logical inversion of every other bit changes in the bit at the position corresponding to the defective flip-flop, and the bit of the flip-flop before the defective flip-flop also changes every other bit. The logic inversion changes. As a result, it is possible to ensure the accuracy of specifying the fault location in the scan chain only by adjusting the flip-flop connection such that the flip-flop serial connection is NQ output repetition.

Further, the fault location method in the scan chain according to the present invention is:
All the flip-flops in the scan chain have an NQ output configuration and can be reset, the NQ output terminal of the first flip-flop is connected to the data input terminal of the next flip-flop, and the NQ output terminal of the next flip-flop Is connected to the data input terminal of the third stage flip-flop, and a scan chain configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →.
Setting all of the flip-flops to “0” by resetting;
Next, the step of identifying the fault location on the scan chain by comparing the bit string output from the scan-out by the scan shift with the expected value bit string is included.

  According to this, after the serial connection state of a plurality of flip-flops constituting the scan chain is set to repeat connection of NQ outputs, all flip-flops are initialized to “0” by reset, and all the outputs are set to “0”. Since it is configured so as to be initially set to 1 ″, if scan shift is performed, it is possible to output in a state where negative logic and positive logic (or positive logic and negative logic) alternate in time series from scan-out. . As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, it is possible to improve the accuracy of specifying the fault location in the scan chain simply by configuring the flip-flop in the NQ output repetition type scan chain with a flip-flop with a reset terminal without a preset terminal and enabling all reset at the time of testing. it can.

Further, the fault location method in the scan chain according to the present invention is:
A plurality of flip-flops in the scan chain can be preset with an NQ output configuration, the NQ output terminal of the first stage flip-flop is connected to the data input terminal of the next stage flip-flop, and the NQ output terminal of the next stage flip-flop Is connected to the data input terminal of the third stage flip-flop, and a scan chain configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →.
Setting all flip-flops to “1” by presetting;
Next, the step of identifying the fault location on the scan chain by comparing the bit string output from the scan-out by the scan shift with the expected value bit string is included.

  According to this, after the serial connection state of a plurality of flip-flops constituting the scan chain is set to the repeated connection of NQ output, all flip-flops are initially set to “1” by presetting, and all outputs are all set to “1”. Since it is configured so as to be initially set to “0”, if a scan shift is performed, it is possible to output in a state in which positive logic / negative logic (or negative logic / positive logic) alternate in time series from scan-out. . As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, it is possible to improve the accuracy of specifying the fault location in the scan chain simply by configuring the flip-flop in the NQ output repetition type scan chain as a flip-flop with a preset terminal without a reset terminal and enabling all presets during testing. it can.

Further, the fault location method in the scan chain according to the present invention is:
All the flip-flops in the scan chain can be reset, the Q output terminal of the first flip-flop is connected to the data input terminal of the next flip-flop, and the NQ output terminal of the next flip-flop is connected to the third stage flip-flop. Connect to the data input terminal of the flip-flop, connect the Q output terminal of the third-stage flip-flop to the data input terminal of the fourth-stage flip-flop, and so on, such as “Q output → NQ output → Q output → NQ output” → ... ”scan chain configured by alternately connecting Q output and NQ output flip-flops as inspection targets,
Setting all of the flip-flops to “0” by resetting;
Next, the step of identifying the fault location on the scan chain by comparing the bit string output from the scan-out by the scan shift with the expected value bit string is included.

  According to this, after the serial connection state of a plurality of flip-flops constituting the scan chain is set to alternately and repeatedly connect Q output and NQ output, all flip-flops are initialized to “0” by reset, Since the output is configured to be initially set to “0” and “1” alternately, if scan shift is performed, positive logic / negative logic (or negative logic / positive logic in units of 2 bits in time series from scan-out) Output in a state of alternating logic) is possible. As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, the flip-flop in the Q output / NQ output alternating scan chain is composed of a flip-flop with a reset terminal without a preset terminal. It is possible to ensure the accuracy of specifying the fault location in the chain.

  In the above, instead of the order of “Q output → NQ output → Q output → NQ output →...”, QN output and Q output are changed as “QN output → Q output → QN output → Q output →. A step chain similar to the above may be performed on a scan chain in which flip-flops are alternately connected, and the same effect is exhibited.

Further, the fault location method in the scan chain according to the present invention is:
All the flip-flops in the scan chain can be preset, the Q output terminal of the first flip-flop is connected to the data input terminal of the next flip-flop, and the NQ output terminal of the next flip-flop is connected to the third stage flip-flop. Connect to the data input terminal of the flip-flop, connect the Q output terminal of the third-stage flip-flop to the data input terminal of the fourth-stage flip-flop, and so on, such as “Q output → NQ output → Q output → NQ output” → ... ”scan chain configured by alternately connecting Q output and NQ output flip-flops as inspection targets,
Setting all of the flip-flops to “1” by presetting;
Next, the step of identifying the fault location on the scan chain by comparing the bit string output from the scan-out by the scan shift with the expected value bit string is included.

  According to this, after the serial connection state of a plurality of flip-flops constituting the scan chain is set to alternately and repeatedly connect Q output and NQ output, all flip-flops are initially set to “1” by preset, Since the output is configured to be initially set to “1” and “0” alternately, if scan shift is performed, negative logic / positive logic (or positive logic / negative logic in chronological order in units of 2 bits from scan out) Output in a state of alternating logic) is possible. As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, the flip-flop in the Q output / NQ output alternating scan chain is composed of a flip-flop with a preset terminal without a reset terminal, and it is possible to scan all in two bits by making all preset possible during testing. It is possible to ensure the accuracy of specifying the fault location in the chain.

  In the above, instead of the order of “Q output → NQ output → Q output → NQ output →...”, QN output and Q output are changed as “QN output → Q output → QN output → Q output →. A step chain similar to the above may be performed on a scan chain in which flip-flops are alternately connected, and the same effect is exhibited.

  According to the present invention, in a scan design for testability of a logic circuit, it is possible to easily identify a fault location with an appropriate circuit scale and design man-hour by devising a connection form of flip-flops constituting a scan chain. .

  Embodiments of a fault location specifying method in a scan chain according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
The first embodiment of the present invention can cope with any flip-flops having no preset terminal and having a reset terminal and flip-flops having no reset terminal and having a preset terminal arranged in any order. Is. A failure location specifying method in a scan chain according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1A shows a circuit configuration of the scan chain SC1 in the case of the first embodiment, and FIG. 1B shows a defective example thereof. The scan chain SC1 is configured by connecting a plurality of flip-flops FF1, FF2,... FF10 via a wiring pattern. Each flip-flop is configured to take data from the data input terminal D one stage before by applying a clock, output the fetched data to the NQ output terminal, and send it to the flip-flop of the next stage. Further, a plurality of flip-flops in the scan chain SC1 are repeatedly connected with NQ output. Each flip-flop can be set to an initial value by a system reset of the LSI, and is set to “0” or “1”. In the illustrated example, the flip-flop FF3 has a preset terminal S and is set to "1" by a system reset, and all other flip-flops have a reset terminal R and are set to "0" by a system reset. It has come to be. Of course, this is only an example, and it is needless to say that it may take other arbitrary forms.

  In this embodiment, a plurality of flip-flops FF1 to FF10 in the scan chain SC1 can output NQ, the NQ output terminal of the first flip-flop FF1 is connected to the data input terminal of the next flip-flop FF2, and the next stage The NQ output terminal of the flip-flop FF2 is connected to the data input terminal of the third-stage flip-flop FF3, and the NQ output terminal of the third-stage flip-flop FF3 is connected to the data input terminal of the fourth-stage flip-flop FF4. For example, a scan chain SC1 formed by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →. Then, a step of setting each flop flop FF1 to FF10 to a predetermined initial value by a system reset, and then comparing a bit string output from the scan-out by a scan shift with an expected value bit string, thereby determining a fault position on the scan chain SC1. Identifying step.

  In the present embodiment, confirmation of the scan shift operation of the scan chain SC1 is performed according to the following procedure.

First, a system reset is applied to give initial values to all stages of flip-flops FF1 to FF10. Next, the scan chain SC1 is scan-shifted. FIG. 2A shows a bit string shift diagram when nine clocks are applied. Individual bit data transition as indicated by diagonal arrows. The bit data is inverted every time it is shifted to the next flip-flop. That is, the transition is made along the arrow in the order of “1” → “0” → “1” → “0”. Alternatively, transition is made as “0” → “1” → “0” → “1”. The output bit string (bit pattern) output from the scan-out that is the output of the flip-flop FF10 is as follows. The initial output bit string in the flip-flops FF1 to FF10 is from left to right.
Initial output bit string: 11011111111
It is. The output bit string of the scanout that is the output of the flip-flop FF10 is from bottom to top,
Output bit string: 0111010101
It is. This is the case when there is no defective flip-flop. When comparing the initial output bit string and the output bit string, the odd bit is inverted as “1” → “0” or “0” → “1”, and the even bit is not inverted. The output bit string when there is no defective flip-flop becomes the expected value bit string. This is the case where the number of flip-flops is an even number of ten.

If the number of flip-flops is an odd number such as 9, the contrast between the initial output bit string and the output bit string is
Initial output bit string: 110111111
Output bit string: 100010101
It becomes. In this case, the even bit is inverted as “1” → “0” or “0” → “1”, and the odd bit is not inverted. Also in this case, the output bit string when there is no defective flip-flop becomes the expected value bit string.

  As described above, since the serial connection state of the plurality of flip-flops FF1 to FF10 constituting the scan chain SC1 is the repeated connection of NQ output, an expected value bit string that is an output bit string from the scan-out when there is no defective flip-flop Are logically inverted every other bit in the initial output bit string.

  Then, the normal scan-out output bit string in FIG. 2A is compared with the expected value bit string (both from bottom to top).

Output bit string: 0111010101
Expected value bit string: 0111010101
As described above, when there is no defective flip-flop, all bits of the output bit string match the expected value bit string.

  On the other hand, when an output bit string different from the expected value bit string is observed, there is a defective flip-flop in the scan chain SC1, and the defective flip-flop is specified by the following method.

  That is, as shown in FIG. 1B, for example, when the sixth-stage flip-flop FF6 is defective, the output bit string becomes “X000100101” as shown in FIG.

Output bit string: X0001 0 0101
Expected value bit string: 01110 1 0101
It is. “1010” (in reverse order) for 4 bits from the back (top) matches each other and does not match at the 5th bit. The fifth bit that does not match is the sixth bit from the front (bottom), which corresponds to a defective flip-flop. In this way, the failure position (position of the defective flip-flop) in the scan chain SC1 can be specified.

  In summary, if there is a defective flip-flop, the logical inversion every other bit changes in the bit at the position corresponding to the defective flip-flop. The logic inversion every other bit changes. As a result, it is possible to ensure the accuracy of specifying the fault location in the scan chain only by adjusting the flip-flop connection such that the flip-flop serial connection is NQ output repetition. As a flip-flop, any flip-flop with a reset terminal without a preset terminal and flip-flop with a preset terminal without a reset terminal can be handled in any order.

  If the method of this embodiment is applied to a flip-flop-connected scan chain in which the initial values alternate between “1” and “0”, there is a possibility that a defective flip-flop may be missed. On the other hand, an embodiment for increasing detection accuracy will be described below.

(Embodiment 2)
In the second embodiment of the present invention, all flip-flops in the scan chain have an NQ output configuration and can be reset. A failure location specifying method in the scan chain according to the second embodiment of the present invention will be described with reference to FIGS.

  FIG. 3A shows a circuit configuration of the scan chain SC2 in the case of the second embodiment, and FIG. 3B shows a defective example thereof. The plurality of flip-flops FF1 to FF10 in the scan chain SC2 are repeatedly connected with the NQ output. A system reset and a soft reset are input to the reset terminals R of the flip-flops FF1 to FF10 via the OR gate 5, and each of the flip-flops FF1 to FF10 is “0” not only by the system reset but also by the soft reset. "Can be set. Other configurations are the same as those in FIG. 1 in the first embodiment, and thus the description thereof is omitted.

  In the present embodiment, all the plurality of flip-flops FF1 to FF10 in the scan chain SC2 can be reset with an NQ output configuration, and the NQ output terminal of the first-stage flip-flop FF1 is used as the data input terminal of the next-stage flip-flop FF2. Connect the NQ output terminal of the next flip-flop FF2 to the data input terminal of the third flip-flop FF3, and connect the NQ output terminal of the third flip-flop FF3 to the data of the fourth flip-flop FF4. For example, a scan chain SC2 configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →...” Is connected to the input terminal. Then, the step of setting all the flip-flops FF1 to FF10 to “0” by reset, and then comparing the bit string output from the scan-out by the scan shift with the expected value bit string, thereby determining the fault position on the scan chain SC2. Identifying step. Since the serial connection state of the flip-flops FF1 to FF10 is repeated connection of NQ outputs, if all the flip-flops FF1 to FF10 are initialized to “0” by reset, all the outputs are initialized to “1”. The This is shown in the soft reset stage in FIGS. 4 (a) and 4 (b).

  In the present embodiment, confirmation of the scan shift operation of the scan chain SC2 is performed according to the following procedure.

  First, a soft reset (or system reset) is applied to set “1” as the initial value of the output to all stages of the flip-flops FF1 to FF10. Next, the scan chain SC2 is scan-shifted. FIG. 4A shows a bit string shift diagram when nine clocks are applied. Individual bit data transition as indicated by diagonal arrows. The bit data is inverted every time it is shifted to the next flip-flop. That is, the transition is made along the arrow in the order of “1” → “0” → “1” → “0”. The output bit string (bit pattern) from the scan-out is compared with the expected scan-out expected value bit string “0101010101” (from the bottom) in FIG. 4A. From the scan-out, the output is in a state of alternating negative logic and positive logic in time series.

  When an output bit string different from the expected value bit string is observed, there is a defective flip-flop in the scan chain SC2, and the defective flip-flop is specified by the following method.

  That is, as shown in FIG. 3B, for example, when the sixth-stage flip-flop FF6 is defective, the output bit string is “X010100101” from bottom to top as shown in FIG. 4B. Become.

Output bit string: X0101 0 0101
Expected value bit string: 01010 1 0101
It is. “1010” (in reverse order) for 4 bits from the back (top) matches each other and does not match at the 5th bit. The fifth bit that does not match is the sixth bit from the front (bottom), which corresponds to a defective flip-flop. In this way, the failure position (position of the defective flip-flop) in the scan chain SC2 can be specified.

  In summary, the serial connection state of a plurality of flip-flops constituting the scan chain is set to NQ output repetitive connection, all flip-flops are initially set to “0” by reset, and each output is all set to “1”. Therefore, if scan shift is performed, it is possible to output in a state where negative logic and positive logic (or positive logic and negative logic) alternate in time series from scan-out. As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, it is possible to improve the accuracy of specifying the fault location in the scan chain simply by configuring the flip-flop in the NQ output repetition type scan chain with a flip-flop with a reset terminal without a preset terminal and enabling all reset at the time of testing. it can.

(Embodiment 3)
In the third embodiment of the present invention, all the plurality of flip-flops in the scan chain have an NQ output configuration and can be preset. A fault location specifying method in the scan chain according to the third embodiment of the present invention will be described with reference to FIGS.

  FIG. 5A shows a circuit configuration of the scan chain SC3 in the case of the third embodiment, and FIG. 5B shows a defective example thereof. A plurality of flip-flops FF1 to FF10 in the scan chain SC3 are repeatedly connected with an NQ output. Each of the flip-flops FF1 to FF10 has a preset terminal S, can be set to “1” by presetting, and an initial value of each output can be set to “0”. Other configurations are the same as those in FIG. 1 in the first embodiment, and thus the description thereof is omitted.

  In the present embodiment, all the plurality of flip-flops FF1 to FF10 in the scan chain SC3 can be preset with an NQ output configuration, and the NQ output terminal of the first-stage flip-flop FF1 is used as the data input terminal of the next-stage flip-flop FF2. Connect the NQ output terminal of the next flip-flop FF2 to the data input terminal of the third flip-flop FF3, and connect the NQ output terminal of the third flip-flop FF3 to the data of the fourth flip-flop FF4. A scan chain SC3 configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →...” Is connected to the input terminal. A step of setting all of the flip-flops FF1 to FF10 to “1” by a preset, and then comparing the bit string output from the scan-out by the scan shift with the expected value bit string, thereby determining the failure position on the scan chain SC3. Identifying step. Since the serial connection state of the flip-flops FF1 to FF10 is a repeated connection of NQ outputs, if all the flip-flops FF1 to FF10 are initialized to “1” by presetting, all outputs are initialized to “0”. The This is shown in the preset stage in FIGS. 6 (a) and 6 (b).

  In the present embodiment, confirmation of the scan shift operation of the scan chain SC3 is performed according to the following procedure.

  First, a preset is applied to set “0” as an initial value of the output to all stages of the flip-flops FF1 to FF10. Next, the scan chain SC3 is scan-shifted. FIG. 6A shows a bit string shift diagram when nine clocks are applied. Individual bit data transition as indicated by diagonal arrows. The bit data is inverted every time it is shifted to the next flip-flop. That is, a transition is made along the arrow as “0” → “1” → “0” → “1”. The output bit string (bit pattern) from the scan-out is compared with the expected scan-out expected value bit string “1010101010” (from the bottom) in FIG. 6A. From the scan-out, the output is in a state of alternating positive logic and negative logic in time series.

  When an output bit string different from the expected value bit string is observed, there is a defective flip-flop in the scan chain SC3, and the defective flip-flop is specified by the following method.

  That is, when the sixth-stage flip-flop FF6 is defective as shown in FIG. 5B, for example, the output bit string is “X1010111010” from bottom to top as shown in FIG. 6B. Become.

Output bit string: X1010 1 1010
Expected value bit string: 10101 0 1010
It is. “0101” (in reverse order) for 4 bits from the back (top) matches each other and does not match at the 5th bit. The mismatched fifth bit is the sixth bit from the back, which corresponds to a defective flip-flop. In this way, a failure position (position of a defective flip-flop) in the scan chain SC3 can be specified.

  In summary, the serial connection state of a plurality of flip-flops constituting the scan chain is set to NQ output repetitive connection, all flip-flops are initially set to “1” by presetting, and each output is all set to “0”. Therefore, if the scan shift is performed, it is possible to output in a state where the positive logic and the negative logic (or the negative logic and the positive logic) alternate in time series from the scan-out. As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, it is possible to improve the accuracy of specifying the fault location in the scan chain simply by configuring the flip-flop in the NQ output repetition type scan chain as a flip-flop with a preset terminal without a reset terminal and enabling all presets during testing. it can.

  If data passes through for two clocks, there is a possibility of missing a defective flip-flop. On the other hand, an embodiment for increasing detection accuracy will be described below.

(Embodiment 4)
In the fourth embodiment of the present invention, a serial connection state of a plurality of flip-flops in a scan chain is made to be alternately repeated connection of Q output and NQ output, and reset is possible. A fault location specifying method in the scan chain according to the fourth embodiment of the present invention will be described with reference to FIGS.

  FIG. 7A shows a circuit configuration of the scan chain SC4 in the case of the fourth embodiment, and FIG. 7B shows a defective example thereof. The flip-flops FF1 to FF10 of the scan chain SC4 take in data from the previous data input terminal D by applying a clock, and alternately output the fetched data to the Q output terminal and the NQ output terminal. Are configured to be sent to the network. The plurality of flip-flops FF1 to FF10 in the scan chain SC4 repeat the alternate connection of the Q output and the NQ output. A system reset and a soft reset are input to the reset terminals R of the flip-flops FF1 to FF10 via the OR gate 5, and each of the flip-flops FF1 to FF10 is “0” not only by the system reset but also by the soft reset. "Can be set. Other configurations are the same as those in FIG. 1 in the first embodiment, and thus the description thereof is omitted.

  In the present embodiment, all of the plurality of flip-flops FF1 to FF10 in the scan chain SC4 can be reset, the Q output terminal of the first flip-flop FF1 is connected to the data input terminal of the next flip-flop FF2, and the next stage The NQ output terminal of the flip-flop FF2 is connected to the data input terminal of the third flip-flop FF3, and the Q output terminal of the third flip-flop FF3 is connected to the data input terminal of the fourth flip-flop FF4. For example, a scan chain SC4 configured by alternately connecting flip-flops of Q output and NQ output as “Q output → NQ output → Q output → NQ output →. Then, the step of setting all the flip-flops FF1 to FF10 to “0” by reset, and then comparing the bit string output from the scan-out by the scan shift with the expected value bit string, thereby determining the fault position on the scan chain SC4. Identifying step. Since the serial connection state of the flip-flops FF1 to FF10 is an alternately repeated connection of Q output and NQ output, if all the flip-flops FF1 to FF10 are initialized to “0” by resetting, the respective outputs are alternately set to “0”. "," 1 "," 0 "," 1 ", etc. are initialized. This is shown in the soft reset stage in FIGS. 8 (a) and 8 (b).

  In the present embodiment, confirmation of the scan shift operation of the scan chain SC4 is performed according to the following procedure.

First, a soft reset (or system reset) is applied to set “0” as an initial value in all stages of the flip-flops FF1 to FF10. That is, “0” and “1” are alternately set as initial values of outputs to the flip-flops FF1 to FF10. Next, the scan chain SC4 is scan-shifted. FIG. 8A shows a bit string shift diagram when nine clocks are applied. Individual bit data transition as indicated by diagonal arrows. Each time the bit data is shifted to the flip-flop of the next stage, the same bit is continued twice and then inverted. That is, along the arrow,
“1” → “1” → “0” → “0” → “1” → “1”…
The transition is as follows. Or
“0” → “1” → “1” → “0” → “0”…
The transition is as follows. When starting with "1", repeat "1" immediately after. When starting with “0”, it immediately changes to “1”. The output bit string (bit pattern) from the scan-out is compared with the expected scan-out expected value bit string “1100110011” (from the bottom) in FIG. 8A. From the scan-out, the output is in a state of alternating positive logic and negative logic in units of 2 bits in time series.

  When an output bit string different from the expected value bit string is observed, there is a defective flip-flop in the scan chain SC4, and the defective flip-flop is specified by the following method.

  As shown in FIG. 7B, for example, consider a case where the sixth-stage flip-flop FF6 is defective.

First, when there is no defective flip-flop, in FIG. 8A, starting from the output of the flip-flop FF5 and tracing downward,
“0” → “1” → “1” → “0” → “0” → “1”
And transition in principle. On the other hand, when the sixth-stage flip-flop FF6 is defective, in FIG. 8B, similarly, starting from the output of the flip-flop FF5 and tracing downward,
“0” → “1” → “0” → “1” → “1” → “0”
It is different. Further, when there is no defective flip-flop, in FIG. 8 (a), starting from the output of the flip-flop FF3 and going down diagonally,
“0” → “1” → “1” → “0” → “0” → “1” → “1” → “0”
And transition in principle. On the other hand, when the flip-flop FF6 in the sixth stage is defective, in FIG. 8 (b), starting from the output of the flip-flop FF3 and tracing down diagonally,
“0” → “1” → “1” → “0” → “1” → “0” → “0” → “1”
It is different.

  Next, regarding the output bit string, when the flip-flop FF6 is defective, the output bit string is “X1100010011” from the bottom to the top as shown in FIG. 8B.

Output bit string: X1 10 01 00 11
Expected value bit string: 11 00 11 00 11
It is. In the case of this embodiment, since it is an alternate output of “Q output → NQ output → Q output → NQ output →...”, It is considered in units of 2 bits. Two sets of 4 bits of 2 bits from the back (upper) match with "1100" (in reverse order), and do not match with the 5th and 6th bits. The mismatched fifth and sixth bits are the sixth and fifth bits from the front (bottom), and this corresponds to a defective flip-flop. In this way, the failure position (position of the defective flip-flop) in the scan chain SC4 can be specified. There are two possibilities for the defective flip-flop, but if the number is limited to two, the failure location can be easily specified by layout verification.

  In summary, the serial connection state of the multiple flip-flops that make up the scan chain is set to alternate repeat connection of Q output and NQ output, and all flip-flops are initialized to “0” by reset, and each output is set to Since the initial setting is alternately set to “0” and “1”, if scan shift is performed, positive logic / negative logic (or negative logic / positive logic) in 2-bit units in time series from scan-out It is possible to output in a state of alternating. As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, the flip-flop in the Q output / NQ output alternating scan chain is composed of a flip-flop with a reset terminal without a preset terminal. It is possible to ensure the accuracy of specifying the fault location in the chain.

  In the above, instead of “Q output → NQ output → Q output → NQ output →...”, A flip-flop of QN output and Q output as “QN output → Q output → QN output → Q output →. The same step process may be performed using the scan chain in which the groups are alternately connected as the inspection target, and the same effect is exhibited.

(Embodiment 5)
The fifth embodiment of the present invention enables presetting after the serial connection state of a plurality of flip-flops in the scan chain is set to alternately and repeatedly connect Q output and NQ output. A fault location specifying method in a scan chain according to the fifth embodiment of the present invention will be described with reference to FIGS.

  FIG. 9A shows a circuit configuration of the scan chain SC5 in the case of the fifth embodiment, and FIG. 9B shows a defective example thereof. Each flip-flop FF1 to FF10 of the scan chain SC5 has a preset terminal S, which can be set to “1” by presetting and the initial value of each output can be alternately set to “1” and “0”. . Since other configurations are the same as those in FIG. 7 in the case of the fourth embodiment, description thereof is omitted.

  In this embodiment, all the plurality of flip-flops FF1 to FF10 in the scan chain SC5 can be preset, the Q output terminal of the first flip-flop FF1 is connected to the data input terminal of the next flip-flop FF2, and the next stage The NQ output terminal of the flip-flop FF2 is connected to the data input terminal of the third flip-flop FF3, and the Q output terminal of the third flip-flop FF3 is connected to the data input terminal of the fourth flip-flop FF4. For example, a scan chain formed by alternately connecting flip-flops of Q output and NQ output such as “Q output → NQ output → Q output → NQ output →. Then, the step of setting all the flip-flops FF1 to FF10 to “1” by the preset, and then comparing the bit string output from the scan-out by the scan shift with the expected value bit string, thereby determining the failure position on the scan chain SC5. Identifying step. Since the serial connection state of the flip-flops FF1 to FF10 is an alternately repeated connection of Q output and NQ output, if all the flip-flops FF1 to FF10 are initially set to “1” by presetting, each output is alternately “1”. “,” “0”, “1”, “0”... This is shown in the preset stage in FIGS. 10 (a) and 10 (b).

  In the present embodiment, confirmation of the scan shift operation of the scan chain SC5 is performed according to the following procedure.

First, a preset is applied to set “1” as the initial value in all stages of the flip-flops FF1 to FF10. That is, “1” and “0” are alternately set in the flip-flops FF1 to FF10 as initial values of their outputs. Next, the scan chain SC5 is scan-shifted. FIG. 10A shows a bit string shift diagram when nine clocks are applied. Individual bit data transition as indicated by diagonal arrows. Each time the bit data is shifted to the flip-flop of the next stage, the same bit is continued twice and then inverted. That is, along the arrow,
“0” → “0” → “1” → “1” → “0” → “0”…
The transition is as follows. Or
“1” → “0” → “0” → “1” → “1”…
The transition is as follows. When starting with "0", repeat "0" immediately after. When starting with “1”, it immediately changes to “0”. The output bit string (bit pattern) from the scan-out is compared with the expected scan-out bit string “0011001100” (from the bottom) in the normal state of FIG. 10A. From the scan-out, the output is in a state of alternating negative logic and positive logic in units of 2 bits in time series.

  When an output bit string different from the expected value bit string is observed, there is a defective flip-flop in the scan chain SC5, and the defective flip-flop is specified by the following method.

  As shown in FIG. 9B, for example, consider a case where the sixth-stage flip-flop FF6 is defective.

First, when there is no defective flip-flop, in FIG. 10 (a), starting from the output of the flip-flop FF5 and tracing downward,
“1” → “0” → “0” → “1” → “1” → “0”
And transition in principle. On the other hand, when the flip-flop FF6 in the sixth stage is defective, in FIG. 10B, starting from the output of the flip-flop FF5 and tracing down diagonally,
“1” → “0” → “1” → “0” → “1” → “1”
It is different. If there is no defective flip-flop, starting from the output of the flip-flop FF3 in FIG.
“1” → “0” → “0” → “1” → “1” → “0” → “0” → “1”
And transition in principle. On the other hand, in the case where the sixth stage flip-flop FF6 is defective, in FIG. 10B, similarly, starting from the output of the flip-flop FF3 and going diagonally downward,
“1” → “0” → “0” → “1” → “1” → “1” → “1” → “0”
It is different.

  Next, regarding the output bit string, when the flip-flop FF6 has a defect, the output bit string becomes “X001101100” from the bottom to the top as shown in FIG. 10B.

Output bit string: X0 01 10 11 00
Expected value bit string: 00 11 00 11 00
It is. In the case of this embodiment, since it is an alternate output of “Q output → NQ output → Q output → NQ output →...”, It is considered in units of 2 bits. Two sets of 4 bits of 2 bits from the back (upper) match with “0011” (described in reverse order), and the 5th and 6th bits do not match. The mismatched fifth and sixth bits are the sixth and fifth bits from the front (bottom), and this corresponds to a defective flip-flop. In this way, the failure position (position of the defective flip-flop) in the scan chain SC5 can be specified. There are two possibilities for the defective flip-flop, but if the number is limited to two, the fault location can be easily identified by layout verification.

  In summary, the serial connection status of the multiple flip-flops that make up the scan chain is set to alternate repeat connection of Q output and NQ output, and all flip-flops are initially set to “1” by presetting, and each output is set to Since the initial setting is alternately set to “1” and “0”, if scan shift is performed, negative logic / positive logic (or positive logic / negative logic) in 2-bit units in time series from scan-out It is possible to output in a state of alternating. As a result, it becomes easier to specify the position of bit inversion from the expected value bit string of the output bit string due to the presence of the defective flip-flop. In other words, the flip-flop in the Q output / NQ output alternating scan chain is composed of a flip-flop with a preset terminal without a reset terminal, and it is possible to scan all in two bits by making all preset possible during testing. It is possible to ensure the accuracy of specifying the fault location in the chain.

  In the above, instead of “Q output → NQ output → Q output → NQ output →...”, A flip-flop of QN output and Q output as “QN output → Q output → QN output → Q output →. The same step process may be performed using the scan chain in which the groups are alternately connected as the inspection target, and the same effect is exhibited.

  The fault location specifying method in a scan chain of the present invention is useful as a technique for specifying a defective flip-flop in a flip-flop group on a scan chain with high accuracy in a semiconductor integrated circuit having a scan chain.

FIG. 1 is a circuit configuration diagram of a scan chain and its failure example in Embodiment 1 of the present invention. Bit string shift diagram for explaining the operation of the fault location specifying method in the scan chain in Embodiment 1 of the present invention Circuit configuration diagram of scan chain and its failure example diagram in Embodiment 2 of the present invention Bit string shift diagram for explaining the operation of the fault location specifying method in the scan chain in Embodiment 2 of the present invention Circuit configuration diagram of scan chain and its failure example diagram in Embodiment 3 of the present invention Bit string shift diagram for explaining the operation of the fault location specifying method in the scan chain in the third embodiment of the present invention Circuit configuration diagram of scan chain and its failure example diagram in Embodiment 4 of the present invention Bit string shift diagram for explaining the operation of the fault location specifying method in the scan chain in Embodiment 4 of the present invention FIG. 5 is a circuit configuration diagram of a scan chain according to Embodiment 5 of the present invention and its failure example diagram. Bit string shift diagram for explaining the operation of the fault location specifying method in the scan chain in the fifth embodiment of the present invention General illustration of the scan chain Circuit diagram of scan chain in conventional technology and its failure example diagram Bit string shift diagram for explaining the operation of the fault location method in the scan chain in the prior art

Explanation of symbols

FF1 to FF10 Flip-flops constituting scan chain SC1 to SC5 Scan chain

Claims (6)

A plurality of flip-flops in the scan chain can output NQ, the NQ output terminal of the first stage flip-flop is connected to the data input terminal of the next stage flip-flop, and the NQ output terminal of the next stage flip-flop is connected to the third stage flip-flop. For example, a scan chain configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →...” Is connected to the data input terminal of the flip-flop.
Setting each flop flop to a predetermined initial value by a system reset; and
And a step of specifying a fault position on the scan chain by comparing a bit string output from scan-out by a scan shift with an expected value bit string. All the flip-flops in the scan chain have an NQ output configuration and can be reset, the NQ output terminal of the first flip-flop is connected to the data input terminal of the next flip-flop, and the NQ output terminal of the next flip-flop Is connected to the data input terminal of the third stage flip-flop, and a scan chain configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →.
Setting all of the flip-flops to “0” by resetting;
And a step of specifying a fault position on the scan chain by comparing a bit string output from scan-out by a scan shift with an expected value bit string. A plurality of flip-flops in the scan chain can be preset with an NQ output configuration, the NQ output terminal of the first stage flip-flop is connected to the data input terminal of the next stage flip-flop, and the NQ output terminal of the next stage flip-flop Is connected to the data input terminal of the third stage flip-flop, and a scan chain configured by repeatedly connecting NQ output flip-flops such as “NQ output → NQ output →.
Setting all flip-flops to “1” by presetting;
And a step of specifying a fault position on the scan chain by comparing a bit string output from scan-out by a scan shift with an expected value bit string. All the flip-flops in the scan chain can be reset, the Q output terminal of the first flip-flop is connected to the data input terminal of the next flip-flop, and the NQ output terminal of the next flip-flop is connected to the third stage flip-flop. Connect to the data input terminal of the flip-flop, connect the Q output terminal of the third-stage flip-flop to the data input terminal of the fourth-stage flip-flop, and so on. → ... ”scan chain configured by alternately connecting Q output and NQ output flip-flops as inspection targets,
Setting all of the flip-flops to “0” by resetting;
And a step of specifying a fault position on the scan chain by comparing a bit string output from scan-out by a scan shift with an expected value bit string. All the flip-flops in the scan chain can be preset, the Q output terminal of the first flip-flop is connected to the data input terminal of the next flip-flop, and the NQ output terminal of the next flip-flop is connected to the third stage flip-flop. Connect to the data input terminal of the flip-flop, connect the Q output terminal of the third-stage flip-flop to the data input terminal of the fourth-stage flip-flop, and so on, such as “Q output → NQ output → Q output → NQ output” → ... ”scan chain configured by alternately connecting Q output and NQ output flip-flops as inspection targets,
Setting all of the flip-flops to “1” by presetting;
And a step of specifying a fault position on the scan chain by comparing a bit string output from scan-out by a scan shift with an expected value bit string.   Instead of the order of “Q output → NQ output → Q output → NQ output →...”, Flip-flops of QN output and Q output are alternately arranged as “QN output → Q output → QN output → Q output →. 6. The fault location specifying method in a scan chain according to claim 4 or 5, wherein the connected scan chain is an inspection target.

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