JP2007036366A - Serial communication circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small-sized serial communication circuit with a simple configuration capable of attaining a stable operation. <P>SOLUTION: The serial communication circuit comprises: a clock/data recovery circuit for extracting received data and a received clock from received serial data; a PLL circuit that receives the received clock extracted by the clock/data recovery circuit and generates an internal clock synchronously with the phase of the received clock; an internal data processing circuit that is operated by the internal clock generated by the PLL circuit, receives the received data extracted by the clock/data recovery circuit and processes the received data; and a transmission circuit that is operated by the internal clock generated by the PLL changeover device and transmits data from the internal data processing circuit as serial data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an improvement in a serial communication circuit that performs clock synchronous communication using, for example, an 8B / 10B encoding method.

  When circuits communicate with each other, it is necessary to consider clock synchronization. That is, on the data receiving side, if there is a speed difference or phase difference between the received data and the read clock inside the circuit, duplication or omission of bits occurs. In order to prevent this, a clock transfer circuit is used. This clock transfer circuit temporarily stores received data having an appropriate number of bits, and outputs the received data in synchronization with the read clock, that is, the receiving clock.

  Specific examples of a serial communication circuit using such a clock transfer circuit are shown in FIGS. In FIG. 9, the clock distribution board 301 distributes the reference clock Cs to the communication boards 311 to 313 that perform communication. On the other hand, the communication boards 311 to 313 perform signal processing and transmission / reception in synchronization with the reference clock Cs.

  As shown in FIG. 10, each of the communication boards 311 to 313 includes a clock / data recovery circuit 321, a serial / parallel conversion circuit 322, an 8B / 10B decoder 323, a clock transfer circuit 324, an internal Data processing circuits 325 and 326, an 8B / 10B encoder 327, a parallel / serial conversion circuit 328, and a PLL circuit 329 are provided.

  The clock / data recovery circuit 321 recovers the reception data and the reception clock Cr from the received serial data S. The serial data S is converted into parallel data by the serial / parallel conversion circuit 322, and the redundant portion is removed by the 8B / 10B decoder 323. Since the communication data output from the 8B / 10B decoder 323 is synchronized with the reception clock Cr, it is output to the internal data processing circuit 325 as communication data synchronized with the internal clock from the PLL circuit 329.

  The PLL circuit 329 multiplies the reference clock Cs from the clock distribution board 301 to generate an internal clock, a clock / data recovery circuit 321, internal data processing circuits 325 and 326, an 8B / 10B encoder 327, This is supplied to the serial / parallel conversion circuit 328.

  In the conventional serial communication circuit as described above, a clock transfer circuit is required to match the phase of the received data synchronized with the reception clock to the phase of the internal clock. That is, the clock change circuit (specifically, the FIFO buffer) absorbs the phase difference between the reception clock and the internal clock and the fluctuation of the clock. For this reason, the circuit on the read side from the FIFO buffer needs to operate while monitoring overflow and depletion of the FIFO buffer, and the circuit becomes large and complicated.

  Further, when viewed from the whole apparatus, a clock used in the communication board is supplied from the clock distribution board to each board, and this clock distribution board and the clock wiring are also obstacles to miniaturization of the circuit.

  Further, in such a configuration, if the clock distribution board stops operating, all the boards cannot be synchronized and all communications become abnormal.

  Accordingly, the present invention has been made in consideration of the above circumstances, and an object thereof is to provide a serial communication circuit having a small and simple configuration capable of stable operation.

  In order to achieve the above object, according to one embodiment of the present invention, a clock / data recovery circuit for extracting received data and a reception clock from received serial data, and a reception clock extracted by the clock / data recovery circuit are provided. The PLL circuit that generates the internal clock synchronized with the phase of the reception clock and the internal clock generated by the PLL circuit and the reception data extracted by the clock / data recovery circuit are input. There is provided a serial communication circuit comprising an internal data processing circuit for processing the received data and a transmission circuit that operates with the internal clock generated by the PLL circuit and transmits data from the internal data processing circuit as serial data. The

  The clock / data recovery circuit preferably uses an internal clock generated by the PLL circuit when the received data is extracted.

  Further, it is preferable that the reception data extracted by the clock / data recovery circuit is encoded by the 8B / 10B encoding method.

  The received data taken out by the clock / data recovery circuit is preferably converted into parallel data by a serial / parallel conversion circuit, decoded by an 8B / 10B decoder, and then input to the internal data processing circuit. is there.

  The transmission circuit preferably includes an 8B / 10B encoder that encodes parallel data from an internal data processing circuit, and a parallel / serial conversion circuit that converts the encoded parallel data into serial data.

  According to the above configuration, it is possible to realize a serial communication circuit that can operate without receiving an external clock distribution and that does not require a clock transfer circuit. Therefore, according to the present invention, a serial communication circuit having a small and simple configuration capable of stable operation is provided.

  Hereinafter, serial communication circuits according to embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a system formed by connecting a plurality of communication boards each having a serial communication circuit according to an embodiment of the present invention. Here, the communication boards 101, 102 and 103 communicate with the serial data S, but the clock distribution board and the clock wiring as in the conventional example are not provided.

  FIG. 2 is a block diagram of a serial communication circuit according to an embodiment of the present invention. The serial communication circuit includes a clock / data recovery circuit 120, a serial / parallel conversion circuit 130, an 8B / 10B decoder 140, internal data processing circuits 150 and 160, an 8B / 10B encoder 170, and a serial / parallel conversion circuit. 180 and a PLL circuit 190 are provided.

  The clock / data recovery circuit 120 recovers the received data and the received clock Sr from the received serial data S. The serial data S is converted into parallel data by the serial / parallel conversion circuit 130, the redundant portion is removed by the 8B / 10B decoder 140, and the data is output as net communication data.

  On the other hand, the PLL circuit 190 receives the received serial data S and generates an internal clock Ci synchronized with the frequency and phase. The internal clock Ci includes a clock / data recovery circuit 120, a serial / parallel conversion circuit 130, an 8B / 10B decoder 140, internal data processing circuits 150 and 160, an 8B / 10B encoder 170, and a serial / parallel conversion circuit. 180, each circuit performs signal processing in synchronization with the internal clock Ci.

  Therefore, since the communication data output from the 8B / 10B decoder 140 is synchronized with the internal clock Ci, it is output to the internal data processing circuit 150 as the communication data Sp without changing the clock.

  The internal data processing circuit 160 generates communication data to be transmitted to other communication boards as parallel data. The parallel data is encoded by the 8B / 10B encoder 170, supplied to the parallel / serial conversion circuit 180, and transmitted as serial data S synchronized with the internal clock Ci. Therefore, the 8B / 10B encoder 170 and the parallel / serial conversion circuit 180 function as a transmission circuit.

  Next, circuit configurations of the clock / data recovery circuit 120 and the PLL circuit 190 will be described with reference to FIG.

  The clock / data recovery circuit 120 includes a phase comparator 121, a latch circuit 122, a loop filter 123, and a voltage controlled oscillator (VCO) 124. The PLL circuit 190 includes frequency dividers 191, 192, a phase comparator 193, a loop filter 194, and a voltage controlled oscillator 195.

  The phase comparator 121 of the clock / data recovery circuit 120 has a temporal difference between the recovered clock Cr and the state change of the received serial data S (in this case, the rise of the signal), that is, the recovered clock Cr and the received serial data S. And a phase difference signal Vc is generated. The 8B / 10B encoding method data has a feature that the phase of the received serial data S can be easily detected because the same bit information (high level or low level) does not continue five or more times.

  The phase difference signal Vc output from the phase comparator 121 is output to the voltage controlled oscillator 124 after the high frequency component is removed by the loop filter 123. The voltage controlled oscillator 124 adjusts the oscillation frequency so as to eliminate the phase difference between the reproduction clock Cr and the received serial data S according to the phase difference signal Vc. FIG. 4 shows a specific example of the reproduction clock Cr and the received serial data S. The reproduction clock Cr is controlled so that the rising timing coincides with the rising timing of the received serial data S.

  The reproduced clock Cr is divided by the frequency divider 191 of the PLL circuit 190, and the phase is compared by the phase comparator 193 with the internal clock Ci / n divided by the frequency divider 192. FIG. 5 shows a specific example of the recovered clock Cr / m divided by the frequency divider 191, and FIG. 6 shows a specific example of the internal clock Ci / n divided by the frequency divider 192. The reproduction clock Cr / m is divided by ¼ and has a frequency that is ¼ of the reproduction clock Cr. Similarly, the internal clock Ci / n is divided by ¼ and has a frequency that is ¼ of the reproduction clock Cr.

  The phase comparator 193 outputs a phase difference signal Vc between the reproduction clock Cr / m and the internal clock Ci / n. FIG. 7 shows a specific example of the reproduction clock Cr / m, the internal clock Ci / n, and the phase difference signal Vc (phase difference control voltage) generated from both. This phase difference signal Vc rises from the reference level at the rising edge of the reproduction clock Cr / m and to the reference level at the rise of the internal clock Ci / n when the reproduction clock Cr / m precedes the internal clock Ci / n. Fall down. Conversely, when the internal clock Ci / n precedes the reproduction clock Cr / m, the internal clock Ci / n falls from the reference level at the rise of the internal clock Ci / n, and rises to the reference level at the rise of the reproduction clock Cr / m.

  The phase difference signal Vc is output to the voltage controlled oscillator 195 after the high frequency component is removed by the loop filter 194. As is well known, the voltage controlled oscillator 195 adjusts the oscillation frequency according to the phase difference signal Vc so as to eliminate the phase difference between the reproduction clock Cr / m and the internal clock Ci / n.

  As described above, the clock inside the circuit is always synchronized with the clock of the received serial data S. Therefore, in FIG. 8, if the communication board 3 fails, it is possible to detect that an abnormality has occurred in the communication board 3 because the reception clock is not reproduced on the communication board 4 and the PLL circuit is unlocked. Further, downstream communication is maintained normally with the reference clock of the communication board 4.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a figure showing a system formed by connecting a plurality of communication boards provided with a serial communication circuit according to an embodiment of the present invention. It is a block diagram of the serial communication circuit concerning the embodiment of the present invention used in the system of FIG. FIG. 3 is a block diagram showing circuit configurations of a clock / data recovery circuit and a PLL circuit used in the serial communication circuit of FIG. 2. FIG. 3 is a diagram showing a specific example of a reproduction clock and received serial data in a clock / data recovery circuit and a PLL circuit used in the communication circuit of FIG. 2. It is a figure which shows the specific example of the frequency-divided reproduction | regeneration clock input into the PLL circuit used with the communication circuit of FIG. It is a figure which shows the specific example of the frequency-divided internal clock output from the PLL circuit used with the communication circuit of FIG. It is a figure which shows the specific example of the phase difference signal (phase difference control voltage) produced | generated from both the reproduction | regeneration clock and internal clock which are shown by FIG. 5 and FIG. It is a figure explaining the advantage of the communication circuit by embodiment of this invention. FIG. 10 is a block diagram showing a conventional system in which a plurality of serial communication circuits are connected. FIG. 10 is a block diagram illustrating an example of the serial communication circuit of FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 120 ... Data recovery circuit, 121 ... Phase comparator, 123 ... Loop filter, 124 ... Voltage controlled oscillator, 190 ... PLL circuit, 191 ... Frequency divider, 191, 192 .. Frequency divider, 193 ... Phase comparator, 194 ... Loop filter, 195 ... Voltage controlled oscillator, 301 ... Clock distribution board, 311 to 313 ... Communication board, 321 ... Data recovery circuit, 322 ... Parallel conversion circuit, 323 ... Decoder, 324 ... Clock transfer circuit, 325 ... Internal data processing circuit, 325, 326 ... Internal data processing circuit, 327 ... Encoder, 328 ... serial conversion circuit, 328 ... parallel conversion circuit, 329 ... PLL circuit.

Claims (5)

A clock / data recovery circuit that extracts received data and a received clock from received serial data;
A PLL circuit that inputs a reception clock extracted by the clock / data recovery circuit and generates an internal clock synchronized with the phase of the reception clock;
An internal data processing circuit that operates with the internal clock generated by the PLL circuit, inputs the received data extracted by the clock / data recovery circuit, and processes the received data;
A serial communication circuit that operates with an internal clock generated by the PLL circuit and includes a transmission circuit that transmits data from the internal data processing circuit as serial data.   The serial communication circuit according to claim 1, wherein the clock / data recovery circuit uses an internal clock generated by the PLL circuit when the received data is extracted.   The serial communication circuit according to claim 1, wherein the reception data extracted by the clock / data recovery circuit is encoded by an 8B / 10B encoding method.   The reception data extracted by the clock / data recovery circuit is converted into parallel data by a serial / parallel conversion circuit, decoded by an 8B / 10B decoder, and then input to the internal data processing circuit. Item 4. The serial communication circuit according to Item 3.   2. The transmission circuit includes an 8B / 10B encoder that encodes parallel data from an internal data processing circuit, and a parallel / serial conversion circuit that converts the encoded parallel data into serial data. The serial communication circuit described in 1.

Images