JP2007035905A - Nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor element that performs normally-off operation without any variations in a threshold voltage. <P>SOLUTION: The nitride semiconductor element comprises a first semiconductor layer made of a nitride semiconductor; a second semiconductor layer that is provided on the first semiconductor layer and is made of a nondoped or n-type nitride semiconductor whose band gap is larger than that of the first semiconductor layer; a control electrode that is provided at the first region on the second semiconductor layer directly or via an insulating film; a third semiconductor layer made of a nondoped or n-type nitride semiconductor provided at second and third regions adjacent to both the ends of the first region on the second semiconductor layer; and a fourth semiconductor layer that is provided on the third semiconductor layer and is made of a nondoped or n-type nitride semiconductor whose band gap is larger than that of the third semiconductor layer. The film thickness of the second semiconductor layer is uniform in the first, second, and third regions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a structure of a nitride semiconductor device, and more particularly to a nitride semiconductor device having a structure of a heterojunction field effect transistor using an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) heterostructure or the like.

Circuits such as switching power supplies and inverters use power semiconductor elements such as switching elements and diodes, and the power semiconductor elements are required to have characteristics such as high breakdown voltage and low on-resistance (R _ON ). There is a trade-off relationship determined by the element material between the breakdown voltage and the on-resistance (R _ON ). Advances in technology development have made it possible to achieve low on-resistance (R _ON ) near the limit of silicon (hereinafter referred to as Si), which is a main element material for power semiconductors. In order to further reduce the on-resistance (R _ON ), it is necessary to change the element material. For example, by using a nitride semiconductor such as gallium nitride (hereinafter referred to as GaN) or aluminum gallium nitride (hereinafter referred to as AlGaN) or a wide band gap semiconductor such as silicon carbide (hereinafter referred to as SiC) as a switching element material, a trade determined by the material. It is possible to improve the OFF relationship and dramatically reduce the _ON resistance (R _ON ).

On the other hand, a device using a nitride semiconductor such as GaN or AlGaN includes a hetero field effect transistor (hereinafter referred to as HFET) using an AlGaN / GaN heterostructure. This HFET realizes a low on-resistance due to the high mobility of the heterointerface channel and the high electron concentration generated by the piezo polarization due to the strain at the heterointerface. For this reason, it has been attracting attention as a high-power high-frequency device.

  For example, Patent Document 1 describes an HFET having a recessed gate structure. The HFET described in FIG. 1 of Patent Document 1 has a structure in which an AlGaN barrier layer is formed on a GaN channel layer, and an n-type GaN layer and an AlGaN layer are formed on the AlGaN barrier layer. A source electrode and a drain electrode are formed in contact with the uppermost AlGaN layer. Further, a part of the AlGaN layer, the n-type GaN layer, and the AlGaN barrier layer is removed, and a gate electrode is formed in contact with the AlGaN barrier layer in the recess formed by the removal.

However, in order to apply this semiconductor element structure as it is to a power semiconductor, there are the following problems.
A normal power semiconductor element requires a normally-off operation in which the gate threshold voltage (V _th ) is positive. However, since the electron mobility at the heterointerface is high in the GaN-HFET, the threshold voltage (V _th ) becomes negative and a normally-on operation occurs. Although it is possible to achieve normally-off operation by lowering the electron concentration at the heterointerface, this increases the offset resistance between the gate and source and between the gate and drain and increases the on-resistance (R _ON ). Resulting in. For this reason, in order to make the gate threshold voltage (V _th ) positive without increasing the on-resistance (R _ON ), it is necessary to selectively reduce the electron concentration directly under the gate electrode.
As a specific method, the recess gate structure described above is particularly useful. As is clear from FIG. 1 of Patent Document 1, the electron concentration in this region can be selectively lowered by thinning only the AlGaN barrier layer directly under the gate electrode by recess gate etching.

However, the thickness of the AlGaN barrier layer directly under the gate electrode necessary for normally-off operation is as thin as several nanometers. For this reason, when this film thickness is controlled by the etching time, the gate threshold voltage (V _th ) greatly depends on the etching variation. For example, in order to etch and remove a part of the AlGaN barrier layer of about 30 nanometers to about 5 to 8 nanometers, it is necessary to perform highly accurate etching control, which is a major obstacle to commercialization. .
JP 2004-22774 A

  An object of the present invention is to provide a nitride semiconductor device having no variation in threshold voltage.

According to one aspect of the invention,
A first semiconductor layer made of a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and made of a non-doped or n-type nitride semiconductor having a band gap larger than that of the first semiconductor layer;
A control electrode provided directly or via an insulating film in the first region on the second semiconductor layer;
A third semiconductor layer made of a non-doped or n-type nitride semiconductor provided in each of the second and third regions adjacent to both ends of the first region on the second semiconductor layer;
A fourth semiconductor layer provided on each of the third semiconductor layers and made of a non-doped or n-type nitride semiconductor having a band gap larger than that of the third semiconductor layer;
With
The nitride semiconductor device is characterized in that the film thickness of the second semiconductor layer is uniform in the first region and the second and third regions.

  According to the present invention, since the AlGaN barrier layer directly under the gate electrode is not subjected to recess etching, it is possible to provide a normally-off nitride semiconductor device with no variation in threshold voltage.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing the structure of a GaN-HFET according to the first embodiment of the present invention.
The HFET shown in FIG. 1 has a structure in which a barrier layer 2 made of a non-doped or n-type nitride semiconductor having a substantially uniform thickness is formed on a channel layer 1 made of a non-doped nitride semiconductor. The band gap of the nitride semiconductor constituting the barrier layer 2 is larger than the band gap of the nitride semiconductor constituting the channel layer 1. Specifically, for example, GaN can be used as the material of the channel layer 1, and AlGaN can be used as the material of the barrier layer 2. Hereinafter, the case where these materials are used as the material of the channel layer 1 and the barrier layer 2 will be described.

  First contact layers 3 and 4 made of non-doped or n-type nitride semiconductor are selectively formed on the AlGaN barrier layer 2, and non-doped or n-type nitride is formed on the first contact layers 3 and 4, respectively. Second contact layers 5 and 6 made of a physical semiconductor are formed. The band gap of the nitride semiconductor constituting the second contact layer is larger than the band gap of the nitride semiconductor constituting the first contact layer.

As will be described later in detail with reference to FIG. 2, the first contact layers 3 and 4 are selectively panned (etched) between the underlying barrier layer 2 and the first contact layers 5 and 6 thereon. It also serves as a layer for
On the other hand, the second contact layers 5 and 6 also promote the piezoelectric polarization between the channel layer 1 and the barrier layer 2 and have a role of increasing the concentration of a two-dimensional electron gas (hereinafter referred to as 2DEG: 2 Dimensional Electoron Gas). . That is, in order to increase the 2DEG concentration, it is necessary to increase the piezo polarization at the interface on the channel layer 1. However, in order to realize the normally-off state, the thickness of the barrier layer 2 cannot be increased. On the other hand, by laminating the second contact layers 5 and 6, piezo polarization in the source / drain regions can be promoted and the 2DEG concentration can be increased.

  Specifically, for example, GaN can be used as the material of the first contact layers 3 and 4, and AlGaN can be used as the material of the second contact layers 5 and 6. Hereinafter, the case where these materials are used as materials of the first contact layers 3 and 4 and the second contact layers 5 and 6 will be described.

On the AlGaN layers 5 and 6, respectively, a source electrode 8 that is in ohmic contact with a two-dimensional electron gas (hereinafter referred to as 2 DEG: 2 Dimensional Electoron Gas) 7 generated at the interface between the AlGaN barrier layer 2 and the GaN channel layer 1. A drain electrode 9 is formed. A control electrode (hereinafter referred to as “gate electrode”) that is Schottky-bonded is formed on the AlGaN barrier layer 2.

In order for the HFET to be normally off (enhancement mode operation), the gate threshold voltage (V _th ) must be positive. For this purpose, when the gate voltage is 0 volt, the electron concentration of 2DEG generated at the interface between the AlGaN barrier layer 2 and the GaN channel layer 1 in the region Lg under the gate electrode 10 needs to be close to zero. In order to reduce the electron concentration of 2DEG, the film thickness of the AlGaN barrier layer 2 in the present embodiment is sufficiently thin.

On the other hand, in the offset regions Lgs and Lgd between the gate and the source and between the gate and the drain, sufficient 2DEG is required even when the gate voltage is 0 volts. This is because if the 2DEG concentration in this region decreases, the resistance in the offset region increases and the on-resistance (R _ON ) of the element increases. For this reason, the HFET shown in FIG. 1 generates a large amount of 2DEG at the heterointerface in the region other than the region Lg under the gate electrode. Specifically, not only the GaN layers 3 and 4 but also the AlGaN layers 5 and 6 are formed on the AlGaN barrier layer 2 in this region, and lattice strain is also generated between the AlGaN layers 5 and 6 and the GaN channel region 1. I am letting. By increasing the lattice distortion, a sufficient concentration of 2DEG can be generated at the heterointerface in the offset region.

By using such a structure, the electron concentration in the region Lg under the gate electrode 10 can be selectively lowered while maintaining the electron concentration in the offset regions Lgs and Lgd sufficiently. That is, it is possible to realize a normally-off HFET with a low on-resistance (R _ON ).

FIG. 2 is a process sectional view showing an example of a manufacturing process of the GaN-HFET according to the first embodiment of the present invention.
First, as shown in FIG. 2A, a non-doped GaN channel layer is formed on a semi-insulating substrate (not shown) by using a gas source molecular beam epitaxial growth method (GSMBE), an organic metal vapor deposition method (MOCVD), or the like. 1. AlGaN barrier layer 2, GaN layer 3 (4), and AlGaN layer 5 (6) are grown sequentially.

Next, as shown in FIG. 2B, the AlGaN layer 5 (6) on the surface is removed by etching using the mask 25 until it reaches the GaN layer 3 (4).
Thereafter, as shown in FIG. 2C, only the GaN layer 3 (4) is removed by selective etching, thereby leaving the AlGaN barrier layer 2. At this time, by using a gas in which chlorine (Cl) and oxygen (O) are mixed, an etching selectivity with AlGaN can be 10 or more, so the AlGaN barrier layer 2 is hardly etched.
Thus, according to this example, for example, by adopting a three-layer structure of the AlGaN barrier layer 2, the GaN first contact layers 3 and 4, and the AlGaN second contact layers 5 and 6, the AlGaN barrier layer 2 Thus, it is possible to perform reliable and easy patterning while accurately reducing the thickness of the film, and to increase the 2DEG concentration by promoting piezo polarization in the offset region (a region other than directly under the gate electrode).
Finally, the mask 25 is removed, source and drain electrodes are formed so as to be in ohmic contact with the AlGaN layer 5, and Schottky contact is formed with the AlGaN barrier layer 2 in the recess, thereby forming a gate electrode. The HFET represented by is obtained.

In the step of FIG. 2C, even if annealing is performed in a hydrogen atmosphere, only GaN can be selectively etched. In this case, damage due to etching can be avoided.
Furthermore, if an indium gallium nitrogen (InGaN) layer is used instead of the GaN layer 3, thermal etching at a low temperature can be performed.

Further, after the AlGaN barrier layer 2 is crystal-grown, a mask such as a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) is formed in the recess portion, and the GaN layer 3 and the AlGaN are formed in the portion where the mask is not formed. Even when the layer 5 is grown, a structure similar to that shown in FIG. 2C can be obtained.

As described above, the thickness of the AlGaN barrier layer 2 shown in FIG. 1 is determined by crystal growth, and etching is not performed. Therefore, the film thickness does not vary, and the gate threshold voltage (V _th ) varies less.

FIG. 3 is a graph showing the relationship between the gate threshold voltage (Vth) and the film thickness of the AlGaN barrier layer 2 under the gate electrode.
From the figure, it can be seen that by making the AlGaN barrier layer 2 thinner, the gate threshold voltage (Vth) shifts to a plus, and when it becomes 8.2 nanometers or less, a threshold value of 0 volts or more is obtained. For this reason, in order to realize a normally-off operation, it is desirable that the AlGaN barrier layer under the gate electrode be 8.2 micrometers or less.

FIG. 4 is a graph showing the relationship between the Al composition ratio of AlGaN and the film thickness when the gate threshold voltage (Vth) is 0V.
When the aluminum (Al) composition ratio of the AlGaN barrier layer 2 changes, the film thickness of the AlGaN layer for realizing normally-off changes. From the figure, the relationship between the thickness tA0 of the AlGaN barrier layer 2 where the threshold voltage (Vth) is 0 volt and the aluminum (Al) composition ratio Y is

tA0 = 1 / (1.15Y ² + 0.326Y + 0.01)

In order to realize normally-off, it is desirable that the thickness of the barrier layer 2 be tA0 or less.

  As is apparent from the graphs of FIGS. 3 and 4, the film thickness of the AlGaN barrier layer 2 is an extremely important element, and it is an important point whether it can be formed with high accuracy. If this film thickness control is to be performed by recess gate etching as in the shape shown in FIG. However, this is difficult to realize.

  On the other hand, in the HFET according to the embodiment of the present invention, the thickness of the AlGaN barrier layer 2 is formed by crystal growth with the region under the gate electrode and other regions uniformly thinned, It is easy to obtain a desired film thickness and there is little variation in film thickness. Therefore, it is possible to stably supply an HFET with little variation in threshold voltage.

Hereinafter, an embodiment of the present invention when used as a power element will be described.
FIG. 5 is a schematic diagram showing the structure of a GaN-HFET according to the second embodiment of the present invention. The same components as those in the HFET shown in FIG.
1 is different from the HFET shown in FIG. 1 in that the gate-drain offset region Lgd is larger than the gate-source offset region Lgs. When a drain voltage is applied, the voltage is maintained between the gate and the drain, so that the element breakdown voltage depends on the gate-drain distance, that is, the gate-drain offset region Lgd. For this reason, in order to realize a high breakdown voltage, it is desirable to increase the offset region Lgd between the gate and the drain. On the other hand, the gate-source distance that does not affect the breakdown voltage, that is, the gate-drain offset region Lgs is desirably small in order to reduce the on-resistance (R _ON ).
For example, in an element that achieves a breakdown voltage of about several hundred volts, the gate-drain distance Lgd is 5 to 10 micrometers, whereas the gate-source distance Lgs is about 1 micrometer.

Thus, the relationship between the gate-drain distance Lgd and the gate-source distance Lgs is

L _gs <L _gd

Thus, it can be applied as a high breakdown voltage power element.

FIG. 6 is a schematic diagram showing the structure of a GaN-HFET according to the third embodiment of the present invention. The same components as those in the HFET shown in FIG.
5 is different from the HFET shown in FIG. 5 in that the gate electrode 10 is formed to the outside of the recess etched. In the recess bottom of the HFET shown in FIG. 5, the 2DEG concentration in the region between the gate electrode end and the recess sidewall is low, which may increase the on-resistance (R _ON ). On the other hand, in the HFET shown in this figure, since the gate electrode can be formed in all the regions of the exposed AlGaN barrier layer 2, the offset regions Lgs and Lgd are limited to the regions filled with 2DEG. And an increase in resistance in this region can be suppressed.

FIG. 7 is a schematic diagram showing the structure of a GaN-HFET according to the fourth embodiment of the present invention. The same components as those of the HFET shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
5 is different from the HFET shown in FIG. 5 in that the source electrode 8 and the drain electrode 9 are formed on the AlGaN barrier layer 2. The source electrode 8 and the drain electrode 9 which are ohmic electrodes may be electrically connected to 2DEG formed at the interface between the AlGaN barrier layer 2 and the GaN channel layer 1. For this reason, it can form on the AlGaN barrier layer 2 instead of the uppermost AlGaN layers 5 and 6, and a lower contact resistance can be obtained. The region where the source electrode 8 and the drain electrode 9 are formed may be etched simultaneously with the region where the gate electrode 10 is formed.

FIG. 8 is a schematic diagram showing the structure of a GaN-HFET according to the fifth embodiment of the present invention. The same components as those of the HFET shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
5 is different from the HFET shown in FIG. 5 in that AlGaN / GaN superlattice layers 11 and 12 are provided on the AlGaN barrier layer 2 in place of the GaN layers 3 and 4 and the AlGaN layers 5 and 6. is there. The superlattice films 11 and 12 that are multilayer films having a periodic structure formed by alternately laminating thin films of two kinds of materials having different band gaps not only facilitate the generation of 2DEG but also a source electrode on the superlattice. By making ohmic contact between 8 and the drain electrode 9, the contact resistance can be reduced.

FIG. 9 is a schematic diagram showing the structure of a GaN-HFET according to the sixth embodiment of the present invention. The same components as those of the HFET shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
5 is different from the HFET shown in FIG. 5 in that GaN cap layers 13 and 14 are formed on the AlGaN layers 5 and 6. In the HFET shown in FIG. 5, the surface of the AlGaN layers 5 and 6 is susceptible to process damage such as formation of a natural oxide film by a process such as recess etching. On the other hand, the HFET of this figure can suppress process damage by forming a GaN cap layer not containing aluminum Al on the surface.

FIG. 10 is a schematic diagram showing the structure of a GaN-HFET according to the seventh embodiment of the present invention. The same components as those of the HFET shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
5 is different from the HFET shown in FIG. 5 in that a gate insulating film 15 is formed between the gate electrode 10 and the AlGaN barrier layer 2. Thus, a MIS (Metal Insulator Semiconductor) gate structure is obtained. By using the MIS gate, the gate leakage current is reduced and the load on the gate driving circuit is reduced.
Of course, it is also possible to apply the MIS gate structure to the HFET according to the embodiment described above.

FIG. 11 is a schematic diagram showing the structure of a GaN-HFET according to the eighth embodiment of the present invention. The same components as those of the HFET shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
5 differs from the HFET shown in FIG. 5 in that a p-type GaN channel layer 16 is used instead of the non-doped GaN channel layer 1 and that the thickness of the AlGaN barrier layer 2 is increased. is there. By making the channel layer p-type, the concentration of 2DEG generated by piezoelectric polarization is reduced. Accordingly, the AlGaN barrier layer 2 can be made thicker. In this way, variations in the thickness of the AlGaN barrier layer 2 due to crystal growth can be reduced, and variations in threshold voltage and on-resistance (R _ON ) can be suppressed. If the 2DEG concentration is reduced too much, the on-resistance (R _ON ) increases. Therefore, the concentration of 2DEG is adjusted by setting the AlGaN barrier layer 2 and the AlGaN layers 5 and 6 to be n-type, and these sheet concentrations are changed to p-type. It is desirable to make it higher than the sheet concentration of the GaN channel layer 16.

FIG. 12 is a schematic diagram showing the structure of a GaN-HFET according to the ninth embodiment of the present invention. The embodiment shown in this figure is a modification of the embodiment shown in FIG. The same components as those of the HFET shown in FIG. 11 are denoted by the same reference numerals, and detailed description thereof is omitted.
In the HFET in this figure, a p-type GaN channel layer 16 is formed on a conductive substrate 18 via a buffer layer 17. Further, the back surface electrode 19 is formed on the back surface of the conductive substrate 18, and the back surface electrode 19 and the source electrode 8 are connected.
By adopting such a structure, it is possible to quickly discharge the holes 20 when a high voltage is applied to the element and an avalanche breakdown occurs, thereby realizing a high avalanche resistance. At this time, AlN or an AlN / GaN superlattice structure can be used for the buffer layer 17, and silicon carbide (SiC), silicon (Si), or the like can be used for the conductive substrate. In order to discharge the holes 20, the buffer layer 17 and the conductive substrate 18 are preferably p-type. In addition, the buffer layer 17 and the conductive substrate 18 serve as a field plate regardless of the p-type and n-type, and the electric field concentration between the gate and the drain is alleviated.

FIG. 13 is a schematic diagram showing the structure of a GaN-HFET according to the tenth embodiment of the present invention. The same components as those in the HFET shown in FIG.
The HFET in this figure has a structure in which an insulating film 21 is formed on the surface of the HFET shown in FIG. 5 and a field plate electrode 22 is formed so as to cover the gate electrode 10 via the insulating film 21. By connecting the field plate electrode 22 to the source electrode 8, electric field concentration at the end of the gate electrode 10 can be relaxed, and a high breakdown voltage can be realized. Further, even if the field plate electrode 22 is connected to the gate electrode 10, the same effect can be obtained.

FIG. 14 shows a modification of the GaN-HFET shown in FIG. The same components as those of the HFET shown in FIG. 5 are denoted by the same reference numerals, and detailed description thereof is omitted.
In this figure, a second field plate electrode 23 connected to the drain electrode 9 is further formed, and the electric field concentration at the end of the drain electrode 9 is also relaxed, thereby realizing a higher breakdown voltage.
So far, the first to tenth embodiments of the present invention have been described, but the present invention is not limited to these embodiments. It is possible to combine the respective embodiments, and those appropriately modified by those skilled in the art are also included in the scope of the present invention as long as the gist of the present invention is included.

  For example, in the drawings other than the ninth embodiment, the substrate is not shown, but any of a sapphire substrate, a SiC substrate, a Si substrate, and a GaN substrate can be used, and the substrate material is not particularly limited. . It is not limited to the insulation and conductivity of the substrate, and further to its conductivity type.

In the specific examples described above, the combination of AlGaN / GaN has been described as the material of the barrier layer / channel layer, but GaN / indium gallium nitride (InGaN), aluminum nitride (AlN) / AlGaN, etc. It can also be implemented in combination. That is, by using a nitride semiconductor having a relatively small band gap as the material of the channel layer and using a nitride semiconductor having a relatively large band gap as the material of the barrier layer, it is possible to obtain the same effect. is there.
Further, the structure between the gate and the drain of the HFET operates as a Schottky Barrier Diode (SBD) using a heterojunction, and can also be implemented as an SBD with a small reverse leakage current.

Note that in this specification, “nitride semiconductor” means a composition ratio and y in a chemical formula of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). Semiconductors of all compositions varied within the respective ranges are included.

It is a schematic diagram showing the structure of GaN-HFET concerning the 1st Embodiment of this invention. It is a schematic diagram showing an example of the manufacturing process of GaN-HFET concerning the 1st Embodiment of this invention. It is a graph showing the relationship between gate threshold voltage (Vth) and the film thickness of the AlGaN barrier layer under a gate electrode. It is a chart showing the relationship between the Al composition ratio of AlGaN and the film thickness when the gate threshold voltage (Vth) is 0V. It is a schematic diagram showing the structure of GaN-HFET concerning the 2nd Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 3rd Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 4th Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 5th Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 6th Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 7th Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 8th Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 9th Embodiment of this invention. It is a schematic diagram showing the structure of GaN-HFET concerning the 10th Embodiment of this invention. It is a modification of GaN-HFET shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 GaN channel layer 2 AlGaN barrier layer 3, 4 GaN 1st contact layer 5,6 AlGaN 2nd contact layer 8 Source electrode 9 Drain electrode 10 Gate electrode 11 Superlattice layer 13 Cap layer 15 Gate insulating film 16 Channel layer 17 Buffer layer 18 conductive substrate 19 back electrode 20 hole 21 insulating film 22 field plate electrode 23 second field plate electrode 25 mask

Claims (5)

A first semiconductor layer made of a nitride semiconductor;
A second semiconductor layer provided on the first semiconductor layer and made of a non-doped or n-type nitride semiconductor having a band gap larger than that of the first semiconductor layer;
A control electrode provided directly or via an insulating film in the first region on the second semiconductor layer;
A third semiconductor layer made of a non-doped or n-type nitride semiconductor provided in each of the second and third regions adjacent to both ends of the first region on the second semiconductor layer;
A fourth semiconductor layer provided on each of the third semiconductor layers and made of a non-doped or n-type nitride semiconductor having a band gap larger than that of the third semiconductor layer;
With
The nitride semiconductor device, wherein the thickness of the second semiconductor layer is uniform in the first region and the second and third regions.   The channel of the two-dimensional electron gas is not formed at the interface between the first semiconductor layer and the second semiconductor layer under the control electrode when a control voltage is not applied to the control electrode. The nitride semiconductor device according to Item 1 The first region is provided in the second region so as to be separated from the control electrode, and is electrically connected to a two-dimensional electron gas formed at an interface between the first semiconductor layer and the second semiconductor layer. A main electrode;
A second region which is provided apart from the control electrode in the third region and is electrically connected to a two-dimensional electron gas formed at an interface between the first semiconductor layer and the second semiconductor layer; A main electrode;
Further comprising
When the gap between the control electrode and the first main electrode is L _gs and the gap between the control electrode and the second main electrode is L _gd ,

L _gs <L _gd

The nitride semiconductor device according to claim 1, wherein:   The nitride semiconductor device according to claim 1, wherein a thickness of the second semiconductor layer is 8.2 nanometers or less. The first semiconductor layer is made of GaN,
The second semiconductor layer is made of Al _Y Ga _1-Y N,
The thickness of the second semiconductor layer is relative to the aluminum composition ratio Y.
1 / (1.15Y ² + 0.326Y + 0.01)
The nitride semiconductor device according to any one of claims 1 to 3, wherein:

Images