JP2007026209A - Hardware system and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable reconstitutable wiring logic elements to dynamically constitute a system by themselves. <P>SOLUTION: A hardware system is provided with; a first information processing part 101 which designates processing of information to a plurality of information processing parts 101-106, 111-116, 121-126, 131-136, and 141-146, which are all the same in composition, from an input part 3, when the plurality of information processing parts are provided, and executes the processing of the information inputted from the input part 3; a transmission path through which a request for executing new information processing is transmitted from the first information processing part 101 to another information processing part when the new information processing is required in information processing in the first information processing part 101; and a second information processing part 102 which receives the request via the transmission path, connects with the first information processing part 101 to execute the new information processing, and executes processing for returning the result of the information processing concerned to the first information processing part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to, for example, a hardware system and an information processing method, and more particularly, to a hardware system and an information processing method thereof capable of arbitrarily configuring a dynamic logic circuit by combining reconfigurable wiring logic elements. .

  Conventionally, a reconfigurable wiring logic element (FPGA: Field Programmable Gate Array) is known. This reconfigurable wiring logic element includes, for example, a large number of units that can perform storage and calculation as a single unit wiring logic element, configure a processor, and when there is a calculation request from the outside, A control means called an officer determines how many wiring logic elements perform necessary operations, and based on the determination, uses them for calculation and storage among many prepared wiring logic elements. The wiring logic element was set.

Patent Document 1 discloses an example of a system that uses a conventional reconfigurable wiring logic element.
Japanese Patent Laid-Open No. 11-167556

  However, if the processing using the reconfigurable wiring logic element is performed under the control of the land officer, each prepared wiring logic element and the land officer are connected to each other so that they can communicate with each other. There is a problem that the system configuration and management become very complicated because it is necessary to transmit a command from the land officer. In particular, the larger the number of wiring logic elements, the more problematic.

  In addition, in the configuration in which a control means such as a land officer is provided and setting is performed by the control, the control means eventually becomes a system that centrally manages operations, and the use of a large number of prepared wiring logic elements There is a problem of lack of state flexibility. If a land officer is required, whether processing using a large number of wiring logic elements is performed efficiently or inefficiently depending on whether the program that operates the land officer is possible or not. There are elements that are determined, and it is impossible for a large number of prepared wiring logic elements to form a system by themselves.

  An object of the present invention is to use a reconfigurable wired logic element so that its own element can be dynamically configured in a system.

  In the present invention, when a plurality of information processing units each having the same configuration are provided, information processing is specified for the plurality of information processing units from the input unit, and processing of information input from the input unit is executed. When new information processing is required in the information processing performed by the first information processing unit and the first information processing unit, the first information processing unit is newly updated with respect to other information processing units. A transmission path for transmitting a request for execution of the information processing, and receiving the request via the transmission path, connecting to the first information processing unit, performing new information processing, and obtaining the information processing result as the first information And a second information processing unit that performs processing to return to the processing unit.

  According to the present invention, when information input from the outside is input to a specific information processing unit, the information processing unit immediately processes, but if there is a shortage of processing in the information processing unit, A request for execution of the process is made directly from the information processing unit to the other information processing unit, the processing is performed by the information processing unit that has received the request, and the processing state is determined by each information processing unit at its own judgment. As a result, the processing capacity is self-replicated, and an optimum processing state is set without requiring external control.

  In this case, the connection path that connects the information processing units is prepared separately from the transmission path that transmits a request for execution of new information processing, regardless of the transmission processing in the transmission path that transmits various requests. Data for information processing can be exchanged between the information processing units, and each transmission can be performed reliably and efficiently.

  In addition, when new information processing is completed in the second information processing unit, the connection with the first information processing unit is released, and the second information processing unit is returned to the original state. The information processing unit is connected only to and the process is executed, and according to the information processing request, not only the use number of the information processing unit increases, but the use number decreases when the process ends, It becomes a flexible system configuration that increases or decreases according to the processing request at that time.

  Furthermore, by providing an output unit that outputs the processing result in the first information processing unit to the outside, the output result is always output from the common output unit even when the number of information processing units used increases. This simplifies the output configuration.

  Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a diagram showing an example of the overall configuration of the arithmetic processing apparatus of this example configured using reconfigurable wiring logic elements. As shown in FIG. 1, a data generation source 1 and a processing result receiving unit 2 are connected to an input / output processing unit 3, and information in which a plurality of cells are arranged in a matrix in the input / output processing unit 3 A processing device is connected.

  Each of the cells 101 to 106, 111 to 116, 121 to 126, 131 to 136, 141 to 146 has a common configuration, and each includes the built-in function processing unit 10 and the variable unit 20. Each of the built-in function processing units 10 is connected to the built-in function processing units 10 of other cells vertically and horizontally through a built-in function communication path so that they can communicate with each other. The cells in the terminal column and the terminal row are also connected to the input / output processing unit 3, and information such as commands can be sent from the input / output processing unit 3 to the cell.

  Each variable unit 20 is also connected to the variable unit 20 of another cell through the general information communication path so as to be able to communicate with each other. The cell in the end column and end row has a general information communication path connected to the input / output processing unit 3 and sends actual information to the cell from the input / output processing unit 3 and inputs the processing result in the cell. The output processing unit 3 can output the data.

  With such a configuration, when processing the information supplied from the data generation source 1 to the input / output processing unit 3, the variable unit 20 of any cell is in response to a command from the input / output processing unit 3. However, information supplied from the data generation source 1 to the input / output processing unit 3 is sent to a cell in which the function circuit is assembled. Information for assembling the cell variable section 20 as a circuit having a predetermined function is sent from the input / output processing section 3 to the cell built-in function processing section 10 via the built-in function communication path. In the built-in function processing unit 10, the variable unit 20 is configured to be a circuit for a predetermined function based on the sent information, and the information input to the variable unit 20 via the general information communication path is received. Then, the processing is performed by the configured circuit. When the processing is completed in one cell, the processed result is sent to the input / output processing unit 3 and supplied from the input / output processing unit 3 to the processing result receiving unit 2. The result processed in one cell can be supplied to another cell for further processing. In addition, as described later, when processing capacity is insufficient in one cell, another circuit is assembled in another cell adjacent to the cell itself, and some processing is performed in the other circuit. It is also possible to return the executed result to its own cell.

  An information processing apparatus configured as described above and having a plurality of cells arranged vertically and horizontally in a matrix is called a plastic cell architecture (PCA). Plastic here means having plasticity, and indicates that the hardware can be programmed as will be described later. In this example, information transmission between the input / output processing unit 3 and each cell and information transmission between each cell are performed by transmitting information as an asynchronous circuit. The system clock is a nonexistent system. As transmission as an asynchronous circuit, for example, in each cell, the signal state of a communication path connected to the cell is detected, and when there is a change in the signal state of the communication path, a process of receiving a signal input, etc. is there.

  Next, the configuration of each cell will be described with reference to FIG. As shown in FIG. 2, each cell includes a built-in function processing unit 10 and a variable unit 20. In the built-in function processing unit 10, built-in function processing unit communication paths 41, 42, 43, 44, 45, 46, 47, and 48 for communicating with surrounding cells and the like are bidirectional in the vertical and horizontal directions. It is installed so that it can communicate. Each of the built-in function processing unit communication paths 41 to 48 is connected to a switch 11 provided in the built-in function processing unit 10, and the switch 11 connects to a communication path in another direction. Are switched to the variable unit 20 side connected to the control unit 16 and to the control unit 16 in the built-in function processing unit 10. Switching by the switch 11 is controlled by the control unit 16. This switching control is performed based on, for example, the operation state of the own cell at that time or the received command.

  Port controllers 12 to 15 are arranged between the communication path in each direction and the switch 11, and inputs and outputs via the communication path are controlled by the controller 16. Specifically, the upward built-in function processing unit communication paths 41 and 42 are connected to the switch 11 via the port control unit 12, and the right built-in function processing unit communication paths 43 and 44. Is connected to the switch 11 via the port control unit 13, and the downward embedded function processing unit communication paths 45 and 46 are connected to the switch 11 via the port control unit 14, and leftward The built-in function processing unit communication paths 47 and 48 are connected to the switch 11 via the port control unit 15. Furthermore, the switch 11 on the built-in function processing unit 10 side and the variable unit 20 are connected via the internal communication paths 49 and 50.

  The variable unit 20 includes a storage / function unit 21. The storage / function unit 21 is a function unit that is incorporated as a circuit that executes (or stores) an arbitrary function in response to an instruction from the variable unit 20, and corresponds to a circuit unit that can program hardware. The variable unit 20 is configured such that general information communication paths 51 to 54 are prepared vertically and horizontally to input and output information to and from the outside and other cells.

  The general information communication paths 51 to 54 are connected to the variable unit 20 via the switches 22 to 25, and input of information to be processed by the storage / function unit 21 in the variable unit 20 and the storage / function unit 21. The output of the processed information to the general information communication paths 51 to 54 in each direction is controlled by these switches 22 to 25. The general information communication paths 51 to 54 are also used when exchanging information to be processed (processed information) with other cells.

  Next, an example of processing performed using the information processing apparatus configured as described above will be described. First, it is assumed that a circuit having a predetermined function is present in an arbitrary cell among the plurality of cells 101, 102,. Information for causing a circuit with a predetermined function to exist is sent from the input / output processing unit 3 to the cell, and the information is received in an empty cell that has not yet been assembled, so that the circuit with the corresponding function is assembled. It is.

  FIG. 3 is an example of a circuit incorporated in the storage / function unit 21 of a specific cell. In this example, a circuit having a function of calculating the factorial is assembled. This circuit will be described. An input terminal 81 and an output terminal 82 are provided, and information is input and output via a general information communication path (FIG. 2). In addition, a control terminal 83 is provided to which an output of a circuit addition request and a completion waiting signal are input. The control terminal 83 is a terminal connected to the built-in function processing unit 10 side via the internal communication paths 49 and 50 (FIG. 2). Input and output of signals obtained at the control terminal 83 are processed by the determination unit 84.

  A signal obtained at the input terminal 81 is supplied to the processing unit 90 via the switch 85. In this example, the processing unit 90 is first supplied to the decrementer 91 to generate a value “1” less than the input value, and the output of the decrementer 91 is the circuit type (here, the circuit type name). 92) (denoted as “fact”). The circuit type 92 is a circuit composed of another cell, and processing is performed in the circuit type 92 (that is, another cell) if necessary. When processing in another cell is not necessary, the output of the decrementer 91 is output as it is.

  The output of the circuit type 92 is supplied to the multiplier 93 and multiplied by the output of the switch 85. The output of the multiplier 93 is supplied to the output terminal 82 via the switch 86. The switches 85 and 86 are switches for switching a path from the decrementer 91 via the multiplier 93 and a path 87 not passing through them, and the switching is controlled by the determination unit 84. When the processing in this cell is not necessary, the route 87 is selected, and when the processing is necessary, the route from the decrementer 91 via the multiplier 93 is selected.

  The determination unit 84 determines whether or not the value obtained at the input terminal 81 is “1”. When the value is not “1” (when the value is 1 or more), a circuit addition request is output from the terminal 83. To do. When the determination unit 84 determines the completion input after outputting the addition request, the cells are connected so that the input and output of the circuit type 92 are connected to another added cell. For this connection, for example, the switches 22 to 25 shown in FIG. 2 are used.

  FIG. 4 is a diagram illustrating an example in which another circuit is added by the addition request. As shown in FIG. 4, as the circuit type 92, a circuit assembled in the storage / function unit 21 'of another cell is connected. Here, the same circuit as the circuit assembled in the storage / function unit 21 is assembled in the storage / function unit 21 ′, and the input terminal 81 and the output terminal of the circuit assembled in the storage / function unit 21 ′. 82 is connected to the circuit type 92 of the storage / function unit 21.

  The circuit assembled in the added memory / function unit 21 ′ also has a circuit type 92 so that a circuit assembled in another cell can be connected.

  An example of calculating the factorial using the circuit configured as described above will be described. For example, when the value input to the input terminal 81 of the first cell is “3”, the determination in the circuit is performed. Since the circuit type (fact) 92 is added by the determination of the unit 84 and the input value is “2” even in the added cell, the circuit type 92 is further added. 2 times, 3 × 2 × 1 calculation is performed, and 3 factorial calculation is performed. As shown in FIG. 4, even if the circuit type is prepared in a plurality of cells, the switches 85 and 86 in the circuit type select the path 87 side and pass through the circuit type. Thus, processing that does not use the circuit type can be easily selected, and whether or not to use the once assembled circuit according to the input at that time can be determined by the circuit itself.

  Thus, in the case of this example, as a configuration assembled in each cell, (1) a part existing from the beginning by an instruction from the outside, (2) a part newly added by an instruction from another cell, ( 3) a part for judging addition, (4) a part for transmitting an addition request to the outside and waiting for its completion, and (5) a switch for switching the connection to the additional part. Either (1) a part existing from the beginning by an instruction from the outside, or (2) a part newly added by an instruction from another cell, either circuit is assembled. The part for determining the addition of (3) and the part for transmitting the addition request of (4) to the outside and waiting for the completion correspond to the determination unit 84 shown in FIGS.

  In the configuration illustrated in FIG. 4, the circuit type (fact) includes a circuit type of another cell. However, the circuit type includes another type, and the circuit type includes the circuit type. There may be cases. There may be a configuration in which one circuit type includes a plurality of circuit types. In the description with reference to FIG. 4, the process of increasing the circuit type has been described. However, when the increased circuit type becomes unnecessary, the state where the circuit is assembled with the increased cell is released. Then, it may be returned to a so-called empty cell.

  Next, an example of a processing state in which the addition or release of the circuit of another cell is performed based on such determination by each cell itself will be described with reference to the flowchart of FIG. First, in each cell, it is determined whether or not there is a function setting request based on a command received via the built-in function processing unit communication path on the built-in function processing unit 10 side (step S11). Here, when it is possible to respond to the request in its own cell, the variable unit 10 is set to a circuit having a corresponding function (step S12). Then, the input and output of the set circuit are set using the general information communication path (step S13).

  With the circuit set in this way, it is determined whether information to be processed has been input via the general information communication path (step S14). Here, if input, the processing (calculation) of the function set in step S12 is executed for the input information (step S15). Here, the necessity of function addition is determined (step S16), and when the function addition is not necessary, the process of step S15 is repeated.

  If it is determined in step S16 that a function addition is necessary, a search for an empty cell in which no function is incorporated in the variable unit is performed by transmitting a necessary command on the built-in function processing unit 10 side ( Step S17). When an empty cell is searched, it is determined that the empty cell is a cell to which a function is to be added, an addition request is made to the cell, and a circuit for executing the additional function is made to the requested cell (step S18). Then, the output and input of the own cell and the input and output of the added cell are connected using the general information communication path (step S19). In this state, the set function is executed (step S20).

  Then, it is determined whether or not the addition of the added function becomes unnecessary (step S21). If the added function is necessary, the process in step S20 is repeated. When the added function becomes unnecessary, a request is made to release the connection with the added cell (step S22), and the connection with the added cell is released (step S23). For example, the process of step S15 is performed. Return. In this way, the addition and release of cells are repeated at the cell's own discretion.

  In the flowchart of FIG. 5, it is assumed that a process of adding one cell is performed, but actually, as described in the example of FIG. 4, a plurality of cells may be added simultaneously or sequentially. In such a case, a plurality of cells are added in the adding process in steps S18 and S19.

  As described above, according to the present invention, when a processing configuration includes a plurality of cells (information processing units), a function of adding a new element can be provided by independent determination in each cell. Circuit configuration. Such addition of functions in hardware can be realized with high performance and low power consumption as compared with the realization of functions by a processor and software included in a conventional general computer apparatus. In particular, since each cell autonomously adds or reduces, there is no need for a means corresponding to a land officer for comprehensively managing the state in a plurality of cells, and the system configuration becomes very simple. In addition, since the asynchronous transmission is performed as the data transmission between the cells, it is not necessary to supply a common system clock to each cell, and the configuration is simple from that point. However, the asynchronous transmission itself is not an essential processing configuration for performing the processing of the present invention. In the above-described embodiment, the example of performing the factorial calculation shown in FIGS. 3 and 4 has been described as an example of the circuit configuration assembled in the cell. However, this arithmetic circuit is a simple example. Yes, it can be applied to various circuit configurations. Even when the variable part of each cell is configured as a storage unit instead of the arithmetic circuit, when the storage in the storage unit is insufficient, the variable part of another cell is configured as the storage unit independently, A storage unit may be additionally used.

1 is a block diagram illustrating a system configuration example according to an embodiment of the present invention. It is the block diagram which showed the cell structural example of 1 unit by one embodiment of this invention. It is explanatory drawing which showed the function setting example of the variable part by one embodiment of this invention. It is explanatory drawing which showed the example of a function setting of the variable part of several cells by one embodiment of this invention. It is the flowchart which showed the example of the function setting process of the cell by one embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Data generation source, 2 ... Processing result receiving part, 3 ... Input / output processing part, 10 ... Built-in function processing part, 11 ... Switch, 12-15 ... Boat control part, 16 ... Control part, 20 ... Variable part, 21 ... Memory / Function part, 22-25 ... Switch, 41-48 ... Built-in function processing part communication path, 49, 50 ... Internal communication path, 51-54 ... General information communication path, 81 ... Input terminal, 82 DESCRIPTION OF SYMBOLS ... Output terminal 83 ... Control terminal 84 ... Judgment part 85, 86 ... Switch, 87 ... Transmission path, 90 ... Processing part, 91 ... Decrementer, 92 ... Circuit type, 93 ... Multiplier, 101-106, 111- 116, 121-126, 131-136, 141-146 ... cell

Claims (6)

In a hardware system including a plurality of information processing units each having the same configuration,
An input unit that specifies information processing for the plurality of information processing units;
A first information processing unit selected from the plurality of information processing units for executing processing of information input from the input unit;
When new information processing is required for information processing in the first information processing unit, execution of the new information processing is performed from the first information processing unit to another information processing unit. A transmission line that conveys the request;
Upon receiving a request via the transmission path, connect to the first information processing unit, perform the new information processing, and perform processing to return the information processing result to the first information processing unit. A hardware system comprising: a second information processing unit selected from a plurality of information processing units. The hardware system according to claim 1,
When new information processing is required for information processing in the second information processing unit, new information processing unit is newly transmitted from the second information processing unit to the other information processing unit via the transmission path. Telling the execution of the information processing,
Upon receiving a request via the transmission path, connect to the second information processing unit, perform the new information processing, and perform processing to return the information processing result to the second information processing unit. A hardware system comprising a third information processing unit selected from a plurality of information processing units. The hardware system according to claim 1,
A hardware system characterized in that a connection path for connecting the first information processing section and the second information processing section is prepared separately from the transmission path. The hardware system according to claim 1,
The second information processing unit opens a connection with the first information processing unit when the new information processing is completed. The hardware system according to claim 1,
A hardware system comprising an output unit for outputting a processing result in the first information processing unit to the outside. In an information processing method in a hardware system including a plurality of information processing units each having the same configuration,
An input step for designating information processing for the plurality of information processing units;
A first processing step of executing processing of information input in the input step by a first information processing unit among the plurality of information processing units;
When new information processing is required in the information processing in the first information processing unit in the first processing step, the first information processing unit A request transmission step for transmitting a request for execution of new information processing;
Upon receiving the request in the request transmission step, the first information processing unit is connected to the second information processing unit, the new information processing is performed, and the information processing result is sent to the first information processing unit. An information processing method comprising: a second processing step for performing a returning process.

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