JP2007026196A - Usb test monitor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a USB test monitor circuit for monitoring interface signals between a physical layer transmitting/receiving differential signals flowing in a USB bus and a serial interface engine conducting communication of the physical layer, for identifying a transaction flowing in the USB bus, and for evaluating validity of a part independent of the physical layer without using an additional measurement apparatus. <P>SOLUTION: The USB test monitor circuit is provided with a state machine 102 for identifying the transaction of the differential signals flowing in the USB bus based on a UTMI signal between a PHY transmitting/receiving the differential signals flowing in the USB bus and an SIE conducting communication of the PHY; a data generation part 101 for generating data signals flowing in the USB bus based on the UTMI signal; and a parallel control part 14 for outputting in parallel the transaction identification result identified in the state machine 102 and the data signal generated in the data generation part 101. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a USB test monitor circuit, and in particular, monitors an interface signal between a physical layer that transmits and receives a differential signal flowing through a USB bus and a serial interface engine that performs physical layer communication and flows through the USB bus. The present invention relates to a USB test monitor circuit that identifies a transaction and evaluates the validity of a part that does not depend on a physical layer without using a new measuring instrument.

  In recent years, USB (Universal Serial Bus), IEEE 1394, and the like have attracted attention as interfaces for connecting PC peripheral devices such as personal computers, printers, and scanners to each other.

  Data transfer between devices connected via these interfaces is a serial transfer method, and data transfer is performed at high speed.

  Controllers that control these interfaces usually send and receive data by converting analog signals flowing between wires into digital signals in the physical layer, transferring them to the data link layer, and converting them into a prescribed format. It is the composition which performs.

  In the physical layer, parallel data sent from the data link layer is serially converted at high speed and output to the wiring. Therefore, the signal measurement at the physical layer becomes more difficult as the data transfer speed increases.

  Therefore, in order to evaluate the controller of the interface that transfers data at high speed, there is a problem that the evaluation cannot be performed unless the environment is equipped with very expensive measuring instruments.

Therefore, Patent Document 1 proposes a high-speed serial controller that can debug a portion that does not depend on the physical layer without preparing a new expensive measuring instrument.
Japanese Patent Application Laid-Open No. 2004-271282

  However, in the above-mentioned Patent Document 1, a signal between the PHY circuit and the LINK circuit is output to the serial I / F in the test mode so that the validity of the circuit portion independent of the PHY can be evaluated. In order to identify a transaction flowing through the high-speed serial bus, it is necessary to prepare a means for identifying the transaction.

  Accordingly, the present invention monitors the interface signal between the physical layer that transmits and receives the differential signal flowing through the USB bus and the serial interface engine that communicates with the physical layer, identifies the transaction flowing through the USB bus, It is an object of the present invention to provide a USB test monitor circuit that performs a new evaluation of the validity of a layer-independent part without using a measuring instrument.

  To achieve the above object, the invention of claim 1 acquires a first interface signal between a physical layer that transmits and receives a differential signal flowing through a USB bus and a serial interface engine that communicates with the physical layer. First interface signal acquisition means, transaction identification means for identifying a differential signal transaction flowing through the USB bus based on the first interface signal, and a data signal flowing through the USB bus based on the first interface signal And a first output means for outputting in parallel the transaction identification result identified by the transaction identification means and the data signal generated by the first interface signal acquisition means. And

  According to a second aspect of the present invention, in the first aspect of the invention, the transaction identifying means identifies a differential signal transaction flowing through the USB bus by identifying a packet identifier included in the first interface signal. Thus, a flag signal for identifying the type of the transaction is output.

  The invention of claim 3 is the invention of claim 2, further comprising a transaction counter that counts the number of occurrences of each type of transaction identified by the transaction identification means based on the flag signal. To do.

  According to a fourth aspect of the present invention, in the first aspect of the present invention, the second interface signal acquisition means for acquiring a second interface signal between the serial interface engine and the DMA control circuit, and the second interface signal And a second output means for outputting the interface signal as parallel data.

  According to the USB test monitor circuit of the present invention, when performing the USB operation evaluation of the ASIC having the built-in PHY and SIE, there is no need for a measuring instrument for monitoring the USB bus, and an existing measuring instrument for evaluation (logic analyzer) is used. ) Can be used to monitor a transaction flowing through the USB bus by observing the interface signal output to the parallel I / F at the ASIC terminal.

  Further, by outputting an identification flag signal for identifying each transaction separately from the UTMI signal that is an interface signal between PHY and SIE, it is possible to easily confirm the type of transaction being operated.

  Also, by counting the number of occurrences of transaction operations with a counter in the ASIC, the number of occurrences of each transaction operation can be confirmed.

  In addition, since a signal between the SIE and the DMA control unit can be output to the parallel I / F, the USB bus signal can be easily monitored when a problem occurs.

  Hereinafter, an embodiment of a USB (Universal Serial Bus) test monitor circuit according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a configuration diagram schematically showing an example of a printer controller 1 provided with a USB test monitor circuit 100 according to the present invention.

  The printer controller 1 includes a printer controller ASIC (= Application Specific Integrated Circuit) 10, a CPU (Central Processing Unit) 20, a transmission / reception buffer memory 30, and a parallel I / F (interface). The printer controller ASIC 10 includes a USB control unit that performs USB control between the USB 2 on the host side (hereinafter referred to as “USB host 2”) and the USB of the printer controller ASIC 10, and a USB test monitor circuit. 100 and a test register 17.

  The USB control unit includes a PHY 11 that performs physical layer transmission / reception, an SIE 12 that is a serial interface engine, a DMA control unit 13 that performs DMA (= Direct Memory Access) control, a parallel control unit 14, and an interrupt control unit 15. The USB test monitor circuit 100 includes a data generation unit 101, a state machine 102, a transaction counter 103, an error counter 104, an operation selection unit 105, a first selector 106, A second selector 107 and a third selector 108 are provided.

  The PHY 11 of the USB control unit performs physical layer transmission / reception between the USB host 2 and the USB of the printer controller ASIC 10, and converts the USB differential signals (D +, D−) transferred from the USB host 2 into digital signals. .

  The SIE 12 interprets a digital signal transmitted from the PHY 11 to recognize a USB packet (hereinafter referred to as “packet”), and transmits the recognized packet to the PHY 11 according to the USB protocol.

  When the SIE 12 receives a packet that does not require CPU processing, the SIE 12 automatically returns the packet to the PHY 11. When the SIE 12 receives a packet that requires CPU processing, the SIE 12 sends an interrupt signal to the interrupt control unit 15. Output and cause interrupt control, and send a packet based on CPU processing to the PHY 11 (control transfer).

  The DMA control unit 13 performs control for direct data transfer between the USB host 2 side and the memory 30 without using the CPU 20.

  The arbitrating unit 16 arbitrates the output order of the input signals.

  Specifically, when a large amount of data such as bulk transfer is transmitted / received, the DMA control unit 13 outputs a DMA request to the arbitration unit 16 based on a transfer request signal output from the SIE 12 to the DMA control unit 13. The arbitration unit 16 arbitrates the output order of data between the memory 30 and an external memory (not shown) based on the DMA request from the DMA control unit 13, so that a large amount of data is transferred between the memory 30 and the external memory (not shown). Sent and received.

  The parallel control unit 14 outputs control signals to the second selector 107 and the third selector 108 of the USB test monitor circuit 100, and the parallel data is transferred to the parallel I / F 40 via the second selector 107 and the third selector 108. To control.

  The USB test monitor circuit 100 monitors a UTMI (USB Transceiver Macrocell Interface) signal, which is an interface signal between the PHY 11 and the SIE 12 of the USB control unit, and uses a PID (= Packet IDentifier: packet identifier) when data is valid. It is configured to recognize the type and detect the number of occurrences of transaction operations for each type.

  The data generation unit 101 of the USB test monitor circuit 100 generates 8-bit data based on the UTMI signal between the PHY 11 and the SIE 12 of the USB control unit, and the generated data is used as an instruction signal of the parallel control unit 14 of the USB control unit. Based on the first selector 106 and the second selector 107, the parallel data is transferred to the parallel I / F 40.

  The signals output from the SIE 12 to the PHY 11 are, for example, DataIn (8 bits), TxValid (1 bit), TxReady (1 bit), and the signals output from the PHY 11 to the SIE 12 are, for example, DataOut (8 bits), RxActive (1 bit). ), RxValid (1 bit), and the like.

  The state machine 102 monitors the UTMI signal between the PHY 11 and the SIE 12, and recognizes the type of transaction based on the PID when the data is valid.

  Further, the state machine 102 sets the flag indicating the transaction operation to “High” or “1”, and sets the flag to “Low” or “0” when the transaction operation ends and returns to the IDLE state, and TxValid, TxReady When both are “High” or “1”, it is recognized that DataIn is valid, and when both RxActive and RxValid are “High” or “1”, it is recognized that DataOut is valid.

The flag value set and output by the state machine 102 is output as a control signal from the control signal line of the parallel I / F 40 in the test mode.
The transaction counter 103 is a counter that can be read and cleared, and counts the number of occurrences for each transaction type.

  The operation selection unit 105 selects and designates a target transaction type to be counted by the transaction counter 103.

  Note that by reading the count value of the transaction counter 102 at an arbitrary timing at the end of the test, the number of occurrences of the target transaction selected and designated by the operation selection unit 105 can be read.

  This transaction counter 103 can operate even when the test mode is OFF, that is, in the normal operation mode that is not the test mode, and by counting the number of occurrences of transactions, handshakes, etc. on the USB bus during normal operation (for example, If the number of occurrences of the NYET handshake is known, it is possible to know a guideline such as the degree of the reception buffer Full.) It is possible to monitor the operation state of the transaction flowing through the USB bus.

  The first selector 106 and the second selector 107 select a valid data line in the USB test monitor circuit 100, and the third selector 108 selects a valid control line in the USB test monitor circuit 100.

  Specifically, in the test mode, the first selector 106 generates a data signal generated by the data generation unit 101 and transferred between the SIE 12 and the DMA control unit 13 according to a select signal transferred from the test register 17. A valid data signal is selected from the generated data signals and transferred to the second selector 107.

  The second selector 107 is a data signal (data generation unit) selected and transferred by the first selector 106 in accordance with a select signal input from a test pin (terminal) or the test register 17 when the printer controller ASIC 10 is in the test mode. The data signal generated and transferred at 101 or the data signal generated between the SIE 12 and the DMA control unit 13 is selected, and during normal operation, the data signal transferred from the parallel control unit 14 is selected to be parallel. Transfer to I / F 40.

  The error counter 104 is a counter that can be read and cleared. When the PID recognized by the state machine 102 does not correspond to any PID type (for example, token, handshake, special, etc.), an error pulse signal is parallelized. While outputting to the I / F 40, the count value is counted up.

  When the data bus of the UTMI signal between PHY11 and SIE12 is 8 bits, it operates as a 60 MHz synchronous signal, and when the data bus of the UTMI signal is 16 bits, it operates as a 30 MHz synchronous signal. The bus is sized to 8 bits within 100, and the parallel I / F 40 operates as a 60 MHz synchronous signal.

  In addition, the data bus of the parallel I / F 40 has an output direction linked to the test mode.

  The third selector 108 selects a signal indicating a flag value transferred from the state machine 102 by the test register 17 or Testpin (terminal) in the test mode of the printer controller ASIC 10, and in the normal operation, the parallel control unit 14. Is selected and transferred to the parallel I / F 40.

  FIG. 2 is a PID list 200 showing an example of PIDs and flag types monitored by the state machine 102 and counting target operations.

  Note that the state machine 102 does not monitor DATA0 and DATA1.

  As shown in the PID list 20, the PID type includes “token”, “handshake”, “special”, etc., and the transaction starts with a “token” or “special” packet and transitions to a phase indicated by each PID name. To do.

  Specifically, “token” includes “OUT”, “IN”, “SOF”, and “SETUP” indicated by PID names, and the “OUT” token packet from the host side (USB host 2 in this embodiment). When an “IN” token packet is issued, a transition is made to an IN transaction. When a “SETUP” token packet is issued, a transition is made to a SETUP transaction.

  When the “SOF” token packet is issued from the host side, frame generation for organizing a plurality of transactions is started on the host side.

  The OUT transaction indicates the start of a transmission transaction from the host side to the device side (printer controller ASIC 10 in this embodiment), the IN transaction indicates the start of a transmission transaction from the device side to the host side, and the SOF transaction indicates the start of a frame. The SETUP transaction indicates that a control transfer request is issued, and each transaction is issued from the host side.

  In addition, “ACK” of “handshake” indicates to notify the transmitting side that a data packet without error has been received, and “NAK” notifies the transmitting side that data transmission / reception has failed on the device side. "STALL" indicates that the communication cannot be continued due to some abnormal state on the device side, and "NYET" indicates that the receiving side is not ready yet Respectively.

  “Special” includes “PING” indicated by a PID name. When a “PING” special packet is issued from the host side, a transition is made to a PING transaction, and the state of the receiving side (the printer controller ASIC 10 in this embodiment) Shows to look into.

  For example, when an “OUT” token packet is issued from the host side, a transition is made to an OUT transaction. At that time, the state machine 102 sets an out flag indicating an OUT transaction operation to “High” or “1”, and the OUT transaction Is issued by the transaction counter 102.

  The host side sends a data packet of DATA0 or DATA1 following the “OUT” token regardless of the state of the device side. If the device side receives the data packet without error, it returns an “ACK” handshake packet. If data reception fails due to poor data reception preparation, a “NAK” handshake packet is returned. If data packet reception fails due to some abnormal condition, a “STALL” handshake packet is returned. Send back.

Further, when an “IN” token packet is issued from the host side and transitions to the IN transaction, the state machine 102 sets the in flag indicating the IN transaction operation to “High” or “1”, and the number of times the IN transaction is issued is the transaction counter It is counted by 102.
When transitioning to an IN transaction, the device transmits a DATA0 or DATA1 data packet if data transmission is possible, and a “NAK” handshake if the device cannot transmit data due to poor preparation for data transmission. A packet is returned, and when data cannot be transmitted for some reason, a “STALL” handshake packet is returned.

  When the host side successfully receives the data packet sent from the device side, it sends an “ACK” handshake packet, and the device side receives the “ACK” handshake packet sent from the host side to transfer the data. Judge that succeeded.

  When a “SETUP” token packet is issued from the host side and transitions to a SETUP transaction, the state machine 102 sets the setup flag indicating the SETUP transaction operation to “High” or “1”, and the number of times the SETUP transaction is issued is a transaction. It is counted by the counter 102.

  When a transition is made to the SETUP transaction, the host side transmits a DATA0 data packet following the “SETUP” token regardless of the state of the device side. If the device side successfully receives the data packet, the “ACK” handshake packet is transmitted. Reply.

  When a “SOF” token packet is issued from the host side, a frame in which a plurality of transactions are organized is generated on the host side, and the state machine 102 sets a sof flag indicating the SOF operation to “High” or “1”. Set to.

  FIG. 3 is a diagram illustrating an example of a data bus signal output between the PHY 11 and the SIE 12 during the SETUP transaction operation, a flag signal generated by the state machine 102, and a data signal output from the parallel I / F 40.

  As shown in FIG. 3, the USB test monitor circuit 100 monitors a UTMI signal that is an interface signal between the PHY 11 and the SIE 12 of the USB control unit, and an RxActive signal 302 and an RxValid signal 304 output from the PHY 11 to the SIE 12 are displayed. When both are “High” or “1”, it is determined that the DataOut “7: 0” signal 303 is valid, and the transaction is performed based on the PID of the DataOut “7: 0” signal 303 (in this case, “SETUP”). Is recognized as a SETUP transaction.

  When the SETUP transaction is recognized, a SETUP flag signal indicating “High” or “1” is output from the state machine 102, and the SETUP transaction counter signal 310 in which the SETUP count value of the transaction counter 103 is incremented. Is output.

  The SETUP flag signal is output as the SETUP flag (parallel I / F) signal 308 via the third selector 10 and the parallel I / F 40, and the DataOut “7: 0” signal 303 including the PID, Data, and Data is The data signal (parallel I / F) 309a is output via the selector 106, the second selector 107, and the parallel I / F 40.

  When the TxValid signal 305 and the TxReady signal 307 output from the SIE 12 to the PHY 11 are both “High” or “1”, it is determined that the DataIn “7: 0” signal 306 is valid, and the DataIn “7: Based on the PID of “0” signal 306 (in this case, “SETUP”), the transaction is recognized as a SETUP transaction, and when both TxValid 305 and TxReady signal 307 become “Low”, the SETUP transaction operation ends, and the IDLE state is entered. A SETUP flag signal 308 in which the SETUP flag is set to “Low” or “1” by determining that it has returned is output via the third selector 10 and the parallel I / F 40.

  As described above, the state machine 102 monitors the UTMI signal between the PHY 11 and the SIE 12 and recognizes the transaction type based on the PID when the data is valid. This will be described with reference to a flowchart.

  As shown in FIG. 4, the state machine 102 of the USB test monitor circuit 100 provided in the printer controller 1 monitors the UTMI signal between the PHY 11 and the SIE 12, and RxActive, which is a signal output from the PHY 11 to the SIE 12. When both RxValid are “High” or “1” (YES in step S401), it is determined that DataOut “7: 0” is valid and is transmitted from the host side (USB host 2 in this embodiment). The token ID or special packet of “SETUP”, “IN”, “OUT”, “PING”, or “SOF” is identified as the PID included in DataOut “7: 0”.

  Specifically, the DataOut “7: 0” PID, “SETUP”, “IN”, “OUT”, “SOF” token packets, and “PING” special packets sent from the host machine to the state machine 102 If the PID of DataOut “7: 0” matches the PID of the “SETUP” token packet (YES in step S402), the token packet transmitted from the host side is set to “SETUP”. Recognizing the token packet, the SETUP flag is incremented by “1”, and the SETUP count value of the transaction counter 103 is incremented by +1.

  If the PID of DataOUT “7: 0” matches the PID of the “IN” token packet (YES in step S403), the token packet transmitted from the host side is recognized as an “IN” token packet, The IN flag is incremented by “1”, and the IN count value of the transaction counter 103 is incremented by +1.

  If the PID of DataOUT “7: 0” matches the PID of the “OUT” token packet (YES in step S404), the token packet transmitted from the host side is recognized as the “OUT” token packet, The OUT flag is incremented by “1” and the OUT count value of the transaction counter 103 is incremented by +1.

  If the PID of DataOUT “7: 0” matches the PID of the “PING” special packet (YES in step S405), the special packet transmitted from the host side is recognized as a “PING” special packet, The ping flag is incremented by “1”, and the ping count value of the transaction counter 103 is incremented by +1.

  If the PID of DataOUT “7: 0” matches the PID of the “SOF” token packet (YES in step S406), the SOF flag is set to “1”.

  If the PID of DataOUT “7: 0” is not “SETUP”, “IN”, “OUT”, “PING”, or “SOF” (NO in step S406), the state machine 102 sets an error flag. “1”, the count value of the error counter is incremented by +1.

Note that when a “SETUP” token packet is transmitted from the host side to the device side (printer controller ASIC 10 in this embodiment) (YES in step S402), the IDLE state is changed to the SETUP transaction (step S500), and “IN”. When the token packet is transmitted (YES in step S403), the state transitions from the IDLE state to the IN transaction (step S600), and when the “OUT” token packet is transmitted (YES in step S404), the state transitions from the IDLE state to the OUT transaction. A transition is made (step S700), and a “PING” token packet is transmitted (YES in step S405), and a transition is made from the IDLE state to a PING transaction (step S800).
As shown in FIG. 5, when a transition is made to a SETUP transaction and a SETUP transaction operation is started (step S500), the state machine 102 indicates that both TxValid and TxReady, which are signals output from the SIE 12 to the PHY 11, are “High”. Alternatively, when “1”, it is determined that DataIN “7: 0” is valid (YES in step S501), and the content of DataIN “7: 0” returned from the device side to the host side is “ACK” handshake. It is determined whether or not there is (step S502). If “ACK”, the SETUP flag is set to “0” (YES in step S502).

  If the content of DataIN “7: 0” is not “ACK” handshake (NO in step S502), the SETUP flag is set to “0”, the error flag is set to “1”, and the error counter 104 counts the error. The value is counted up by +1.

  In addition, after the transition to the SETUP transaction, an “ACK” handshake is responded from the device side to the host side, thereby transitioning from the SETUP transaction to the IDLE state (step S503).

  As shown in FIG. 6, when the transition to the IN transaction is started and the IN transaction operation is started (step S600), the state machine 102 indicates that both TxValid and TxReady, which are signals output from the SIE 12 to the PHY 11, are “ It is determined that DataIN “7: 0” is valid when “High” or “1” (YES in step S601), and the content of DataIN “7: 0” returned from the device side to the host side is “NAK” or It is determined whether or not each “STALL” handshake, and each flag and counter value is counted up based on the contents of each handshake.

  Specifically, when the content of DataIN “7: 0” returned from the device side to the host side is “NAK” handshake (YES in step S603), the state machine 102 sets the IN flag to “0”. Then, after the count value of NAK (IN) is incremented by +1 by the transaction counter 103, the transaction transits from the IN transaction to the IDLE state (step S606).

  If the content of DataIN “7: 0” is “STALL” handshake (YES in step S604), the state machine 102 sets the IN flag to “0”, and the transaction counter 103 counts STALL (IN). After the value is incremented by +1, the IN transaction transits to the IDLE state (step S606).

  In addition, the state machine 102 determines that DataOUT “7: 0” is valid when both RxActive and RxValid, which are signals output from the PHY 11 to the SIE 12, are “High” or “1” (YES in Step S602). ) Each flag and counter value are counted up based on the contents of DataOUT “7: 0” transmitted from the host side to the device side.

  Specifically, when the content of DataOUT “7: 0” is an “ACK” handshake (YES in step S605), the IN flag is set to “0” by the state machine 102, and then the IDLE state from the IN transaction. (Step S606).

  If the content of DataOUT “7: 0” is not the “ACK” handshake (NO in step S605), the state machine 102 sets the IN flag to “0”, the error flag to “1”, and the error counter 104 Thus, after the count value of the error count is incremented by +1, the transition from the IN transaction to the IDLE state is made (step S606).

  As shown in FIG. 7, when the transition is made to the OUT transaction, the OUT transaction operation is started (step S700), and the state machine 102 has both TxValid and TxReady, which are signals output from the PHY 11 to the SIE 12, being “High” or “ When “1”, it is determined that DataIN “7: 0” is valid (YES in step S701), and each flag and counter value is counted based on the content of DataIN “7: 0” returned from the device side to the host side. Up.

  Specifically, when the content of DataIN “7: 0” transmitted from the host side to the device side is “ACK” handshake (YES in step S702), the state machine 102 sets the OUT flag to “0”. Then, the transition from the OUT transaction to the IDLE state is made (step S706).

  If the content of DataIN “7: 0” is “STALL” handshake (YES in step S703), the state machine 102 sets the OUT flag to “0” and the transaction counter 103 counts the STALL (OUT). After the value is counted up by +1, the transition from the OUT transaction to the IDLE state is made (step S706).

  If the content of DataIN “7: 0” is a “NAK” handshake (YES in step S704), the state machine 102 sets the OUT flag to “0” and the transaction counter 103 counts the NAK (OUT). After the value is counted up by +1, the transition from the OUT transaction to the IDLE state is made (step S706).

  When the content of DataIN “7: 0” is “NYET” handshake (YES in step S705), the state machine 102 sets the OUT flag to “0” and the transaction counter 103 counts NYET (OUT). After the value is counted up by +1, the transition from the OUT transaction to the IDLE state is made (step S706).

  If the content of DataIN “7: 0” is not any of “ACK”, “STALL”, “NAK”, and “NYET” handshake (NO in step S705), the state machine 102 sets the OUT flag to “ “0” and the error flag are set to “1”, and the error counter value is incremented by +1 by the error counter 104. Then, the OUT transaction transits to the IDLE state (step S706).

  As shown in FIG. 8, when a transition to a PING transaction starts and the operation of the PING transaction is started (step S800), the state machine 102 indicates that both TxValid and TxReady, which are signals output from the PHY11 to the SIE12, are “High”. "Or" 1 ", each flag and counter value are counted up based on the contents of DataIN" 7: 0 ".

  Specifically, when the content of DataIN “7: 0” transmitted from the host side to the device side is “ACK” (YES in step S801), the PING flag is set to “0” by the state machine 10 Thereafter, the PING transaction makes a transition to the IDLE state (step S805).

  If the content of DataIN “7: 0” is “STALL” handshake (YES in step S802), the state machine 102 sets the PING flag to “0” and the transaction counter 103 counts the STALL (PING). After the value is incremented by +1, the PING transaction transits to the IDLE state (step S805).

  If the content of DataIN “7: 0” is a “NAK” handshake (YES in step S804), the state machine 102 sets the PING flag to “0” and the transaction counter 103 counts the NAK (PING). After the value is incremented by +1, the PING transaction transits to the IDLE state (step S805).

  If the content of DataIN “7: 0” is not any of “ACK”, “STALL”, and “NAK” handshake (NO in step S804), the state machine 102 sets the PING flag to “0” and an error. After the flag is set to “1” and the count value of the error counter 104 is incremented by +1 by the transaction counter 103, the PING transaction is changed to the IDLE state (step S805).

  As described above, the USB test monitor circuit 100 according to the present invention uses the existing measuring instrument (logic analyzer) for parallel I / O when performing USB operation evaluation of the printer controller ASIC 10 incorporating the PHY 11 and SIE 12. Transactions flowing through the USB bus can be monitored by measuring the interface signal output to F at the printer controller ASIC 10 terminal.

  In addition to the UTMI signal that is an interface signal between the PHY 11 and the SIE 12, by outputting an identification flag signal for identifying each transaction, it is possible to easily confirm the type of the transaction that is operating.

1 is a block diagram schematically showing an example of a printer controller 1 provided with a USB test monitor circuit 100 according to the present invention. PID list 200 showing an example of PID types The figure which shows an example of the flag signal and data bus signal which the state machine 102 produces | generates at the time of a SETUP transaction operation | movement A flow chart showing an operation in which the state machine 102 recognizes a transaction type and transitions to a transaction operation for each type. Flow chart of SETUP transaction operation Flow chart of IN transaction operation OUT transaction flow diagram Flow chart of PING transaction operation

Explanation of symbols

1 Printer Controller 2 USB Host 10 Printer Controller ASIC (= Application Specific Integrated Circuit)
11 PHY (physical layer)
12 SIE (Serial Interface Engine)
13 DMA (= Direct Memory Access) Control Unit 14 Parallel Control Unit 15 Interrupt Control Unit 16 Arbitration Unit 17 Test Register 20 CPU (Central Processing Unit)
30 memory (transmission / reception buffer)
40 Parallel I / F (= Interface: interface)
100 USB Test Monitor Circuit 101 Data Generation Unit 102 State Machine 103 Transaction Counter 104 Error Counter 105 Operation Selection Unit 106 First Selector 107 Second Selector 108 Third Selector 200 PID List 301 Clock Signal 302 RxActive Signal 303 DataOut “7: 0” ”Signal 304 RxValid signal 305 TxValid signal 306 DataIn“ 7: 0 ”signal 307 TxReady signal 308 SETUP flag signal 309a Data signal (parallel I / F)
309b Data signal (parallel I / F)
310 SETUP transaction counter signal

Claims (4)

First interface signal acquisition means for acquiring a first interface signal between a physical layer that transmits and receives a differential signal flowing through the USB bus and a serial interface engine that performs communication of the physical layer;
Transaction identifying means for identifying a differential signal transaction flowing through the USB bus based on the first interface signal;
Data signal generating means for generating a data signal flowing through the USB bus based on the first interface signal;
A USB test monitor circuit comprising: first output means for outputting in parallel the transaction identification result identified by the transaction identification means and the data signal generated by the first interface signal acquisition means. The transaction identification means includes
The flag signal for identifying the transaction of the differential signal flowing through the USB bus by identifying the packet identifier included in the first interface signal and identifying the type of the transaction is output. The USB test monitor circuit described. The USB test monitor circuit according to claim 2, further comprising a transaction counter that counts the number of occurrences of each type of transaction identified by the transaction identification unit based on the flag signal. Second interface signal acquisition means for acquiring a second interface signal between the serial interface engine and the DMA control circuit;
The USB test monitor circuit according to claim 1, further comprising: second output means for outputting the second interface signal as parallel data.

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