JP2007026184A - Function-processing electronic circuit and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for reducing a management load on a function-processing block of a CPU in a system having a CPU and a plurality of function-processing blocks to realize efficient load distribution in the system. <P>SOLUTION: A system has a plurality of DMACs, a plurality of function-processing blocks, a switching circuit which optionally connects them, and a function-processing resource management mechanism which manages the resources of the DMACs, the function-processing blocks and the switching circuit. The function-processing resource management mechanism is provided with; a means which designates function-processing to be executed, an original data pointer, a result data pointer or the like; a means which allocates resources to each DMAC, each function-processing block and the switching circuit based on the designation; and a processing setting means. By this, loads on the resource management of a CPU and block management, which are the main management, are relieved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic circuit having a DMA controller (hereinafter referred to as DMAC), and more particularly to an electronic circuit realized using a plurality of function processing hardware and a DMAC.

  In an embedded system, a hardware function processing block that implements specific functions in addition to the CPU, memory control circuit, and interface circuit is installed inside the system, thereby reducing software processing and hardware processing. It is possible to speed up. In addition, by installing hardware functional processing blocks, it becomes possible to perform processing resource load distribution by parallelizing processing and pipelining.

  The function processing block of hardware generally implements a function by performing specific signal processing provided for data stored in a memory and holding the result data in the memory again. In other words, the original data in the memory is taken in by the DMAC, the data is processed by the circuit in the function processing block, and the result data after processing is written back to the memory by the DMAC. It is realized with. For example, the functional processing block (101) for performing JEPG decoding shown in FIG. 1 is composed of two sets of DMAC (102, 103) and JEPG decoding block (104). The read DMAC (102) that reads data from one memory reads the encoded JPEG data stored in the memory (105), and inputs the read data to the JPEG decoding circuit (104). The JPEG decoding circuit (104) decodes the input JPEG data and outputs the resulting decoded data. The decoded data output by the JPEG decoding circuit (104) is input to the Write DMAC (103) for writing the data to the other memory, and the decoded data that is the result data is transferred to the memory (105) by the DMAC. The JPEG decoding function is realized by writing back to the memory.

  In many systems, in order to realize a plurality of functions, a plurality of types of function processing blocks are mounted by hardware to realize high-speed processing of functions and parallel processing. Figure 2 shows an example of the system. The system includes a CPU (201) that controls the entire system, a memory device control circuit (202) that controls a memory device such as a main memory, an interface circuit (203) that controls an external interface such as a network, and a plurality of It has function processing blocks (204 to 209), each function processing block has a DMAC for reading and writing data from the memory device and a function processing circuit for realizing a predetermined function, and JPEG encoding Functional processing such as decryption and encryption processing is realized as a block. For example, when the system realizes the function A processing, the function processing block reads the original data from the memory by activating the DMAC of the function processing block A (204) and the function processing circuit A from the CPU (201), and the function processing This is realized by processing in the circuit A and writing the result data in the memory by the DMAC. By performing this setting for each function processing block from the CPU (201), the system can execute each function process in parallel. By implementing the processing realized by the system in hardware as a function processing block in this way, it is possible to realize high-speed processing by hardware. When a plurality of JPEG encoding processes are executed in parallel in the system, a plurality of function processing blocks for implementing the same function processing are configured by mounting JPEG encoding processing circuits on the function processing circuits A and B, respectively. Also, a functional processing block that performs processing to decode JPEG data encoded for each rectangle as a continuous image and a functional processing block that performs processing to decode JPEG data encoded as one continuous image as an image for each rectangle. In the system that requires the same JPEG decoding processing circuit for each of the function processing circuits C and D, the reading DMAC of one function processing block is fetched for each rectangle, and the writing DMAC is continuously imaged The two functional processing systems are realized by adopting a configuration in which the data is written in the memory, the reading DMAC of the other functional processing block is taken in as a continuous image, and the writing DMAC is written in the memory as a rectangular image.

  As described above, functional processing that requires high-speed processing in the system is implemented by hardware as functional processing blocks necessary for the system, and the performance required by the system is realized.

Moreover, as a prior art example, patent document 1 and patent document 2 can be mention | raise | lifted, for example.
JP 05-274249 A JP 09-223103 A

  However, while each function processing block transfers data from memory, the maximum transfer speed of the connected bus and memory is finite, so even if multiple function processing blocks are installed and DMAC is built in, Since the maximum processing speed is limited by the bus transfer speed and the memory transfer speed, an excessive DMAC that cannot operate simultaneously as the entire system is built in. Also, a functional processing block that performs processing to decode JPEG data encoded for each rectangle as a continuous image and a functional processing that performs processing to decode JPEG data encoded as one continuous image as an image for each rectangle. In a system that has one block at a time, for example, if you want to operate in parallel two processes for decoding JPEG data encoded for each rectangle as a continuous image, it is necessary to implement two such equal processing blocks If only one is implemented, functional processing is performed even if the JPEG decoding circuit of the functional processing block that performs processing to decode JPEG data encoded as a continuous image as an image for each block is unused. Since the function is limited as a block, it cannot be used as a resource, and the former two function processing blocks are implemented. If the hardware scale is increased and only one process is performed, hardware resources cannot be used effectively.

  In a system having a plurality of functional processing blocks, the main processor generally needs to manage the operation status of each block, availability in time series, setting of each block, and the like. However, due to recent advances in semiconductor technology, the hardware installed in the system increases exponentially, and the load on the CPU for managing each function processing block and various settings has increased. This limits the use of the processor for processing, or the processing speed of the processor decreases, limiting the performance of the system. For example, when a certain process is realized by reading DMAC, writing DMAC, and function processing block, the main processor sets each DMAC and function processing block, and receives an end notification from the DMAC or function processing block. When the function of the system is increased and a plurality of function processes implemented by hardware are operated in parallel, it is necessary to manage hardware resources and perform frequent interrupt processes for each function process. Originally, functional processing is realized by hardware, so that processing speed can be increased and other processing can be performed by software to improve overall system performance. However, the performance of the processor is significantly limited for the reasons described above, and the performance of the software executed by the processor is degraded.

  The present invention has been made in view of the above problems, and in a system having a CPU and a plurality of functional processing blocks, provides means for reducing the management load of the functional processing blocks of the CPU, and provides an efficient load in the system. Distribute will be realized.

The DMA controller comprising at least one CPU, a plurality of function processing blocks, a plurality of DMA controllers, a memory device control circuit, and a switch circuit that can be arbitrarily combined with the function processing blocks and the DMA controller. Is connected to a memory control circuit, and the other is connected to an arbitrary function processing block via the switch circuit. The switch circuit has a switch switching designation input signal or a switch switching designation register, and is designated. In an electronic circuit having means for switching the combination of the functional processing block and the DMA controller according to
Has a function processing management mechanism,
Function processing designation means;
The function processing management mechanism is:
The switch circuit control means;
The DMA controller control means;
The function processing block control means;
A function processing end determination means;
A function processing end notification means;
An electronic circuit comprising:

  According to the conventional method, in a system with multiple DMACs and multiple functional processing blocks, the main CPU performs resource management for each DMAC and each functional processing block, and an interrupt is generated by an end notification from each DMAC and functional processing block And it put a big load on the CPU.

  According to the present invention, in a system having a plurality of DMACs and a plurality of function processing blocks, it is not necessary to perform resource management of each DMAC or function processing block that has been conventionally performed by a CPU that mainly starts processing, and processing to be executed Only the address space to be processed is specified, the dedicated function processing management control mechanism performs each setting and startup, and the entire function processing is notified collectively, so the function processing block management and control of the main CPU are performed. The load can be reduced, and the performance of processing performed by other CPUs can be improved.

  4 includes a CPU, a plurality of function processing blocks, a plurality of DMA controllers, a memory device control circuit, and a switch circuit that can be arbitrarily combined with the function processing blocks and the DMA controller. One of the controllers is connected to a memory control circuit, and the other is connected to an arbitrary function processing block via the switch circuit. The switch circuit has a switch switching designation input signal or a switch switching designation register. An electronic circuit having means for switching the combination of the functional processing block and the DMA controller according to the designation has the following configuration.

  That is, in this system, the CPU (303), the memory control circuit (302), the memory device (301) connected thereto, two sets of ReadDMAC (401,402), two sets of WriteDMAC (403,404), and these devices are connected. System bus (306), six function processing blocks (312 to 317), and a data transfer switch (405) for connecting each DMAC to the function processing block.

  The function processing circuit included in the function processing block (312 to 317) is a circuit that performs arbitrary data signal processing such as JPEG encoding and decoding, performs signal processing provided for input data, and outputs result data. Output. Data subjected to signal processing in the function processing circuit is input from the data transfer connection switch (405) via the data input IF, and signal processing result data is output to the data transfer connection switch (405) via the data output IF. Is done.

  ReadDMAC (401, 402) has a DMAC setting register that sets the DMAC operation, a register that specifies the memory address of the data to be read, a register that specifies the data transfer amount, a rectangular transfer width register, a rectangular transfer address offset register, and a DMAC transfer It consists of setting registers that perform DMAC transfer, such as registers to be activated. The contents of the setting register are arbitrary. The ReadDMA control circuit issues a data read transfer request to the memory via the system bus (306) when instructed to start DMAC transfer according to the settings of the address, transfer amount, etc. specified in the setting register group. Read data on device (301). The read data is output to the data transfer switch (405) via the data output IF. In addition, by specifying the rectangular transfer width register and the rectangular transfer address offset register, the rectangular transfer in the memory space is performed, the rectangular transfer width is set arbitrarily, and the rectangular transfer address offset register value is set to 0, continuous transfer is possible It is.

  On the other hand, WriteDMAC (403, 404) has a DMAC setting register that sets the DMAC operation, such as a register that specifies the memory address of the data to be written, a rectangular transfer width register, a rectangular transfer address offset register, a register that starts DMAC transfer, etc. It consists of a set register group that performs transfer. The contents of the setting register are arbitrary. WriteDMAC (403, 404) receives data from the data transfer switch (405) via the data input IF. The WriteDMA control circuit is instructed to start DMAC transfer according to the setting of the address specified in the setting register group, and when data is input via the data input IF, it is sent to the memory via the system bus (306). A data write transfer request is issued and data is written on the memory device (301). In addition, by specifying the rectangular transfer width register and the rectangular transfer address offset register, the rectangular transfer in the memory space is performed, the rectangular transfer width is set arbitrarily, and the rectangular transfer address offset register value is set to 0, continuous transfer is possible It is.

  Data from the data output IF of ReadDMAC (401, 402) is connected to one data input IF of the function processing blocks (312 to 317) by the data read switch in the data transfer connection switch (405), and the function processing block The data output from the data output IF (312 to 317) is connected to the data input IF of WriteDMAC (403, 404) by the data write switch in the data transfer connection switch (405). The data transfer protocol for connecting ReadDMAC (401, 402) and the function processing blocks (312 to 317) and the data transfer protocol for connecting the function processing block (312 to 317) and WriteDMAC (403, 404) are arbitrary. FIG. 5 shows a signal waveform example of this data transfer protocol. In this example, the data input IF issues the READY signal in the cycle immediately before the receivable cycle, the data output IF issues the DATA_VALID signal and the DATA signal in the next cycle after the READY signal is issued, The DATA_END signal is issued simultaneously when the final data is transferred. The signal waveform example in FIG. 5 is an example of 8-beat data transfer (8 data transfers). When a READY signal is issued from the data input interface in cycle 1, the data output IF outputs a DATA_VALID signal and valid DATA from cycle 2. In cycle 3, the data input IF cancels the READY signal because it cannot take in the data of the next cycle. On the other hand, since the READY signal of cycle 2 is issued, the data output IF transfers valid data. In cycle 4, the valid data transfer is not performed in response to the release of the READY signal in cycle 3, and the valid transfer of the third beat is performed in cycle 5 because the READY signal is issued again in cycle 4. In this data transfer protocol, the signal to the next data input IF after the READY signal is issued is Don't Care. This is the last data transfer cycle of the eighth beat in cycle 12, and the DATA_END signal is transferred in the same cycle as the last data transfer, and the data transfer is completed.

  As shown in FIG. 6, the data transfer connection switch (405) includes a data read switch (601) and a data write switch (602), and a read data transfer destination designation signal for designating the data transfer destination of each ReadDMAC (401, 402). (603) and a read data transfer source specifying signal (604) for specifying the data transfer source of each function processing block (312 to 317), and a write data transfer source specifying signal for specifying the data transfer source of each WriteDMAC (403, 404) ( 606) and a write data transfer destination designation signal (605) for designating the result data transfer destination of each function processing block (312 to 317). Each transfer designation signal (603 to 606) is set by a register (not shown) in the data transfer connection switch.

  FIG. 7 shows a configuration diagram of the data read switch (601). Corresponding to each ReadDMAC (401, 402), the data transfer destination changeover switch (701) for the ReadDMAC output signal, the input changeover MUX (702) for the ReadDMAC input signal, and the connected function processing blocks (312 to 317) A transfer source switching MUX (703) for the output signal and an input switching switch (704) for the input signal from the function processing block are configured. Each switch and MUX switching signal includes a read data transfer destination designation signal (603) and a read data transfer source designation signal (604). The read data transfer destination designation signal (603) is a signal for selecting function processing blocks (312 to 317) that are data transfer destinations of ReadDMAC. In this example, it is realized by a 3-bit signal as a signal for selecting six function processing blocks. The read data transfer source selection signal (604) is a signal for designating ReadDMAC (401, 402) as a transfer source on the function processing block (312 to 317) side. In this example, it is realized by a 1-bit signal as a signal for selecting two ReadDMACs.

  Data transfer destination changeover switch (701), input changeover MUX (702), and read data transfer destination designation signal (603) are implemented for the number of connected ReadDMACs, and this example corresponds to ReadDMAC-1 / 2 (401, 402). 2 pairs are included. Transfer source change MUX (703), input changeover switch (704), and read data transfer source selection signal (604) are implemented for the number of function processing blocks to be connected. In this example, function processing block -A / B / C / Six sets are included corresponding to D / E / F (312 to 317).

  The operation of the read data switch (601) is described below. The data transfer destination changeover switch (701) receives the output signal from the connected ReadDMAC and the read data transfer destination designation signal (603) as inputs, and has outputs for the number of function processing blocks connected as output. It has two output signal sets. The data transfer changeover switch (701) connects the output signal and the input signal to the designated function processing block according to the signal value of the read data transfer destination designation signal (603). The output signal to the function processing block that is not specified by the read data transfer destination specifying signal (603) is output as an invalid signal. Specifically, a signal obtained by canceling the DATA_VALID signal of the data transfer signal is output. By the above mechanism, the output signal to the function processing block selected by the read data transfer destination designation signal (603) is output as it is from the data output IF of ReadDMAC by the switch operation, and the function processing block that is out of selection The output signal to becomes invalid data, that is, a non-transfer state. Data output for each function processing block of the data transfer destination changeover switch (701) is connected to the transfer source changeover MUX (703). The transfer source switching MUX (703) inputs the output signals (two sets in this example) and read data transfer source selection signal (604) of the data transfer switch (701) corresponding to each ReadDMAC, and the data input of the function processing block Has data output connected to IF. The data output transfer source change-over MUX (703) determines the ReadDMAC of the transfer source based on the signal value of the read data transfer source designation signal (604) and outputs the input signal from the corresponding ReadDMAC as an output signal to the function processing block . By the above mechanism, the output data of the data transfer changeover switch (701) corresponding to each ReadDMAC becomes the input of the transfer source changeover MUX (703), and the ReadDMAC designated as the transfer source by the read data transfer source selection signal (604) Is input as an input signal of the function processing block. In contrast, the input changeover switch (704) and input changeover MUX (702) are switch mechanisms for the READY signal transmitted from the function processing block to the ReadDMAC, and the READY signal from the function processing block is transmitted from the input changeover switch (704). ReadDMAC is selected by the value of the read data transfer source selection signal (604), the READY signal for the selected ReadDMAC is transmitted as it is from the function processing block, and the READY signal for ReadDMAC that has been selected is released Transferred in state. The input switch MUX (702) receives the output of the input switch (704) of each function processing block as input, selects the READY signal issue source based on the signal value of the read data transfer destination designation signal (603), and sends it to ReadDMAC READY signal is transmitted.

  FIG. 8 shows a configuration diagram of the data write switch (602). Corresponding to each WriteDMAC (403, 404), the data transfer source changeover switch (802) for the input signal of WriteDMAC, the output changeover MUX (801) for the output signal of WriteDMAC, and each function processing block (312 to 317) connected A transfer destination switching MUX (804) for the output signal and an output switching switch (803) for the input signal from the function processing block are configured. A write data transfer destination designation signal (606) and a write data transfer source designation signal (605) are provided as switching signals for each switch and MUX. The write data transfer source designation signal (605) is a signal for selecting the function processing blocks (312 to 317) that are the data transfer source of WriteDMAC. In this example, it is realized by a 3-bit signal as a signal for selecting six function processing blocks. The write data transfer destination selection signal (606) is a signal that designates WriteDMAC (403, 404) as a transfer source on the function processing block (312 to 317) side. In this example, it is realized by a 1-bit signal as a signal for selecting two WriteDMACs.

  Data transfer source changeover switch (802), output changeover MUX (801), and write data transfer source designation signal (605) are implemented for the number of connected WriteDMACs, and this example corresponds to WriteDMAC-1 / 2 (403, 404). 2 pairs are included. The transfer destination switching MUX (804), output changeover switch (803), and write data transfer destination selection signal (606) are implemented as many as the number of function processing blocks to be connected. In this example, the function processing block -A / B / C / Six sets are included corresponding to D / E / F (312 to 317).

  The operation of the write data switch (602) is described below. The data transfer destination changeover switch (803) receives the output signal from the function processing block to be connected and the write data transfer destination designation signal (606) as inputs, and has outputs for the number of WriteDMACs connected as outputs. It has two output signal sets. The data transfer destination changeover switch (803) connects the output signal and the input signal to the designated WriteDMAC according to the signal value of the write data transfer destination designation signal (606). An output signal to WriteDMAC that is not designated by the write data transfer destination designation signal (606) is output as an invalid signal. Specifically, a signal obtained by canceling the DATA_VALID signal of the data transfer signal is output. With the above mechanism, the output signal for WriteDMAC selected by the write data transfer destination designation signal (606) is output as it is from the data output IF of the function processing block by the switch operation, and is sent to the WriteDMAC that is out of selection. The output signal becomes invalid data, that is, a non-transfer state. The data output for each write of the data transfer destination changeover switch (803) is connected to the transfer source changeover MUX (801). The transfer source switching MUX (801) is the input of the output signal (six sets in this example) and the write data transfer source selection signal (605) of the data transfer source changeover switch (803) corresponding to each function processing block, and the data of WriteDMAC Has a data output connected to the input IF. The data output transfer source switching MUX (801) discriminates the function processing block of the transfer source from the signal value of the write data transfer source designation signal (605) and outputs the input signal from the corresponding function processing block as an output signal to WriteDMAC To do. With the above mechanism, the output data of the data transfer changeover switch (803) corresponding to each function processing block becomes the input of the transfer source changeover MUX (801) and is designated as the transfer source by the write data transfer source selection signal (605). An input signal from the function processing block is output as an input signal of WriteDMAC. On the other hand, the output changeover switch (803) and the output changeover MUX (801) are switch mechanisms for the READY signal transmitted from the WriteDMAC to the function processing block, and the function for transmitting the READY signal from the WriteDMAC from the output changeover switch (802). The processing block is selected by the value of the write data transfer source selection signal (605), the READY signal for the selected function processing block is transmitted as it is from the WriteDMAC, and the READY signal for the selected function processing block is released. It is transferred in the state. The output switch MUX (804) receives the output of the output switch (802) of each WriteDMAC, selects the issuer of the READY signal according to the signal value of the write data transfer source designation signal (605), and sends it to the function processing block READY signal is transmitted.

  With the above switch configuration, the connection between the ReadDMAC (401, 402), WriteDMAC (403, 404) and the data of each function processing block (312 to 317) is established by the switch switching designation signal (603 to 606), and the data in each combination Transfer is possible.

  As an embodiment of the present invention applied to the above configuration, a system shown in FIG. 9 will be described as an example. This system adds a function processing management control circuit (901) to the system shown in FIG. 4, and controls the function processing specifying means (1006) and the switch circuit as an interface for which the function processing is mainly specified from the CPU (303). Control circuit (1002, 1004).

  The configuration of the function processing management control circuit (901) is shown in FIG. The function processing management control circuit (901) has function processing designation means (1006), and receives designation of signal processing realized by the configuration of the function processing block of the DMAC. In this embodiment, the function processing circuit of the function processing block-A / B (312,313) is a JPEG encoding circuit, and the function processing circuit of the function processing block-C / D (314,315) is a JPEG decoding circuit, as described in the previous example. The function processing circuit of the function processing block-E (316) is a resolution conversion circuit, and the function processing circuit of the function processing block-F (317) is a color space conversion circuit. The function processing designation means has a function processing designation register group as shown in FIG. 3, and includes at least a function processing field register (1102), an original data start address register (1103), an original data size register (1104), a result It has a data start address register (1105), each function processing parameter register (1106), and a function processing start flag register (1101). The function processing specification register group has the number of sets of ReadDMAC (401, 402) or WriteDMAC (403, 404), and in this example, has two sets. The registers provided in the function processing designation register group have register fields provided in each ReadDMAC (401, 402) and each WriteDMAC (403, 404), and each DMAC as described in the previous example has a block transfer function. In the case of having, a rectangular transfer width register and a rectangular transfer address offset register are mounted in the function processing designation register group. The function processing parameter register (1106) has register groups for the types of function processing blocks (312 to 317), and has register fields set in the respective function processing blocks. In the present embodiment, six function processing blocks (312 to 317) have four types of function processing blocks, JPEG encoding, JPEG decoding, resolution conversion, color space conversion, and the function processing parameter register (1106). ) Implements JPEG encoding parameters, JPEG decoding parameters, resolution conversion parameters, and color space conversion parameters as shown in FIG.

  The CPU (303) issues access to the function processing designation register group according to the processing to be performed. The CPU obtains the start address and data size of the original data for signal processing on the memory as the original data start address register (1103), the original data size register (1104), and the start address on the memory for storing the data after signal processing. Write to the data start address, etc. (1105), and add 2 bits to the function processing field register (1102), “00” for JPEG encoding, “01” for JPEG decoding, and for resolution conversion “10”, when color space conversion is performed, “11” is specified, and the function processing is specified by setting the function processing start flag (1101) and issuing access.

  The resource determination register (1002) is composed of a ReadDMAC resource flag register, a WriteDMAC resource flag register, and a function processing block resource flag register, set by the function processing specifying means (1006), and released by an end notification from each resource. . The field of each resource flag register has fields corresponding to the number of each resource, and 1 is set when the corresponding resource is in use, and 0 is set when the resource is not used. In the configuration of this embodiment, the ReadDMAC resource flag register and the WriteDMAC resource flag register have two fields, and the function processing block resource flag register has the number of function processing blocks, that is, six fields. When the function processing designation means receives the function processing designation in the above process from the CPU and the start flag is set, the function processing designation means (1006) refers to the resource judgment register (1002) and is necessary for the function processing. Determine whether ReadDMAC, WriteDMAC and functional processing blocks are available.

  For example, when a JPEG decoding process is specified, the ReadDMAC resource flag register and the WriteDMAC resource flag register are accessed, and if there is an unused DMAC, it is used for JPEG decoding. Set and secure DMAC resources, access the function processing block resource flag register, refer to the JPEG decoding field, and if there is an unused JPEG decoding block, set the corresponding field to 1 to secure the resource . When each resource is in use, the function processing specifying means (1006) secures the resource after waiting for each resource to be unused, that is, the corresponding resource flag is cleared.

  After securing the resource in the resource determination register (1006), the function processing designation unit (1006) accesses the switch selection mechanism (1004). The switch selection mechanism has a register for setting the connection of the switch circuit (405). In each field, a read data transfer destination designation signal (603), a read data transfer source designation signal (604), and a write data transfer source designation A signal (606) and a write data transfer destination designation signal (605) are generated. The read data transfer destination designation register is 2 sets, which is the number of ReadDMAC, the read data transfer source designation register is the number of function processing blocks, 6 sets, the write data transfer destination designation register is the number of function processing blocks, 6 sets, Two sets of data transfer source designation registers, which are the number of WriteDMACs, are mounted and correspond to the respective DMAC and function processing blocks.

  In the JPEG decoding process, if the resources secured via the resource determination register (1006) are ReadDMAC-2, WriteDMAC-1, and function processing block-C, the register in the switch selection mechanism (1004) reads ReadDMAC-2 And function processing block-C data input IF and WriteDMAC-1 and function processing block-C data output IF in order to establish a connection between the read data transfer destination designation register corresponding to ReadDMAC-2, function processing block-C The DMAC function processing block switch connection is set in the corresponding read data transfer source designation register, write data transfer destination designation register, and write data transfer source designation register corresponding to WriteDMAC-1. The function processing specifying means (1006) also performs setting for each DMAC and function processing block via the function setting means (1003). Set the original data start address and the original data size specified in the function processing specification means (1006) to the selected ReadDMAC-2 using any method, and register the result data start address to WriteDMAC-1 using any method. Since the function processing field is specified as 01 and JPEG decoding, the JPEG decoding parameters that have been set are set for function processing block-C in any way and all settings are completed. Later, writeDMAC, function processing block, and readDMAC process start are instructed to start data transfer and JPEG decoding process. When the start of processing is instructed, the function processing end determination means (1001) determines the end. The function processing end judging means (1001) has an input interface for processing completion notification from each ReadDMAC, WriteDMAC, function processing block, and the function processing specifying means (1006) performs function processing via the function setting means (1003). When started, it determines the ReadDMAC, WriteDMAC, and function processing block used for the function processing, and waits for an end notification from each block. The end of the function process is confirmed at the end of all the processes. When the end notification from the three blocks is received, the function process end notification means (1005) is activated and an interrupt is given to the CPU that is the process start source. Notify the end.

It is a simple block diagram of a general JPEG decoding processing block This is a system configuration example with multi-function processing hardware It is a conceptual diagram of a function process designation | designated register field. 1 is a block configuration diagram of a system serving as a base of the present embodiment It is a signal waveform diagram which describes a data transfer protocol. It is a circuit simplified block diagram of a data transfer connection switch. It is a circuit simplified block diagram of a read data transfer connection switch. It is a circuit simplified block diagram of a write data transfer connection switch. 5 is a block configuration diagram of an embodiment in which the present invention is applied to the system of FIG. It is a simplified block diagram of a function processing management control circuit.

Explanation of symbols

101 JPEG decoding block
102,401,402 ReadDMAC
103,403,404 WriteDMAC
104 JPEG decoding circuit
105,301 memory devices
201,303 CPU
202,302 Memory control circuit
203 Interface circuit
204 to 209 DMAC-included function processing block
306 System bus
405 Data transfer connection switch
312 to 317 Function processing block
601 Read data transfer connection switch
602 Write data transfer connection switch
603 Read data transfer destination selection signal
604 Read data transfer source selection signal
605 Write data transfer source selection signal
606 Write data transfer destination selection signal
701 Transfer destination selector switch
702 Input switching MUX
703 Transfer source switching MUX
704 Input selector switch
801 Output switching MUX
802 Transfer source selector switch
803 Output selector switch
804 Transfer destination switching MUX
901 Function processing management control circuit
1001 Function processing end judgment means
1002 Resource judgment register
1003 Function setting method
1004 Switch circuit selection mechanism
1005 Function processing end notification means
1006 Function processing specification method
1101 Function processing start flag register
1102 Function processing field register
1103 Original data start address register
1104 Original data size register
1105 Result data start address register
1106 Function processing parameter registers

Claims (2)

The DMA controller comprising at least one CPU, a plurality of function processing blocks, a plurality of DMA controllers, a memory device control circuit, and a switch circuit that can be arbitrarily combined with the function processing blocks and the DMA controller. Is connected to a memory control circuit, and the other is an electronic circuit that can be connected to an arbitrary function processing block via the switch circuit.
Has a function processing management mechanism,
Function processing designation means;
The function processing management mechanism is:
The switch circuit control means;
The DMA controller control means;
The function processing block control means;
A function processing end determination means;
A function processing end notification means;
An electronic circuit comprising:   The electronic circuit according to claim 1, wherein the function processing management mechanism is realized by a CPU.

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