JP2007026070A - Data transfer device, method thereof, and rapid startup method of computer therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer device and a method thereof which perform data transfer to a chipset of a computer. <P>SOLUTION: This data transfer device includes a data transfer control unit 20, a first storage unit 21, and a second storage unit 22. When data is going to be transmitted between a chipset and the first storage unit, the data transfer control unit may determine whether destination can receive all transmitted data or not: if possible, the destination receives all data directly from the chipset; otherwise the destination receives a part of data first, and the second storage unit receives data of remainder beforehand and next transmits the data stored in the second storage unit and the destination receives it after the destination finishes receiving of a part of previous data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus and method, and more particularly to a data transfer apparatus and method between a chipset and a storage device in a computer. The present invention also relates to a computer-initiated rapid method.

  Referring to FIG. 1, this is a schematic diagram of a conventional computer mechanism. The CPU (Central Processing Unit) 70 reads data from the main memory 74 via the Northbridge chipset 71, and is responsible for accessing computer peripherals for the Northbridge chipset 72. 72 can be connected to peripheral devices externally via the PCI interface 721, IDE interface 722, or input / output chip 73. Generally speaking, peripheral devices to which the input / output chip 73 is connected, such as a floppy (registered trademark) disk, keyboard, mouse, and handle, belong to slow transfer. However, peripheral devices belonging to a higher-speed transfer are via a PCI interface 721 or IDE interface 722, for example, a display card connected to the PCI interface 721, an Internet card or a hard disk connected to the IDE interface 722, an optical disk, or the like.

  However, for computers, the hard disk is the main storage device and has the great advantage of storage capacity, however, the data access speed provided is not as great as the main memory 74, so the central processing unit 70 is When transferring large amounts of data, data transfer is limited because the transfer bandwidth provided by the IDE interface 722 is limited, and the hard disk itself belongs to a mechanical access mechanism and cannot provide a satisfactory access speed. In the process, the hard disk is often limited to the fixed and finite bandwidth provided by the IDE interface 722, thereby affecting the work efficiency of the overall computer mechanism. In addition, the hard disk is always used to store data that needs to be started by the computer, and the data access speed of the hard disk that is too slow results in too long a computer startup time.

  The technical problem to be solved by the present invention is to provide a data transfer apparatus and method, which can elastically adjust the transfer bandwidth, avoid the concentration of all data amount in a single storage device and transmit The ability to increase the interface bandwidth improves the data transfer speed and at the same time accelerates the startup speed.

  In order to solve the above-mentioned technical problem, a data transfer device is provided based on a method of the present invention, data transfer with a computer chipset is performed, a first storage device, a second storage device, A data transfer control unit, wherein the data transfer control unit electrically connects the first storage device and the second storage device respectively, and the data transfer control unit provides the chipset and the first storage device. And control the data transfer between the second storage device. Therefore, when the chipset performs data transfer with the first storage device, the chipset or the first storage device may be the data reception method, or the data transfer control unit may Whether or not all data can be received immediately can be determined according to the data reception status. If it is determined that the data can be received, the data transfer control unit controls the data reception method and immediately receives the data. If the data transfer control unit determines that it is impossible, the data transfer control unit first temporarily stores a part of the data to be received by the data receiving method in the second storage device. The data is directly received by the data receiving method, and the data receiving method completes the reception of the data and transmits the data stored in the second storage device so as to be received by the data receiving method.

  The transmission interface between the aforementioned data transfer control unit and the chipset is a PCI-E interface.

  In order to solve the above technical problem, a data transfer method is provided based on another method of the present invention, and data transfer with a computer chipset is performed. Providing a data transfer control unit for transmission to receive to the storage device, receiving the data transmitted by the data transfer control unit from the chipset, and the first transfer device by the data transfer control unit Determine if all data can be received immediately, and if the first storage device can receive all data immediately, the data transfer control unit controls the first storage device directly Receiving the transmitted data and if the first enclosure If the data transfer control unit cannot receive the data, the data transfer control unit first temporarily stores a part of the data to be received by the first storage device in the second storage device and the other part of the data to the first storage device. And the first storage device finishes receiving the other part of the data and transmits the data stored in the second storage device so as to be received by the first storage device. Including.

  According to still another aspect of the present invention, a computer rapid start method is provided, and a data transfer control unit connected between a chipset and a memory is provided, and the data transfer control unit is connected to the chipset and the memory. And the computer boot end information can be stored in the memory and the chip set can read the computer boot information in the memory via the data transfer control unit. This memory needs to provide the power necessary to store data from the standby power supply in the end state, but automatically supplies power from the power supply in the activated state.

  Adopting the data transfer device and method of the present invention, at the time of data transfer between the chipset and the first storage device, the reception rate of the data transfer destination is judged by the data transfer control unit, Part of the transmitted data is elastically adjusted and temporarily stored in the second storage device, and the received data rate at the destination is thus reduced, thus affecting the data transfer efficiency of the entire computer. It does not lead to. In addition, transfer bandwidth can be increased by using a PCI-E interface between the data transfer control unit and the chipset. In addition, the computer startup information is stored in a second storage device, i.e., memory, so that it is not necessary to read the startup information from the hard disk when the computer is started up, and it is read from the memory electrically connected to the data transfer control unit. Can be achieved to accelerate the speed of computer startup.

  The objects, features, and features of the present invention will be described below with reference to the detailed description of the present invention and the accompanying drawings, but the present invention is not limited thereto.

  Reference is made to FIG. 1, which is a system mechanism diagram of a more preferred embodiment of the present invention. The chip set 10 described in the present embodiment provides a south bridge chip set or a north bridge chip set with a PCI-E interface, and the chip set 10 electrically connects the data transfer control unit 20. The transmission interface between the data transfer control unit 20 and the chipset 10 is a PCI-E interface, and the data transfer control unit 20 matches a number of PCI-E channels into one, thus reducing the bandwidth. The width can be increased and the data processing speed can be accelerated, and the data transfer control unit 20 of this embodiment is executed by the chip.

  The data transfer control unit 20 of the present embodiment electrically connects the first storage device 21 and the second storage device 22 respectively, and the chipset 10, the first storage device 21 and the second storage device 22 respectively. Used to control data transfer between, for example, chipset 10 transmits data to first storage device 21, or first storage device 21 receives data to chipset 10 The data transfer control unit 20 can provide a temporary storage space during the data transfer process, i.e., provide a temporary storage space for the data transfer process. It is used to be used to elastically adjust the transfer bandwidth.

  The first storage device 21 of this embodiment may be an IDE, SATA, 1394, or SCSI transmission interface hard disk, but the second storage device 22 of this embodiment has a higher data access speed than the hard disk. It is memory. The data transfer control unit 20 can determine the data reception status at the destination when performing the data transfer control. If the processing speed of the destination does not reach or becomes busy, the processing data is first sent to the second data. The destination can be stored in the storage device 22, for example, a memory, and the destination pointed to by the present embodiment is the chip set 10 or the first storage device 21.

  Accordingly, a hard disk having a large storage capacity and a memory having a high data access speed can be circumscribed via the data transfer control unit 20, and the hard disk and the memory are respectively stored in the first storage device 21 and the second storage device described in the present embodiment. Device 22. Since the second storage device 22 of the present embodiment is a memory, the memory is mounted in a memory slot electrically connected to the data transfer control unit 20, which is expanded on the mother board of the computer. Furthermore, depending on the amount of transmitted data, the first storage device 21 and the second storage device 22 of this embodiment may be designed in multiple pieces, so that the data transfer speed is accelerated.

  Between the chipset 10 of this embodiment and the data transfer control unit 20, the transfer bandwidth using the PCI-E interface, PCI-E × 1 (representing one set of channels) is 250 MB / S, Since the PCI-E plan has various specifications such as x1, x2, x4, x8, x16, x32, etc., the transfer band of PCI-E x16 in full biplex operation mode When the width reaches 8GB / S, it greatly exceeds the data access speed of main memory or hard disk of ordinary computers. Based on this factor, the second storage device 22 of this embodiment can also be designated as the computer startup position from the basic input / output system (BIOS), and the computer startup information is stored in the second storage device 22 in advance, In other words, it can be used for computer rapid startup. In order to ensure that the data stored in the second storage device 22 is not affected by the computer startup, this embodiment provides one spare power supply 23 and supplies it to the second storage device 22 to start the computer. Used when The computer startup information stored in the memory includes multiple startup files, multiple register files, multiple execution files, or multiple end files of the operating system (for example, Windows (registered trademark) system, OS2 system, or Linux system). Alternatively, the computer startup information may be a startup video file.

  Referring to FIG. 3, this is a flowchart of the data transfer of the present invention. This flowchart posts that the data transfer control unit 20 controls to transmit data from the chipset 10 to the first storage device 21 and includes the following steps, but from the chipset 10 to the first storage Starts transmitting data to the device 21 (S301), the data transfer control unit 20 receives the data transmitted by the chipset 10 (S303), and determines whether the first storage device 21 can receive all the data immediately Judgment is made (S305), and the data transfer control unit 20 determines whether one of the data amounts that can be received by the first storage device 21 is larger than the total amount of data transmitted from the chipset 10 to the first storage device 21. to decide.

  If the determined result is affirmative, the first storage device 21 directly receives the data transmitted by the chipset 10 (S307). If the determined result is negative, the data transfer control unit 20 First, a part of the data transmitted by the chipset 10 is temporarily stored in the second storage device 22 (S309), and a part of the remaining other data transmitted by the chipset 10 is stored in the first storage device. When the first storage device 21 finishes receiving data (S313), the data stored in the second storage device 22 is further received by the first storage device 21. (S315).

  Reference is made to FIG. 4, which is a flowchart of another data transfer of the present invention. This flowchart posts that the data transfer control unit 20 controls to transmit data from the first storage device 21 to the chipset 10 and includes the following steps, but from the first storage device 21 to the chip Start transmitting data to the set 10 (S401), the data transfer control unit 20 receives the data transmitted from the first storage device 21 (S403), and whether the chip set 10 can receive all the data immediately Judgment (S405), by the data transfer control unit 20, to determine whether one of the data amount that can be received by the chipset 10 is larger than all the data amount transmitted from the first storage device 21 to the chipset 10, And the chipset 10 is not yet busy.

  If the determined result is affirmative, the chip set 10 directly receives the data transmitted from the first storage device 21 (S407). If the result of the determination is negative, the data transfer control unit 20 first temporarily stores a part of the data transmitted by the first storage device 21 in the second storage device 22 (S409), and A part of the remaining other data transmitted by the storage device 21 of 1 is directly received by the chipset 10 (S411), and when the chipset 10 finishes receiving data (S413), the second storage The data stored in the device 22 is transmitted so as to be received by the chipset 10 (S415).

  Therefore, the data transfer control unit 20 provided in the present embodiment can control the time when data transfer is performed between the chipset 10 and the first storage device 21, and the size of the transmitted data amount For example, when the amount of data transmitted is less than one of the receivable data amounts at the destination, the destination receives the data transfer directly. Conversely, when the amount of data transmitted is larger than one of the data amounts that can be received at the destination, within the processing range of the data amount that can be received at the destination, a part of the data is received first, and the remaining data is preliminarily received. Since the data is stored in the second storage device 22 and the destination receives and processes one of the previous data amounts, the data stored in the second storage device 22 is received again by the destination device. To be transmitted. The speed of data transfer performed between the chipset 10 and the first storage device 21 is further increased through temporary storage of data provided from the second storage device 22, for example, installation of a cache memory. I can do it.

  Referring to FIG. 5, this is a flowchart of the computer on / off operation of the present invention. Computer startup information can be stored in the second storage device 22 in advance, so that when the computer is started up, the chipset 10 reads the data in the second storage device 22 via the data transfer control unit 20 (S501), and the computer The necessary data for startup can be quickly acquired, and the startup state is entered based on the computer startup information read by the computer (S503), and the computer startup method provided by this embodiment is significantly more than traditional startup. When the startup data from the hard disk gets faster and the computer shuts down or attempts to enter sleep mode, the computer startup information is first stored in the second storage device (S505). Sometimes read computer startup information directly from the second enclosure 22 It is subjected to.

  Therefore, the present invention can provide a completely different design from the prior art by the above-described techniques, and can improve the overall use value, and has not yet appeared in publications or used publicly before the application. Rather, it already conforms to the requirements of the invention patent, and hereby file an application for an invention patent by patent law.

  However, the above-mentioned drawings and explanations are only examples of the present invention, and those skilled in the art can make various other improvements based on the above-mentioned explanations, and these changes still remain in the present invention. It belongs to the spirit of the invention and the following limited claims.

It is a conventional computer mechanism schematic diagram. It is a system mechanism diagram of a more preferred embodiment of the present invention. It is a flowchart of the data transfer of this invention. It is a flowchart of another data transfer of the present invention. It is a flowchart of computer on / off operation of this invention.

Explanation of symbols

10 chipsets
20 Data transfer control unit
21 First enclosure
22 Second enclosure
23 Standby power
70 CPU
71 Northbridge chipset
72 Northbridge chipset
73 I / O chip
74 Main memory
721 PCI interface
722 IDE interface

Claims (10)

A data transfer device for transferring data to and from a computer chipset,
A first enclosure;
A second enclosure;
The first storage device and the second storage device are electrically connected to each other, and used to control data transfer between the chipset, the first storage device, and the second storage device. Including a data transfer control unit,
When performing data transfer between the chipset and the first storage device, the data receiving control is one of the chipset and the first storage device, and the data transfer control unit Can determine whether or not all data can be received immediately according to the data reception status of the person receiving the data. If it is determined that the data is received, the data transfer control unit controls the data receiving method and immediately If the data transfer control unit receives the data but determines that it is impossible, the data transfer control unit first temporarily stores a part of the data to be received by the data receiving method in the second storage device. The other part of the data is directly received by the data receiving method, and the data receiving method finishes receiving the data, Data Transfer device according to claim the data stored in the second storage device to transmit to receive in the data receiving side.   2. The data transfer device according to claim 1, wherein the first storage device is a hard disk, and the second storage device is a memory.   2. The data transfer device according to claim 1, wherein a transmission interface between the data transfer control unit and the chipset is a PCI-E (PCI-Express) interface. A data transfer method for transferring data to and from a computer chipset,
Providing a data transfer control unit for controlling the chipset and transmitting data to be received by the first storage device;
The data transfer control unit receives the data transmitted by the chipset,
The data transfer control unit determines whether the first storage device can receive all data immediately;
If the first storage device can receive all data immediately, the data transfer control unit controls the first storage device to receive the data transmitted by the chipset directly,
If the first storage device cannot receive all the data immediately, the data transfer control unit first temporarily sends a part of the data to be received by the first storage device to the second storage device. The other part of the data is directly received by the first storage device, and the first storage device finishes receiving the other part of the data, and the second storage A data transfer method comprising the step of transmitting data stored in a storage device so as to be received by the first storage device.   The first storage device can receive all data immediately because the amount of data that can be processed and received at one time by the first storage device is greater than the amount of data transmitted from the chipset to the first storage device. 5. The data transfer method according to claim 4, wherein the data transfer method is a large number. A data transfer method for transferring data to and from a computer chipset,
Providing a data transfer control unit for controlling the first storage device and transmitting the data to be received by the chipset;
The data transfer control unit receives the data transmitted by the first storage device,
Determine if the chipset can receive all data immediately by the data transfer control unit,
If the chipset can receive all data immediately, the data transfer control unit controls the chipset and receives the data transmitted from the first storage device directly,
If the chipset cannot receive all the data immediately, the data transfer control unit first temporarily stores a part of the data to be received by the chipset in the second storage device. A part of the data is directly received by the chipset, and the chipset finishes receiving the other part of the data, and the data stored in the second storage device is stored in the chipset. A data transfer method comprising the step of transmitting to receive.   The chipset can receive all data immediately when the amount of data that can be processed and received at one time is larger than the amount of data transmitted from the first storage device to the chipset. 7. The data transfer method according to claim 6, wherein Providing a data transfer control unit that is electrically connected between the chipset and the memory, the data transfer control unit controls the data transfer between the chipset and the memory, and the memory is activated by the computer Storing information and obtaining power supply,
A computer rapid activation method, comprising: a step of reading the computer activation information of the memory by the chipset via the data transfer control unit when the computer is activated.   9. The computer rapid activation method according to claim 8, wherein a transmission interface between the data transfer control unit and the chipset is a PCI-E (PCI-Express) interface. Setting the memory to be the startup device specified by the computer's basic input / output system before starting the computer;
9. The computer rapid activation method according to claim 8, further comprising storing computer activation information in the memory when the computer is terminated or in sleep mode.

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