JP2007019784A - High frequency power amplifier and operation voltage control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output power control technique capable of reducing leakage of a signal to a reception band in a high frequency power amplification circuit which fixes a bias voltage applied to a control terminal of an amplification element and varies an operation voltage (source voltage) in accordance with a signal indicating an output level, to control an output power. <P>SOLUTION: In high frequency power amplifiers (210 and 220) including an operation voltage control circuit (220) which varies an operation voltage (Vldo) supplied to amplification elements (211 to 213) in accordance with a signal (Vramp) indicating the output level, to control the output power, a bipolar transistor is used as a transistor (Q0) for power control which outputs the operation voltage to be supplied to amplification elements. Furthermore, a clamp circuit (222) is provided which clamps an output voltage of the transistor for power control so that the transistor doesn't enter the saturation region even in the case that the signal indicating the output level is set to a maximum level within its variable range. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a high-frequency power amplifier circuit that amplifies and outputs a high-frequency signal, and an open-loop high-frequency circuit that controls output power by changing the operating voltage (power supply voltage) of the amplifying element in accordance with a signal indicating the output level. The present invention relates to a technology that is effective when applied to a power amplifier circuit, for example, a technology that is effective when used for a high-frequency power amplifier circuit used in a mobile phone and an electronic component (power module) incorporating the high-frequency power amplifier circuit.

  In general, a transmission-side output unit in a wireless communication device (mobile communication device) such as a mobile phone is provided with a high-frequency power amplification circuit (power amplifier) that amplifies a modulated transmission signal. In the conventional wireless communication apparatus, a control voltage output from a circuit called an APC (Automatic Power Control) circuit is used to control the output power amplification factor of the high-frequency power amplifier circuit according to the transmission request level supplied from the base station. Accordingly, a configuration is adopted in which a bias voltage applied to the control terminal of the high-frequency power amplifying element is generated and the gain is controlled. The APC circuit adjusts the gain of the amplifying element so that the output power is necessary for a call based on the signal detected by the detection circuit or the like and the output level instruction signal from the baseband circuit or the like. Generate a signal to control. A wireless communication device of such a control method is disclosed in Patent Document 1, for example.

  By the way, conventionally, there is a system called GSM (Global System for Mobile Communication) as one of communication systems in a mobile phone. In this GSM system, a phase modulation system called GMSK (Gaussian Minimum Shift Keying) that shifts the phase of a carrier wave according to transmission data is used as a modulation system. In a GSM communication system, a phase-modulated signal may be amplified and output according to a required output level. Therefore, in this GSM mobile phone, generally, the amplitude of the input signal is fixed and the idle current of each amplifying element of the high-frequency power amplifier circuit is controlled by the bias circuit in accordance with the signal indicating the output level. The feedback control is performed. Such a control method is generally called a closed loop method.

However, since the output power control method using the closed loop method requires the provision of an APC circuit, there is a problem that the circuit scale is increased correspondingly and miniaturization of the device is hindered. Therefore, based on the signal indicating the output level, the amplifying element is linearly operated by controlling the operating voltage (power supply voltage) of the amplifying element so that the output level changes in proportion to the signal. Has been proposed (for example, see Patent Document 2). This method is called an open loop method and has an advantage that the circuit scale can be reduced as compared with the closed loop method.
JP 2000-151310 A Japanese Patent Laid-Open No. 2005-020383

  The operating voltage control circuit used in Patent Document 2 generates an operating voltage to be applied to a power supply voltage terminal (drain terminal or collector terminal) of a high-frequency power amplifying element using a PNP bipolar transistor. Further, since a relatively large current flows through the PNP transistor, the base of the PNP transistor is not directly driven by the signal Vramp indicating the transmission output level, but is driven using a buffer amplifier. An operation voltage control circuit is also proposed in which a P-channel MOSFET is used instead of a bipolar transistor to generate an operation voltage of the high-frequency power amplification element.

  By the way, recently, in order to enable high-speed data transmission in the GSM standard, EDGE (Enhanced Data Rates for GMS Evolution) using 8-PSK modulation that shifts the phase and amplitude of a carrier according to transmission data as a modulation method. ) Is defined. In this EDGE system, the operating voltage control circuit needs to operate following the change in Vramp at a higher speed than in the case of GMSK modulation. Therefore, in a system having the EDGE method, a bipolar transistor is more suitable than a MOSFET as a power source control transistor of the operating voltage control circuit.

  However, when a bipolar transistor is used as the power supply control transistor in the operating voltage control circuit of the system having the EDGE method, the reception frequency separated from the transmission frequency band by 20 MHz when Vramp is lowered from the maximum voltage within the allowable variable range. The signal leakage to the band cannot satisfy −79 dBm or less specified by the GSM standard. Therefore, the present inventors examined the cause.

  As a result, when Vramp is set to the maximum voltage, the bipolar transistor for power supply control of the operating voltage control circuit enters the saturation region. Therefore, when Vramp is lowered, the transistor cannot immediately follow the change, and an instantaneous current flows due to the charge remaining in the base-collector capacitance, and as shown in FIG. A glitch G is generated in the output voltage Vldo. Then, it has been found that the fact that the glitch wraps around the receiving system circuit via the power supply line is a cause of deteriorating the reception band noise. In FIG. 10, (B) is an enlarged view of the portion indicated by the alternate long and short dash line B in (A).

  An object of the present invention is to provide a high-frequency power for controlling the output power by changing the operating voltage (power supply voltage) in accordance with a signal indicating the output level while keeping the bias voltage applied to the control terminal of the high-frequency power amplifying element constant. In an amplifier (power module), an object is to provide an output power control technique capable of reducing signal leakage to a reception band.

Another object of the present invention is to provide an operating voltage control circuit suitable for a radio communication system that performs amplitude control of a phase and amplitude modulated transmission signal by an operating voltage control method, and a high-frequency power amplifier (power module) including the operating voltage control circuit. There is to do.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, in a high-frequency power amplifier having an operating voltage control circuit that controls the output power by changing the operating voltage supplied to the amplifying element in accordance with the signal indicating the output level, the operating voltage supplied to the amplifying element is output. A bipolar transistor is used as the power control transistor. In addition, a clamp circuit is provided for restricting the power supply control transistor from entering the saturation region even when the signal indicating the output level is set to the maximum level of the variable range. Here, preferably, the clamp circuit is configured as a soft clamp circuit that gently clamps the power supply control transistor even if the signal indicating the output level changes suddenly.

  Such a soft clamp circuit includes, for example, a differential amplifier circuit that compares an output voltage with a reference voltage, and a transistor that receives the output at a control terminal. The transistor controls the base terminal of the power control transistor. There is a circuit configured to apply feedback to a buffer to be driven to shift an offset voltage.

  According to the above-described means, the clamp circuit can clamp the power supply control transistor of the operating voltage control circuit before entering the saturation region. Therefore, even if the power control transistor is operated following the change of the signal (Vramp) indicating the output level, and Vramp suddenly falls, the current flowing instantaneously through the transistor can be suppressed. As a result, signal leakage to the reception frequency band can be reduced.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, according to the present invention, the bias voltage applied to the control terminal of the high-frequency power amplifying element is made constant, and the output voltage is controlled by changing the operating voltage (power supply voltage) according to the signal indicating the output level. In the power amplifier, there is an effect that signal leakage to the reception frequency band can be reduced.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a high-frequency power amplifier (power module) according to the present invention comprising a high-frequency power amplifier circuit and an operating voltage control circuit (variable operating voltage generation circuit) that generates its operating voltage and controls output power. It is shown.

  The high-frequency power amplifier circuit 210 of the high-frequency power amplifier according to this embodiment includes three amplification stages 211, 212, and 213 each including an amplification element such as an FET or a bipolar transistor. Fixed bias voltages Vb1, Vb2, Vb3 from a bias circuit (not shown) are applied to the control terminals (gate terminals or base terminals) of the amplification elements of the amplification stages 211, 212, 213. The fixed bias voltages Vb1, Vb2, and Vb3 are set to a level that causes the amplification transistors of the amplification stages 211, 212, and 213 to operate in the saturation region. Normally, it is set so that Vb1 <Vb2 <Vb3.

  The operating voltage control circuit 220 receives the power supply voltage Vdd, outputs a power supply voltage Vldo proportional to an output level instruction signal Vramp supplied from a baseband circuit (not shown), and outputs the power supply conversion circuit 221. The semiconductor integrated circuit is formed as a semiconductor integrated circuit on one semiconductor substrate.

  Among these, the power supply conversion circuit 221 has a differential amplifier AMP0 that receives Vramp at its inverting input terminal, a level shift circuit LS that is provided in a subsequent stage of the differential amplifier AMP0, and a base terminal that is driven by the level shift circuit LS. The PNP bipolar transistor Q0 is provided, and the operating voltage Vldo of the amplification stages 211 to 213 is generated according to Vramp. The level shift circuit LS is composed of a constant current source CC2 and a MOSFET Q1, and has a function of compensating the shortage of driving force of the differential amplifier AMP0 and shifting the signal level.

  This level shift circuit LS can also be regarded as an output stage of the differential amplifier AMP0. That is, the circuit in which the differential amplifier AMP0 and the level shift circuit LS in FIG. 1 are represented by a single amplifier symbol can be regarded as the same as the circuit of this embodiment. The power conversion circuit 221 includes a constant current source CC1 in series and a resistor R1 that generates an offset voltage Voff applied to the non-inverting input terminal of the differential amplifier AMP0.

  Further, the power conversion circuit 221 is connected between the stabilization capacitor C1 connected to the output terminal OUT, the connection node N1 between the constant current source CC1 and the resistor R1, and the collector terminal of the power control transistor Q0. The resistor R2 has a resistor R0 and a capacitor C0 connected between the collector terminal of Q0 and the output terminal of the differential amplifier AMP0. The resistor R0 and the capacitor C0 function as a phase compensation circuit that prevents oscillation. Among the above elements constituting the power conversion circuit 221, the output PNP transistor Q0, the stabilization capacitor C1, the phase compensation resistor R0, and the capacitor C0 are provided on the semiconductor chip on which the differential amplifier AMP0 and the clamp circuit 222 are formed. It is connected as an external element.

  By applying the potential of the connection node N1 of the resistors R1 and R2 to the non-inverting input terminal of the differential amplifier AMP0, the differential amplifier AMP0 uses the potential of the connection node N1 of the resistors R1 and R2 as the output level instruction signal Vramp. The power supply control transistor Q0 is driven so as to match. As a result, the collector voltage of the power supply control transistor Q0 is proportional to the output level instruction signal Vramp, and is lower than the power supply voltage Vdd by the voltage drop due to the on-resistance. This is smoothed by the stabilization capacitor C1 and supplied to the amplification stages 211 to 213 as the operating voltage Vldo.

  The reason why the potential of the connection node N1 of the resistors R1 and R2 is applied to the non-inverting input terminal of the differential amplifier AMP0 is as follows. That is, even if the baseband circuit attempts to set the output power to “0” due to manufacturing variation or the like, the output level instruction signal Vramp may not be completely 0V. This is because the power conversion circuit 221 outputs a significant level of the operating voltage Vldo, thereby giving an offset to prevent the amplification stages 211 to 213 from performing an amplification operation. By applying the offset voltage Voff to the non-inverting input terminal of the differential amplifier AMP0, the operating voltage Vldo increases in proportion to Vramp from the time when Vramp exceeds Voff, as shown in FIG. .

  The clamp circuit 222 includes a differential input MOSFET Q2 that receives the output voltage of the power conversion circuit 221 at the gate terminal, and a differential input MOSFET Q3 that is connected in common to the source of Q2 and receives the reference voltage Vref at the gate terminal. An amplifying stage and an output MOSFET Q6 in which the drain voltage of Q2 is applied to the gate terminal. A constant current source CC3 is connected to the common source terminal of the differential input MOSFETs Q2 and Q3, and a gate and a drain are coupled between the drain terminal of Q2 and Q3 and the power supply terminal to which the power supply voltage Vdd is applied. Diode-connected load MOSFETs Q4 and Q5 are connected. Q2 and Q3 are N-channel MOSFETs, and Q4, Q5 and Q6 are P-channel MOSFETs.

  The reference voltage Vref applied to the gate terminal of the MOSFET Q3 is generated by the resistor R3 and the constant current source CC4. For example, a voltage lower by about 0.2V than the power supply voltage Vdd is selected. The drain terminal of the output MOSFET Q6 is connected to the collector terminal of the transistor Q0, that is, the output node N0 of the power conversion circuit 221, and the source terminal of Q6 is connected to the connection node N1 between the constant current source CC1 that generates the offset voltage Voff and the resistor R1. Has been.

  Further, the MOSFETs Q2 and Q6 have a size ratio of 1: 5, so that a relatively large current can be output from Q6 for a slight change in input. Further, the influence of the clamp circuit 222 on the output of the power conversion circuit 221 can be reduced by reducing the size of Q2. Further, the size of Q2 and Q6 is set to 1: 5, so that the gain is made smaller than that of a general differential amplifier circuit, thereby gradually changing the output Vldo with respect to the sudden change of Vramp as will be described later. Is done. A desirable range of the ratio of the currents flowing through Q2 and Q6 as a condition for gradual change in the output Vldo is 1:10 or less.

Next, the operation of the clamp circuit 222 will be described with reference to FIGS.
The clamp circuit 222 in the present embodiment is constituted by a differential amplifier circuit, and a reference voltage Vref lower by about 0.2V than the power supply voltage Vdd is applied to its non-inverting input terminal. Further, the power control transistor Q0 of the power conversion circuit 221 has a collector voltage that is about 0.1 V lower than Vdd in the saturation region. Therefore, when Vramp is increased and the output voltage of the power supply conversion circuit 221 exceeds (Vdd−0.2 V), a current starts to flow through the MOSFET Q2. As a result, the drain voltage of Q2 decreases and Q6 is turned on, and a current flows into the resistor R1. Therefore, the offset voltage Voff applied to the non-inverting input terminal of the differential amplifier AMP0 of the power conversion circuit 221 increases.

  Then, the output voltage of AMP0 rises and the resistance between the source and drain of MOSFET Q1 receiving the output voltage of AMP0 at the gate rises, so that the base potential of the power supply control transistor Q0 is increased and the collector current is reduced. As a result, the output Vldo operates in a decreasing direction. As a result, the power supply control transistor Q0 can be prevented from entering the saturation region. As described above, even when Vramp is at the maximum level, the power supply control transistor Q0 is not saturated. Therefore, when Vramp is lowered from the maximum level, the current of Q0 immediately decreases following the change. . As a result, as shown in FIG. 4B, which shows an enlarged waveform of the portion surrounded by the alternate long and short dash line B in FIG. 4A, an instantaneous current flows through the power supply control transistor Q0 and the output voltage Vldo has a glitch G. Will not occur. This also makes it possible to reduce signal leakage to the reception band.

  FIG. 5A shows the result of examining the change in the transmission signal by simulation when Vramp is lowered from the vicinity of 2 V, which is the maximum voltage, to 0 V in the high frequency power amplifier circuit to which the present embodiment is applied. For comparison, FIG. 5B shows changes in the transmission signal when Vramp is lowered from the vicinity of 2V to 0V in the high frequency power amplifier circuit to which the present embodiment is not applied. From FIG. 5, when this embodiment is applied, no noise is generated in the transmission signal when Vramp is lowered from near 2V to 0V. However, when this embodiment is not applied, there is a large noise in the transmission signal. It can be seen that it occurs.

  In the clamp circuit 222 of the embodiment of FIG. 1, the drain terminal of the output MOSFET Q6 is connected to the output node N0 of the power supply conversion circuit 221, but the power supply terminal to which the power supply voltage Vdd is applied is connected to the drain terminal of Q6. You may make it connect to. However, when the drain terminal of Q6 is connected to the power supply terminal, when Vramp falls and the output Vldo falls, the charge remains at the connection node between the MOSFETs Q2 and Q4, and it turns off when Q6 should shift to the off state. There is a risk of not. On the other hand, if the drain terminal of Q6 is connected to the output terminal of the power conversion circuit 221, Q6 can be reliably turned off even in such a case.

  FIG. 3 shows another embodiment of the operating voltage control circuit 220 including a power conversion circuit 221 and a clamp circuit 222 that clamps its output. In this embodiment, a clamp circuit 222 comprising a plurality of diodes D1, D2,... Dn and resistors Rs in series is provided between the output terminal of the power conversion circuit 221 and the ground point. The clamp voltage is about 0.2 V lower than the power supply voltage Vdd, as in the above embodiment. The forward voltage and the number of connections “n” of the diodes D1 to Dn are determined so that such a voltage can be obtained. The resistor Rs is a protective element that prevents an excessive current from flowing through the diodes D1 to Dn. As the diodes D1 to Dn, for example, Schottky barrier diodes or Zener diodes are suitable.

  When this embodiment is applied, substantially the same effect as that of the first embodiment can be obtained, but the clamp accompanying the rise of Vramp and the release of the clamp accompanying the drop of Vramp are executed more steeply than the above embodiment. As a result, a slight noise may occur in the switching operation. Therefore, when the first embodiment is applied, the change in the output Vldo in the vicinity of the maximum value Vramp (max) of Vramp becomes gentler, and the generated switching noise is reduced.

FIG. 6 shows a detailed configuration of the high-frequency power amplifier circuit 210 in the high-frequency power amplifier to which the present invention is applied.
The high frequency power amplifier circuit 210 of this embodiment includes three power amplifying FETs 211, 212, and 213. Of the FETs 212 and 213 in the subsequent stage, the gate terminals are connected to the drain terminals of the FETs 211 and 212 in the previous stage, respectively. This is configured as a three-stage amplifier circuit. Further, the gate bias voltages Vb1, Vb2, and Vb3 (Vb1 <Vb2 <Vb3) supplied from the bias circuit 230 are applied to the gate terminals of the FETs 211, 212, and 213 in each stage, and the drain current corresponding to these voltages is applied. Is allowed to flow through each FET 211, 212, 213.

  The operation voltage Vldo from the operation voltage control circuit 220 having the configuration as shown in FIG. 1 is applied to the drain terminals of the FETs 211, 212, and 213 at the respective stages via inductors L1, L2, and L3, respectively. . An impedance matching circuit 241 and a DC cut capacitive element C11 are provided between the gate terminal of the first stage FET 211 and the input terminal In, and the high frequency signal Pin is input to the gate terminal of the FET 211 via these circuits and elements. The

  Between the drain terminal of the first-stage FET 211 and the gate terminal of the second-stage FET 212, an impedance matching circuit 242 and a DC-cut capacitive element C12 are connected. An impedance matching circuit 243 and a DC cut capacitive element C13 are connected between the drain terminal of the second stage FET 212 and the gate terminal of the final stage FET 213. The drain terminal of the FET 213 at the final stage is connected to the output terminal OUT via the impedance matching circuit 244 and the capacitive element C14, and the signal Pout obtained by cutting the DC component of the high-frequency input signal Pin and amplifying the AC component is output. .

  The bias circuit 230 includes, but is not limited to, resistors R11 to R16 and the like, and includes a resistor voltage dividing circuit that generates the gate bias voltages Vb1, Vb2, and Vb3 by dividing the constant voltage Vcnt by a predetermined resistance ratio. Has been. Note that the resistance voltage dividing circuit of FIG. 6 is not an exact circuit, but is shown as a circuit concept, and is not limited to the illustrated circuit. The resistors R11 to R16 constituting the bias circuit 230 are the amplification FETs 211, 212, and 213 of the high-frequency power amplifier circuit 210 and the operation voltage control circuit 220 (the power supply control transistor Q0, the stabilization capacitor C1, the phase compensation resistor R0, and And a semiconductor integrated circuit on one semiconductor chip.

  In this embodiment, the semiconductor chip on which the amplifying FETs 211, 212, and 213, the operating voltage control circuit 220, and the bias circuit 230 of the high-frequency power amplifier circuit 210 are formed includes the stabilizing capacitor C1 and the DC-cut capacitors C11 to C14. A module (hereinafter referred to as an RF power module) is mounted on an insulating substrate together with external elements such as. In this specification, a plurality of semiconductor chips and discrete components are mounted on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside, and each component has a predetermined role in the printed wiring or bonding wire. A module that can be handled as one electronic component is called a module.

  Inductors L1 to L3 are formed of bonding wires connected between pads of a semiconductor chip in this embodiment, but can be formed by a microstrip line formed on a module substrate. The third-stage amplification EFT 213 may be formed as a separate semiconductor element. As a result, the operating voltage control circuit 220 can be made less susceptible to the noise generated by the final stage amplification EFT 213. The resistors R11 to R16 can also use external elements.

FIG. 7 shows another circuit example of the bias circuit 230.
In this embodiment, a bias transistor Qb3 connected in a current mirror connection via a resistor Rb3 is provided at the gate terminal of the amplifying EFT 213, and a bias current Ib3 is supplied from the current generation circuit 231 to the transistor Qb3. Thus, a drain current proportional to the size ratio of the transistors Qb3 and Qa3 is allowed to flow as an idle current through the amplifying EFT 213. Similarly, bias transistors (Qb1 and Qb2) connected in a current mirror are provided in the amplification transistors in the previous stage, and the bias currents Ib1 and Ib2 are also supplied from the current generation circuit 231 to these transistors. ing. The current generation circuit 231 and bias transistors Qb1, Qb2, and Qb3 constitute a bias circuit 230.

  The current generation circuit 231 is the same as the differential amplifier AMP2 that receives the constant voltage Vcnt at its non-inverting input terminal and the resistors R30 and Q30 that are connected in series with the MOSFETs Q30 and Q30 that receive the output of the differential amplifier AMP2 at the gate terminal. MOSFETs Q31, Q32, and Q33 that receive the gate voltage. Then, the potential of the connection node N3 between Q30 and R30 is fed back to the inverting input terminal of the differential amplifier AMP2, so that the MOSFET Q30 is driven so that the potential of the connection node N3 matches Vcnt, and Q31, Q32, Q33 A current that is proportional to the constant voltage Vcnt is supplied.

  This current is supplied as bias currents Ib1, Ib2, and Ib3 to the bias transistors Qb1, Qb2, and Qb3 connected to the amplifying elements 211, 212, and 213 as a current mirror. By setting transistors Q30 and Q31, Q32, Q33 or 211, Qb1, 212, Qb2, 213, and Qb3 in a predetermined size ratio in advance, a current of a desired magnitude proportional to the constant voltage Vcnt is used for amplification. It can flow to the elements 211, 212, 213. Usually, Ib1 <Ib2 <Ib3.

  FIG. 8 shows an application example of a radio communication system to which the high frequency power amplifier of the above embodiment is applied. Although not particularly limited, this application example is configured as a dual-band radio communication system capable of transmission / reception by two systems of GSM and DCS (Digital Cellular System) of 1710 to 1785 MHz band.

  In FIG. 8, 100 is a front-end module, 200 is an RF power module to which the high-frequency power amplifier of the above embodiment is applied, and 300 is a modulation method for converting an audio signal into a baseband signal or converting a received signal into an audio signal. This is a baseband circuit that generates a switching signal MODE, a band switching signal BAND, and a transmission start signal TXON. Reference numeral 400 denotes a modulation / demodulation LSI that down-converts and demodulates a received signal to generate a baseband signal or modulates a transmission signal. FLT1 and FLT2 are filters that remove noise and interference waves from the received signal.

  Of these, for example, the filter FLT1 is a GSM circuit, and the filter FLT2 is a DCS circuit. The baseband circuit 300 can be composed of a plurality of LSIs and ICs such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory. Although not shown in FIG. 6, the RF power module 200 is provided with two high-frequency power amplifier circuits 210a and 210b having the same configuration. The high frequency power amplifier circuit 210a amplifies a GSM transmission signal using a frequency of 880 to 915 MHz, and the high frequency power amplifier 210b amplifies a DCS transmission signal using a frequency of 1710 to 1785 MHz. To be.

  In the RF power module 200 used in this application example, two bias circuits 230 and operating voltage control circuits 220 are provided corresponding to the high-frequency power amplifier circuit 210a and the high-frequency power amplifier circuit 210b, respectively. However, some elements may be shared and provided as a common circuit. The output level instruction signal Vramp from the baseband circuit 300 may be supplied to the RF power module 200 via the modulation / demodulation LSI 400.

  The front-end module 100 is connected to a transmission output terminal of the RF power module 200, impedance matching circuits 121 and 122 for impedance matching, low-pass filters 131 and 132 for attenuating harmonics, and a transmission / reception switching switch circuit 141. , 142 and the like. Further, capacitors 151 and 152 for cutting a direct current component from the received signal, a demultiplexer 160 for demultiplexing a 900 MHz band GSM signal and a 1.8 GHz band DCS signal, and these circuits and elements are provided. A module is mounted on a single ceramic substrate. The switching signals CNT1 and CNT2 of the transmission / reception switching switch circuits 141 and 142 are supplied from the baseband circuit 300.

  Note that the operating voltage control circuit 220 of the above embodiment amplifies not only a GMSK modulated transmission signal having only a phase modulation component but also an 8-PSK modulated transmission signal having a phase modulation component and an amplitude modulation component. This is particularly effective when applied to high-frequency power amplifiers that support Enhanced Data Rates for GMS Evolution.

  FIG. 9 shows a configuration example of an EDGE-compatible high-frequency power amplifier circuit. In this embodiment, a phase / amplitude separation circuit 430 that separates a phase modulation component and an amplitude modulation component from a transmission signal having a phase modulation component and an amplitude modulation component is provided before the high frequency power amplifier circuit 210. At the same time, a changeover switch SW1 for selecting the output level instruction signal Vramp from the baseband circuit or the signal VAM including the amplitude component separated by the phase amplitude separation circuit 430 is provided in the previous stage of the operating voltage control circuit 220. .

  This switch SW1 selects Vramp and supplies it to the operating voltage control circuit 220 when the signal MODE indicating the mode supplied from the baseband circuit indicates the GSM mode for amplifying the GMSK modulated transmission signal. To do. On the other hand, when the mode signal MODE indicates the EDGE mode for amplifying the transmission signal subjected to 8-PSK modulation, the signal VAM including the amplitude component separated by the phase amplitude separation circuit 430 is selected by the switch SW1. Is supplied to the operating voltage control circuit 220.

  Thus, the operating voltage control circuit 220 generates an operating voltage Vldo proportional to Vramp and supplies it to the high frequency power amplifier circuit 210 in the GSM mode. On the other hand, in the EDGE mode, an operating voltage Vldo corresponding to the signal VAM including the amplitude component is generated and applied to the high frequency power amplifier circuit 210. In the EDGE mode, a transmission signal having an amplitude corresponding to the output level instruction signal Vramp is generated in a circuit preceding the phase / amplitude separation circuit 430 and supplied to the phase / amplitude separation circuit 430 as an input signal IN.

  Then, the signal Pin having only the phase modulation component is input to the high frequency power amplifier circuit 210. Therefore, the high frequency power amplifier circuit 210 amplifies and outputs the input signal Pin according to the operating voltage Vldo that changes according to the amplitude component VAM. As described above, when the amplitude control is performed with the operating voltage Vldo, it is necessary that the operating voltage Vldo change at a high speed. Therefore, as in the operating voltage control circuit 220 described above, a bipolar transistor is used as the power supply control transistor. It is effective to use the circuit used.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, three amplification FETs are connected, but a two-stage configuration or four or more stages may be used. In the embodiment, MOSFETs are used as the power amplifying elements 211 to 213, but other transistors such as bipolar transistors, GaAs MESFETs, heterojunction bipolar transistors (HBTs), and HEMTs (High Electron Mobility Transistors) are used. May be.

  In the above description, when the invention made mainly by the present inventor is applied to a power module constituting a EDGE-compliant GSM wireless communication system capable of GMSK modulation and 8-PSK modulation, which is the field of use behind it. However, the present invention is not limited thereto. For example, the present invention can also be used for a power module used in a CDMA mobile phone.

It is a circuit block diagram which shows one Example of the high frequency power amplifier to which this invention is applied. It is a graph which shows the relationship between the output level instruction | indication signal Vramp and the output operating voltage Vldo in the operating voltage control circuit of an Example. It is a circuit diagram which shows the other Example of an operating voltage control circuit. FIG. 4A is a waveform diagram showing the change of the output level instruction signal Vramp input to the operating voltage control circuit of the embodiment and the operating voltage Vldo output, and FIG. 4B is a partially enlarged explanatory view thereof. It is. FIG. 5A is a waveform diagram showing the result of examining the change in the transmission signal by simulation when Vramp is lowered from the vicinity of 2V to 0V in the high frequency power amplifier circuit to which this embodiment is applied, FIG. 5B. These are the wave form diagrams which show the change of a transmission signal when Vramp is lowered | hung from 2V vicinity to 0V in the high frequency power amplifier circuit which does not apply a present Example. It is a circuit block diagram which shows the more specific structural example of a high frequency power amplifier circuit. It is the circuit block diagram which showed the other structural example of the high frequency power amplifier circuit. It is a block diagram which shows one application example of the radio | wireless communications system to which the high frequency power amplifier (RF power module) of an Example is applied. It is a block diagram which shows the structural example of the high frequency power amplifier corresponding to EDGE. FIG. 10A is a waveform diagram showing how the output level instruction signal Vramp input to the conventional operating voltage control circuit and the output operating voltage Vldo change, and FIG. 10B is a partially enlarged explanatory diagram thereof. is there.

Explanation of symbols

Q0 Power control transistor 200 High frequency power amplifier (RF power module)
210 High Frequency Power Amplifier 211, 212, 213 Amplifier (Power Amplifier Transistor)
220 Operating voltage control circuit 221 Power supply conversion circuit 222 Clamp circuit 230 Bias circuit 241 to 244 Impedance matching circuit

Claims (10)

An operating voltage control circuit for controlling an output power by changing an operating voltage supplied to an amplifying element of a high frequency power amplifier circuit according to a control signal indicating an output level,
A power supply control transistor that receives a power supply voltage and outputs an operating voltage supplied to the amplifying element; and a control circuit that drives the power supply control transistor in response to the control signal. A transistor is used, and the control circuit controls the power supply control transistor so that it always operates in a linear region in a variable range of the control signal.   The control circuit includes a first differential amplifier circuit that receives the control signal at one input terminal and receives a feedback voltage according to an output voltage of the power control bipolar transistor at the other input terminal; and the power control 2. The second differential amplifier circuit according to claim 1, further comprising: a second differential amplifier circuit that receives the output voltage of the bipolar transistor at one input terminal and compares it with a reference voltage to displace the feedback voltage by a voltage corresponding to the potential difference. Operating voltage control circuit. An operating voltage control circuit for controlling an output power by changing an operating voltage supplied to an amplifying element of a high frequency power amplifier circuit according to a control signal indicating an output level,
A power supply control bipolar transistor that receives a power supply voltage and outputs an operating voltage supplied to the amplification element, a drive circuit that drives the transistor in response to the control signal, and the transistor saturates the output voltage of the transistor An operating voltage control circuit comprising: a clamp circuit that clamps so as not to operate in a region. The drive circuit includes a first differential amplifier circuit that receives the control signal at one input terminal and receives a feedback voltage according to an output voltage of the power control bipolar transistor at the other input terminal;
The clamp circuit receives the output voltage of the power control bipolar transistor at one input terminal, compares it with a reference voltage, and displaces the feedback voltage by a voltage corresponding to the potential difference. The operating voltage control circuit according to claim 3, comprising:   The feedback voltage includes a first resistor connected between the other input terminal of the first differential amplifier circuit and a reference potential, an output terminal of the power control bipolar transistor, and the first voltage. And a second resistor connected to the other input terminal of the differential amplifier circuit, and the output transistor of the second differential amplifier circuit generates a current through the first resistor. The operation voltage control circuit according to claim 4, wherein the operation voltage control circuit is configured to displace the feedback voltage by flowing a current.   6. The operating voltage control circuit according to claim 5, wherein a ratio of a current flowing through the differential input transistor of the second differential amplifier circuit to a current flowing through the output transistor is 1:10 or less. A high-frequency power amplifier circuit comprising a plurality of amplifier elements and a bias circuit that applies a bias voltage to a control terminal of the amplifier elements, and the amplifier elements in response to a control signal that indicates a transmission output level with the bias voltage fixed A high frequency power amplifier having an operating voltage control circuit for controlling output power by changing an operating voltage to be supplied to
The operating voltage control circuit includes a power supply control bipolar transistor that receives a power supply voltage and outputs an operating voltage supplied to the amplifying element, a drive circuit that drives the transistor in response to the control signal, and And a clamp circuit that clamps the output voltage so that the transistor does not operate in a saturation region. The drive circuit includes a first differential amplifier circuit that receives the control signal at one input terminal and receives a feedback voltage according to an output voltage of the power control bipolar transistor at the other input terminal;
The clamp circuit receives the output voltage of the power control bipolar transistor at one input terminal, compares it with a reference voltage, and displaces the feedback voltage by a voltage corresponding to the potential difference. The high frequency power amplifier according to claim 7, comprising:   The feedback voltage includes a first resistor connected between the other input terminal of the first differential amplifier circuit and a reference potential, an output terminal of the power control bipolar transistor, and the first voltage. And a second resistor connected to the other input terminal of the differential amplifier circuit, and the output transistor of the second differential amplifier circuit generates a current through the first resistor. The high frequency power amplifier according to claim 8, wherein the feedback voltage is displaced by flowing a current.   10. The operating voltage control circuit and the amplifying element are formed on the same semiconductor chip, and the power control bipolar transistor is connected as an external element. The described high-frequency power amplifier.

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