JP2007013120A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having the configuration of an antenna advantageous to miniaturization without changing the number of processes or communication distances. <P>SOLUTION: The semiconductor device capable of achieving the items has a substrate, a tag including a thin film device provided on the substrate, a first antenna, and a second antenna. The first and the second antennae are formed in different layers isolated by an insulating film, the first antenna and the second antenna are partially connected electrically, the first antenna is formed of the same material and in the same layer as in the wiring that is connected to the thin film device, and the second antenna is formed in a layer different from the wiring that is connected to the thin film device. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of transmitting and receiving data by wireless communication. In particular, the present invention relates to a semiconductor device capable of transmitting and receiving data by wireless communication advantageous for downsizing.

Semiconductor devices that can send and receive data by wireless communication such as card-type, tag-type, and coin-type with IC tags are equipped with abundant amount of information and high security, so traffic, distribution, information, etc. It is spreading in the field. Further, the non-contact IC tag device is attracting attention because it can transmit data wirelessly, has excellent reliability, and can process a plurality of data simultaneously.

The semiconductor device capable of transmitting and receiving data by wireless communication is, for example, an exterior made of plastic or the like, which is an antenna for connecting a power supply and transmitting and receiving data by electromagnetic coupling with the main unit and an external terminal of the tag. There are configurations in which materials are bonded from both sides.

As an antenna of a semiconductor device capable of transmitting and receiving data by wireless communication, a copper foil or aluminum foil pasted on a plastic film is formed into a predetermined shape by etching, or a conductive paste is formed by printing There are things.

The external size of the semiconductor device capable of transmitting and receiving data by the wireless communication varies depending on the application. In general, an electromagnetic coupling type semiconductor device is electromagnetically coupled by a change in magnetic flux linked to an antenna. Therefore, a small antenna area has a short communication distance and a large antenna has a long length.

Examples of semiconductor device applications capable of transmitting and receiving data by wireless communication include indexes of cards, video tapes, and CD boxes.

When the semiconductor device capable of transmitting and receiving data by the antenna-mounted wireless communication is used as the proximity type, the antenna 6502 for electromagnetic coupling with the main body device is used as shown in FIG. Thus, power supply to the semiconductor device and data transmission / reception are performed. Note that as illustrated in FIG. 5, the antenna 6502 is formed using an antenna formation layer 6503 and the tag 6500 is formed using a wiring formation layer 6501.

Non-Patent Document 1 describes a case where one antenna is divided into two layers in order to increase the communication distance. Specifically, a structure in which resin is sandwiched between the Si substrate and the first antenna and between the first antenna and the second antenna is used. This antenna is formed by winding one Cu wire in a spiral shape (see, for example, Non-Patent Document 1).
“Nikkei Electronics”, April 11, 2005, p. 26-p. 27

Currently, the maximum output from the reader / writer antenna is determined by the Radio Law. Since a semiconductor device capable of transmitting and receiving data by wireless communication must receive the determined output efficiently, it is desirable to make the length of the antenna as long as possible. As a result, the antenna size is often larger than a circuit in a semiconductor device capable of transmitting and receiving data by wireless communication. Semiconductor devices capable of transmitting and receiving data by wireless communication are currently considered for various uses, and it can be expected that the applications will be further expanded if the semiconductor device capable of transmitting and receiving data by wireless communication can be reduced. For example, consider a case in which a semiconductor device capable of transmitting and receiving data by wireless communication is attached to a 1 cm square article for management. At this time, if a semiconductor device capable of transmitting and receiving data by wireless communication becomes larger than 1 cm square, it seems to hinder the management of goods. If a semiconductor device capable of transmitting and receiving data by wireless communication can be made to a size that does not interfere with the management of goods, there are no restrictions on the use of the semiconductor device that can transmit and receive data by wireless communication by size, and data can be transmitted by wireless communication. There is a possibility that the application of a semiconductor device capable of transmitting and receiving the information will expand. With the above background, when reducing the size of a semiconductor device capable of transmitting and receiving data by wireless communication, the problem is how to reduce the antenna size without changing the communication distance.

In order to solve the above problem, Non-Patent Document 1 discloses a semiconductor device capable of transmitting and receiving data by wireless communication having two antenna layers. At that time, the problem is that the number of processes increases to form two antenna layers, and the throughput and yield decrease.

In view of the above, it is an object of the present invention to provide a semiconductor device having an antenna structure that is advantageous for downsizing without changing the number of steps and the communication distance.

  One of the configurations of the present invention for solving the above problems includes a substrate, a tag portion including a circuit formed of a thin film element provided on the substrate, a first antenna, and a second antenna. The first antenna and the second antenna are formed in different layers separated by an insulating film, and the first antenna and the second antenna are partially electrically connected to each other. Are formed in the same layer with the same material as the source or drain wiring connected to the thin film element, and the second antenna is formed in a different layer from the source or drain wiring connected to the thin film element. It is a semiconductor device.

  One of the configurations of the present invention for solving the above problems includes a substrate, a tag portion including a circuit formed of a thin film element provided on the substrate, a first antenna, and a second antenna. The first antenna and the second antenna are formed in different layers separated by an insulating film, and the first antenna and the second antenna are partially electrically connected to each other. Are formed in the same layer with the same material as the source or drain wiring connected to the thin film element, and the second antenna is formed in a different layer from the source or drain wiring connected to the thin film element. The first antenna and the second antenna are semiconductor devices that do not overlap except for a portion that is electrically connected to an intersecting portion when viewed from a direction perpendicular to the substrate.

  One of the structures of the present invention for solving the above problems is that in the above structure, the thin film element includes a thin film transistor including a semiconductor layer, a gate insulating film, and a gate electrode, and the tag portion and the first antenna Are electrically connected, and the wiring connecting the tag portion and the first antenna is a semiconductor device formed of the same material and in the same layer as the gate electrode of the thin film transistor.

  One of the other structures of the present invention is the above structure, wherein the gate electrode is an alloy or compound containing one or more kinds selected from tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, and niobium. It is a semiconductor device formed by using.

  One of the other configurations of the present invention is the above configuration, wherein the first antenna is one or more selected from aluminum, nickel, tungsten, molybdenum, titanium, platinum, copper, tantalum, gold, and manganese. A semiconductor device formed using an alloy or a compound made of

  One of the other configurations of the present invention is the above configuration, wherein the second antenna is one or more selected from aluminum, nickel, tungsten, molybdenum, titanium, platinum, copper, tantalum, gold, and manganese. A semiconductor device formed using an alloy or a compound made of

  The semiconductor device of the present invention is a semiconductor device capable of transmitting and receiving data by wireless communication that can be miniaturized without changing the number of steps and the communication distance. Further, the semiconductor device of the present invention can extend the communication distance without changing the size. In addition, the semiconductor device of the present invention can be reduced in size or size without increasing the communication distance, and yield and throughput can be prevented from decreasing. In addition, the semiconductor device of the present invention can be reduced in size or size without increasing the communication distance, and an increase in manufacturing cost can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

(Embodiment 1)
Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device capable of exchanging data without contact. A semiconductor device capable of transmitting and receiving data by wireless communication is also referred to as an RFID (Radio Frequency Identification) tag, an ID tag, an IC tag, an IC chip, an RF tag (Radio Frequency), a wireless tag, an electronic tag, or a wireless chip, depending on the form of use. It is released. In the present invention, it is called an RFID tag for convenience, but it can be applied to any of the above forms. A semiconductor device capable of transmitting and receiving data by wireless communication includes data transmission and reception by wireless communication having a communication control circuit with an antenna unit 101 of a read / write communication control circuit 100 (hereinafter referred to as a reader / writer or R / W). Communication and power transmission / reception are performed with the tag antenna 502 of the semiconductor device capable of performing the above. A semiconductor device capable of transmitting and receiving data by wireless communication includes a tag antenna 502 and a tag 500 that performs communication control by generating a power supply voltage and a demodulated signal from radio waves received by the tag antenna 502. The tag antenna 502 includes a first antenna 102 and a second antenna 103. The tag 500 mainly includes an analog unit 104 that demodulates and modulates a power supply voltage and a signal, and a digital unit 105 that generates signal analysis and transmission data using the power supply voltage and the demodulated signal generated by the analog unit 104. Is done.

A top view of a semiconductor device capable of transmitting and receiving data by wireless communication of the present invention is shown in FIG. In order to stably supply the power supply potential (VDD) and the reference potential (GND) to the entire tag 500, the VDD wiring 200 and the GND wiring 201 are arranged so as to surround the analog portion 104 and the digital portion 105. The analog unit 104 is electrically connected to one end of the first antenna 102. The other end of the first antenna 102 is electrically connected to one end of the second antenna 103. The other end of the second antenna 103 is electrically connected to the GND wiring 201. As shown in FIG. 6, the first antenna 102 is manufactured with the wiring formation layer 501 of the tag 500, and the second antenna 103 is separately manufactured with the antenna formation layer 503. By doing so, an antenna having a two-layer structure can be manufactured without increasing the number of steps. By forming and connecting the wirings in two layers, an inductance equivalent to that of a large-sized antenna is generated, and a communication distance larger than that of an antenna of the same size having one wiring layer can be generated. Conversely, when an antenna having the same communication distance is manufactured, the size can be reduced.

Further, the positional relationship between the first antenna 102 manufactured in the wiring formation layer 501 and the tag 500 may be such that the first antenna 102 is arranged so as to surround the tag 500 as shown in FIG. As described above, the tag 500 may be disposed outside the first antenna 102. Further, the positional relationship between the tag 500 and the antenna is not limited to the above, and the tag 500 and the antenna can be freely arranged without departing from the gist of the present invention. In the configuration in which the tag is arranged outside the antenna as shown in FIG. 7, it is possible to reduce the influence of the magnetic flux passing through the inside of the antenna on the tag.

FIG. 3 shows a top view of a semiconductor device capable of transmitting and receiving data by wireless communication according to the present invention, and a cross-sectional view taken along line AB in FIG. As shown in FIG. 3, a semiconductor device capable of transmitting and receiving data by wireless communication according to the present invention includes a substrate 300, a first insulating film 302, a tag 500 including a digital portion 105 and an analog portion 104, a VDD wiring 200, and a GND. A wiring 201, a first antenna 102, a second insulating film 303, and a second antenna 103 are included. A base film 301 and other structures may be provided as necessary. The tag 500 including the analog unit 104 and the digital unit 105 is composed of many thin film elements typified by thin film transistors. In the cross-sectional view, the analog portion 104 and the digital portion 105 are located between the VDD wiring 200, the GND wiring 201, and the first antenna 102. The first insulating film 302 is a layer provided to electrically insulate the thin film transistor wiring formation layer from the semiconductor layer formation layer. The second insulating film 303 is a layer that separates the first antenna 102 and the second antenna 103. In other words, the first antenna and the second antenna are provided in different layers separated by the second insulating film 303.

By the way, as shown in FIG. 2, when viewed from a direction perpendicular to the substrate 300 in FIG. 3, the wiring of the first antenna 102 and the wiring of the second antenna 103 overlap with the second insulating film 303 interposed therebetween. When arranged at a position, an unintended parasitic capacitance is generated between the wirings of the first antenna 102 and the second antenna 103. This parasitic capacitance hinders the resonance of the semiconductor device capable of transmitting and receiving data by wireless communication. In order to avoid this influence, the position of the wiring of the first antenna 102 and the wiring of the second antenna 103 is electrically connected to the position where the two antennas intersect when viewed from a direction perpendicular to the substrate 300. It is good to arrange so that it does not overlap except the position where it is. That is, the first antenna and the second antenna are preferably arranged so as not to overlap except for a portion that is electrically connected to the intersecting portion when viewed from a direction perpendicular to the substrate. Note that FIG. 2 illustrates a portion 210 where the first antenna 102 and the second antenna 103 intersect and a portion 220 that is electrically connected when viewed from a direction perpendicular to the substrate 300. The distance between the wiring of the first antenna 102 and the wiring of the second antenna 103 is not particularly limited, and can be set as appropriate by the user.

In the present invention, since the wiring of the first antenna 102 is formed of the wiring material of the thin film transistor in the wiring formation layer of the thin film transistor, the thickness is thinner than that of the wiring of the second antenna 103, and thus the impedance (resistance) is increased. May end up. This is a loss in extracting power. In order to reduce the impedance (resistance) and increase the efficiency of electromagnetic coupling, the wiring width of the first antenna 102 may be formed thick as shown in FIG.

  As another configuration of the antenna, as shown in FIG. 9, a resonant capacitor 506 may be provided in the antenna. The resonance capacitor unit 506 can cut the resonance capacitor originally in the tag 500, and can reduce the size of the RFID.

4 is a cross-sectional view taken along line CD in FIG. 2, which is a top view of a semiconductor device capable of transmitting and receiving data by wireless communication according to the present invention, that is, a cross-sectional view of a connection portion between the analog portion 104 and the first antenna 102. Show. Here, only one thin film transistor among the many thin film elements in the analog portion 104 is shown and described.

  As shown in FIG. 4, a semiconductor layer 400 that serves as an active layer of the thin film transistor is provided over the base film 301. The semiconductor layer 400 is covered with a gate insulating film 401 and is electrically insulated from the gate electrode 402. In the analog portion 104 constituting the tag 500 described in FIG. 1, a thin film transistor including a semiconductor layer 400, a gate insulating film 401, and a gate electrode 402 is provided as shown in FIG. A source or drain wiring 404 formed on the first insulating film 302 is electrically connected to the semiconductor layer 400 of the thin film transistor through a contact hole provided in the first insulating film 302. . On the first insulating film 302, a VDD wiring 200, a GND wiring 201, and a first antenna 102 which are simultaneously formed in the same layer with the same material as the source or drain wiring 404 are also provided. At this time, the VDD wiring 200 and the GND wiring 201 are located between the source or drain wiring 404 and the first antenna 102.

  Further, the analog unit 104 included in the tag 500 described with reference to FIG. 1 is electrically connected to one end of the first antenna 102 as illustrated in FIG. At this time, as shown in FIG. 4, in order to reduce the number of steps, the wiring 403 connecting the thin film transistor provided in the analog portion 104 and the first antenna 102 is made of the same material as the gate electrode 402 and is simultaneously formed in the same layer. It is good to form. Note that the thin film transistor provided in the analog portion 104 is electrically connected to the wiring 403 through a wiring 404 for source or drain. In other words, the source or drain wiring 404 and the first antenna 102 are connected to each other through the wiring 403 formed of the same material as the gate electrode 402. A VDD wiring 200 and a GND wiring 201 are formed over the wiring 403 with the first insulating film 302 interposed therebetween.

  Although not shown in FIG. 4, a second antenna is formed over the second insulating film 303. The second antenna formed here is formed in a different layer separated by the first antenna 102 and the second insulating film 303. In other words, the second antenna is formed in a layer different from the first antenna formed in the same layer at the same time with the same material as the source or drain wiring 404.

  The semiconductor device having such a structure and capable of transmitting and receiving data by wireless communication according to the present invention is a semiconductor device capable of transmitting and receiving data by wireless communication that can be downsized without changing the number of steps and the communication distance. Further, the semiconductor device of the present invention can extend the communication distance without changing the size. In addition, the semiconductor device of the present invention is a semiconductor device capable of transmitting and receiving data by wireless communication in which a communication distance is increased without being downsized or changed in size, and a decrease in yield and throughput is suppressed. In addition, the semiconductor device of the present invention is a semiconductor device capable of transmitting and receiving data by wireless communication in which a communication distance becomes long without being downsized or changed in size, and an increase in manufacturing cost is suppressed.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device capable of transmitting and receiving data by wireless communication according to the present invention will be described with reference to FIGS. In this embodiment mode, only one thin film transistor in the analog portion is shown and described for the thin film element in the tag. Other thin film elements can be manufactured in the same manner, and it is easy for those skilled in the art to apply this manufacturing method to other thin film elements based on common general technical knowledge.

  As the substrate 300, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a substrate in which an insulating film is formed on the surface of a semiconductor substrate may be used. A flexible substrate such as plastic may be used. Further, the surface of the substrate may be polished and planarized by a CMP method or the like, and a glass substrate, a quartz substrate, or a semiconductor substrate that is thinned by polishing may be used.

  A base film 301 is formed on the substrate 300. The base film 301 can be formed using an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide. By forming the base film 301, diffusion of impurities in the substrate 300 that adversely affects the semiconductor layer 400 can be suppressed. Although the base film 301 is formed with a single layer in FIG. 10A, it may be formed with a plurality of layers of two or more layers. Note that the base film 301 is not necessarily formed when impurities in the substrate 300 do not matter.

The base film 301 may be formed by processing the surface of the substrate 300 with high-density plasma. The high-density plasma is generated by using a microwave of 2.45 GHz, for example, and has an electron density of 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ^{3, an} electron temperature of 2 eV or less, and an ion energy of 5 eV or less. . Such high-density plasma has low kinetic energy of active species, and is less damaged by plasma than conventional plasma treatment, and can form a film with few defects. The distance from the antenna generating the microwave to the substrate 300 is 20 to 80 mm, preferably 20 to 60 mm.

  In addition, by performing the high-density plasma treatment in a nitriding atmosphere, for example, an atmosphere containing nitrogen and a rare gas, an atmosphere containing nitrogen, hydrogen and a rare gas, or an atmosphere containing ammonia and a rare gas. The surface of the substrate 300 can be nitrided. In the case where a glass substrate, a quartz substrate, a silicon wafer, or the like is used as the substrate 300, when the nitriding treatment by the high-density plasma is performed, the nitride film formed on the surface of the substrate 300 contains silicon nitride as a main component. 301 can be used. Silicon oxide or silicon oxynitride may be formed on the nitride layer by a plasma CVD method to form a base film 301 composed of a plurality of layers.

  A nitride film can be formed on the surface of the base film 301 made of silicon oxide, silicon oxynitride, or the like by performing the same nitriding treatment with high-density plasma. This nitride film can suppress diffusion of impurities from the substrate 300. In addition, since it can be formed very thin, it is preferable because the influence of stress on the semiconductor layer formed thereon is small.

  Subsequently, the semiconductor layer 400 is formed on the base film 301. As the semiconductor layer 400, a patterned crystalline semiconductor film, amorphous semiconductor film, or organic semiconductor can be used. For patterning, a mask formed by exposing and developing a photosensitive resist using a photomask is used. At this time, it is possible to suppress the transmittance of light to be exposed in an arbitrary portion of the photomask, and to control the thickness of the mask after development. Finer and more accurate patterning can be performed by controlling the thickness of the mask.

  In this embodiment, an example in which the semiconductor layer 400 is formed using a crystalline semiconductor film is described. The crystalline semiconductor film can be obtained by crystallizing an amorphous semiconductor film. As a crystallization method, laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or the like can be used. The semiconductor layer 400 includes a channel formation region and an impurity region to which an impurity element imparting conductivity is added. Note that an impurity element imparting a conductivity type may be added to a portion corresponding to the channel region, whereby the threshold voltage of the semiconductor layer can be controlled.

  Subsequently, a gate insulating film 401 is formed. The gate insulating film 401 may be formed with a single layer or a plurality of layers using silicon oxide, silicon nitride, silicon nitride oxide, or the like. In this case, the surface of the gate insulating film 401 may be densified by treatment with high-density plasma in an oxidation atmosphere or a nitridation atmosphere, and an oxidation or nitridation treatment.

  Note that before the gate insulating film 401 is formed, the surface of the semiconductor layer 400 may be subjected to high-density plasma treatment to be oxidized or nitrided. At this time, when the temperature of the substrate 300 is set to 300 to 450 ° C. and treatment is performed in an oxidizing atmosphere or a nitriding atmosphere, a favorable interface with the gate insulating film 401 formed thereover can be formed.

  As the gate electrode 402, a single layer selected from tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, niobium, or a single layer or a plurality of layers made of an alloy or compound containing a plurality of types is used. it can. At the same time, a wiring 403 that electrically connects the analog portion and the first antenna 102 is formed. By simultaneously forming the wiring 403 with the same material as the gate electrode 402, the number of steps can be reduced, and the yield and throughput can be improved. Here, wirings such as the gate electrode 402 and the wiring 403 manufactured at the same time as the gate electrode 402 are preferably routed so that the corners are rounded when viewed from a direction perpendicular to the substrate 300. By rounding the corners, dust and the like can be prevented from remaining at the corners of the wiring, and defects caused by the dust can be suppressed and the yield can be improved. For patterning, a mask formed by exposing and developing a photosensitive resist using a photomask is used. At this time, it is possible to suppress the transmittance of light to be exposed in an arbitrary portion of the photomask, and to control the thickness of the mask after development. Finer and more accurate patterning can be performed by controlling the thickness of the mask.

  The thin film transistor includes a semiconductor layer 400, a gate insulating film 401, and a gate electrode 402. Although the thin film transistor is described as a top-gate transistor in this embodiment mode, a bottom-gate transistor or a dual-gate transistor having gate electrodes above and below a semiconductor layer may be used.

  Next, a first insulating film 302 is formed (FIG. 10B). As the first insulating film 302, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin on Glass) method, or the like can be used. As the organic insulating film, a film made of polyimide, polyamide, BCB (benzocyclobutene), acrylic, positive photosensitive organic resin, negative photosensitive organic resin, or the like can be used.

  Alternatively, the first insulating film 302 can be formed using a material having a skeleton structure formed of a bond of silicon and oxygen. A substituent containing at least hydrogen (for example, an alkyl group or an aryl group) is used as a substituent of this material. A fluoro group may be used as a substituent. Moreover, you may have both these substituents.

  In the case where the first insulating film 302 is formed using a plurality of layers, it is preferable that the layer closer to the semiconductor layer 400 be formed of a barrier insulating film that blocks ionic impurities, such as a film containing silicon nitride as a main component. . This can be used as a protective film that prevents contamination of the semiconductor layer 400. After this layer is formed, hydrogenation may be performed by introducing hydrogen gas and performing high-density plasma treatment. Thereby, the said layer can be densified. Further, after that, heat treatment at 400 to 450 ° C. is performed to release hydrogen, so that the semiconductor layer 400 can be hydrogenated.

  The thin film transistor wiring 404 is formed by patterning a single layer or a plurality of layers using one or more alloys or compounds selected from aluminum, nickel, tungsten, molybdenum, titanium, platinum, copper, tantalum, gold, and manganese. Formed. The figure shows an example of a single layer structure. Note that the wiring 404 is preferably formed so that a corner is round when viewed from a direction perpendicular to the substrate 300. By rounding the corner, it is possible to prevent dust and the like from remaining in the corner. In addition, the VDD wiring 200, the GND wiring 201, and the first antenna 102 are simultaneously formed using the same material as the wiring 404. For patterning, a mask formed by exposing and developing a photosensitive resist using a photomask is used. At this time, it is possible to suppress the transmittance of light to be exposed in an arbitrary portion of the photomask, and to control the thickness of the mask after development. Finer and more accurate patterning can be performed by controlling the thickness of the mask.

  Next, a second insulating film 303 is formed (FIG. 10C). As the second insulating film 303, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. A specific material is similar to that of the first insulating film 302.

  After that, the second antenna 103 is formed over the second insulating film 303. The second antenna 103 is formed so as not to overlap with the first antenna 102. The second antenna 103 is formed of a single layer or a plurality of layers using an alloy or a compound selected from one or a plurality selected from aluminum, nickel, tungsten, molybdenum, titanium, platinum, copper, tantalum, gold, and manganese. Is done. The figure shows an example of a single layer structure. The second antenna 103 can also be formed by a droplet discharge method using a conductive paste containing nanoparticles such as Au, Ag, and Cu. The droplet discharge method is a general term for a method of forming a pattern by discharging droplets, such as an ink jet method or a dispenser method, and has advantages such as an improvement in material utilization efficiency.

  Subsequently, a third insulating film 600 is formed over the second insulating film 303 and the second antenna 103. The third insulating film 600 may be formed with a single layer or a stacked structure of an inorganic insulating film or an organic insulating film. The third insulating film 600 functions as a protective layer for the second antenna 103.

  Thereafter, sealing is performed to complete the semiconductor device of the present invention. Note that a semiconductor device formed over the substrate 300 may be used as it is, but an element manufactured over the substrate 300 may be peeled off and attached to a flexible substrate.

  As a peeling method, there is a method in which a peeling layer is provided on the substrate 300 in advance, and the peeling layer is removed by removing the peeling layer with an etching agent. In addition, there are a method in which the peeling layer is partially removed with an etching agent and then physically removed, a method in which the substrate 300 is mechanically removed, a method in which the substrate 300 is removed by etching with a solution or a gas, and the like.

  In addition, a commercially available adhesive may be used for attaching the peeled element to the flexible substrate, for example, an epoxy resin adhesive.

  By manufacturing the semiconductor device of the present invention over the flexible substrate in this manner, the semiconductor device can be thin, light, and not easily damaged even if dropped. In addition, by using a flexible substrate having flexibility, it can be easily attached to a substrate having a curved surface.

  In this embodiment, the use of the semiconductor device of the present invention will be described with reference to FIGS. The semiconductor device 700 of the present invention includes, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 12A), packaging containers (wrapping paper, bottles, etc.) , See FIG. 12B), recording media such as DVD software, CD, video tape, etc. (see FIG. 12C), vehicles such as cars, motorcycles and bicycles (see FIG. 12D), bags and glasses. Etc. (see FIG. 12E), foods, clothing, daily necessities, electronic devices, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions or television receivers), cellular phones, and the like.

  The semiconductor device of the present invention can be fixed to an article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing the semiconductor device of the present invention for bills, coins, securities, bearer bonds, certificates, etc. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic equipment, etc., the efficiency of inspection systems and rental store systems will be improved. Can do. Forgery and theft can be prevented by providing the semiconductor device of the present invention in vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a wireless tag in a living creature such as livestock, it is possible to easily identify the year of birth, sex, type, or the like.

  As described above, the semiconductor device of the present invention can be provided and used for any article (including a living thing).

  The semiconductor device of the present invention is advantageous for downsizing, has a good yield and throughput, and can be manufactured at low cost. Therefore, it is easy to attach and is very effective for these uses that are used in large quantities.

  Next, one mode of a system using the semiconductor device of the present invention is described with reference to FIG. A reader / writer 3302 is provided on the side surface of the mobile terminal including the display portion 3301. Further, a semiconductor device 700 of the present invention is provided on a side surface of the article 3303 (see FIG. 11A). When the reader / writer 3302 is held over the semiconductor device 700 of the present invention included in the article 3303, information on the product such as the raw material and origin of the article 3303, the inspection result for each production process, the history of the distribution process, and the description of the product on the display unit 3301. Is displayed. As another system, the article 3305 can be inspected using the reader / writer 3304 and the semiconductor device 700 when the article 3305 is conveyed by a belt conveyor (see FIG. 11B). In this manner, by utilizing the semiconductor device of the present invention for the system, information can be easily acquired, and a system that realizes high functionality and high added value can be provided.

  FIG. 18 is a diagram showing one mode of another system using the semiconductor device of the present invention. This system is applied when sending packages using a courier. As shown in FIG. 18B, the sender attaches the semiconductor device 801 of the present invention to an article 805 to be sent in advance. The semiconductor device 801 stores at least sender information in advance. In addition, the information to be stored may be other information such as destination information, courier service, and contents. In the case of mail order sales, the amount to be paid may be displayed. When the delivery company comes to deliver the package, the reader / writer 802 attached to the front door 800 (or the entrance) reads the package information and can also serve as an intercom in the house 803 as shown in FIG. The information is displayed on the good display portion 804. The householder can respond after confirming this information, and can prevent misdelivery, solicitation posing as a courier, and crimes, and is particularly effective as a safety measure for families with children. Since the semiconductor device of the present invention has a long communication distance (high sensitivity) if it is the same size, even if the semiconductor device of the present invention is installed in a package, the package information can be received reliably. In addition, this system may be applied not only to a large package but also to small mail such as a sealed letter typified by registered mail or delivery record. In this case, the semiconductor device of the present invention that can be easily downsized is preferably used. Can do.

  FIG. 13 is a diagram showing a cross-sectional structure of a transistor constituting part of a circuit included in the semiconductor device of the present invention. FIG. 13 illustrates an n-channel transistor 2001, an n-channel transistor 2002, a capacitor element 2004, a resistor element 2005, and a p-channel transistor 2003. Each transistor includes a semiconductor layer 1305, a gate insulating layer 1308, and a gate electrode 1309. The gate electrode 1309 is formed with a stacked structure of a first conductive layer 1303 and a second conductive layer 1302. 14A to 14D are top views corresponding to the transistor, the capacitor, and the resistor shown in FIG. 13 and can be referred to together.

  In FIG. 13, an n-channel transistor 2001 is doped in a channel length direction (carrier flow direction) with an impurity region 1306 that forms a source and drain region connected to a wiring 1304 and a lower concentration than the impurity concentration. An impurity region 1307 is formed in the semiconductor layer 1305. The impurity region 1307 is also called a low concentration drain (LDD). In the case where the n-channel transistor 2001 is formed, phosphorus or the like is added to the impurity region 1306 and the impurity region 1307 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 14A, in the gate electrode 1309 of the n-channel transistor 2001, the first conductive layer 1303 is formed so as to spread on both sides of the second conductive layer 1302. In this case, the first conductive layer 1303 is formed thinner than the second conductive layer. The first conductive layer 1303 is formed to have a thickness that allows the ion species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 1307 is formed so as to overlap with the first conductive layer 1303 of the gate electrode 1309. That is, an LDD region overlapping with the gate electrode 1309 is formed. In this structure, an impurity region 1307 is formed in a self-aligned manner in the gate electrode 1309 by adding one conductivity type impurity through the first conductive layer 1303 using the second conductive layer 1302 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  Transistors having LDDs on both sides of the channel formation region are applied to transistors for rectification of a power supply circuit and transistors forming a transmission gate (also referred to as an analog switch) used in a logic circuit. In these transistors, since both positive and negative voltages are applied to the source electrode and the drain electrode, it is preferable to provide LDDs on both sides of the channel formation region.

  In FIG. 13, an n-channel transistor 2002 includes an impurity region 1306 that forms source and drain regions connected to a wiring 1304 in a semiconductor layer 1305, and an impurity region 1307 that is doped at a lower concentration than the impurity concentration. ing. The impurity region 1307 is provided on one side of the channel formation region so as to be in contact with the impurity region 1306. As shown in FIG. 14B, in the gate electrode 1309 of the n-channel transistor 2002, the first conductive layer 1303 is formed so as to spread on one side of the second conductive layer 1302. In this case as well, an LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 1303 using the second conductive layer 1302 as a mask.

  A transistor having an LDD on one side of the channel formation region may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 13, the capacitor element 2004 is formed by sandwiching a gate insulating layer 1308 between a first conductive layer 1303 and a semiconductor layer 1305. The semiconductor layer 1305 for forming the capacitor element 2004 includes an impurity region 1310 and an impurity region 1311. The impurity region 1311 is formed in a position overlapping with the first conductive layer 1303 in the semiconductor layer 1305. Further, the impurity region 1310 forms a contact with the wiring 1304. Since the impurity region 1311 can be doped with one conductivity type impurity through the first conductive layer 1303, the impurity concentration in the impurity region 1310 and the impurity region 1311 can be the same or different. It is. In any case, since the semiconductor layer 1305 functions as an electrode in the capacitor 2004, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 14C, the first conductive layer 1303 can function sufficiently as an electrode by using the second conductive layer 1302 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 1303 and the second conductive layer 1302 are combined, the capacitor element 2004 can be formed in a self-aligning manner.

  The capacitor element is used as a storage capacitor included in the power supply circuit or a resonance capacitor included in the resonance circuit. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

  In FIG. 13, the resistance element 2005 is formed by the first conductive layer 1303. Since the first conductive layer 1303 is formed to a thickness of about 30 to 150 nm, the resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element is used as a resistance load included in the modulation circuit. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 13, a p-channel transistor 2003 includes an impurity region 1312 in a semiconductor layer 1305. This impurity region 1312 forms source and drain regions connected to the wiring 1304. The gate electrode 1309 has a structure in which the first conductive layer 1303 and the second conductive layer 1302 overlap each other. The p-channel transistor 2003 is a single drain transistor without an LDD. In the case of forming the p-channel transistor 2003, boron or the like is added to the impurity region 1312 as an impurity imparting p-type conductivity. On the other hand, when phosphorus is added to the impurity region 312, an n-channel transistor having a single drain structure can be obtained.

One or both of the semiconductor layer 1305 and the gate insulating layer 1308 are excited by microwaves, have an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by high density plasma treatment. At this time, the temperature of the substrate is set to 300 to 450 ° C., and the treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, or the like) or a nitriding atmosphere (N ₂ , NH _3, or the like). The defect level of can be reduced. By performing this treatment on the gate insulating layer 1308, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 1308. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 1305 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 1308 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 2004. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 13 and 14, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 14A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  13 and 14, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used as the first conductive layer, and a tungsten film can be used as the second conductive layer.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same patterning process using a photomask or reticle provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  An example of forming a static RAM (SRAM) as one of the elements constituting the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

  The semiconductor layers 10 and 11 illustrated in FIG. 15A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. The semiconductor layer is etched using the mask pattern to form island-shaped semiconductor layers 10 and 11 having a specific shape including the source and drain regions of the TFT and the channel formation region. The semiconductor layers 10 and 11 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layers 10 and 11 shown in FIG. 15A includes a mask pattern 2000 shown in FIG. The mask pattern 2000 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, the mask pattern 2000 shown in FIG. 15B is manufactured as a light shielding portion. The mask pattern 2000 has a shape obtained by deleting the top A of the polygon. Further, the bent portion B has a shape that is bent over a plurality of steps so that the corner (inside the corner) does not become a right angle. In the photomask pattern, for example, the corners of the pattern (right triangles) are removed so that one side is 10 μm or less.

  The shape of the mask pattern 2000 shown in FIG. 15B is reflected in the semiconductor layers 10 and 11 shown in FIG. In that case, a shape similar to the mask pattern 2000 may be transferred, but it may be transferred so that the corners of the mask pattern 2000 are further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 2000 may be provided.

  On the semiconductor layers 10 and 11, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as shown in FIG. 16A, gate wirings 12, 13, and 14 are formed so as to partially overlap the semiconductor layer. The gate wiring 12 is formed corresponding to the semiconductor layer 10. The gate wiring 13 is formed corresponding to the semiconductor layers 10 and 11. The gate wiring 14 is formed corresponding to the semiconductor layers 10 and 11. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

  A photomask for forming this gate wiring is provided with a mask pattern 2100 shown in FIG. This mask pattern 2100 is a corner, and one side of the (right triangle) is 10 μm or less, or less than 1/2 of the line width of the wiring, and the corner is deleted to a size of 1/5 or more of the line width. is doing. The shape of the mask pattern 2100 shown in FIG. 16B is reflected in the gate wirings 12, 13, and 14 shown in FIG. In that case, a shape similar to the mask pattern 2100 may be transferred, or the corner of the mask pattern 2100 may be transferred so as to be further rounded. That is, the gate wirings 12, 13, and 14 may be rounded so that the pattern shape is smoother than the mask pattern 2100. That is, the corners of the gate wirings 12, 13, and 14 may be rounded at the corners that are 1/2 or less of the line width and 1/5 or more. The convex portions (outside the corner portions) of the gate wirings 12, 13, and 14 can suppress generation of fine powder due to abnormal discharge during dry etching using plasma. In the recess (inside the corner portion), even when fine powder is adhered to the substrate during cleaning, the cleaning liquid can be washed away without staying in the corner portion of the wiring pattern, and a significant improvement in yield can be expected.

  The interlayer insulating layer is a layer formed next to the gate wirings 12, 13 and 14. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material such as polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 12, 13, and 14. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the TFT, such as exogenous metal ions and moisture.

  Openings are formed in predetermined positions in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 17A, wirings 15 to 20 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 15 to 20 includes a mask pattern 2200 shown in FIG. Also in this case, the wiring is each corner portion bent into an L shape, and one side of the right triangle is 10 μm or less, or 1/2 or less of the wiring line width and 1/5 or more of the line width. Remove the corners and make the corners rounded. That is, the outer periphery of the wiring layer at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring layer corresponding to the right isosceles triangular portion formed by is removed. When removed, two obtuse angle parts are newly formed in the wiring layer. By appropriately setting the mask design and etching conditions, a curve that touches both the first straight line and the second straight line is formed at each obtuse angle part. It is preferable to etch the wiring layer as described above. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. Such a wiring shape can suppress generation of fine powder due to abnormal discharge during dry etching using plasma. Further, when the substrate is cleaned, even if fine powder adheres to the substrate, the cleaning liquid can be washed away without staying in the corner portion of the wiring pattern, and as a result, the yield is improved. This is also an advantage that when there are a large number of parallel wirings on the substrate, the attached fine powder can be easily removed by washing. It can be expected that the corner portion of the wiring is electrically conducted by taking a round. In addition, a large number of parallel wires are very convenient for washing away dust.

  In FIG. 17A, n-channel transistors 21 to 24 and p-channel transistors 25 and 26 are formed. The n-channel transistor 23 and the p-channel transistor 25, and the n-channel transistor 24 and the p-channel transistor 26 constitute an inverter. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

1 is a block diagram illustrating a structure of a semiconductor device according to the present invention. 1 is a plan view of a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. Sectional drawing of the connection part of the analog part and 1st antenna in the semiconductor device of this invention. FIG. 10 illustrates a structure of a semiconductor device capable of transmitting and receiving data by conventional wireless communication. (A) FIG. 14 illustrates one embodiment of a semiconductor device of the invention. FIG. 10 illustrates one embodiment of a semiconductor device of the invention. FIG. 10 illustrates one embodiment of a semiconductor device of the invention. FIG. 10 illustrates one embodiment of a semiconductor device of the invention. 8A and 8B illustrate a method for manufacturing a semiconductor device of the present invention. 1 is a diagram showing a system using a semiconductor device of the present invention. FIG. 11 illustrates uses of a semiconductor device of the present invention. FIG. 10 is a cross-sectional view of part of the semiconductor device of the invention. FIG. 6 is a top view of part of the semiconductor device of the present invention. FIG. 6 is a top view of part of the semiconductor device of the present invention. FIG. 6 is a top view of part of the semiconductor device of the present invention. FIG. 6 is a top view of part of the semiconductor device of the present invention. 1 is a diagram showing a system using a semiconductor device of the present invention.

Explanation of symbols

10 semiconductor layer 11 semiconductor layer 12 gate wiring 13 gate wiring 14 gate wiring 15 wiring 21 n-channel transistor 23 n-channel transistor 24 n-channel transistor 25 p-channel transistor 26 p-channel transistor 100 read / write communication control circuit 101 antenna Part 102 first antenna 103 second antenna 104 analog part 105 digital part 200 VDD wiring 201 GND wiring 210 intersecting part 220 electrically connecting part 300 substrate 301 base film 302 first insulating film 303 second insulation Film 312 Impurity region 400 Semiconductor layer 401 Gate insulating film 402 Gate electrode 402 Gate electrode 403 Wiring 404 Wiring 500 Tag 501 Wiring forming layer 502 Antenna 503 Antenna forming layer 506 Resonance capacitance part 600 Third insulating film 700 Semiconductor device 800 Entrance 801 Semiconductor device 802 Reader / writer 803 House 804 Display unit 805 Article 1302 Second conductive layer 1303 First conductive layer 1304 Wiring 1305 Semiconductor layer 1306 Impurity region 1307 Impurity region 1308 Gate Insulating layer 1309 Gate electrode 1310 Impurity region 1311 Impurity region 1312 Impurity region 2000 Mask pattern 2001 n-channel transistor 2002 n-channel transistor 2003 p-channel transistor 2004 Capacitor element 2005 Resistor element 2100 Mask pattern 2200 Mask pattern 3301 Display unit 3302 Reader / Writer 3303 Article 3304 Reader / Writer 3305 Article 6500 Tag 6501 Wiring forming layer 6502 Antenna 6503 Ann Na-forming layer

Claims (6)

A substrate,
A tag portion including a circuit made of a thin film element provided on the substrate;
A first antenna and a second antenna;
The first antenna and the second antenna are formed in different layers separated by an insulating film,
The first antenna and the second antenna are electrically connected in part,
The first antenna is formed in the same layer with the same material as the source or drain wiring connected to the thin film element, and the second antenna is a source or drain wiring connected to the thin film element. The semiconductor device is formed in a different layer. A substrate,
A tag portion including a circuit made of a thin film element provided on the substrate;
A first antenna and a second antenna;
The first antenna and the second antenna are formed in different layers separated by an insulating film,
The first antenna and the second antenna are electrically connected in part,
The first antenna is formed in the same layer with the same material as the source or drain wiring connected to the thin film element, and the second antenna is a source or drain wiring connected to the thin film element. And is formed in a different layer,
The semiconductor device, wherein the first antenna and the second antenna do not overlap except for a portion that is electrically connected to an intersecting portion when viewed from a direction perpendicular to the substrate. In claim 1 or claim 2,
The thin film element includes a thin film transistor including a semiconductor layer, a gate insulating film, and a gate electrode,
The circuit and the first antenna are electrically connected;
A wiring for connecting the circuit and the first antenna is formed of the same material and in the same layer as the gate electrode of the thin film transistor. In claim 3,
2. The semiconductor device according to claim 1, wherein the gate electrode is formed using an alloy or a compound including one or more selected from tantalum, tungsten, titanium, molybdenum, aluminum, copper, chromium, and niobium. In any one of Claims 1 thru | or 4,
The first antenna is formed using an alloy or a compound selected from one or more selected from aluminum, nickel, tungsten, molybdenum, titanium, platinum, copper, tantalum, gold, and manganese. Semiconductor device. In any one of Claims 1 thru | or 5,
The second antenna is formed using an alloy or compound of one or more selected from aluminum, nickel, tungsten, molybdenum, titanium, platinum, copper, tantalum, gold, and manganese. Semiconductor device.

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