JP2007005443A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a manufacturing cost of a multi-chip package. <P>SOLUTION: A flash memory chip 1M and a controller chip 1C are sealed in a resin package 2 of the multi-chip package (MCP1). Respective centers of opposed two long sides of the resin package 2 go back to the center side of the resin package 2 from opposite ends thereof. An outer lead 6o disposed along the two long sides of the resin package 2 among outer leads 6o connected to the controller chip 1C is taken out outward from the central part of the resin package 2, and tip ends thereof are located to the center side of the resin package 2 from the opposite ends. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique that is effective when applied to a multichip package on which a plurality of semiconductor chips each having a different integrated circuit are mounted.

  As data storage media for various portable information terminal devices such as cellular phones, memory cards incorporating a plurality of flash memory chips and memory cards incorporating a flash memory chip and an interface controller for controlling the operation thereof are used. Yes.

Japanese Patent Application Laid-Open No. 2004-13738 (Patent Document 1) discloses a memory card that uses an inexpensive material to reduce the manufacturing cost. The memory card disclosed in this publication is composed of a thin plate-like cap made of synthetic resin and a sealing portion mounted inside the cap. Inside the sealing portion, a metal lead frame and three semiconductor chips (two memory chips and one controller chip) mounted on a part (lead) of the lead frame are sealed. Has been. These chips are electrically connected to leads via Au wires, and connection terminals formed integrally with the lead frame are exposed on the back surface of the sealing portion.
JP 2004-13738 A

  In recent years, with the increase in the number of functions of portable information terminal devices, the types and sizes of memory cards have been steadily increasing. In particular, in the case of a memory card in which different types of chips are mixedly mounted, such as a memory card in which a memory chip and a controller chip are combined, the number of external connection terminals differs depending on the type even if the package size is the same.

  Therefore, when performing an electrical test to determine whether a memory card is a good product or a defective product, a different test socket must be prepared for each product type, which is a factor that increases the manufacturing cost of the memory card. It has become.

  An object of the present invention is to provide a technique for reducing the manufacturing cost of a multichip package in which different types of chips are mixedly mounted.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device of the present invention includes a plurality of inner leads provided on a lead frame, and a first device mounted on one surface of the lead frame and electrically connected to a part of the plurality of inner leads via wires. A semiconductor chip and a second semiconductor chip mounted on one surface of the first semiconductor chip via the lead frame or directly connected to the other parts of the plurality of inner leads via wires Are sealed in a resin package, and the first semiconductor chip and the second semiconductor chip are formed with different integrated circuits, and the resin package includes first and second sides facing each other; A third side and a fourth side opposite to each other, and the first and second sides have their center portions set back toward the center side of the resin package from both ends, The part of the inner leads electrically connected to one semiconductor chip is drawn outward from at least one of the third and fourth sides of the resin package to form an outer lead, and the second lead The inner lead of the other part electrically connected to the semiconductor chip is drawn outward from the central part of at least the first and second sides of the resin package to constitute an outer lead, Each of the outer leads projecting outward from the central portion is positioned closer to the center of the resin package than the both end portions.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Since it is possible to perform an electrical test of different types of multi-chip packages using a common test socket, the manufacturing cost of the multi-chip package can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The semiconductor device of the present embodiment is a multi-chip package for a small memory card that is used by being mounted on, for example, a mobile phone. FIG. 1 is a plan view showing the appearance of the multichip package of the present embodiment, FIGS. 2 and 3 are views showing the internal structure of the multichip package shown in FIG. 1, and FIG. FIG. 3 is a plan view seen from the lower surface side of the multi-chip package for a small memory card, FIG. 4 is a sectional view taken along line AA in FIG. 1, and FIG. FIG. 2 is a cross-sectional view taken along line BB in FIG. 1.

  The multi-chip package (MCP1) includes a first semiconductor chip (hereinafter referred to as a flash memory chip) 1M in which an electrically erasable and writable nonvolatile memory (flash memory) is formed, and a memory for the flash memory chip 1M A second semiconductor chip (hereinafter referred to as controller chip) 1C on which an interface controller for controlling the interface operation is formed has a SOP (Small-Outline Package) structure sealed in a rectangular resin package 2. The flash memory chip 1M is a chip having a storage capacity of 32 megabytes to 16 gigabytes. In the present embodiment, a chip having a storage capacity of 1 gigabyte is illustrated.

  The flash memory chip 1M is a chip in which a semiconductor element is formed on a semiconductor substrate (rectangular single crystal silicon), and is sealed in the resin package 2 with its main surface (integrated circuit formation surface) facing downward. ing. As shown in FIG. 3, on the main surface of the flash memory chip 1M, a plurality of (for example, 24) bonding pads 3 are arranged in a line along one of a pair of short sides. In FIG. 3, the number of bonding pads 3 is shown to be smaller than the actual number in order to simplify the description. In the vicinity of the short side where the bonding pads 3 are arranged, a plurality of inner leads 5 i are arranged, and the inner leads 5 i and the corresponding bonding pads 3 are electrically connected by Au wires 7. ing. The other end side of each inner lead 5 i is drawn outward from one of a pair of short sides of the resin package 2 to constitute an outer lead 5 o. That is, the outer lead 5o functions as an external connection terminal of the flash memory chip 1M. The number of outer leads 5o is, for example, 24. The resin package 2 is made of a thermosetting resin such as an ortho-cresol novolac type epoxy resin or a biphenyl type epoxy resin, and has a major purpose of sealing the flash memory chip 1M and the controller chip 1C satisfactorily. As one of them.

  On the other hand, the controller chip 1C is smaller than the flash memory chip 1M and is a chip in which a semiconductor element is formed on a semiconductor substrate (substantially square single crystal silicon), and its main surface (integrated circuit formation surface) faces upward. It is mounted on the upper surface of the flash memory chip 1M. On the upper surface of the flash memory chip 1M, as an adhesive sheet, a die attach film (Die Attach Film) 8 coated with an adhesive on both sides is attached. The controller chip 1C is flashed via the die attach film 8. It is bonded to the upper surface of the memory chip 1M.

  As shown in FIG. 2, a plurality of (for example, 64) bonding pads 4 are arranged in a row along the four sides on the main surface of the controller chip 1C. In FIG. 2, the number of bonding pads 4 is shown to be smaller than the actual number in order to simplify the description. Further, a plurality of inner leads 6i are arranged in the vicinity of each side of the controller chip 1C, and each inner lead 6i and the corresponding bonding pad 4 are electrically connected by Au wires 7. Yes. These inner leads 6i are bonded to the upper surface of the flash memory chip 1M via the die attach film 8 described above.

  The other end side of the inner lead 6i is drawn outward from three sides (one short side and two long sides) of the resin package 2 to constitute an outer lead 6o. That is, the outer lead 6o functions as an external connection terminal of the controller chip 1C.

  Also, some of the two long side inner leads 6i of the multichip package MCP1 are longer than the length of the other long side inner leads 6i. The partial inner leads 6i are arranged at the center of the multi-chip package MCP1, and among the four sides of the controller chip 1C, inner leads 5i and outer leads 5o that are electrically connected to the flash memory chip 1M are arranged. It is arrange | positioned along one side of the side by which it is carried out, and is electrically connected with the bonding pad 4 of the main surface of the controller chip 1C. The length of some of the inner leads 6i is longer than half of the short side length of the multichip package MCP1, so as to be longer than half of the short side length of the flash memory chip 1M, or There are some chips that are formed to be longer than the length of one side of the controller chip 1C. In this way, by making the length of some of the inner leads 6i longer than the length of the other inner leads 6i, it is possible to wire-connect with the bonding pads 4 arranged on the four sides of the controller chip 1C. Become.

  Further, in the present embodiment, the arrangement positions of some of the inner leads 6i are outer leads 5o and inner leads 5i that are electrically connected to the flash memory chip 1M, dummy inner leads 6di described later, The inner leads 6i, the controller chip 1C, and the inner leads 6i and outer leads 6o on the short side of the multichip package MCP1 are arranged.

  Of these outer leads 6o, the number of outer leads 6o drawn from the short side of the resin package 2 is the same as the number of outer leads 5o drawn from the other short side of the resin package 2 (for example, 24). Further, the number of outer leads 6o drawn outward from the two long sides of the resin package 2 is 64-24 = 40 when the number of bonding pads 4 of the controller chip 1C is 64. Further, for example, a plurality of bonding pads 4 constituting a power supply (Vcc) terminal are connected to one outer lead 5o, or a plurality of bonding pads 4 constituting a GND terminal are connected to one outer lead 5o. As a result, the number of outer leads 5o drawn outward from the two long sides can be reduced to less than 40.

  In the multichip package (MCP1) of the present embodiment, the central portions of the two opposing long sides of the resin package 2 are set back toward the center of the resin package 2 from both ends thereof. The plurality of outer leads 6o arranged along the two long sides of the resin package 2 are drawn outward from the center portion of the resin package 2, and their tips are more resin than the both end portions. It is located on the center side of the package 2. That is, as shown in FIG. 5, the tip of the outer lead 6o drawn outward from the center of the long side of the resin package 2 has a length α (α is a positive value) than both ends of the long side of the resin package 2. The number is set back inside the resin package 2. The outer leads 5o and 6o are bent into a gull wing shape so that the multi-chip package (MCP1) is solder-mounted on the wiring board of the small memory card. For this reason, when the length α is increased, the length of the outer lead 5o is shortened, making bending difficult. Further, when the length of the outer lead 5o is shortened, the area in contact with the electrode of the wiring board is also reduced, and the connection reliability between the outer lead 5o and the electrode is lowered. Therefore, it is desirable that the length α be as close to 0 as possible within the allowable range of processing errors.

  The resin package 2 is made of, for example, an epoxy resin having a long side = 15.4 mm, a short side = 12.0 mm, and a thickness = 0.62 mm. The flash memory chip 1M has a thickness of 0.08 mm, for example, and the controller chip 1C has a thickness of 0.08 to 0.16 mm, for example. The inner leads 5i and 6i and the outer leads 5o and 6o are made of, for example, 42 alloy having a thickness of 0.1 mm or copper.

  As shown in FIG. 2, the outer lead 6o drawn outward from the center of the long side of the resin package 2 includes a dummy outer lead 6do that is not connected to the controller chip 1C. The dummy outer lead 6do is configured integrally with a dummy inner lead 6di disposed inside the resin package 2. The dummy inner lead 6di is a lead that is not electrically connected to the flash memory chip 1M and the controller chip 1C, and therefore the outer lead 6do does not function as an external terminal. The inner lead 6di and the outer lead 6do are formed so as to be covered with the resin package 2, and the outer lead 6do is not supplied with a voltage from the outside.

  The dummy inner lead 6di is extremely thin (for example, 0.08 mm) in order to ensure the flatness of the flash memory chip 1M and prevent the flash memory chip 1M from being deformed when the resin package 2 is molded. It is bonded to the upper surface of the flash memory chip 1M via the die attach film 8 described above. Further, the controller chip 1C and the inner leads 6i arranged around the controller chip 1C have a function of ensuring the flatness of the flash memory chip 1M together with the dummy inner leads 6di. Accordingly, the dummy inner lead 6di is disposed so as to cover a region where the controller chip 1C and the inner lead 6i are not disposed on the upper surface of the flash memory chip 1M.

  In order to assemble the multichip package (MCP1) of the present embodiment, first, the flash memory chip 1M and the controller chip 1C described above and the lead frame LF shown in FIG. 6 are prepared. The lead frame LF includes the above-described inner leads 5i and 6i and outer leads 5o and 6o (including dummy inner leads 6di and outer leads 6do) and a frame body 9 that supports them. However, the outer lead 6do and the inner lead 6di can take advantage of the insulating properties of the insulating die-bonding film and adhesive to apply a potential such as a power supply ground or a power supply (Vcc) as necessary. FIG. 6 shows a part of the lead frame LF (for two packages). The actual lead frame LF has, for example, a multiple structure capable of simultaneously molding eight packages.

  The flash memory chip 1M is obtained by polishing the back surface of a silicon wafer on which a flash memory is formed by a known manufacturing method to reduce the thickness to 0.08 mm, and then dicing the silicon wafer. The controller chip 1C is obtained by polishing the back surface of the silicon wafer on which the interface controller is formed by a well-known manufacturing method to reduce the thickness to 0.08 to 0.16 mm, and then dicing the silicon wafer. It is done. When dicing the silicon wafer on which the flash memory is formed, the above-described die attach film 8 and dicing tape are attached to the back surface thereof. In this way, since the controller chip 1C having the die attach film 8 attached to the back surface is obtained, it is not necessary to apply an adhesive when mounting the flash memory chip 1M on the lead frame LF. The same applies to the case where the chip thickness is polished to a thickness of 0.08 mm or less as required.

  Next, as shown in FIG. 7, the flash memory chip 1M is fixed at a predetermined position of the lead frame LF by attaching the inner lead 6i and the dummy inner lead 6di to the die attach film 8 on the back surface of the flash memory chip 1M. After that, the controller chip 1 </ b> C is attached to a predetermined position of the die attach film 8. Subsequently, the flash memory chip 1M and the controller chip 1C are simultaneously mounted on the lead frame LF by heating the lead frame LF and thermosetting the adhesive applied to the die attach film 8.

  As another method for mounting the flash memory chip 1M and the controller chip 1C on the lead frame LF, for example, after the flash memory chip 1M is attached to the lead frame LF using a known adhesive, the controller chip 1C is attached to the flash memory chip 1M. There is a method to paste. Further, after the flash memory chip 1M is attached to the lead frame LF using an adhesive tape previously attached to the inner lead 6i, the controller chip 1C is attached to the flash memory chip 1M using a known adhesive. There is also a method. However, since the method using the die attach film 8 described above is simpler than these methods, it is effective in reducing the manufacturing cost of the multichip package (MCP1).

  Next, the bonding pad 3 of the flash memory chip 1M and the inner lead 5i are connected by the Au wire 7, the bonding pad 4 of the controller chip 1C and the inner lead 6i are connected by the Au wire 7, and then the lead frame LF is molded. The flash memory chip 1M, the controller chip 1C, the inner leads 5i and 6i, and the Au wire 7 are sealed in the resin package 2 after being mounted on the mold. Subsequently, after cutting and removing unnecessary portions such as a tie bar region of the lead frame LF exposed to the outside of the resin package 2, the outer leads 5o and 6o are bent into a gull wing shape to obtain the above-described FIGS. The multi-chip package (MCP1) shown is obtained.

  Of the inner leads 5i connected to the flash memory chip 1M and the inner leads 6i connected to the controller chip 1C, those having a common function (for example, a GND terminal) may be configured by a common inner lead. it can. In this way, since the number of outer leads 6o drawn outward from the two long sides of the resin package 2 can be reduced, the design of the lead frame LF is facilitated.

  As described above, the multi-chip package (MCP1) of the present embodiment has the flash memory chip 1M and the controller chip 1C mounted on the lead frame LF, which is an inexpensive material, and sealed with the resin package 2. There is an advantage that the material cost can be reduced compared with the multi-chip package in which the memory chip 1M and the controller chip 1C are mounted on the wiring board.

  Next, an electrical test is performed to determine whether the multichip package (MCP1) manufactured by the above method is a good product or a defective product. This electrical test is performed with the multi-chip package (MCP1) mounted in a test socket connected to the tester.

  When performing the electrical test of the multi-chip package (MCP1), for example, the same test socket as that used when performing the electrical test of another type of multi-chip package (MCP2) as shown in FIGS. 8 and 9 is used. To do.

  The multi-chip package (MCP2) has an SOP structure in which two flash memory chips 1M are sealed in a resin package 2. The dimensions of the resin package 2 are the same as those of the multichip package (MCP1) of the present embodiment. The two flash memory chips 1M are the same as the flash memory chip 1M used in the multi-chip package (MCP1) of the present embodiment, and one of the two flash memory chips 1M faces down. The other side is bonded to the lower surface of the die pad portion 10 and the other side is bonded to the upper surface of the die pad portion 10 with its main surface facing upward.

  The bonding pad 3 formed on the main surface of one flash memory chip 1M and the inner lead 5i disposed in the vicinity thereof are electrically connected by an Au wire 7. The other end side of the inner lead 5i is drawn outward from one of a pair of short sides of the resin package 2 to constitute an outer lead 5o. Further, the bonding pad 3 formed on the main surface of the other flash memory chip 1M and the inner lead 5i disposed in the vicinity thereof are electrically connected by the Au wire 7. The other end side of the inner lead 5i is drawn outward from the other of the pair of short sides of the resin package 2 to constitute an outer lead 5o. The number of outer leads 5o drawn from the pair of short sides of the resin package 2 is the same as that of the multichip package (MCP1) of the present embodiment (for example, 24 + 24).

  FIG. 10 is a cross-sectional view of an essential part of a test socket used when an electrical test of the multichip package (MCP2) is performed. The test socket 20 includes a resin socket body 21 and a carrier 22 that houses a multi-chip package (MCP2). The same number of terminals 23 as the outer leads 5o of the multi-chip package (MCP2) are embedded in the socket body 21, and one end of each terminal 23 is exposed at the bottom of the carrier 22. Further, the other end of each terminal 23 is connected to a tester (not shown) so that a predetermined test signal is supplied.

  When performing an electrical test, the multichip package (MCP2) is accommodated in the carrier 22 using tweezers or the like. Then, since each of the outer leads 5o comes into contact with the corresponding terminal 23, the lower end of the pusher 24 is pressed against the outer lead 5o, and the outer lead 5o is adhered and fixed to the terminal 23. Then, a test signal is supplied from the tester to each flash memory chip 1M through the terminal 23 to perform an electrical test.

  On the other hand, when the multi-chip package (MCP1) of the present embodiment is accommodated in the carrier 22 of the test socket 20, each of the outer leads 5o connected to the flash memory chip 1M comes into contact with the corresponding terminal 23. In addition, among the outer leads 6o connected to the controller chip 1C, each of the outer leads 6o drawn from the short side of the resin package 2 comes into contact with the corresponding terminal 23. As described above, the tips of the outer leads 6o drawn outward from the two long sides of the resin package 2 are located closer to the center of the resin package 2 than both ends of the long side. When the (MCP1) is accommodated in the carrier 22 of the test socket 20, these outer leads 6o do not hinder. Therefore, a test signal is supplied only to the terminal 23 that is in contact with the outer lead 5o connected to the flash memory chip 1M to determine whether the flash memory chip 1M is good or bad. On the other hand, whether the controller chip 1C is good or bad is determined by an electrical test using another test socket having terminals that contact the outer leads 6o connected to the controller chip 1C.

  As described above, when the electrical test of the multi-chip package (MCP1) of the present embodiment is performed, it is only necessary to newly create a test socket for determining whether the controller chip 1C is good or bad. As the test socket 20 for determining whether the chip 1M is good or bad, the test socket 20 used when performing an electrical test of another type of multi-chip package (MCP2) is used as it is. As a result, the cost for creating the test socket can be reduced, and thus the manufacturing cost of the multichip package (MCP1) can be reduced.

  Further, when the multi-chip package (MCP1) of the present embodiment is transported, a transport tray created for another type of multi-chip package (MCP2) can be used, so that the cost for creating the transport tray is also reduced. be able to.

  In addition, by separately determining whether the flash memory chip 1M sealed in the same resin package 2 is good or bad and the controller chip 1C good or bad, one of the flash memory chip 1M and the controller chip 1C is good. The multi-chip package (MCP1) determined to be can be recycled. That is, by using a combination of a multi-chip package (MCP1) in which only the flash memory chip 1M is a non-defective product and a multi-chip package (MCP1) in which only the controller chip 1C is a non-defective product, one multi-chip package (MCP1) is used. A product with the same function can be obtained.

  FIG. 11 is a diagram in which the multi-chip package (MCP1) is mounted on the upper surface of the wiring board 31. FIG. This multi-chip package (MCP1) is covered with a cap (resin sealing body) 33 described in FIGS. 13 to 15 to constitute a memory card 30a as shown in FIG. The external dimensions of the memory card 30a are, for example, a long side of about 24 mm, a short side of about 18 mm, and a thickness of about 1.4 mm. This dimension is a dimension standardized by the Multimedia Card Association, and this memory card 30a is referred to as a reduced size MMC (hereinafter referred to as RSMMC). The memory card 30a can be used for a small electronic device such as a mobile phone or a digital camera, for example, as long as it has the above-mentioned outer dimensions, but by attaching a metal adapter (auxiliary device) 34 or the like. The structure can be used for relatively large electronic devices such as portable personal computers. Further, on the wiring substrate 31, a passive element 32 such as a chip capacitor element or a chip resistance element can be provided as necessary.

  FIG. 12 is a view showing the back surface of the wiring board 31, and external terminals C1 to C7 are provided. These external terminals C1 to C7 are RSV (reserve), CMD, Vss1 (first ground terminal), Vdd (power supply terminal), CLK (clock terminal), Vss2 (second ground terminal), and DAT (data terminal), respectively. It is a functioning terminal. The signal terminals of the flash memory chip 1M and the controller chip 1C formed in the multi-chip package (MCP1) are connected to the external terminals C1 to C7 by wiring (not shown) formed on the wiring board 31. And are electrically connected.

  FIG. 13 is a view showing a cap (resin sealing body) 33 that covers the upper surface of the wiring substrate 31 and the multichip package (MCP1). The cap 33 is provided with a fitting part 35a and a claw hook part 35b which are parts for connecting to the adapter 34 shown in FIG. The cap 33 is made of, for example, polycarbonate, ABS resin (acrylonitrile butadiene styrene resin), PBT (polybutylene terephthalate), PPE (Poly Phenylen Ether), from the viewpoint of weight reduction, processability and flexibility. It is made of a thermoplastic resin such as nylon, LCP (liquid crystal polymer), PET (polyethylen terephtalate) or a mixture thereof.

  14 is a cross-sectional view taken along the line XX of FIG. 13, and FIG. 15 is an adhesive (not shown) for bonding the multichip package (MCP1) mounted on the wiring board 31 into the groove 36 of the cap 33. It is sectional drawing which shows the state mounted via.

  FIG. 17 shows a memory card 30b when the multi-chip package (MCP1) mounted on the wiring board 31 shown in FIGS. 11 and 12 is covered with another type of cap (resin sealing body) 37. FIG. 18 is a cross-sectional view taken along line YY of FIG. The external dimensions of the memory card 30b are, for example, a long side of about 32 mm, a short side of about 24 mm, and a thickness of about 1.4 mm. This dimension is the same as the multimedia card (MMC) standardized by the Multimedia Card Association.

  FIG. 19 is a cross-sectional view showing a state in which the multichip package (MCP1) mounted on the wiring board 31 is mounted in the groove 36 of the cap 37 via an adhesive (not shown). The groove 36 is the same as the groove provided in the cap 33 of the memory card 30a described above, and the groove 36 has such a shape that the multichip package (MCP1) mounted on the wiring board 31 of FIG. is there. FIG. 20 is an external view showing the back surface of the memory card 30b.

  FIGS. 21 to 24 show a memory card 30c in which the multi-chip package (MCP1) mounted on the wiring board 31 shown in FIGS. 11 and 12 is applied with the SD card dimensions standardized by the SD card association. FIG. The external dimensions are, for example, a long side of 32 mm, a width of 24 mm, and a thickness of 2.1 mm. The external shape of the memory card 30c is formed by the first and second cases 38a and 38b.

  As shown in FIGS. 21 to 23, the chamfered portion CF1 for index is standardized, makes it easy to recognize the mounting direction when the memory card 30c is mounted in a desired electronic device, and the memory card. Has a function of preventing the connector from being inserted into the connector in the opposite direction. In addition, grooves 39a and 39b that are recessed in the short direction of the memory card 30c are formed in a part of both long sides of the cases 38a and 38b. The exposed portion 40a of the switch 40 is exposed from the groove 39a on one long side. The switch 40 is a switch for switching whether data can be written. The exposed portion 40a of the switch 40 is movable in the longitudinal direction of the memory card 30c. In this example, the electronic device optically or mechanically reads the position of the exposed portion 40a of the switch 40 and automatically determines whether or not data can be written according to the read position of the exposed portion 40a. Has been. On the other hand, the long side groove 39b on the other side of the cases 38a, 38b is a groove for realizing a latch mechanism that prevents the memory card 30c from being inadvertently removed from a desired electronic device.

  In the vicinity of the front surface side of the second case 38b on the back surface side of the memory card 30c, for example, a plurality of planar rectangular openings 41 are opened at predetermined intervals in a line along the short side of the front surface side of the memory card 30c. It is formed (FIG. 23). The external connection terminals C1 to C9 are exposed from the opening 41. Here, a state in which nine external connection terminals C1 to C9 are exposed is illustrated. Two external connection terminals C8 and C9 are exposed from the rightmost opening 41 in FIG.

  FIG. 24 shows an exploded perspective view of the memory card 30c shown in FIGS. The memory card 30c has a first case 38a, a second case 38b, a switch 40 and a multichip package (MCP1) mounted on the wiring board 31, and is mounted on the switch 40 and the wiring board 31. The multi-chip package (MCP1) is held so as to be sandwiched between the cases 38a and 38b.

(Embodiment 2)
FIG. 25 is a plan view showing the internal structure of the multichip package of the present embodiment. For example, as shown in FIG. 25, the die pad portion 10a may be disposed on the upper surface of the flash memory chip 1M, and the controller chip 1C may be bonded onto the die pad portion 10a. In this case, the die pad portion 10a is effective in ensuring the flatness of the thin flash memory chip 1M. In addition, as shown in FIG. 26, the controller chip 1C is arranged inside the frame-shaped die pad portion 10b, and the controller chip 1C is bonded directly or via the die attach film 8 to the back surface of the flash memory chip 1M. Good.

  By using the die pad portions 10a and 10b as described above, when a flash memory having a large chip size and a thin thickness is resin-molded in a mold, deformation of the chip is bent or bent due to pressure during resin flow. Can be suppressed.

(Embodiment 3)
The flash memory chip 1M used in the above embodiment has the bonding pad 3 disposed on one of the pair of short sides, but uses a flash memory chip in which the bonding pad 3 is disposed on each of the pair of short sides. May be. In this case, the outer leads 5o that function as external connection terminals of the flash memory chip 1M are drawn outward from the two long sides of the resin package 2, and the outer leads 6o that function as external connection terminals of the controller chip 1C are resin. It is pulled out from the two long sides of the package 2. At this time, the unused short-side lead that is not connected to the bonding wire in the flash memory 1M can also be used for connection to the controller. In particular, this is effective for a flash memory having a large number of I / Os and a x16 bit bus, and is effective for high-speed operation of the flash memory.

  In the present embodiment, the external connection terminals (outer leads 6o) of the controller chip 1C are arranged so as to be drawn outward from the two long sides of the resin package 2. However, as in FIG. 2 of the first embodiment. Of course, the resin package 2 may be arranged so as to be drawn out from three long sides or four long sides.

(Embodiment 4)
FIG. 27 is a plan view showing the internal structure of the multichip package of the present embodiment. In the third embodiment, an example in which one flash memory chip 1M is mounted is shown. However, in this embodiment, as shown in FIG. 27, two flash memory chips 1M and 1M and one controller chip are provided. It can also be applied to a multi-chip package in which 1C is sealed in a resin package 2.

  In this case, the outer lead 5o that functions as an external connection terminal of one flash memory chip 1M is drawn outward from one short side of the resin package 2, and the outer lead 5o that functions as an external connection terminal of the other flash memory chip 1M. The lead 5o is drawn out from the other short side of the resin package 2. Further, the outer leads 6o functioning as external connection terminals of the controller chip 1C are drawn outward from the two long sides of the resin package 2.

  In either case, the central portions of the two opposing long sides of the resin package 2 are set back toward the center of the resin package 2 from both ends thereof. And the front-end | tip of the outer lead 6o pulled out outward from two long sides of the resin package 2 is located in the center side of the resin package 2 rather than the said both ends.

  As described above, when two flash memory chips 1M and 1M are mounted, not only can the memory capacity be doubled, but also the controller control method can be increased for each flash memory by interleave operation. Become. Of course, the configuration of the present embodiment can be used in combination with the above-described second or third embodiment, and similar effects can be obtained.

As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the flash memory chip 1M is exemplified as the first semiconductor chip on which the electrically erasable and writable nonvolatile memory is formed. As such a nonvolatile memory, an EEPROM (Electrically Erasable Programmable Lead Only Memory) is used. Alternatively, a phase change memory or a ferroelectric memory can be exemplified instead.

  The present invention can be applied to a multi-chip package in which different types of chips are mixedly mounted.

It is a top view which shows the external appearance of the multichip package which is one embodiment of this invention. FIG. 2 is a top plan view showing the internal structure of the multichip package shown in FIG. 1. FIG. 2 is a bottom plan view showing the internal structure of the multichip package shown in FIG. 1. It is sectional drawing along the AA line of FIG. It is sectional drawing along the BB line of FIG. It is a principal part top view of the lead frame used for manufacture of the multichip package which is one embodiment of this invention. It is a principal part top view of the lead frame which shows the manufacturing process of the multichip package which is one embodiment of this invention. It is a top view which shows the internal structure of the multichip package different from this invention. It is sectional drawing of the multichip package different from this invention. It is principal part sectional drawing of the test socket used when performing the electrical test of a multichip package. It is the perspective view which mounted the multichip package of this invention on the wiring board. It is a perspective view which shows the back surface of the wiring board by which the multichip package of this invention was mounted. It is a perspective view which shows the cap which covers the multichip package of this invention. It is sectional drawing along the XX line of FIG. It is sectional drawing of a memory card at the time of applying to RSMMC. It is a perspective view of the memory card at the time of applying to RSMMC. It is a perspective view which shows the cap which covers the multichip package of this invention. It is sectional drawing along the YY line of FIG. It is sectional drawing of a memory card at the time of applying to MMC. It is a perspective view of the memory card at the time of applying to MMC. It is a perspective view which shows the upper surface of a memory card at the time of applying to an SD card. It is a perspective view which shows the back surface of a memory card at the time of applying to an SD card. It is the principal part perspective view which expanded the opening part of FIG. It is a disassembled perspective view of the memory card at the time of applying to an SD card. It is a top view which shows the internal structure of the multichip package which is other embodiment of this invention. It is a top view which shows the internal structure of the multichip package which is other embodiment of this invention. It is a top view which shows the internal structure of the multichip package which is other embodiment of this invention.

Explanation of symbols

1M flash memory chip (first semiconductor chip)
1C controller chip (second semiconductor chip)
2 Resin package 3, 4 Bonding pad 5 i, 6 i Inner lead 5 o, 6 o Outer lead 6 di Dummy inner lead 6 do Dummy outer lead 7 Au wire 8 Die attach film 9 Frame body 10, 10 a, 10 b Die pad portion 20 Test socket 21 Socket Main body 22 Carrier 23 Terminal 24 Pusher CF1 Chamfered portion LF Lead frame MCP1, MCP2 Multi-chip packages 30a, 30b, 30c Memory card 31 Wiring board 32 Passive element 33 Cap 34 Adapter 35 Joint portion 35a Fitting portion 35b Claw hook portion 36 Groove 37 Caps 38a, 38b Cases 39a, 39b Groove 40 Switch 40a Exposed portion 41 Opening portion

Claims (11)

A plurality of inner leads provided on the lead frame;
A first semiconductor chip mounted on one surface of the lead frame and electrically connected to a part of the plurality of inner leads via wires;
The second semiconductor chip mounted on one surface of the first semiconductor chip via the lead frame or directly and electrically connected to the other part of the plurality of inner leads via a wire is a resin package Sealed
The first semiconductor chip and the second semiconductor chip are formed with different integrated circuits,
The resin package has first and second sides facing each other and third and fourth sides facing each other, and each of the first and second sides has a central portion from both ends. Also retracted to the center side of the resin package,
The part of the inner leads electrically connected to the first semiconductor chip is drawn outward from at least one of the third and fourth sides of the resin package to constitute an outer lead,
The other inner lead electrically connected to the second semiconductor chip is drawn outwardly from the central portion of at least the first and second sides of the resin package to serve as an outer lead. Configure
Each of the tips of the outer leads protruding outward from the central portion is located closer to the center of the resin package than the both end portions.   2. The integrated circuit formed on the first semiconductor chip is mainly a memory circuit, and the integrated circuit formed on the second semiconductor chip is mainly a logic circuit. Semiconductor device.   3. The semiconductor according to claim 2, wherein the memory circuit includes an electrically erasable and writable nonvolatile memory, and the logic circuit includes an interface controller that controls a memory interface operation with respect to the nonvolatile memory. apparatus. The part of the inner leads that are electrically connected to the first semiconductor chip are drawn outward from the third side of the resin package to form outer leads,
The other inner leads electrically connected to the second semiconductor chip are drawn outward from the first, second and fourth sides of the resin package to form outer leads. The semiconductor device according to claim 1. The part of the inner leads electrically connected to the first semiconductor chip are drawn outward from the third and fourth sides of the resin package to form outer leads,
The other inner lead electrically connected to the second semiconductor chip is drawn outward from the first and second sides of the resin package to form an outer lead. The semiconductor device according to claim 1.   2. The semiconductor device according to claim 1, wherein the second semiconductor chip is mounted on the first semiconductor chip through an adhesive layer formed on the back surface of the first semiconductor chip.   A structure that is adhered to the back surface of the first semiconductor chip, is not electrically connected to the first and second semiconductor chips, and is drawn outward from at least one of the first and second sides. The semiconductor device according to claim 1, further comprising an outer lead. A third semiconductor chip sealed in the resin package and formed with the same integrated circuit as the first semiconductor chip; and an inner lead electrically connected to the third semiconductor chip via a wire; Further comprising
The inner lead electrically connected to the first semiconductor chip is drawn outward from the third side of the resin package to constitute an outer lead,
The inner leads electrically connected to the second semiconductor chip are drawn outward from at least the first and second sides of the resin package to form outer leads,
2. The inner lead electrically connected to the third semiconductor chip is drawn outward from the fourth side of the resin package to constitute an outer lead. Semiconductor device.   2. The semiconductor device according to claim 1, wherein a thickness of the first semiconductor chip is the same as or thinner than a thickness of the lead frame. A plurality of inner leads provided on the lead frame;
A first semiconductor chip mounted on one surface of the lead frame and electrically connected to a part of the plurality of inner leads via wires;
The second semiconductor chip mounted on one surface of the first semiconductor chip via the lead frame or directly and electrically connected to the other part of the plurality of inner leads via a wire is a resin package Sealed
The first semiconductor chip and the second semiconductor chip are formed with different integrated circuits,
The resin package has first and second sides facing each other and third and fourth sides facing each other, and each of the first and second sides has a central portion from both ends. Also retracted to the center side of the resin package,
The part of the inner leads electrically connected to the first semiconductor chip is drawn outward from at least one of the third and fourth sides of the resin package to constitute an outer lead,
The other inner lead electrically connected to the second semiconductor chip is drawn outwardly from the central portion of at least the first and second sides of the resin package to serve as an outer lead. Configure
Each of the tips of the outer leads protruding outward from the central portion is a method for manufacturing a semiconductor device located on the center side of the resin package with respect to the both ends,
The electrical characteristics of the first semiconductor chip are measured using first test means having terminals that contact the outer leads drawn outward from at least one of the third and fourth sides of the resin package. A process of inspecting;
The electrical characteristics of the second semiconductor chip are inspected using second test means having terminals that contact the outer leads drawn out from at least the first and second sides of the resin package. And a method of manufacturing a semiconductor device.   The integrated circuit formed on the first semiconductor chip includes an electrically erasable and writable nonvolatile memory, and the integrated circuit formed on the second semiconductor chip is a memory for the nonvolatile memory. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising an interface controller for controlling an interface operation.

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