JP2006345348A - Video decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce operation frequency required for arithmetic decoding process. <P>SOLUTION: The video decoding device comprises: a first arithmetic decoding means for arithmetically decoding a part of the arithmetically coded input data; a multiplexing means for multiplexing a binary data arithmetically decoded by the first arithmetic decoding means and the non-arithmetically decoded input data; an separating means for separating the data outputted from the multiplexing means into the arithmetically decoded binary data and the non-arithmetically decoded input data; a second arithmetically decoding means for arithmetically decoding the non-arithmetically decoded input data outputted from the separating means; and a multilevel generating means for generating multilevel signal from the binary data outputted from the separating means and the binary data arithmetically decoded by the second arithmetic decoding means. In this video decoding device, the first arithmetically decoding means and the second arithmetically decoding means distributes processing load of the arithmetic decoding into a plurality of arithmetic decoding means by simultaneously and arithmetically decoding the different portions of the input data. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image decoding apparatus that decodes an encoded image signal.

  With digitalization of AV equipment such as digitalization of terrestrial analog broadcasting and satellite broadcasting, moving image compression technology is used to efficiently communicate image data with a large amount of information using digital signals. .

  As a typical moving image compression technique, there is a method based on MPEG (Moving Picture Experts Group). This is an encoding method that is discussed in ISO / IEC and internationally standardized and compresses the amount of data using correlation between screens and within screens. Entropy is used for differentially encoded data and transform encoded data. This is an encoding method in which data is compressed by encoding. As one of the entropy encoding methods, arithmetic encoding is used.

  In the following, an outline of arithmetic coding will be described.

  In general, when performing arithmetic coding on an information source sequence (symbol sequence) in which a plurality of symbols are combined, first, on each number symbol (0, 1) on the number line (probability number line), A section corresponding to the appearance probability is assigned. The relationship between the symbol and the interval on the number line is called a probability table. In entropy coding by arithmetic coding, the symbol sequence is expressed on the number line by referring to this probability table. A codeword is generated.

  Hereinafter, arithmetic coding will be described using a specific example.

  FIG. 6 shows a conceptual diagram of arithmetic coding. A case where the character string “abac” is encoded when there are three types of symbols a, b, and c and the appearance probabilities of the symbols are 0.5, 0.25, and 0.25 will be described. . First, the area of [0, 1) is proportionally distributed according to the appearance probability of each character. Since the appearance probability of each character is 0.5, 0.25, and 0.25 respectively for a, b, and c, the area “a” is [0, 0.5), and the area “b” is [0. 5,0.75), and the area of “c” is [0.75,1). Next, the area of [0, 0.5) that is the area of the first character “a” in the character string “abac” is again proportionally distributed according to the appearance probability of each character. As a result, the area “a” is [0, 0.25), the area “b” is [0.25, 0.375), and the area “c” is [0.375, 0.5). . Next, the area of [0.25, 0.375) that is the area of “b” of the second character is proportionally distributed according to the appearance probability. Accordingly, the region “a” is [0.25, 0.3125), the region “b” is [0.3125, 0.34375), and the region “c” is [0.34375, 0.375). It becomes. Next, the area of [0.25, 0.3125) that is the area of the third character “a” is proportionally distributed according to the appearance probability. Thus, the region “a” is [0.25, 0.28125), the region “b” is [0.28125, 0.296875), and the region “c” is [0.296875, 0.3125). It becomes. Here, the area “c” of the fourth character [0.296875, 0.3125] represents the character string “abac”, which is the result of arithmetic coding (codeword).

  Hereinafter, decoding of arithmetically encoded symbols will be described using a specific example.

  The case where the character string “abac” is decoded from the region [0.296875, 0.3125), which is the code word generated in the above-described arithmetic coding example, will be described. At the time of arithmetic decoding, the appearance probability of each character and a region [0.296875, 0.3125] (hereinafter, this region is referred to as R), which is a code word generated by arithmetic coding, are given. First, the area of [0, 1) is proportionally distributed according to the appearance probability of each character. Since the appearance probability of each character is 0.5, 0.25, and 0.25 respectively for a, b, and c, the area “a” is [0, 0.5), and the area “b” is [0. 5,0.75), and the area of “c” is [0.75,1). Among the regions shown here, the region R is included in the region of the character “a”, and it is derived that the leading character is “a”. Next, the area of [0, 0.5) that is the area of the derived character “a” is again proportionally distributed according to the appearance probability of each character. As a result, the area “a” is [0, 0.25), the area “b” is [0.25, 0.375), and the area “c” is [0.375, 0.5). . Among the regions shown here, the region R is included in the region of the character “b”, and it is derived that the second character is “b”. Next, the area of [0.25, 0.375) that is the area of the derived character “b” is proportionally distributed according to the appearance probability. Accordingly, the region “a” is [0.25, 0.3125), the region “b” is [0.3125, 0.34375), and the region “c” is [0.34375, 0.375). It becomes. Thereafter, this procedure is repeated, and finally the character string “abac” is derived.

  Thus, in entropy coding of a symbol sequence using arithmetic coding, an arbitrary symbol sequence can be represented by a codeword on the number line [0, 1) by associating each symbol with a section on the number line. Can be expressed.

  Furthermore, the data compression efficiency by encoding can be improved by adaptively changing the probability table for associating symbols with sections according to the appearance frequency of each symbol.

  Hereinafter, arithmetic coding when the probability table is adaptively changed according to the appearance frequency of each symbol will be described using a specific example.

  FIG. 7 shows a conceptual diagram of arithmetic coding when the probability table is adaptively changed. The character string “abac” is encoded when there are three types of symbols a, b, and c, the initial appearance probability of each symbol is the same (all 1/3), and the initial appearance frequency is all 1. The case where it does is demonstrated. First, the area of [0, 1) is proportionally distributed according to the appearance probability of each character. Since the initial appearance probability of each character is 1/3, the area “a” is [0, 1/3), the area “b” is [1/3, 2/3), and the area “c”. Becomes [2/3, 1). Here, since the first character is “a”, the appearance frequency of “a” is incremented by 1 to be 2. Next, the area of [0, 1/3) that is the area of the first character “a” in the character string “abac” is proportionally distributed according to the appearance probability of each character at this time. At this time, the appearance frequency of the character “a” is 2, whereas the appearance frequency of the characters “b” and “c” is 1. Therefore, the appearance probability of each character is a, b, and c, respectively. 2/4, 1/4, and 1/4. Thus, the area “a” is [0, 2/12), the area “b” is [2/12, 3/12), and the area “c” is [3/12, 4/12). . Next, since the second character is “b”, the appearance frequency of “b” is incremented by 1 to obtain 2. The area of [2/12, 3/12) which is the area of “b” of the second character is proportionally distributed according to the appearance probability of each character at this time. At this time, the appearance frequency of the characters “a” and “b” is 2, whereas the appearance frequency of the character “c” is 1. Therefore, the appearance probability of each character is a, b, and c, respectively. 2/5, 2/5, and 1/5. Accordingly, the area “a” is [10/60, 12/60), the area “b” is [12/60, 14/60), and the area “c” is [14/60, 15/60]. It becomes. Next, since the third character is “a”, the appearance frequency of “a” is incremented by 1 to obtain 3. The area of [10/60, 12/60), which is the area of the third character “a”, is proportionally distributed according to the appearance probability of each character at this point. At this time, since the appearance frequency of the character “a” is 3, the appearance frequency of the character “b” is 2, and the appearance frequency of the character “c” is 1, the appearance probability of each character is a, b, c respectively. 3/6, 2/6, and 1/6. Accordingly, the area “a” is [30/180, 33/180), the area “b” is [33/180, 35/180), and the area “c” is [35/180, 36/180). It becomes. Here, [35/180, 36/180], which is the area of the fourth character “c”, represents the character string “abac”, which is the result of arithmetic coding (codeword).

  Hereinafter, arithmetic decoding when the probability table is adaptively changed according to the appearance frequency of each symbol will be described using a specific example.

  The case where the character string “abac” is decoded from the region [35/180, 36/180), which is the code word generated in the above-described arithmetic coding example, will be described. In arithmetic decoding, the initial appearance probability (all 1/3) and initial appearance frequency (all 1) of each symbol, and a region [35/180, 36/180] which are codewords generated by arithmetic coding (Hereinafter this region is referred to as R). First, the area of [0, 1) is proportionally distributed according to the appearance probability of each character. Similar to encoding, the initial value of the appearance probability of each character is 1/3. Therefore, the area “a” is [0, 1/3), the area “b” is [1/3, 2/3), and the area “c” is [2/3, 1). Among the regions shown here, the region R is included in the region of the character “a”, and it is derived that the leading character is “a”. Here, since the first character is “a”, the appearance frequency of “a” is incremented by 1 to be 2. An appearance probability is obtained from the changed appearance frequency. Next, the area of [0, 1/3) that is the area of the derived character “a” is proportionally distributed according to the appearance probability of each character. Thus, the area “a” is [0, 2/12), the area “b” is [2/12, 3/12), and the area “c” is [3/12, 4/12). . Among the regions shown here, the region R is included in the region of the character “b”, and it is derived that the second character is “b”. Thereafter, this procedure is repeated, and finally the character string “abac” is derived.

  In this way, high coding efficiency can be realized by dynamically changing the appearance probability according to the appearance frequency of the symbol. However, on the other hand, since the appearance probability corresponding to the current symbol depends on the symbol processed immediately before, it must be processed sequentially, and when there are many symbols having such dependency Processing time increases.

  There is MPEG-4 Advanced Video Coding (hereinafter referred to as MPEG-4 AVC) as a moving picture coding system in which such adaptive arithmetic coding is adopted.

  MPEG-4 AVC employs arithmetic coding called CABAC (Context-based Adaptive Binary Arithmetic Coding). In CABAC, the symbols to be encoded are only binary values of 0 and 1, and the appearance probability is adaptively changed according to the appearance frequency of each symbol as in the example of arithmetic coding. In MPEG-4 AVC, image information is subjected to predictive encoding, transform encoding, and quantization, and then converted to binary data of 0 or 1, and arithmetically encoded. FIG. 5 shows an example of conversion to binary data (hereinafter referred to as binarization). In FIG. 5, for example, data 6 is converted into a 7-bit symbol sequence of 1111110. In this example, multi-value data having a 4-bit range is converted into a symbol sequence of 1 bit at the shortest and 17 bits at the longest. Assuming that it takes one clock to arithmetically encode a 1-bit symbol, one multivalued data can be processed in one clock when the number of symbols is the shortest, If the number is the longest, 17 clocks are required. Similarly, assuming that it takes one clock to arithmetically decode a 1-bit symbol, one multivalued data can be processed in one clock when the number of symbols is shortest, If the number is the longest, 17 clocks are required. This means that one piece of data cannot be processed with a fixed number of clocks and the processing time varies greatly depending on the data, and real-time processing is performed even when data of the maximum number of symbols is continuous. It shows that processing must be performed at a very high operating frequency in order to realize.

  In the case of application to consumer equipment such as a digital TV receiver and a DVD player, mounting with a high operating frequency is particularly undesirable because it causes an increase in power consumption. In general, mounting at a high operating frequency is more difficult and costly than mounting at a low operating frequency.

  The configuration of a conventional MPEG-4 AVC image decoding device will be described below with reference to the drawings. FIG. 4 shows an example of the configuration of a conventional MPEG-4 AVC image decoding apparatus. The buffer memory 4000, the separation means 4001, the synchronization control means 4002, the arithmetic decoding means 4003, the multi-value quantization means 4004, the inverse quantization / inverse. It comprises an orthogonal transform unit 4005, a frame memory 4006, an inter-screen predictive decoding unit 4007, an intra-screen predictive decoding unit 4008, and a deblock filter unit 4009.

  The buffer memory 4000 is a FIFO buffer that holds input data, and outputs the data to the separator 4001 in the order of input. The separation unit 4001 separates the data input from the buffer memory 4000 into synchronization information and arithmetic code data, and outputs the synchronization information to the synchronization control unit 4002 and the arithmetic code data to the arithmetic decoding unit 4003. Here, the synchronization information is necessary for performing synchronization control such as data indicating the processing start position in the input data, data indicating the time to start the processing, and data indicating the time to output the processing result. It is data. Arithmetic code data is arithmetically encoded data and various types of header information necessary for decoding the arithmetically encoded data. The synchronization control unit 4002 performs synchronization control such as detection of a process start position in input data, control of a process start time, and control of an output time of a process result. Arithmetic decoding means 4003 arithmetically decodes the arithmetic code data and outputs binarized data. The multi-value conversion means 4004 converts the binary data input from the arithmetic decoding means 4003 and outputs multi-value data. The inverse quantization / inverse orthogonal transform unit 4005 performs an inverse quantization process and an inverse orthogonal transform process on the data input from the multi-value quantization unit 4004. The inverse quantization / inverse orthogonal transform unit 4005 outputs the result to the intra-screen predictive decoding unit 4008 when the processing target data is subjected to intra-screen predictive coding, and when the data to be processed is inter-screen predictive coded. Outputs the result to the inter-screen predictive decoding unit 4007. The intra-screen predictive decoding unit 4008 performs intra-screen predictive decoding processing on the data input from the inverse quantization / inverse orthogonal transform unit 4005. The inter-picture prediction decoding unit 4007 performs motion compensation decoding using the data input from the inverse quantization / inverse orthogonal transform unit 4005 and the past decoded data input from the frame memory 4006. The deblocking filter unit 4009 performs a filtering process on the processing result of the intra prediction decoding unit 4008 or the inter prediction decoding unit 4007 to remove block noise. The frame memory 4006 holds the processing result of the deblocking filter unit 4009 and holds data necessary for subsequent inter-screen predictive decoding.

In order to solve the problem in the implementation of the arithmetic decoding, a method of temporarily holding binary data after arithmetic decoding in a buffer memory is disclosed (for example, refer to Patent Document 1). FIG. 3 shows a configuration example of an image decoding apparatus when binary data after arithmetic decoding is temporarily held in a buffer memory. 3, the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 3, a buffer memory 3000 is a FIFO buffer that temporarily holds the binary data arithmetically decoded by the arithmetic decoding unit 4003, and outputs the binary data to the multilevel converting unit 4004 in the order of input. In this method, a large fluctuation in the processing time of arithmetic decoding can be absorbed by providing the buffer memory 3000, and the influence on the processing time after the multi-value quantization means 4004 in the subsequent stage of the buffer memory 3000 can be reduced. Become.
US Patent Application Publication No. 2004/0085233

  However, in the conventional method, the arithmetic decoding process must be performed at a rate equal to or higher than the data input rate so that the buffer memory 4000 does not overflow and the process fails. Cannot be solved at a high operating frequency. Further, when the capacity of the buffer memory 3000 is increased, there is a problem that the delay time of the subsequent stage with respect to the previous stage of the buffer memory 3000 increases.

  The present invention solves such a conventional problem, and an object of the present invention is to provide an image decoding apparatus that can easily realize real-time processing at a low operating frequency.

  First arithmetic decoding means for arithmetically decoding a part of input data that has been arithmetically encoded, binary data arithmetically decoded by the first arithmetic decoding means, and arithmetic decoding by the first arithmetic decoding means Multiplexing means for multiplexing the input data that has not been converted, data output from the multiplexing means, binary data obtained by arithmetic decoding by the first arithmetic decoding means, and arithmetic by the first arithmetic decoding means Separating means for separating the input data that has not been decoded, and second arithmetic decoding means for arithmetically decoding the input data that has not been arithmetically decoded by the first arithmetic decoding means separated by the separating means Binary data arithmetically decoded by the first arithmetic decoding means separated by the separating means and binary data arithmetically decoded by the second arithmetic decoding means The has a multi-value unit that multi-value, wherein the first arithmetic decoding means second arithmetic decoding means for arithmetically decoding simultaneously different parts of the input data.

  With this configuration, arithmetic decoding can be performed by a plurality of processing means, and the processing load of arithmetic decoding can be distributed to the plurality of processing means.

  According to the image decoding apparatus of the present invention, since the processing load of arithmetic decoding can be distributed to a plurality of processing means, each processing means can be easily realized at a low operating frequency.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a configuration example of an image decoding apparatus according to Embodiment 1 of the present invention. In FIG. 1, the same components as those in FIGS. 3 and 4 are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 1 shows an image decoding apparatus according to Embodiment 1 of the present invention. In FIG. 1, the same components as those in FIGS.

  In FIG. 1, an arithmetic decoding unit 1000 arithmetically decodes a part of the arithmetic code data separated by the separating unit 4001 and outputs binarized data. The multiplexing unit 1001 includes synchronization information separated from the input data by the separation unit 4001, binary data arithmetically decoded by the arithmetic decoding unit 1000, and arithmetic code data separated from the input data by the separation unit 4001. The arithmetic code data that has not been arithmetically decoded by the arithmetic decoding means 1000 is multiplexed and output to the buffer memory 3000. The separation unit 1002 synchronizes the multiplexed data input from the buffer memory 3000, binary data arithmetically decoded by the arithmetic decoding unit 1000, and arithmetic that has not been arithmetically decoded by the arithmetic decoding unit 1000. Separate into code data. The arithmetic decoding unit 1004 arithmetically decodes the arithmetic code data input from the separating unit 1002 and not arithmetically decoded by the arithmetic decoding unit 1000, and outputs binarized data. The multi-value converting means 1005 converts the binary data arithmetically decoded by the arithmetic decoding means 1000 inputted from the separating means 1002 and the arithmetically decoded binary data inputted from the arithmetic decoding means 1004. To output multi-value data. The synchronization control unit 1003 performs synchronization control such as detection of the processing start position in the input data, control of the processing start time, and control of the output time of the processing result based on the synchronization information input from the separation unit 1002.

  According to such a configuration, by adding the multiplexing unit 1001, the separating unit 1002, and the arithmetic decoding unit 1004, the arithmetic decoding unit 1000 and the arithmetic decoding unit 1004 simultaneously receive different arithmetic code data in the input data. Decoding processing can be performed. As a result, the processing load of arithmetic decoding can be distributed to the arithmetic decoding unit 1000 and the arithmetic decoding unit 1004, and the operating frequency required for the arithmetic decoding unit 1000 and the arithmetic decoding unit 1004 is reduced. Can do. Further, the synchronization information is multiplexed by the multiplexing means 1001, and the synchronization control means 1003 is added at the subsequent stage of the buffer memory 3000, so that the synchronization is reestablished at the subsequent stage even when a delay occurs due to the expansion of the capacity of the buffer memory 3000. Is possible. Further, since all data necessary for the processing means subsequent to the buffer memory 3000 is multiplexed by the multiplexing means 1001, the dependency between the processing means preceding the buffer memory 3000 and the processing means subsequent to the buffer memory 3000 is Only supply status. In other words, the processing unit in the subsequent stage only needs to execute processing when there is data to be processed in the buffer memory 3000 regardless of the detailed processing status in the previous stage. As a result, it is possible to easily operate the upstream processing means and the downstream processing means of the buffer memory 3000 in parallel.

  In this embodiment, the processing targeted for load distribution is arithmetic decoding, and arithmetic decoding means 1000 and arithmetic decoding means 1004 are provided. However, the processing targeted for load distribution is variable length decoding. Also good. Furthermore, in the present embodiment, two arithmetic decoding units, the arithmetic decoding unit 1000 and the arithmetic decoding unit 1004, are provided to perform load distribution. However, three or more arithmetic decoding units may be provided.

(Embodiment 2)
FIG. 2 is a configuration example of an image decoding apparatus according to Embodiment 2 of the present invention.

  2, the same components as those in FIGS. 1, 3, and 4 are denoted by the same reference numerals, and description thereof is omitted.

  In FIG. 2, a processor 2000 and a processor 2001 are general-purpose DSPs (signal processing processors) that operate according to various programs stored in the instruction memory 2002. Here, the processor 2000 and the processor 2001 can execute the same program. The processor 2000 receives the data in the buffer memory 4000 and outputs the execution result to the buffer memory 3000. The processor 2001 receives the data of the buffer memory 3000 and outputs the execution result to the inverse quantization / inverse orthogonal transform unit 4005. The instruction memory 2002 is a memory in which the processor 2000 and various programs to be executed by the processor 2001 (separation program 1, synchronization control program 2, arithmetic decoding program 3, multiplex program 4, and multi-value program 5) are stored. The separation program 1 is a program that separates input data into synchronization information, arithmetic code data, and binary data subjected to arithmetic decoding. The synchronization control program 2 is a program that performs synchronization control based on the synchronization information separated by the separation program 1. The arithmetic decoding program 3 is a program that arithmetically decodes the arithmetic code data separated by the separation program 1 to generate binary data. The multiplexing program 4 multiplexes the synchronization information separated by the separation program 1, binary data arithmetically decoded by the arithmetic decoding program 3, and arithmetic code data that has not been arithmetically decoded by the arithmetic decoding program 3. Is a program to output. The multi-value program 5 is a program for converting the binary data subjected to arithmetic decoding separated by the separation program 1 and the binary data arithmetic-decoded by the arithmetic decoding program 3 into multi-value data.

  In FIG. 2, a processor 2000 includes an instruction memory 2002, a separation program 1, a synchronization control program 2, an arithmetic decoding program 3, and a multiplexing program 4, and a separation means 4001, a synchronization control means 4002, and an arithmetic decoding in FIG. Means 1000 and multiplexing means 1001 are configured. Further, the processor 2001 includes the instruction memory 2002, the separation program 1, the synchronization control program 2, the arithmetic decoding program 3, and the multi-value program 5, and the separation means 1002, the synchronization control means 1003, and the arithmetic decoding in FIG. Means 1004 and multi-value quantization means 1005 are configured.

  What is characteristic in the image decoding apparatus configured as described above is that each processing means can share the same function. As a result, the mounting cost can be reduced.

  According to this configuration, the processor 2000 and the processor 2001 can simultaneously decode different arithmetic code data in the input data. As a result, the processing load of arithmetic decoding can be distributed to the processor 2000 and the processor 2001, and the operating frequency required for the processor 2000 and the processor 2001 can be reduced. Further, by synchronizing the synchronization information in the processor 2000 and executing the synchronization control program 2 in the processor 2001 in the subsequent stage of the buffer memory 3000, even if a delay occurs due to the expansion of the capacity of the buffer memory 3000, the synchronization is performed again in the subsequent stage. It becomes possible to retake. Further, since all data necessary for the processing means in the subsequent stage of the buffer memory 3000 are multiplexed in the processor 2000, the dependency between the processing means in the previous stage of the buffer memory 3000 and the processing means in the subsequent stage of the buffer memory 3000 is the data supply. Only the situation will be. In other words, the processing unit in the subsequent stage only needs to execute processing when there is data to be processed in the buffer memory 3000 regardless of the detailed processing status in the previous stage. As a result, it is possible to easily operate the upstream processing means and the downstream processing means of the buffer memory 3000 in parallel.

  In the present embodiment, the process targeted for load distribution is arithmetic decoding and the arithmetic decoding program 3 is provided. However, the process targeted for load distribution may be variable length decoding. Furthermore, in this embodiment, two processors, the processor 2000 and the processor 2001, are provided for load distribution. However, three or more processors may be provided.

  The image decoding apparatus according to the present invention can be used as an image reproduction apparatus realized by an electronic circuit such as an LSI. For example, the present invention is useful as an image reproducing apparatus provided in a computer, a PDA, a digital broadcast receiver, a mobile phone, and the like that decode and reproduce an encoded image.

The figure which shows the structural example of the image decoding apparatus in this invention The figure which shows the structural example of the image decoding apparatus in this invention The figure which shows the structural example of the conventional image decoding apparatus. The figure which shows the structural example of the conventional image decoding apparatus. The figure which shows the example of conversion from multi-value data to binary data Conceptual diagram of arithmetic coding Conceptual diagram of arithmetic coding

Explanation of symbols

1000 Arithmetic decoding means 1001 Multiplexing means 1002 Separating means 1003 Synchronization control means 1004 Arithmetic decoding means 1005 Multi-value quantization means 2000 Processor 2001 Processor 2002 Instruction memory 3000 Buffer memory 4000 Buffer memory 4001 Separation means 4002 Synchronization control means 4003 Arithmetic decoding means 4004 Multi-value quantization means 4005 Inverse quantization / inverse orthogonal transform means 4006 Frame memory 4007 Inter-screen predictive decoding means 4008 In-screen predictive decoding means 4009 Deblock filter means

Claims (4)

An image decoding device that performs at least a first process and a second process on input data,
First processing means for performing the first processing on a part of the input data;
Multiplexing means for multiplexing and outputting the result of the first processing performed by the first processing means and the data of the input data that has not been subjected to the first processing by the first processing means;
The data output from the multiplexing means is separated into the result of the first processing performed by the first processing means and the data of the input data that has not been subjected to the first processing by the first processing means. Separating means;
Second processing means for performing the first processing on data that has not been subjected to the first processing by the first processing means separated by the separation means;
A third process for performing the second process on the result of the first process performed by the first process unit separated by the separation unit and the result of the first process performed by the second process unit. An image decoding apparatus comprising processing means. The first processing means is formed by first arithmetic decoding means for decoding binary code data by decoding arithmetic code data,
The second processing means is formed by second arithmetic decoding means for decoding binary code data by decoding arithmetic code data,
The image decoding apparatus according to claim 1, wherein the third processing means is formed by multi-value conversion means for converting binary data obtained by arithmetic decoding into multi-value data. An image decoding device that performs at least a first process and a second process on input data including synchronization information,
First synchronization control means for performing synchronization control according to the synchronization information included in the input data;
First processing means for performing the first processing on a part of the input data;
The synchronization information included in the input data, the result of the first processing performed by the first processing means, and the data of the input data that has not been subjected to the first processing by the first processing means are multiplexed. Multiplex means for outputting,
The data output from the multiplexing means is the synchronization information, the result of the first processing performed by the first processing means, and the data of the input data that has not been subjected to the first processing by the first processing means. Separating means for separating into,
Second synchronization control means for performing synchronization control according to the synchronization information separated by the separation means;
Second processing means for performing the first processing on data that has not been subjected to the first processing by the first processing means separated by the separation means;
A third process for performing the second process on the result of the first process performed by the first process unit separated by the separation unit and the result of the first process performed by the second process unit. An image decoding apparatus comprising processing means. The first processing means is formed by first arithmetic decoding means for decoding binary code data by decoding arithmetic code data,
The second processing means is formed by second arithmetic decoding means for decoding binary code data by decoding arithmetic code data,
The image decoding apparatus according to claim 3, wherein the third processing means is formed by multi-value conversion means for converting binary data obtained by arithmetic decoding into multi-value data.

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