JP2006344746A - Nonvolatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor nonvolatile memory device which restrains interference effect between cells and realizes highly reliable high integration, and to provide its manufacturing method. <P>SOLUTION: The nonvolatile semiconductor memory device consists of a semiconductor substrate 100; a floating gate which is provided to the upper part of the semiconductor substrate via a tunnel insulating film 120 thereon, and consists of a second conductive layer 140 connected to a first conductive layer 130 and an upper part of the first conductive layer; an interelectrode insulating film 150 formed in an upper part of the floating gate; and a control gate 160 formed in an upper part of the interelectrode insulating film. In the second conductive layer 140, both a width in a cross-section along the widthwise direction of the control gate 160, and a width in a cross section along a longitudinal direction of the control gate 160, are narrower than the width of the first conductive layer 130. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a memory cell structure suitable for high density and high integration and a method for manufacturing the same.

  A flash memory is well known as a nonvolatile semiconductor memory device that can electrically rewrite data and is suitable for high density and large capacity. In order to realize a further increase in capacity, a method of reducing the device structure in accordance with the proportional reduction law is being promoted by promoting the miniaturization of the design rule with a microfabrication apparatus that can realize microfabrication of the memory cell.

  However, a NAND flash memory that is currently widely used has a structure in which a floating gate is provided on a substrate via a tunnel insulating film, and an electric field is generated in the floating gate by using an FN (Fowler-Nordheim) tunnel phenomenon. It is known that it is difficult to reduce the thickness of the gate insulating film to a certain thickness or less because of the operation of injecting or extracting. In addition, the interelectrode insulating film provided between the floating gate and the control gate above it is also miniaturized in order to make the coupling ratio, which is the ratio of the interelectrode insulating film capacity and the tunnel insulating film capacity, more than a certain level. Then, since the parasitic capacitance increases, it is necessary to increase the capacitance of the interelectrode insulating film. However, it is known that it is difficult to reduce the thickness of the interelectrode insulating film, which is one method for increasing the capacitance of the interelectrode insulating film. It has been. These mean that when the design rule of the memory cell is reduced, the thickness of the tunnel insulating film and the interelectrode insulating film cannot be reduced proportionally.

  If the coupling ratio is to be kept constant, the cell shape needs to increase the area of the inter-electrode insulating film by making the floating gate vertically long with respect to miniaturization due to the influence of parasitic capacitance. In this case, the distance between the adjacent cells is reduced by miniaturization, whereas the opposing area of the floating gate between adjacent cells is increased, and the capacitance between the floating gates of adjacent cells is increased. For this reason, the inter-cell interference effect which is the modulation of the threshold value of the memory cell transistor due to the charge accumulated in the adjacent memory cell becomes large, and the problem that the threshold value of the adjacent memory cell fluctuates apparently becomes significant.

  In other words, the inter-cell interference effect becomes larger as the size becomes smaller, and it has a larger influence on a multi-value type memory cell that needs to control the distribution width of an allowable threshold value narrowly.

  Therefore, in the process of forming the floating gate of the flash memory in two layers, forming the element isolation region after forming the first floating gate, and subsequently forming the second floating gate, the first floating gate is formed. A method has been proposed in which a polycrystalline silicon layer, which is a second floating gate, is deposited only on the polycrystalline silicon, which is a gate, in a self-aligning manner and selectively. (For example, refer to Patent Document 1).

  Using this proposed method, the second polycrystalline silicon layer is grown laterally on the element isolation insulating film, thereby making the floating gate width wider than the tunnel insulating film and reducing the area of the interelectrode insulating film. Although it is possible to increase the coupling ratio as a result, the proposed method increases the difficulty of structurally enclosing the miniaturization because the adjacent floating gates in the second layer are closer to each other. There is a problem and it is not suitable for cell miniaturization.

  On the other hand, a method has been proposed in which the gate width of the second silicon layer of the floating gate composed of two layers is made smaller than that of the first silicon layer by using a conventional CVD (Chemical Vapor Deposition) method (for example, Patent Documents). 2).

However, in this proposed method, if the buried groove becomes deep, there is a limit due to the filling performance by the CVD method. Therefore, the gate width of the second layer silicon formed by CVD is small, so that the groove is deepened due to the filling limit. In other words, the capacity due to the area of the interelectrode insulating film cannot be obtained, and the coupling ratio is reduced.
JP 2004-22819 A JP 2001-284556 A

  An object of the present invention is to provide a highly reliable non-volatile semiconductor memory device that suppresses the inter-cell interference effect and a manufacturing method thereof.

  One embodiment of the present invention includes a semiconductor substrate and a second conductive layer provided on the semiconductor substrate via a tunnel insulating film and connected to the first conductive layer and the upper portion of the first conductive layer. A floating gate comprising a layer, an interelectrode insulating film formed on the floating gate, and a control gate formed on the interelectrode insulating film, wherein the second conductive layer has a control gate width direction. The width in the cross section along the control gate and the width in the cross section along the control gate length direction are narrower than the width of the first conductive layer.

  According to one embodiment of the present invention, a tunnel insulating film, a first conductive layer, and a mask layer are sequentially formed over a semiconductor substrate, the mask layer in the partial region on the substrate, the first Forming a trench groove by sequentially removing a part of the conductive layer, the tunnel insulating film and the substrate, forming an element isolation layer on the substrate including the inside of the trench groove, and the element isolation Forming a sacrificial film over the layer; forming a hole in a part of the sacrificial film; exposing a part of the first conductive layer; and forming a second conductive layer in the hole. The method includes a step of selectively forming and a step of removing the sacrificial film.

  INDUSTRIAL APPLICABILITY According to the semiconductor nonvolatile memory device and the manufacturing method thereof of the present invention, the nonvolatile semiconductor memory device capable of high integration with high reliability with respect to the memory cell operation, in which the threshold modulation of the memory cell transistor due to the inter-cell interference effect is suppressed. And a method for manufacturing the same.

  Examples according to the present invention will be described below.

  A first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a plan view showing a configuration implemented in a NAND cell type EEPROM according to this embodiment. As an EEPROM that can be highly integrated, a NAND cell type EEPROM in which a plurality of memory cells are connected in series is known. In FIG. 1, reference numeral 10 denotes one block of the memory cell array.

In this EEPROM, a memory cell 20 is formed with a channel, a source diffusion layer, and a drain diffusion layer on a semiconductor substrate, and a source / drain diffusion layer is formed between adjacent memory cells as shown in FIG. They are connected in series in a shared manner to form a NAND string. Drain diffusion layer of the one end of the NAND string is connected via a selection gate SG _D to the bit line BL, and the source diffusion layer of the other end side is connected to the source line SL shared via a select gate SG _S. The control gate CG of each memory cell is continuously arranged in the row direction and becomes a word line WL. An EEPROM is constructed by arranging a plurality of such memory cells in a matrix.

The plurality of word lines WL and the selection gate SG _D, SG _S, at the time of writing data, erasing, and respectively at the time of read are those selected driven based on the address signal, the address signal causes a row decoder (not )). A predetermined voltage is supplied to the bit line BL by a sense amplifier / write / read circuit (not shown).

  FIG. 2 is a cross-sectional view taken along the line Aa of FIG. FIG. 3 is a cross-sectional view taken along line B-b of FIG.

  In the cross-sectional structure of the memory cell in the bit line direction of FIG. 2 and the word line direction of FIG. 3, element isolation trench grooves are formed in a substrate 100 made of p-type silicon, and element isolation insulation is formed inside the trench grooves. As a material, for example, a silicon oxide film is embedded to form the element isolation layer 110.

  A tunnel insulating film 120 made of a silicon oxide film having a thickness of 10 nm or less, for example, is formed as a thin insulating film through which a tunnel current can flow over the entire channel region on the substrate on which the element isolation layer 110 is formed. A first conductive layer 130 made of, for example, polycrystalline silicon doped with phosphorus at a high concentration or polycrystalline silicon obtained by crystallizing a part of amorphous silicon is formed on the tunnel insulating film 120. The side end portion of one conductive layer 130 is located at the same position as the end portion of the element isolation layer 110 as shown in FIG. Note that polycrystalline silicon obtained by crystallizing part of polycrystalline silicon and amorphous silicon is hereinafter collectively referred to as polysilicon.

  A second conductive layer 140 is formed on the first conductive layer 130 by being physically and electrically connected thereto, and charge accumulation is performed by a laminated structure of the first conductive layer 130 and the second conductive layer 140. A floating gate FG which is a layer is configured.

  In both the bit line direction (FIG. 2) and the word line direction (FIG. 3), the width of the second conductive layer 140 in each memory cell is narrower than the width of the first conductive layer 130. At the boundary between the first conductive layer 130 and the second conductive layer 140, the width of the bottom surface of the second conductive layer 140 is narrower than the top surface of the first conductive layer 130, thereby forming a step.

  The upper part and the peripheral part of the second conductive layer 140 are covered with an interelectrode insulating film 150.

  The interelectrode insulating film 150 is made of, for example, a silicon nitrogen oxide film. The inter-electrode insulating film may be a structure in which, for example, a silicon oxide film and a silicon nitride film are stacked in multiple layers, or a film obtained by nitriding a part of the silicon oxide film, instead of the silicon nitrogen oxide film. In addition, the insulating film may be formed by nitriding a part of polysilicon forming the second conductive layer and the first conductive layer. Alternatively, for example, an aluminum oxide film, a hafnium oxide film, a laminated film including these films, a mixed film, a film obtained by nitriding a part of these oxide films, or the like may be used as a so-called high dielectric film. Further, a structure in which a silicon nitrogen oxide film and a high dielectric film are combined may be used.

  A control gate CG made of, for example, a third conductive layer 160 made of polysilicon is formed above the interelectrode insulating film. There is a region where the second conductive layer 140 is not directly formed on the upper surface of the first conductive layer 130, and an interelectrode insulating film 150 is formed in this region.

  The first and third conductive layers in the bit line direction (FIG. 2) are processed in a self-aligned manner so that the side end faces thereof are substantially perpendicular to the substrate surface. Is formed with an n-type diffusion layer.

  The word line direction (FIG. 3) differs from the bit line direction (FIG. 2) in that the control gate CG made of the third conductive layer 160 is shared between cells connected in series.

  Next, a method for manufacturing the nonvolatile semiconductor memory device in Example 1 will be described with reference to FIGS.

  First, a tunnel insulating film 120 is formed on a semiconductor substrate 100, and a first polysilicon layer 130a to which an impurity is added as a first conductive layer 130 is formed using a CVD method (Chemical Vapor Deposition method) or the like. Then, a resist mask layer 170 is deposited thereon as a mask material. (See FIG. 4).

  Next, the mask layer 170, the first polysilicon layer 130a, the tunnel insulating film 120, and the substrate 100 are removed by etching so that the positions of the side end portions thereof coincide with each other to form a trench groove.

  Subsequently, an oxidation process or a surface modification process is performed to oxidize the sidewalls of the trench grooves and the sidewalls of the first polysilicon layer, and then an element isolation layer 110 is deposited on the entire surface, and etched by, for example, dry etching. The element isolation layer 110 is planarized by back polishing or surface polishing by CMP (Chemical Mechanical Polishing), and finally the upper surface of the mask layer 170 is exposed. (See FIG. 5).

  Next, after peeling the mask layer 170 to expose the upper surface of the first polysilicon layer, a sacrificial layer 180 made of, for example, a silicon oxide film is deposited, for example, about 300 nm. (See FIG. 6).

  Here, a resist is applied on the sacrificial layer 180, and a mask is processed using a normal photoresist method, thereby forming a hole 190 at a position corresponding to the sacrificial layer 180 on the first polysilicon. (See FIG. 7).

  At this time, the width in the bit line direction and the width in the word line direction of the hole 190 are set to be smaller than the width in the bit line direction and the width in the bit line direction of the first polysilicon in each memory cell. An example of a detailed manufacturing method for forming such a hole 190 thinner than the first polysilicon will be described with reference to FIG.

  As shown in FIG. 8D-2, first, a first sacrificial film 180a is deposited, and a hole 190a is formed using a normal photolithography method. At this time, the width of the hole 190a may be equal to or wider than the width in the bit line direction and the width in the word line direction of the first polysilicon. A second sacrificial film 180b made of, for example, a silicon oxide film is formed on the entire surface including the hole 190a using a CVD method or the like. At this time, the second sacrificial film 180b does not completely embed the hole 190a, but stops deposition when it is deposited only on the side wall and bottom of the hole, resulting in the shape shown in FIG. 8D-2.

  Subsequently, a hole 190b in which a part of the second conductive layer 120 is exposed is formed in the bottom of the hole 190a in the second sacrificial film 180b by using an etching method such as a CDE method or an RIE method. . (See FIG. 8 (d-2)). As described above, by using the first sacrificial film 180a and the second sacrificial film 180b, the hole 190 narrower than the width in the bit line direction and the width in the word line direction of the first polysilicon layer can be formed. It becomes possible.

  Here, the shape of the side wall of the hole 190b, that is, the hole 190 may not be a straight line as shown in FIG. Further, the hole 190 may have a Taber shape that is wider toward the top, or may have a reverse taper shape. Further, unevenness may be formed on the side wall of the hole 190.

  Next, a second polysilicon layer to be the second conductive layer 140 is formed in the formed hole 190 by selective growth using the first polysilicon layer as a nucleus. The second polysilicon layer formed by selective growth contains a high concentration of phosphorus as a dopant.

  The method of selective growth of the second polysilicon layer doped with phosphorus is as follows.

A substrate having a hole 190 on the surface as shown in FIG. 7 is transferred to an LPCVD furnace, and dichlorosilane (DCS), hydrogen chloride (HCl), and phosphine (PH ₃ ) are supplied to the substrate surface as source gases. At this time, the atmosphere gas may contain hydrogen (H ₂ ), nitrogen (N ₂ ), or the like. The substrate temperature during film formation was about 600 ° C. to about 900 ° C., the pressure was about 5 Torr to 50 Torr, and the phosphorus concentration in the formed polysilicon was 1 × 10 ²⁰ cm ⁻³ or more. At this time, the polysilicon doped with phosphorus grows at a deposition rate of about 2 nm / min to about 10 nm / min, and the second polysilicon layer formed in the hole 190 is controlled by controlling the deposition time. The height can be controlled by the height of the hole 190 formed in advance. Here, a thick sacrificial film 180 for forming the hole 190 is deposited, and the height of the hole 190 is set to 300 nm or more, whereby the thickness of the second polysilicon layer to be formed is also controlled to 300 nm or more. Is possible.

  Further, by using film formation conditions that allow selective growth, the second polysilicon layer is not deposited on the surface of the sacrificial film 180 other than the hole 190, for example. (See FIG. 9).

  Here, even when the hole 190 is tapered or uneven, the second polysilicon layer can be selectively grown in a shape that fills the hole 190.

  In addition, when the hole has a tapered shape or unevenness, there is an effect that the surface area of the second conductive layer 140 is effectively increased, which may be preferable.

  In addition, when the second polysilicon layer is selectively grown beyond the thickness of the sacrificial film 180 that forms the hole 190, the surface of the second polysilicon layer can be planarized using CMP or the like thereafter. it can. This planarization is preferable because the height of the second conductive layer 140 of different memory cells can be made uniform.

  The second polysilicon layer formed by such selective growth becomes the second conductive layer 140 electrically and physically connected to the first conductive film.

Here, when the second polysilicon layer is selectively grown, a slight oxide film is formed on the first polysilicon layer by cleaning the upper surface of the first polysilicon layer by chemical treatment, In some cases, an extremely thin oxide film is sandwiched between the first polysilicon layer and the second polysilicon layer. However, since this oxide film is very thin, there is no problem in electrical conduction, and the first polysilicon layer and the second polysilicon layer are kept at the same potential.

Here, the sacrificial film 180 used to form the hole 190 is removed by a wet etching method using a solution containing hydrofluoric acid or the like, or a dry etching method using CDE or the like. (See FIG. 10) At this time, as described above, when the first sacrificial film 180a and the second sacrificial film 180b are used when forming the hole 190, the first and second sacrificial films 180a and 180b are used. Are also peeled off in the same manner.

  Subsequently, an interelectrode insulating film 150 is deposited on the entire surface including the upper part and the periphery of the second polysilicon layer. (See FIG. 11) As the interelectrode insulating film 150, a laminated structure composed of a silicon nitride film and a silicon oxide film may be used, or a silicon oxide film is deposited and subjected to nitriding to form a silicon nitride oxide film. May be. Further, a so-called high dielectric film (for example, aluminum oxide, hafnium oxide, or an oxynitride or nitride thereof, or a mixture or stacked film thereof) may be used. Moreover, you may make the laminated structure which combined these, or a mixed phase film.

  Subsequently, a third conductive layer 160 made of a third polysilicon layer containing a high concentration of phosphorus as a dopant is deposited on the entire surface by CVD or the like. (See FIG. 12) This third conductive layer 160 becomes the control gate CG. At this time, a low resistance film (not shown) such as silicide may be deposited on the third conductive layer 160. Further, gate processing for separating each memory cell in the bit line direction is performed, and ion implantation for forming the diffusion layer 200 is performed on the substrate 100 to form a transistor, thereby completing the memory cell structure. (See FIGS. 2 and 3).

  The memory cell according to the first embodiment has the following characteristics. In the memory cell according to the first embodiment, the interelectrode insulating film 150 is covered with the third conductive layer 160, and the parasitic capacitance between adjacent cells is shielded by the electrical shielding effect and does not affect the cell. Thereby, it becomes a structure which can suppress the interference effect between adjacent cells very small. By controlling the film thickness of the first conductive layer 130 to be smaller than the height of the second conductive layer 140, the interference effect between adjacent cells can be further suppressed.

  Further, in the manufacturing method according to Example 1, the height of the second conductive layer 140 can be controlled by selective growth, and the hole portion having a high aspect ratio that was difficult to be embedded by the conventional CVD method is used. It is also possible to form the second conductive layer.

  Furthermore, the area of the floating gate can be controlled by controlling the height of the second conductive layer, and the coupling ratio can be increased. Further, since the width of the second conductive layer 140 is narrower than that of the first conductive layer 130, there is an effect that the embedding characteristics of the interelectrode insulating film 150 and the third conductive layer 160 thereabove are improved.

  A second embodiment of the present invention will be described with reference to FIG.

  In the second embodiment, instead of the second polysilicon layer to which phosphorus is added in the first embodiment, a polysilicon layer into which impurities are not intentionally introduced is formed by selective growth, and thereafter, a polysilicon layer is formed by ion doping. The difference from Example 1 is that an impurity is added to the silicon layer.

  The structure in the second embodiment is the same as that of the first embodiment and will not be described again here. The manufacturing method in Example 2 is the same as that in Example 1 except for the method for forming the second conductive layer 140 in Example 1, and the description thereof is omitted here.

Reference is made to FIG. As in Example 1, the substrate having the holes 190 is transferred to an LPCVD furnace, and dichlorosilane (DCS) and hydrogen chloride (HCl) gas are supplied to the substrate surface as source gases. The substrate temperature was about 700 ° C. to about 800 ° C., and the pressure was about 5 Torr to about 20 Torr. At this time, the second polysilicon layer grew at a deposition rate of about 3 nm / min to about 20 nm / min, and the dopant concentration in the film was 1 × 10 ¹⁹ cm ⁻³ or less. At this time, the second polysilicon layer was not deposited on the silicon insulating film or the sacrificial film 180 as the element isolation layer 110, and polysilicon was selectively grown only in the hole 190.

  Next, as shown in FIG. 14B, phosphorus ions are implanted into the second polysilicon layer by ion doping.

  Thereafter, the surface of the second polysilicon layer is flattened using a technique such as a CMP method, and the shape of the second conductive layer 140 is made uniform.

  Here, an activation heat treatment for activating ions doped in the second polysilicon layer may be added. Further, activation may be performed at the same time as heat treatment in a later step.

  The form of the memory cell of the second embodiment has the same effect as that of the first embodiment. Further, by using the manufacturing method of Example 2, it is possible to increase the film formation rate and improve the productivity as compared with the film formation method in which impurities are added simultaneously with film formation.

  The present invention is not limited to the above configuration, and various modifications are possible. For example, in Embodiment 2, phosphorus ions are doped, but this may be arsenic, or the floating gate may be made p-type by using boron or the like.

  A third embodiment of the present invention will be described with reference to FIG.

  The third embodiment is the same as the second embodiment in that the second polysilicon layer not intentionally introducing the dopant is selectively grown in the method of forming the second conductive layer 140. However, the dopant was introduced by ion implantation in Example 2, but Example 3 differs in that a gas doping method in which impurities are added from the gas phase is used.

  The structure in Example 3 and the part other than the method for manufacturing the second conductive layer 140 are the same as in Example 1, and will not be described again here.

  Further, the process of forming polysilicon without adding impurities in the hole 190 by selective growth in the third embodiment is the same as that of the second embodiment, and will not be described here again.

Refer to FIG. The substrate on which the second polysilicon layer is selectively grown only in the hole 190 on the substrate is transported into the vacuum apparatus, for example, in phosphine gas (PH ₃ ) or AsH ₃ gas diluted with an inert gas or hydrogen. Heat treatment is performed on the substrate. This doping process may be performed continuously with the selective growth of polysilicon. By this heat treatment, phosphorus or arsenic is introduced as a dopant.

  Thereafter, the surface of the second conductive film 140 is flattened using a technique such as a CMP method, and the shape of the second conductive film 140 is made uniform.

  The form of the memory cell of the third embodiment has the same effect as that of the first embodiment. Further, by using the manufacturing method of Example 3, it is possible to increase the film formation speed and improve the productivity as compared with the film formation method in which impurities are added simultaneously with film formation.

  The present invention is not limited to the above configuration, and various modifications are possible. For example, although phosphorus ions are doped in the second embodiment, the floating gate may be made p-type by using a gas containing boron or the like.

  In the first to third embodiments, a polysilicon layer is used for the second conductive layer 140. However, the fourth embodiment is different in that silicon germanium (SiGe) is used for at least a part of the second conductive layer 140. Yes.

  By using silicon germanium, selective growth having selectivity equivalent to that of polysilicon is possible, and the deposition rate is higher than that of polysilicon, and the productivity is improved. Silicon germanium is particularly effective in a nonvolatile semiconductor memory device and a method for manufacturing the same, which have higher resistance to high temperature processing than polysilicon and high thermal budget.

  The overall structure of the nonvolatile semiconductor device in the fourth embodiment is the same as that of FIG. 1 in the first embodiment, and will not be described again here. FIG. 15 shows a cross-sectional structure of the nonvolatile semiconductor memory device according to the fourth embodiment. The fourth embodiment is different from the first embodiment in that silicon germanium is used for the second conductive layer 140. As shown in FIG. 15, the second conductive layer has a structure composed of a silicon germanium layer 210.

  Next, the manufacturing method in Example 4 is demonstrated using FIG. However, the portions other than the method for manufacturing the second conductive film 140 are the same as those in the first embodiment, and will not be described again here.

Refer to FIG. The substrate 100 having the hole 190 on the surface formed in the same manner as in FIG. 7 is transferred to the LPCVD furnace, and dichlorosilane (DCS), germane (GeH ₄ ), and phosphine (PH ₃ ) gas are supplied to the substrate surface as source gases. . (See FIG. 16 (a)). The substrate temperature was about 700 ° C. to 800 ° C., and the pressure was about 5 Torr to about 20 Torr. At this time, silicon germanium grows at a deposition rate of about 3 nm / min to about 30 nm / min, and the germanium concentration in the silicon germanium is controlled to about 10 atomic% to about 80 atomic% by controlling the gas flow rate during film formation. be able to. At this time, silicon germanium is not deposited on the upper surface of the silicon insulating film which is the element isolation layer 110, and silicon germanium can be selectively grown only inside the hole 190. (See FIG. 16 (b)).

  Thereafter, the surface of the second conductive film 140 made of silicon germanium is planarized using a technique such as a CMP method, and the shape of the second conductive film 140 is made uniform.

  Subsequently, an interelectrode insulating film is formed on the entire surface including the second conductive film 140. Since the subsequent steps are the same as those in the first embodiment, they will not be described here.

  The form of the memory cell of the fourth embodiment has the same effect as that of the first embodiment. Furthermore, by using the manufacturing method of the fourth embodiment, it becomes possible to increase the film forming speed as compared with the film forming method in the first to third embodiments, and the productivity is improved. Silicon germanium has a smaller heat capacity at the time of film formation than silicon, and is particularly effective when it is desired to reduce the heat capacity in order to improve device performance in the manufacturing process of a semiconductor device.

  The present invention is not limited to the above configuration, and various modifications are possible. For example, as shown in FIG. 17A, a polysilicon layer 140b and a second conductive layer made of silicon germanium 210b may be formed on the first conductive layer 130 by selective growth. As shown in FIG. 17B, a second conductive layer made of silicon germanium 210c and a polysilicon layer 140c is formed on the first conductive layer 130 by selective growth. It is also possible to do. Also, as shown in FIG. 17C, a second conductive layer having a three-layer structure of polysilicon 140d, silicon germanium layer 210d, and polysilicon layer 140e is formed on the first conductive layer 130 by selective growth. May be.

  By depositing a polysilicon layer on top of silicon germanium, the interelectrode insulating film and silicon germanium are not in direct contact with each other, causing surface flow during the formation of the interelectrode insulating film or degrading the film quality of the interelectrode insulating film. Or the effects of charge accumulation at the interface can be suppressed. In addition, the structure in which the polysilicon layer is deposited below the silicon germanium can suppress fluidization of the first conductive layer, which is a concern when silicon germanium is selectively grown directly on the first conductive layer. .

  A fifth embodiment of the present invention will be described with reference to FIGS.

In Examples 1 to 4, a drain side selection gate SG _D and the source side selection gate SGS is the second conductive layer 140 is selectively grown on the first conductive layer 130 similarly to the memory cell 20 structure There, the drain-side select gate SG _D example 5 is different in that it has a second without forming the conductive layer 140, the structure comprising only the first conductive layer 130.

  The plan configuration diagram of the nonvolatile semiconductor memory device according to the fifth example is the same as that of FIG. 1 in the first example, and will not be described again here. Further, the cross-sectional structure of the memory cell in the fifth embodiment is the same as that in FIGS. 2 and 3 in the first embodiment, and will not be described again here.

Please refer to FIG. Figure 18 shows cut along the C-c line in the memory cell array of FIG. 1, namely a cross-sectional view in a word line direction of the drain side select gate SG _D moiety. Figure 19 shows cut along the D-d line in Figure 1, i.e. a cross-sectional view of a bit line direction of the drain side select gate SG _D moiety. The drain side select gate SG _D is constituted by the first conductive layer 130 and the third conductive layer 150, on the first conductive layer 130 and the second conductive layer is not formed.

Thus it is possible to form a selection gate SG same floating gate and the memory cell section in _D. In such a structure may take the methods such as writing to a memory cell portion after setting the threshold value once the write to the select gate SG _D.

Also, be any electrical contact can take structure and the first conductive layer at the position of the select gate SG _D in the cell array (not shown) is also possible.

With such a structure, has the effect of control of the threshold of the drain side select gate SG _D becomes easy, miniaturization of the memory cell array is facilitated.

Section of the source side select gates SG _S moiety may also be similar to the cross-sectional structure of the drain side select gate SGD portion.

  A sixth embodiment of the present invention will be described with reference to FIGS.

The third conductive construed Example in 1 to Example 4, the drain side select gate SG _D and the source side selection gate SG _S interelectrode insulating film 150 on the second conductive layer 140 similarly to the memory cell 20 a layer 160, but the floating gate consisting of first and second conductive layer and a structure having a control gate formed of the third conductive layer, the drain side select example 6 gates SG _D and the source side selection gate SG _S differs in that an opening is provided in the interelectrode insulating film and the first, second, and third conductive layers are electrically short-circuited.

  The plan configuration diagram of the nonvolatile semiconductor memory device according to Example 6 is the same as FIG. 1 in Example 1, and will not be described here again. Further, the cross-sectional structure of the memory cell in the sixth embodiment is the same as that in FIGS. 2 and 3 in the first embodiment, and will not be described again here.

Refer to FIG. Figure 20 shows cut along the C-c line in the memory cell array of FIG. 1 is a cross-sectional view i.e. in the drain side select gate SG _D of the word line direction. Figure 21 shows cut along the D-d line in Figure 1, i.e. a cross-sectional view of the drain side select gate SG _D portion of the bit line direction. The drain side select gate SG _D is an opening provided in the insulating film, the first conductive layer 130, a second conductive layer 140 and the third conductive layer 160 are electrically short-circuited to connect. With such a structure, there is a threshold effect control is facilitated in the drain side select gate SG _D and the source side selection gate SG _S, miniaturization of the memory cell array is facilitated.

Section of the source side select gates SG _S moiety may also be similar to the cross-sectional structure of the drain side select gate SG _D moiety.

  The present invention is not limited to the above configuration, and various modifications are possible. For example, in the first to sixth embodiments, polysilicon or silicon germanium is formed as the second conductive layer. However, the second conductive layer may be formed of a metal material formed using a selective growth process, such as tungsten or molybdenum. Good. By selectively growing a material having a work function smaller than that of the polysilicon on the second conductive layer, there is an effect of suppressing the leakage current of the interelectrode insulating film. In addition, the structures and processes described in Embodiments 1 to 6 can be combined as appropriate.

1 is a plan view of a nonvolatile semiconductor memory device according to Example 1. FIG. 1 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to Example 1. FIG. 1 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to Example 1. FIG. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device according to the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. FIG. 6 is a cross-sectional view showing the manufacturing process of the nonvolatile semiconductor memory device in accordance with the first embodiment. 9 is a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory device according to Example 2. FIG. 9 is a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory device according to Example 3. FIG. FIG. 6 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to Example 4; FIG. 10 is a cross-sectional view showing a manufacturing process of the nonvolatile semiconductor memory device in accordance with the fourth embodiment. FIG. 6 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to Example 4; FIG. 10 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to a fifth embodiment. FIG. 10 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to a fifth embodiment. FIG. 10 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to Example 6. FIG. 10 is a diagram showing a cross-sectional structure of a nonvolatile semiconductor memory device according to Example 6.

Explanation of symbols

10 memory cell array 20 memory cell SDG drain side selection gate SDS source side selection gate BL bit line WL word line SL source line CG control gate FG floating gate 100 substrate 110 element isolation layer 120 tunnel insulating film 130 first conductive layer 140 second Conductive layer 140a-140e polysilicon layer 150 interelectrode insulating film 160 third conductive layer 170 mask layer 180 sacrificial film 180a first sacrificial film 180b second sacrificial film 190 190a 190b hole 200 diffusion layer 210 210a-210c Silicon germanium layer

Claims (5)

A semiconductor substrate;
A floating gate comprising a first conductive layer and a second conductive layer connected to an upper portion of the first conductive layer on the semiconductor substrate via a tunnel insulating film;
An interelectrode insulating film formed on the floating gate;
A control gate formed on the interelectrode insulating film;
The non-volatile semiconductor characterized in that the second conductive layer has a width in a cross section along the control gate width direction and a width in a cross section along the control gate length direction smaller than the width of the first conductive layer. Storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the second conductive layer is formed by selective growth using the first conductive layer as a nucleus. Forming a tunnel insulating film, a first conductive layer, and a mask layer in order on a semiconductor substrate;
Forming a trench groove by sequentially removing the mask layer, the first conductive layer, the tunnel insulating film, and a part of the substrate in a partial region on the substrate;
Forming an element isolation layer on the substrate including the inside of the trench groove;
Forming a sacrificial film on the element isolation layer;
Forming a hole in a part of the sacrificial film and exposing a part of the first conductive layer; selectively forming a second conductive layer in the hole;
And a step of removing the sacrificial film. A method for manufacturing a nonvolatile semiconductor memory device. Selectively forming the second conductive layer in the hole,
selectively forming the second conductive layer doped with n-type or p-type impurities on the first conductive layer, or
2. The method according to claim 1, further comprising the step of adding an n-type or p-type impurity to the second conductive layer after selectively forming the second conductive layer on the first conductive layer. 3. A method for manufacturing a nonvolatile semiconductor memory device according to 3. 5. The nonvolatile semiconductor memory device according to claim 1, further comprising a NAND flash memory configured by connecting a plurality of MOSFETs each having a floating gate and a control gate in series. Its manufacturing method.

Images