JP2006343997A - Communication storage apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that when both a non-contact type interface and a contact type interface are used simultaneously in a communication recorder for performing control by performing switching between the non-contact type interface and the contact type interface with one CPU, the CPU is occupied by processing of one of the interfaces, the communication control cannot perform control of the other, and a communication storage apparatus system can be unstable due to a communication frame loss. <P>SOLUTION: The CPU for performing protocol control of the contact type interface and non-contact type interface is provided for each interface. The storage apparatus is provided with an arbitration means between the CPUs for realizing transmission of data of both the interfaces, and a means for enabling both the CPUs to confirm input signals, power supply states of the interfaces, and operating situations of the opposing CPU for improvement of synchronism between the CPUs. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a configuration of a communication storage device having a contact type and a non-contact type interface.

The composite IC card having both the contact type interface internationally standardized by ISO / IEC 7816 and the non-contact type interface standardized by ISO / IEC 14443 has high security required for the contact type. In recent years, it has appeared in the market as a credit card or bank card because of the convenience of applications such as electronic tickets that are realized in a contactless manner. In addition, new service forms such as renewal of card value via the Internet network have been realized by tackling non-contact IC card functions on mobile phones.
Here, the switching of the contact type / non-contact type interface used by the composite IC card is exclusively switched at any time depending on the state of the power supply or the input signal (for example, Patent Document 1). The CPU grasps the communication interface to be used in the interface switching state, and realizes a contact type or non-contact type interface protocol.

Japanese Patent Laid-Open No. 11-272824

However, in the non-contact IC card function mounted on the mobile terminal, simultaneous use of the contact interface and the non-contact interface is assumed. In the case of following the configuration of the composite IC card, one CPU can handle two different interface protocols at the same time.
For this reason, if the CPU is occupied in one communication interface process, the other communication interface process cannot be performed, which may cause a communication frame loss, which causes the system to become unstable. In this respect, the conventional technique does not assume simultaneous use.

  A CPU for controlling the protocol of the contact type interface and the non-contact type interface is provided for each interface, and data transmission of both interfaces (transmission / reception of data to / from each interface and data transfer between each interface and non-contact type interface) In order to improve the synchronism between the CPUs for realizing the data communication via the contact-type interface), both CPUs have the interface input signal and power supply status, and the operation status of the opposing CPUs. A means for confirming the above is provided.

  By providing a CPU for each interface, the load due to communication interface processing is distributed to each CPU, and communication frame loss can be reduced. Further, the CPU for controlling the interface protocol has a different configuration for each interface, and the arbitration means provided between the two interfaces serves as a firewall, thereby improving security.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration diagram of a communication storage device according to an embodiment of the present invention. The communication storage device (100) is broadly divided into a non-contact interface control system for realizing a non-contact interface application, a contact interface control system for realizing a contact interface application, means for arbitrating both interfaces, It comprises means for managing the system operation of the communication storage device.

  The non-contact interface control system is an antenna coil (201) serving as a transmitting / receiving antenna, a means (202) for generating a power source from a received waveform captured by the antenna coil, and a received waveform from the antenna coil (202). 1st communication control means (203) composed of a reception function for decoding / decoding and inspecting a received frame and a transmission function for generating a transmission frame, encoding / modulating to generate a transmission waveform, and used for a non-contact protocol A first cryptographic operation means (204), a first nonvolatile memory (205) for storing data used in a contactless protocol, a first communication control means (203), a first cryptographic operation means (204), and 1st CPU (206) which controls 1st non-volatile memory (205), 1st ROM (207) used for 1st CPU (206) Constituted by the first RAM (208).

  The contact interface control system includes a connector (301) serving as a contact of the contact interface, a means (302) for generating an internal power supply from an input power supply from the connector (301), and a reception included in an input signal from the connector (301). A second communication control means (303) comprising a reception function for inspecting a frame and a transmission function for generating a transmission frame and sending a transmission signal to the connector; a second cryptographic operation means (304) used for a contact protocol; The second nonvolatile memory (305) for storing data used in the contact protocol, the second communication control means (303), the second cryptographic operation means (304), and the second nonvolatile memory (305) are controlled. Consists of a second CPU (306), a second ROM (307) used for the second CPU, and a second RAM (308).By providing a CPU for each interface, the communication frame loss can be reduced by not interrupting the transaction of each interface and by distributing the load caused by the communication interface processing.

  The system power supply is generated by means (401) for generating / controlling the system power supply of the communication storage device according to the power supply state generated by the non-contact type interface control system and the power generation means (202) (302) in the contact type interface control system. Is supplied.

  Activation / inactivation of the non-contact interface control system and the contact interface control system is performed by a reset signal generated by the reset generation means (402). The reset release / generation conditions of the non-contact interface control system and the contact interface control system depend on the supply state of the power source (202) (302) generated by the non-contact interface control system and the contact interface control system. .

  Means (403) for generating a free-running clock independent of both interfaces is provided, and the free-running clock is supplied as a system clock of the communication storage device. The difference in frequency between the interface clock of both interfaces and the free-running clock is absorbed by the communication control means (203) (303).

  Arbitration means with the CPUs (206) and (306) of both interfaces is performed in the shared memory (404). By storing the command / response defined between the CPUs (206) and (306) in the shared memory (404) and passing it to the opposing CPU, it is possible to request specific processing from the opposing CPU.

  However, a procedure for avoiding shared memory access conflict between both CPUs is required. A semaphore register (405) is provided as a method for avoiding this access conflict. The semaphore register is a register for storing a shared flag accessible from both CPUs. Both CPUs write a specific flag (access right request) to the register and read the result. By monitoring the obtained flag state (access right not acquired or access right acquired), both CPUs can determine whether the shared memory can be accessed or not.

  The access procedure to the shared memory is shown in FIG. Each CPU (206) (306) having a request to access the shared memory performs a read operation indicating an access right confirmation (521) (531) in order to confirm the usage status of the shared memory (404). To run. Each CPU (206) (306), which has recognized that the shared memory is unused in the access right non-acquisition (522) (523), requests the semaphore register (405) to access the shared memory (523) (533). ) Is performed. Thereafter, a read operation indicating access right confirmation (524) (534) is executed on the semaphore register (405) to grasp whether the access right has been acquired. As a result of the read operation, the CPU (306) that has read the result indicating the access right acquisition (535) can access the shared memory, and the CPU (206) that has not acquired the access right (525) has the access right released. Until then, access to shared memory is restricted.

  After completing the series of shared memory access processing, the access right acquired CPU (306) performs a write operation indicating access right release (536) on the semaphore register (405) to release the access right.

When the access right is released, the CPU (206) that has not acquired the access right is notified of the release of the access right by an interrupt (526), thereby smoothly transferring data stored in the shared memory. Can be realized. The interrupt notification due to the release of the access right is performed by the interrupt means (406) in FIG.
The above semaphore procedure avoids shared memory access contention.

  Note that when the access right of the semaphore register (405) is not acquired, a circuit configuration that restricts access control of the shared memory (404) by hardware is desirable. For example, a signal obtained by ANDing a signal indicating an access right acquisition state and an access signal to the shared memory of the CPU is used as a final access signal to the shared memory. The access operation can be invalidated. In addition, it is desirable that a circuit configuration that prioritizes one CPU access in advance for the access conflict of the access right acquisition request to the semaphore register (405).

The status register (407) of FIG. 1 is provided for the purpose of monitoring the signal / power supply status of each interface and the operating status of the opposing CPU by each CPU (206) (207). It is possible to limit and manage applications that can be executed now.
Note that the status register (407) opposes the input clock state of the contactless interface, the power supply state of the contactless interface, the input clock signal state of the contact interface, the input reset signal state of the contact interface, the supply power state of the contact interface. It consists of a flag indicating the state of the CPU. Further, the state of the opposing CPU includes a flag indicating a CPU processing state defined between both CPUs.

  The communication storage device (100) of FIG. 3 is an example in which the non-volatile memory (205) is mounted only on the non-contact interface side and the non-volatile memory is not mounted on the contact interface side. Access to the non-volatile memory (205) at the request of the second CPU (302) is performed under the control / management of the first CPU (202) via the shared memory (404) access according to the semaphore procedure. To be implemented. The communication storage device of FIG. 4 is an example in which the non-volatile memory (305) is mounted only on the contact interface side and the non-volatile memory is not mounted on the non-contact interface side, unlike FIG.

  3 to 4, the processing load on the first CPU (206) and the second CPU (306) is naturally heavier and the other is lighter. This means that both CPUs do not necessarily have the same function / performance, and one of the CPUs can be simplified and the circuit scale can be reduced by integrating the nonvolatile memory.

  According to the present invention, it is possible to avoid contention for access to the communication storage device by the non-contact interface and the contact interface, and therefore it is suitable as a communication storage device mounted on a mobile terminal in which both interfaces are accessed irregularly.

It is a block diagram of the communication storage apparatus of this invention. It is the access contention avoidance procedure to the shared memory in the communication storage device of the present invention. In the communication storage device of the present invention, it is a configuration diagram when a nonvolatile memory is integrated into a non-contact interface control system. In the communication storage device of the present invention, it is a configuration diagram when a nonvolatile memory is integrated into a contact type interface control system.

Explanation of symbols

100 Communication storage device 201 of the present invention Antenna coil 202 Non-contact interface power supply generation means 203 Non-contact interface communication control means 204 First cryptographic operation means 205 First nonvolatile memory 206 First CPU
207 First ROM
208 First RAM
301 Connector 302 Contact Interface Power Supply Generation Unit 303 Contact Interface Communication Control Unit 304 Second Cryptographic Operation Unit 305 Second Nonvolatile Memory 306 Second CPU
307 Second ROM
308 Second RAM
401 Power control means 402 Reset generation means 403 Clock generation means 404 Shared memory 405 Semaphore register 406 Interrupt notification means 407 Status register 521 Confirmation of access right from the first CPU (part 1)
522 Notification of non-acquisition of access right to first CPU (part 1)
523 Access right request from first CPU 524 Access right confirmation from first CPU (Part 2)
525 Counter CPU access right acquisition state notification to first CPU 526 Interrupt notification due to release of access right to first CPU 527 Access right confirmation from first CPU (part 3)
528 Notification of non-acquisition of access right to the first CPU (part 2)
531 Access Right Confirmation from Second CPU (Part 1)
532 Notification of non-acquisition of access right to second CPU (part 1)
533 Access right request from second CPU 534 Access right confirmation from second CPU (2)
535 Access right acquisition state notification to second CPU 536 Access right release from second CPU 537 Access right confirmation from second CPU (part 3)
538 Notification of non-acquisition of access right to the second CPU (part 2).

Claims (5)

A contact interface;
A non-contact interface;
A first CPU for controlling the protocol of the contact interface;
A second CPU for controlling the protocol of the contactless interface;
Arbitration means between the two CPUs;
A communication storage device comprising: a confirmation means for confirming an operation state of the CPU opposite to an input signal and a power supply state of each interface. The mediation means is
A shared memory accessible from the first CPU and the second CPU, and a semaphore configured to give priority to access by either the first or second CPU in the case of an access conflict in the case of access conflict. Has a register,
The first CPU or the second CPU having an access request to the shared memory requests the semaphore register to acquire an access right, and the CPU having acquired the access right is accessed to the shared memory. The communication storage device according to claim 1.   3. The information processing apparatus according to claim 2, further comprising means for sending / notifying with an interrupt signal to the CPU that has not acquired the access right when the CPU that has acquired the access right releases the access right. Communication storage device.   The confirmation means has a register for notifying an input signal of the interface and a power supply state, an operation state of the CPU, and an input state of a clock and a reset. The first CPU and the second CPU 4. The communication storage device according to claim 1, wherein the communication storage device grasps an operation state of both CPUs and a state of both interfaces by accessing. The communication storage device according to claim 1, wherein the two CPUs have different processing loads.

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