JP2006340016A - Error-correction encoding/decoding device and decoding method using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce memory capacity for a Min-Sum decoding method. <P>SOLUTION: An absolute value calculator 21, a minimum value searcher 22, a positive/negative sign calculator 23, and a row processing output encoder 24 are provided at a row processing circuit 15 of an error-correction encoding/decoding device 1. Two kinds of an absolute value and a 2-bit code information are outputted as a row processing output to a row processing output memory 12 from the row processing circuit 15. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an error correction code decoding process, and in particular, an error correction code using a low density parity check code (Low Density Parity Check Code, hereinafter referred to as an LDPC code) and a Min-Sum algorithm approximating a Sum-Product algorithm. The present invention relates to a decoding device.

  The error correction code is a technique for reducing the influence of noise mixed during data transmission by processing such as encoding and decoding. The turbo code (Turbo Code) that is a convolutional code and the Reed-Solomon Code (Reed-Solomon Code) that is a cyclic code. ), LDPC codes that are non-cyclic codes are known. Encoding is a process of adding redundancy to the data to be transmitted. The encoded data is called a code word. The code word sent to the communication channel is affected by noise and some bits of the code word are received at the time of reception. An error such as inversion occurs. Decoding is a process of restoring data from a received word affected by this error using redundancy.

  In recent years, with the increase of the code length n and the higher data rate, the LDPC code having a defect compensation function with a high error correction capability (high coding gain), a small amount of calculation, and a small error floor is next. Application to digital satellite broadcasting (HDTV), mobile communication (UWB or wireless LAN), magnetic recording, recording media, optical communication, etc. has been studied as the most promising candidate for the generation error correction code.

  In decoding processing using an LDPC code, Sum-Product decoding using the Sum-Product algorithm is frequently used. However, when the check node calculation is executed in parallel, a lookup table for parallel execution is required and signal processing is performed. The circuit scale of the circuit that performs is increased. For this reason, a Min-Sum decoding method using a Min-Sum algorithm that uses an approximation of Gallager's f function to reduce the circuit scale has been studied (for example, see Non-Patent Document 1).

In the Min-Sum decoding method, the largest amount of calculation is row processing, and there is a problem that the row processing data occupies a large amount in the memory storing the decoding processing data. Further, if a row processing output memory and a column processing output memory are separately prepared so that the row processing and the column processing can be executed in parallel in order to increase the throughput of the hardware configuration, a memory that occupies most of the integrated circuit as a decoding device. There is a problem that the occupied area of the device increases.
Marjan Kortooi, et'al, `` Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Coding '', Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), IEEE, Computer Society, 2004

  An object of the present invention is to provide an error correction code decoding apparatus and a decoding method using the error correction code decoding apparatus in which the memory capacity in the Min-Sum decoding method is reduced.

  To achieve the above object, an error correction code decoding apparatus according to an aspect of the present invention includes a memory unit that stores row processing information, column processing information, and log likelihood ratio information, and the memory unit that stores the memory unit. An absolute value calculation unit that inputs column processing information and converts it into an absolute value, input absolute value information that is output from the absolute value calculation unit, obtain a minimum value and a second smallest value from the absolute value information, A minimum value search unit that outputs to the memory unit as row processing output information; a positive / negative code calculation unit that inputs the column processing information stored in the memory unit and calculates a positive / negative code corresponding to each input; Information indicating an input corresponding to the minimum value output from the minimum value search unit and calculation information output from the sign calculation unit are input, a 2-bit code corresponding to the input is generated, and line processing output information is generated. Output to the memory unit A row processing circuit having a row processing output encoding unit, a column processing input decoding unit that inputs the row processing information stored in the memory unit and converts the input into column processing input information, and the column processing input An adder input selection unit that selectively outputs conversion information output from the decoding unit; and the log likelihood ratio information stored in the memory unit and the conversion information output from the adder input selection unit. And a column processing circuit having an adder that outputs the result to the memory unit as column processing output information.

  Furthermore, in order to achieve the above object, a decoding method using an error correction code decoding apparatus according to an aspect of the present invention inputs column processing information stored in a memory unit to a row processing circuit, and the row processing circuit Calculating the column processing information as two types of absolute value and 2-bit code information, and outputting the updated external value log ratio information to the memory unit as row processing output information; and a row stored in the memory unit Processing information is input to a column processing circuit, the row processing information is converted into column processing information by the column processing circuit, column processing is performed, and the prior value log ratio information updated as column processing output information is stored in the memory. And a step of outputting to the unit.

  ADVANTAGE OF THE INVENTION According to this invention, the error correction code decoding apparatus which reduced the capacity | capacitance of the memory by Min-Sum decoding method, and the decoding method using the same can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, an error correction code decoding apparatus according to Embodiment 1 of the present invention will be described with reference to the drawings. 1 is a block diagram showing an error correction code decoding apparatus, FIG. 2 is a block diagram showing a row processing circuit of the error correction code decoding apparatus, and FIG. 3 is a block diagram of a column processing circuit of the error correction code decoding apparatus. In this embodiment, a row processing output memory, a column processing output memory, an input likelihood ratio memory, and an estimated word memory are provided in the memory unit.

  As shown in FIG. 1, the error correction code decoding apparatus 1 includes a memory unit 2, a controller 3, a partial parallel row processing circuit unit 4, a partial parallel column processing circuit unit 5, a partial parallel estimated word calculation circuit unit 6, and a parity. A check circuit 7 is provided, and simultaneously executes row processing and column processing of error correction code decoding processing based on the log domain Min-Sum decoding method. Note that the row processing circuit, the column processing circuit, and the estimated word calculation circuit have a partial parallel configuration (partial parallel type configuration) in order to cope with a long code length. Here, the partial parallel configuration is a configuration in which processing information is subjected to row processing, column processing, and estimated word calculation for each partial unit.

  The controller 3 supervises various processing operations in the error correction code decoding apparatus 1, and includes a memory unit 2, a partial parallel row processing circuit unit 4, a partial parallel column processing circuit unit 5, a partial parallel estimated word calculation circuit unit 6, and a parity An execution instruction or control to the inspection circuit 7 is performed.

  The memory unit 2 includes an input likelihood ratio memory 11, a row processing output memory 12, a column processing output memory 13, and an estimated word memory 14.

  The input likelihood ratio memory 11 inputs log likelihood ratio (also referred to as Log Likelihood Ratio LLR, expressed as λ) information input from the outside of the error correction code decoding apparatus 1 as an input signal IN, and the information Remember. Then, the log likelihood ratio λ information is output from the output node N1 to the partial parallel string processing circuit unit 5 and the partial parallel estimated word calculation circuit unit 6 during the decoding process.

  The row processing output memory 12 receives the row processing information output from the output node N4 of the partial parallel row processing circuit unit 5, and stores the information. Then, the row processing information is output from the output node N5 to the partial parallel column processing circuit unit 5 and the partial parallel estimated word calculation circuit unit 6.

  The column processing output memory 13 inputs column processing information output from the output node N2 of the partial parallel column processing circuit unit 5, and stores the information. Then, the column processing information is output from the output node N3 to the partial parallel row processing circuit unit 4.

  The estimated word memory 14 receives temporary estimated word information output from the output node N6 of the partial parallel estimated word calculation circuit unit 6, and stores the information. Then, the temporary estimated word information is output from the output node N7 to the parity check circuit 7, and the output estimated word information is output to the outside of the error correction code decoding apparatus 1 as an output signal Out1.

  In the partial parallel row processing circuit unit 4, a plurality of row processing circuits (also referred to as Check Function Unit CFUs) 15 for inputting column processing information (prior value log ratio information) output from the column processing output memory 13 are arranged in parallel. Has been. Each row processing circuit 15 performs row processing on each part of the column processing information based on the control of the controller 3.

  The column to which the log likelihood ratio λ information output from the input likelihood ratio memory 11 and the row processing information (external value log ratio information) output from the row processing output memory 12 are input to the partial parallel column processing circuit unit 5 A plurality of processing circuits (also referred to as Bit Function Unit BFU) 16 are arranged in parallel. Each column processing circuit 16 performs column processing on each part of the row processing information based on the control of the controller 3.

  The partial parallel estimated word calculation circuit unit 6 includes a plurality of estimated word calculation circuits 17 for inputting log likelihood ratio information output from the input likelihood ratio memory 11 and row processing information output from the row processing output memory 12. They are arranged in parallel. Each estimated word calculation circuit 17 calculates an estimated word from the log likelihood ratio and the row processing information based on the control of the controller 3, and calculates a decoding result as a temporary estimated word.

  The parity check circuit 7 receives the temporary estimated word information output from the estimated word memory 14, and determines whether or not the temporary estimated word is correctly decoded based on the control of the controller 3 (check whether it is a code word). To do. Then, the output parity information as the determination result is output to the outside of the error correction code decoding apparatus 1 as the output signal Out2.

  As shown in FIG. 2, the row processing circuit 15 includes an absolute value calculation unit 21, a minimum value search unit 22, a positive / negative code calculation unit 23, and a row processing output encoding unit 24.

  The absolute value calculator 21 receives column processing information output from the column processing output memory 13 and converts the information into an absolute value. The minimum value search unit 22 receives the absolute value information output from the absolute value calculation unit 21, obtains the minimum value and the second smallest value of the information, and outputs them to the row processing output memory 12 as a row processing output. In addition, information corresponding to the minimum value is output to the row processing output encoding unit 24.

  The positive / negative encoding calculation unit 23 receives the column processing information output from the column processing output memory 13 and calculates a positive / negative code corresponding to each input. The row processing output encoding unit 24 receives the information output from the minimum value search unit 22 and the information output from the positive / negative encoding calculation unit 23, generates a 2-bit code corresponding to the input, and outputs the code as a row processing output. Output to the row processing output memory 12.

  Here, instead of the row processing output encoding unit 24, the information output from the minimum value search unit 22 and the information output from the positive / negative sign calculation unit 23 are input, and the minimum value and the second smallest value are positive or negative. Add a sign to select either the minimum positive value, the minimum negative value, the second smallest positive value, or the second smallest negative value corresponding to each row processing input data, and the row processing of that information The amount of information output to the row processing output memory 12 can be reduced and the row processing output memory 12 can be suppressed as compared with the case where an absolute value / signed conversion unit that outputs to the output memory 12 is provided.

  As shown in FIG. 3, the column processing circuit 16 includes a column processing input decoding unit 25, an adder input selection unit 26, and a plurality of adders 27.

  The column processing input decoding unit 25 converts two types of absolute values and 2-bit codes as row processing output into data serving as input information for column processing. The adder input selection unit 26 outputs the converted information output from the column processing input decoding unit 25 to each adder 27. The adder 27 receives the log-likelihood ratio λ information output from the input likelihood ratio memory 11 and the converted information output from the adder input selection unit 26, adds them, and outputs the information as column processing output. Output to the memory 13.

  Next, decoding processing using the error correction code decoding apparatus will be described with reference to FIG. FIG. 4 is a flowchart showing the decoding process of the error correction code decoding apparatus.

  As shown in FIG. 4, first, for example, a binary M × N matrix (H = {Hmn}) is set as a parity check matrix of an LDPC code to be decoded, and for all sets (m, n) satisfying the parity check matrix Hmn. The prior value logarithmic ratio βmn is set to 0 (zero). Further, the loop variable L is set to 1, and the maximum number of loops is set to the variable Lmax (step S1).

  Next, the external value logarithmic ratio αmn is updated for all sets (m, n) in which the check matrix Hmn satisfies 1 in the order of m = 1, 2,... 12 is stored. The external value log ratio αmn is calculated by substituting the prior value log ratio βmn into the equation. Here, column processing information output from the column processing output memory 13 and input to the row processing circuit 15 is subjected to row processing by the row processing circuit 15 and output to the row processing output memory 12 in two types. Thus, the memory capacity of the row processing output memory 12 can be reduced. In addition, the display and description of the formula used to update the external value logarithmic ratio αmn are omitted.

  As the column processing, the prior value logarithmic ratio βmn is updated and stored in the column processing output 13 memory for all sets (m, n) in which the check matrix Hmn satisfies 1 in the order of n = 1, 2,. Is done. Here, the row processing information output from the row processing output memory 12 and input to the column processing circuit 16 is converted into data serving as column processing input information by the column processing input decoding unit 25 of the column processing circuit 16. The column processing circuit 16 performs column processing, and the information is output to the column processing output memory 13. Note that the prior value log ratio βmn is updated based on the log likelihood ratio λn and the corresponding external value log ratio αmn, but the display and description of the equations used for the update are omitted. Here, as described with reference to FIGS. 2 and 3, the row processing and the column processing are simultaneously performed in parallel (step S2).

  Subsequently, temporary estimated words are calculated by the estimated word calculation circuit 17 for n = 1, 2,... N (step S3). Then, the parity check circuit 7 checks whether the temporary estimated word is a code word (step S4). In addition, the display and description of the formula used for the inspection are omitted. When the temporary estimated word satisfies the check condition, it is output as an output parity that is an estimated word, and the decoding process ends. If the temporary estimated word does not satisfy the checking condition, if the loop count L is L ≦ Lmax, the loop count L is incremented and the process returns to step S2. If L> Lmax, it is regarded as a decoding error, a temporary estimated word is output, and the decoding process ends (step S6).

  As described above, in the error correction code decoding apparatus of the present embodiment, the row processing circuit 15 having the absolute value calculation unit 21, the minimum value search unit 22, the positive / negative code calculation unit 23, and the row processing output encoding unit 24 is provided in parallel. An arranged partial parallel row processing circuit unit 4 is provided. Then, two types of absolute values and 2-bit code information as the row processing output are output from the row processing circuit 15 to the row processing output memory 12.

  For this reason, it is possible to reduce the row processing information output to the row processing output memory more than before, and to reduce the memory capacity of the row processing output memory. Accordingly, it is possible to reduce a memory area that occupies a large occupied area of the error correction code decoding apparatus 1 as a semiconductor integrated circuit, and to reduce the cost of the correction code decoding apparatus 1.

  In this embodiment, the hardware configuration of the error correction code decoding apparatus uses a partial parallel configuration (partial parallel type configuration) in which row processing and column processing are executed in parallel at the same time. Alternatively, a serial type configuration in which column processing is executed collectively or a fully parallel configuration (Fully Parallel type configuration) in which row processing and column processing are executed in parallel may be used. Even in this case, the amount of row processing information can be reduced, and the memory capacity for storing the row processing information can be reduced.

  Next, an error correction code decoding apparatus according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a row processing circuit of the error correction code decoding apparatus. The error correction code decoding apparatus of the present embodiment has the same configuration as that of the first embodiment. In this embodiment, the column processing information output from the column processing output memory and input to the row processing circuit is converted into six data of 6 bits each. Yes.

  As shown in FIG. 5, the row processing circuit 15a of the error correction code decoding apparatus includes an absolute value calculation unit 21a, a minimum value search unit 22a, a positive / negative code calculation unit 23a, and a row processing output encoding unit 24a. Yes.

  The absolute value calculation unit 21a inputs six pieces of data column processing information output from the column processing output memory 13 and calculates the information as six absolute values of 5 bits each. The minimum value search unit 22a receives the absolute value information output from the absolute value calculation unit 21a, obtains the minimum value and the second smallest value of the information, and stores them in the row processing output memory 12a as two data in 5 bits each. Output. In addition, information indicating an input corresponding to the minimum value is output to the row processing output encoding unit 24a as 3-bit data.

  The positive / negative encoding calculation unit 23a inputs six pieces of column processing information of 6 bits output from the column processing output memory 13, and calculates 6 pieces of data by 1 bit. The row processing output encoding unit 24a inputs 3-bit data information output from the minimum value search unit 22a and 6 data information in each 1-bit output from the positive / negative encoding calculation unit 23a, and the minimum value corresponding to the input Alternatively, 6 data are generated in 2 bits each of 1-bit information for selecting the second smallest value and 1-bit information for selecting the positive / negative sign, and are output to the row processing output memory 12a as the row processing output. . Since the configuration of the column processing circuit is the same as that of the first embodiment, illustration and description thereof are omitted.

  Next, the memory capacity of the row processing output memory of the error correction code decoding apparatus will be described with reference to FIG. FIG. 6 is a diagram comparing the memory capacities of the row processing output memories of the error correction code decoding apparatus. Here, the information output from the minimum value search unit and the information output from the positive / negative sign calculation unit are input, the positive and negative signs are attached to the minimum value and the second smallest value, and each line processing input data is supported. Select the positive minimum value, negative minimum value, positive second smallest value or negative second smallest value, and output the information to the row processing output memory. The case where it is provided is conventional. The number of rows is A.

  As shown in FIG. 6, conventionally, the row processing output memory capacity per row is 6 bits × 6 = 36 bits, and the memory capacity of the row processing output memory is 36 bits × A = 36 Abits.

  On the other hand, in this embodiment, the row processing output memory capacity per row is (2 bits × 6) + (5 bits × 2) = 22 bits, and the memory capacity of the row processing output memory 12a is 22 bits × A = 22 Abit. As a result, the memory capacity of the 38.9% row processing output memory can be reduced.

  As described above, the error correction code decoding apparatus according to the present embodiment includes the row processing circuit 15a including the absolute value calculation unit 21a, the minimum value search unit 22a, the positive / negative code calculation unit 23a, and the row processing output encoding unit 24a. It has been. The column processing information output from the column processing output memory 13 and input to the row processing circuit 15a has six data (36 bits of data) each having 6 bits, and each 5 bits as a row processing output from the row processing circuit 15a. 2 code values (2 bits) and 6 code information (22 bits data) are output to the row processing output memory 12a.

  For this reason, the line processing information output to the row processing output memory can be reduced by 38.9% as compared with the prior art, and the memory capacity of the row processing output memory can be reduced. Therefore, it is possible to reduce a memory area that occupies a large occupied area of the error correction code decoding apparatus 1 as a semiconductor integrated circuit, and to reduce the cost of the error correction code decoding apparatus 1.

  Next, an error correction code decoding apparatus according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a row processing circuit of the error correction code decoding apparatus. The error correction code decoding apparatus of this embodiment has the same configuration as that of the first embodiment except for the row processing circuit. In this embodiment, the column processing information output from the column processing output memory and input to the row processing circuit is 6 bits each. There are 6 data.

  As shown in FIG. 7, the row processing circuit 15b of the error correction code decoding apparatus includes an absolute value calculation unit 21b, a minimum value search unit 22b, and a positive / negative code calculation unit 23b.

  The absolute value calculation unit 21b inputs six pieces of data column processing information output from the column processing output memory 13 and calculates the information as six absolute values of 5 bits each. The minimum value search unit 22b receives the absolute value information output from the absolute value calculation unit 21b, obtains the minimum value and the second smallest value of the information, and stores them in the row processing output memory 12b as two data in 5 bits each. Output. In addition, information indicating an input corresponding to the minimum value is output to the row processing output memory 12b as 3-bit data.

  The positive / negative encoding calculation unit 23b inputs six pieces of column processing information of 6 bits each output from the column processing output memory 13, calculates 6 pieces of data by 1 bit, and stores the information in the row processing output memory 12b. Output. Since the configuration of the column processing circuit is the same as that of the first embodiment, illustration and description thereof are omitted.

  Next, the memory capacity of the row processing output memory of the error correction code decoding apparatus will be described with reference to FIG. FIG. 8 is a diagram comparing the memory capacities of the row processing output memories of the error correction code decoding apparatus. Here, the information output from the minimum value search unit and the information output from the positive / negative sign calculation unit are input, the positive and negative signs are attached to the minimum value and the second smallest value, and each line processing input data is supported. Select the positive minimum value, negative minimum value, positive second smallest value or negative second smallest value, and output the information to the row processing output memory. The case where it is provided is conventional. The number of rows is A.

  As shown in FIG. 8, conventionally, the row processing output memory capacity per row is 6 bits × 6 = 36 bits, and the memory capacity of the row processing output memory is 36 bits × A = 36 Abits.

  On the other hand, in this embodiment, the row processing output memory capacity per row is (1 bit × 6) + (5 bits × 2) +3 bits = 19 bits, and the memory capacity of the row processing output memory 12b is 19 bits × A = 19 Abits. The memory capacity of the 47.2% row processing output memory can be reduced as compared with the prior art.

  As described above, the error correction code decoding apparatus according to the present embodiment includes the row processing circuit 15b including the absolute value calculation unit 21b, the minimum value search unit 22b, and the positive / negative code calculation unit 23b. The column processing information output from the column processing output memory 13 and input to the row processing circuit 15b has 6 data (36 bits of data) each having 6 bits, and each 5 bits as a row processing output from the row processing circuit 15b. The two absolute values, the 3-bit data corresponding to the minimum value, and the 6-bit data information (19-bit data) in 1 bit are output to the row processing output memory 12b.

  For this reason, the row processing information output to the row processing output memory can be reduced by 47.2%, and the memory capacity of the row processing output memory can be reduced. Therefore, it is possible to reduce a memory area that occupies a large occupied area of the error correction code decoding apparatus 1 as a semiconductor integrated circuit, and to reduce the cost of the error correction code decoding apparatus 1.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the second and third embodiments, the information output from the column processing output memory to the row processing circuit has a 6-bit 6-data (36-bit) configuration, but is not limited to this configuration. For example, a 6-bit 3 data (18-bit) configuration may be used.

The present invention can be configured as described in the following supplementary notes.
(Supplementary note 1) A memory unit for storing row processing information, column processing information, and log likelihood ratio information, and column processing information having 6 data stored in 6 bits stored in the memory unit, and 6 bits each for 6 bits. An absolute value calculation unit that calculates as two pieces of absolute value information, and the absolute value information output from the absolute value calculation unit are input to obtain the minimum value and the second smallest value, and two data are processed in 5 bits each. A minimum value search unit that outputs to the memory unit as output information, and a positive / negative code calculation unit that inputs column processing information having 6 data in 6 bits stored in the memory unit and calculates 6 data in 1 bit each And 3 bits of data indicating the input corresponding to the minimum value output from the minimum value search unit and 6 data of each 1 bit output from the positive / negative sign calculation unit, and corresponding to the input 6 data are generated in 2 bits each consisting of 1 bit data for selecting the smallest value or the second smallest value and 1 bit data for selecting the positive / negative sign, and are stored in the memory unit as row processing output information. A row processing circuit having a row processing output encoding unit to output, and column processing by inputting 22-bit row processing information consisting of 2 data in 5 bits each and 6 data in 2 bits each stored in the memory unit A column processing input decoding unit that converts 6-bit data into 6-bit data as input information, an adder input selection unit that selectively outputs conversion information output from the column processing input decoding unit, and a memory unit The log likelihood ratio information to be stored and the conversion information output from the adder input selection unit are input and added, and output to the memory unit as column processing output information. Error correction code decoding apparatus comprising a column processing circuit and an adder.

(Supplementary Note 2) A memory unit for storing row processing information, column processing information, and log likelihood ratio information, and column processing information having 6 data stored in the memory unit and 6 bits of data are input, and 6 bits for each 5 bits. An absolute value calculation unit that calculates as two pieces of absolute value information, and the absolute value information output from the absolute value calculation unit are input, and the minimum value and the second smallest value are obtained to obtain two data and minimum values in 5 bits each. A minimum value search unit that outputs 3-bit data indicating input corresponding to the row processing output information to the memory unit, and column processing information having 6 data stored in the 6-bit stored in the memory unit, A row processing circuit having a row processing output encoding unit that calculates 6-bit data in 1 bit and outputs the data to the memory unit as row processing output information, and two 5 bit units stored in the memory unit. Column processing input for inputting data, 3 bits of data indicating input, and 19 bits of the row processing information including 6 data in 1 bit and converting the data into 6 data in 6 bits as input information of column processing From the decoding unit, the adder input selection unit that selectively outputs the conversion information output from the column processing input decoding unit, the log likelihood ratio information stored in the memory unit, and the adder input selection unit An error correction code decoding apparatus comprising: a column processing circuit including an adder that inputs the conversion information to be output and performs addition processing and outputs the addition information to the memory unit as column processing output information.

1 is a block diagram showing an error correction code decoding apparatus according to Embodiment 1 of the present invention. 1 is a block diagram showing a row processing circuit of an error correction code decoding apparatus according to Embodiment 1 of the present invention. 1 is a block diagram showing a column processing circuit of an error correction code decoding apparatus according to Embodiment 1 of the present invention. 3 is a flowchart showing decoding processing of the error correction code decoding apparatus according to Embodiment 1 of the present invention. The block diagram which shows the row processing circuit of the error correction code decoding apparatus which concerns on Example 2 of this invention. The figure which compared the memory capacity of the row processing output memory of the error correction code decoding apparatus which concerns on Example 2 of this invention. The block diagram which shows the row processing circuit of the error correction code decoding apparatus which concerns on Example 3 of this invention. The figure which compared the memory capacity of the row processing output memory of the error correction code decoding apparatus which concerns on Example 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Error correction code decoding apparatus 2 Memory part 3 Controller 4 Partial parallel row processing circuit part 5 Partial parallel column processing circuit part 6 Partial parallel estimation word calculation circuit part 7 Parity check 11 Input likelihood ratio memory 12, 12a, 12b Row processing output Memory 13 Column processing output memory 14 Estimated word memories 15, 15a, 15b Row processing circuit 16 Column processing circuit 17 Estimated word calculation circuits 21, 21a, 21b Absolute value calculation units 22, 22a, 22b Minimum value search units 23, 23a, 23b Positive / negative code calculation unit 24, 24a Row processing output encoding unit 25 Column processing input decoding unit 26 Adder input selection unit 27 Adder IN Input signal N1-7 Output nodes Out1, Out2 Output signal

Claims (5)

A memory unit for storing row processing information, column processing information, and log likelihood ratio information;
An absolute value calculation unit that inputs the column processing information stored in the memory unit and converts it into an absolute value, inputs absolute value information output from the absolute value calculation unit, and inputs the minimum value and the absolute value information from the absolute value information. Find the second smallest value, input the minimum value search unit to output to the memory unit as row processing output information, and input the column processing information stored in the memory unit, and enter the positive and negative signs corresponding to each input A sign calculation unit to calculate, information indicating an input corresponding to the minimum value output from the minimum value search unit and calculation information output from the sign calculation unit are input, and a 2-bit code corresponding to the input is input. A row processing circuit having a row processing output encoding unit that generates and outputs to the memory unit as row processing output information;
A column processing input decoding unit that inputs the row processing information stored in the memory unit and converts it into column processing input information, and an adder that selectively outputs the conversion information output from the column processing input decoding unit An input selection unit, the log likelihood ratio information stored in the memory unit and the conversion information output from the adder input selection unit are input and added, and output to the memory unit as column processing output information A column processing circuit having an adder for
An error correction code decoding apparatus comprising: A memory unit for storing row processing information, column processing information, and log likelihood ratio information;
An absolute value calculation unit that inputs the column processing information stored in the memory unit and converts it into an absolute value, and inputs absolute value information that is output from the absolute value calculation unit. Input a second value information and a minimum value search unit that outputs information indicating the input corresponding to the minimum value to the memory unit as row processing output information, and the column processing information stored in the memory unit. A row processing circuit having a positive / negative sign calculation unit that calculates a positive / negative sign corresponding to each input and outputs the calculated value as row processing output information to the memory unit;
A column processing input decoding unit that inputs the row processing information stored in the memory unit and converts it into column processing input information, and an adder that selectively outputs the conversion information output from the column processing input decoding unit An input selection unit, the log likelihood ratio information stored in the memory unit and the conversion information output from the adder input selection unit are input and added, and output to the memory unit as column processing output information A column processing circuit having an adder for
An error correction code decoding apparatus comprising: A memory unit for storing row processing information, column processing information, estimated word information, and log likelihood ratio information;
An absolute value calculation unit that inputs the column processing information stored in the memory unit and converts it into an absolute value, inputs absolute value information output from the absolute value calculation unit, and inputs the minimum value and the absolute value information from the absolute value information. Find the second smallest value and input the minimum value search unit to output to the memory unit as row processing information and the column processing information stored in the memory unit to calculate the positive and negative signs corresponding to each input A sign calculation unit that performs input, information indicating an input corresponding to the minimum value output from the minimum value search unit, and calculation information output from the sign calculation unit are input, and a 2-bit code corresponding to the input is generated. A partial parallel row processing circuit unit in which row processing circuits having a row processing output encoding unit that outputs to the memory unit as row processing output information are arranged in parallel;
A column processing input decoding unit that inputs the row processing information stored in the memory unit and converts it into column processing input information, and an adder that selectively outputs the conversion information output from the column processing input decoding unit An input selection unit, the log likelihood ratio information stored in the memory unit and the conversion information output from the adder input selection unit are input and added, and output to the memory unit as column processing output information A partial parallel column processing circuit unit in which column processing circuits having an adder are arranged in parallel;
The log likelihood ratio information stored in the memory unit and the row processing information stored in the memory unit are input to calculate an estimated word, a decoding result is calculated as a temporary estimated word, and as estimated word output information A partially parallel estimated word calculation circuit unit in which estimated word calculation circuits to be output to the memory unit are arranged in parallel;
A parity check circuit that inputs the estimated word information stored in the memory unit and determines whether or not it has been correctly decoded;
An error correction code decoding apparatus using a log domain Min-Sum decoding method. A memory unit that stores row processing information, column processing information, estimated word information, and log likelihood ratio information; and an absolute value calculation unit that inputs the column processing information stored in the memory unit and converts the column processing information into an absolute value; The absolute value information output from the absolute value calculation unit is input, and the memory unit uses, as row processing information, information indicating the minimum value, the second smallest value information, and the input corresponding to the minimum value from the absolute value information. A minimum value search unit that outputs to the memory, and the row processing that inputs the column processing information stored in the memory unit, calculates a positive / negative sign corresponding to each input, and outputs the calculated sign as row processing output information to the memory unit A partial parallel row processing circuit unit in which row processing circuits having an output encoding unit are arranged in parallel;
A column processing input decoding unit that inputs the row processing information stored in the memory unit and converts it into column processing input information, and an adder that selectively outputs the conversion information output from the column processing input decoding unit An input selection unit, the log likelihood ratio information stored in the memory unit and the conversion information output from the adder input selection unit are input and added, and output to the memory unit as column processing output information A partial parallel column processing circuit unit in which column processing circuits having an adder are arranged in parallel;
The log likelihood ratio information stored in the memory unit and the row processing information stored in the memory unit are input to calculate an estimated word, a decoding result is calculated as a temporary estimated word, and as estimated word output information A partially parallel estimated word calculation circuit unit in which estimated word calculation circuits to be output to the memory unit are arranged in parallel;
A parity check circuit that inputs the estimated word information stored in the memory unit and determines whether or not it has been correctly decoded;
An error correction code decoding apparatus using a log domain Min-Sum decoding method. The column processing information stored in the memory unit is input to the row processing circuit, the column processing information is calculated as two kinds of absolute values and 2-bit code information in the row processing circuit, and updated as row processing output information. Outputting value log ratio information to the memory unit;
The row processing information stored in the memory unit is input to the column processing circuit, the row processing information is converted into column processing information by the column processing circuit, the column processing is performed, and the column processing output information is updated. Outputting prior value log ratio information to the memory unit;
A decoding method using an error correction coding apparatus characterized by comprising:

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