JP2006331476A - Nonvolatile semiconductor memory apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory apparatus in which occurrence of a reactive current can be prevented. <P>SOLUTION: The apparatus is provided with a memory cell array in which nonvolatile memory cells being electrically re-writable are arranged in a matrix state, a plurality of word line selecting circuit selecting a word line of the memory cell in accordance with address input, a potential supply circuit supplying the prescribed potential to a word line, and a plurality of discharge circuits discharging the word line in write in operation, the discharge circuit can switch a discharge condition. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).

  A NAND flash memory is known as one of the EEPROMs. A nonvolatile memory cell of a NAND flash memory has a charge storage layer called a floating gate, which is formed on a semiconductor substrate via an insulating film, and a control gate stacked via an insulating film. In a NAND flash memory, a plurality of nonvolatile memory cells are connected in series, and a memory cell array is configured by integrating a plurality of NAND columns each having a selection transistor connected to a bit line and a selection transistor connected to a common source line at both ends thereof. Has been. Therefore, the NAND flash memory has a high integration density and is suitable as a large-capacity storage device. Therefore, the demand for NAND flash memories is expanding as a recording medium used for digital still cameras, digital video cameras, portable music terminals, video terminals and the like.

In a NAND flash memory, a plurality of NAND strings are integrated to form a block, which is normally used as an erase unit. Usually, a plurality of blocks are integrated to form a memory cell array.
The data write operation of the NAND flash memory is mainly performed in order from the memory cell located farthest from the bit line. First, when the data write operation is started, 0 V (“0” data write) or power supply voltage Vcc (“1” data write) is applied to the bit line according to the write data, and the selected bit line side is selected. Vcc is applied to the gate line. In this case, when the bit line is 0V, in the connected selected NAND cell, the channel portion in the NAND cell is fixed to 0V via the selection gate transistor. When the bit line is at Vcc, in the connected selected NAND cell, the channel portion in the NAND cell reaches [Vcc-Vtsg] (where Vtsg is the threshold voltage of the selected gate transistor) via the selection gate transistor. After being charged, it enters a floating state.

  Subsequently, the control gate line of the selected memory cell in the selected NAND cell is changed from 0 V to Vpp (= about 20 V: high voltage for writing), and the control gate line of the non-selected memory cell in the selected NAND cell is changed from 0 V to Vmg (= 10V: intermediate voltage).

  Here, when the bit line is 0V, in the selected NAND cell connected, the channel portion in the NAND cell is fixed at 0V. Therefore, the gate (= Vpp potential) and the channel portion of the selected memory cell in the selected NAND cell. A large potential difference (about 20V) is generated at (= 0V), and electrons are injected from the channel portion to the floating gate. As a result, the threshold value of the selected memory cell is shifted in the positive direction. This state is data “0”.

  On the other hand, when the bit line is at Vcc, in the selected NAND cell connected, the channel portion in the NAND cell is in a floating state, so control due to the influence of capacitive coupling between the control gate line and the channel portion in the selected NAND cell. As the gate line voltage rises (0 V → Vpp, Vmg), the potential of the channel portion rises from the [Vcc-Vtsg] potential to Vmch (= about 8 V) while maintaining the floating state. At this time, since the potential difference between the gate (= Vpp potential) and the channel portion (= Vmch) of the selected memory cell in the selected NAND cell is as small as about 12 V, electron injection does not occur. The threshold does not change and remains negative. This state is data “1”.

  Data erasure in the NAND flash memory is simultaneously performed on all the memory cells in the selected NAND cell block. That is, all the control gates in the selected NAND cell block are set to 0 V, the bit line, the source line, the control gates in the non-selected NAND cell block and all the selection gates are set to floating, and the p-type well (or p-type substrate) is set. ) Is applied with a high voltage of about 20V. Thereby, in all the memory cells in the selected NAND cell block, electrons of the floating gate are released to the p-type well (or p-type substrate), and the threshold voltage is shifted in the negative direction. As described above, in the NAND cell type flash memory, the data erasing operation is collectively performed in units of blocks.

  In the data read, the control gate of the selected memory cell is set to 0V, and the control gate and the select gate of the other memory cells are set to a voltage (for example, 5V) defined by the stress during the read operation. This is done by detecting whether or not.

  Normally, the threshold value after writing “0” data must be controlled between about 0V and about 4V. For this reason, the write verify is performed, only the memory cells insufficiently written “0” are detected, and the rewrite data is set so that only the memory cells insufficiently written “0” data are rewritten (for each bit). (Verify). A memory cell in which “0” data is insufficiently written is detected by reading the selected control gate with, for example, 0.5 V (verify voltage) (verify read). That is, if the threshold voltage of the memory cell is not 0.5 V or more with a margin with respect to 0 V, a current flows in the selected memory cell, and it is detected that “0” data writing is insufficient.

  By writing data while repeating the write operation and write verify, the write time is optimized for each memory cell, and the threshold value after writing “0” data is controlled between 0V and about 4V. .

Usually, the write operation is managed in units of blocks. However, there is a case where it is required to perform writing to a plurality of blocks at once, which is disclosed in Patent Document 1, for example. Such batch writing to all blocks and all memory cells is referred to as flash write in this specification.
JP 2003-208793 A

    An object of the present invention is to provide a nonvolatile semiconductor memory device that prevents a defective writing operation.

  A memory cell array in which electrically rewritable nonvolatile memory cells are arranged in a matrix, a plurality of word line selection circuits for selecting word lines of the memory cells in response to an address input, and a predetermined potential on the word lines And a plurality of discharge circuits for discharging the word line in a write operation, wherein the discharge circuit can switch discharge conditions.

  According to the present invention, a nonvolatile semiconductor memory device with low current consumption can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a chip layout example of the semiconductor integrated circuit device according to the first embodiment of the present invention. The semiconductor integrated circuit device shown in FIG. 1 is, for example, a NAND flash memory.

  As shown in FIG. 1, for example, two memory cell arrays 110 are arranged on a semiconductor chip, for example, a silicon chip 100. For example, row decoders 102 are arranged at both ends of the memory cell array 110 in the column direction, for example. For example, a page buffer 3, a memory peripheral circuit 104, a charge pump circuit 106, and a pad 108 are sequentially arranged at one of both end portions along the row direction of the memory cell array 101. The memory peripheral circuit 104 includes circuits such as a command decoder and a memory cell array control circuit, and the charge pump circuit 106 includes capacitors and transistors used for a booster circuit (charge pump circuit). A terminal (pad) serving as a connection point between the chip 100 and the outside is disposed on the pad 108. As shown in the figure, in this embodiment, terminals, charge pump circuits, and the like are arranged only on one side of the memory cell array.

  A detailed configuration of the semiconductor memory device of FIG. 1 will be described with reference to FIGS. An example of the NAND string of the present invention is shown in FIG. As shown here, for example, NAND type memory cells MC are connected in series from MC0 to MC15. MC0 is connected to the common source line CELSRC via the selection gate SG1. MC15 is connected to the bit line BL via the selection gate SG2.

  FIG. 3 is a block diagram of the nonvolatile semiconductor memory device according to this embodiment. The configuration of FIG. 2 corresponds to the NAND cell 10 of FIG. 3 includes a selection transistor ST2 on the bit line BL0 to BLi (i is an integer of 0 or more) side, a selection transistor ST1 on the common source line CELSRC side, and the two selection transistors ST1 and ST2. The memory cells MC are connected in series. Further, the word lines WL0 to WL15 and the select gate lines SG1 and SG2 are arranged to share the block 12 (BLOCK n), and a plurality of blocks 12 are arranged to form a memory cell array. In FIG. 3, adjacent blocks 11 and 13 are shown in a simplified manner. This memory cell array corresponds to the memory cell array 110 of FIG. The block 12 and the like correspond to the block 120 in the memory cell array of FIG.

In order to output a desired voltage to the word lines and selection gates in the NAND cell, the SGS driver 7 for the selection gate line SG1, the SGD driver 5 for the selection gate line SG2, and a plurality of words for the plurality of word lines. The CG driver 6 and the word line discharge control circuit 15 are connected via the transfer transistor 9. These driver circuits 5 to 7 and the word line control circuit 15 are all arranged in the peripheral circuit 104 of FIG.

  A word line is selected by a row decoder 14 including a decoder 1 to which a row address signal is input, a VT driver 2 and a transfer transistor 9. The row decoder is arranged in the row decoder 102 in FIG.

The CG driver 6 receives the V _PGM potential from the V _PP pump, the V _PASS pump receives the V _PASS potential, and the transfer transistor 9 receives the VT _GATE potential from the V _PP pump 3 via the VT driver 2. Yes. Each pump is arranged in the area of the charge pump circuit 106 in FIG.

  Here, a write operation to the NAND type memory cell will be described with reference to FIGS. 2 and 3 and FIG. FIG. 4 shows a timing chart of the write operation.

When writing to the memory cell with threshold shift, the bit line BL is set to 0V.

Here, when the V _DD potential is applied to the gate of the selection transistor ST2, the selection transistor ST2 is turned on, and the V _PASS potential is applied to the gates of the non-write memory cells MC0 and MC2 to MC15, and writing is performed. A _VPGM potential is applied to the gate of the memory cell MC1 to be performed, and each memory cell is turned on. The CELSRC signal line is applied with a potential of 1 to 2 V, but 0 V is applied to the gate of the selection transistor ST1, and the selection transistor ST1 is cut off. The potential of 0V from the bit line is transferred to the memory cell MC1 via a selection gate ST2 and memory cell MC2～MC15, the memory cell MC1, the potential difference _{V PGM} occurs between the gate and the channel.

Therefore, electrons are injected into the floating gate and writing is performed. Since the V _PASS potential which is an intermediate potential is applied to the gates of the memory cells MC0 and MC2 to MC15, writing to these memory cells is not performed.

On the other hand, when writing without threshold shift, the bit line BL is set to the V _DD potential. In this case, the select transistor ST2 cuts off after transferring the potential of V _DD -Vt (Vt is the threshold value of the select transistor ST2) into the NAND cell. Accordingly, the memory cell MC 0, gives _{V PASS} potential to the gate of MC2～MC15, given a _{V PGM} potential to the gate of the memory cell MC1, the NAND type cell all channels potential coupling a _{floating, V DD} It rises to a potential higher than −Vt. As a result, a potential difference that does not generate an FN (Fowler-Nordheim) tunnel current is applied between the gate and the channel of the selected memory cell MC1, and a threshold shift does not occur.

When the write operation is started at time T0, the potential of V _PGM + Vtn is applied to the transfer gate 9 to turn on, and at time T1, the V _PGM potential is applied to the selected word line and the V _PASS potential is applied to the unselected word line. At time T2, the selected word line potential starts to drop. Next, at time T3, the potential of the unselected word line starts to drop. At time T4, the transfer gate starts to descend. The selected bit line BL, if "1" is _programmed, becomes _{V DD} level, if "0" is _programmed, the _{V SS} level. The selection gates SGD and SGS become V _DD and 0 V, respectively, at time T0, and both become 0 V at time T4.

  The write operation described above is usually performed in units of predetermined blocks. On the other hand, as another function, there is a write operation to all memory cells in all blocks of the nonvolatile semiconductor memory device. This operation is hereinafter referred to as a flash write operation. Hereinafter, the flash write operation will be described with reference to FIG. FIG. 5 is a write timing chart during flash write.

As shown in FIG. 5, the write operation starts at time T0 ′ (for example, 0 μs). Then, the potential of V _PGM + Vtn is applied to the transfer gate 9 to be turned on, and the V _PGM potential is applied to all the word lines at time T1 ′ (for example, 5 μs after T0 ′). At this time, since all the word lines are selected, the potential of the transfer gate temporarily decreases. Thereafter, it gradually returns to the original potential. Next, at time T2 ′ (for example, 20 μs after T0 ′), the selected word line potential starts to drop.

  Here, the present inventor has found that a problem may occur in the following operation following the above. In the following, problems found by the present inventor and countermeasures thereof will be described.

At T2 ′ in FIG. 5, the selected word line potential starts to drop. At this time, the potentials of all the word lines are suddenly _extracted from the _VPGM potential to 0V. This completes the potential drop at time T3 ′ (for example, 21 μs after T0 ′). The selection gate SGD that has been at the V _DD potential due to this coupling and the SGS that has been at 0 V may drop to a negative potential of about −0.5 V, as shown in the figure. I understood it. It has been found that this phenomenon is likely to occur particularly when the gate length of the nonvolatile memory cell is 90 nm or less. A phenomenon that may occur in this case will be described with reference to FIG. 7 which is a circuit diagram showing the potential relationship during flash write, and FIG. 6 is a conceptual diagram of a cell section showing the potential relationship during flash write. As shown here, for example, a negative potential (for example, through a P well region under the STI region that partitions each transistor from the n channel region (the Gate 3 portion in FIG. 6) of the row decoder having a high potential (for example, 20 V). It has been found that there is a possibility that a current flows in the n-channel region (the Gate 1 portion in FIG. 6) of the selection gate SGD or SGS that is −0.5 V). That is, it was found that unexpected bipolar operation may occur in this region. The generation of such a current is not preferable because it is not only a reactive current that does not contribute to a desired operation of the semiconductor device but also may cause a malfunction.

Hereinafter, based on the above knowledge, a second embodiment of the present invention will be described with reference to the drawings.
(Second Embodiment)
A nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a schematic configuration diagram of the nonvolatile semiconductor memory device, FIG. 9 is a specific circuit example of the nonvolatile semiconductor memory device shown in FIG. 8, and FIG. 10 shows an operation waveform of the flashlight.

  FIG. 8 is the same as the first embodiment except that the configuration of the word line discharge control circuit 15 is different from that of the nonvolatile semiconductor memory device shown in FIG. 3 of the first embodiment. is there. Therefore, the same parts are denoted by the same reference numerals and description thereof is omitted. In the present embodiment, the word line discharge control circuit 8 corresponding to the word line discharge control circuit 15 in FIG. 8 performs a write operation performed in a predetermined block unit and a write operation (flash) to all memory cells in all blocks. The discharge method can be switched between “light” and “light”.

  The word line discharge circuit control 8 includes a word line discharge circuit control 8A that is controlled by DISCHARGE_A and DISCHARGE_B signals that are turned on during a normal write operation, and a word line discharge circuit control 8B that is controlled by a DISCHARGE_C signal that is turned on during flash write. Is done.

The word line discharge control circuit of this embodiment will be described in more detail with reference to FIG. The word line discharge control circuit of FIG. 9 includes a D type (depletion type) transistor T20 having V _DD supplied to the gate and CGn connected to the drain side, and a transistor having the signal DISCHARGE_A supplied to the gate connected thereto. The unit in which T26 is connected in series is a plurality of sets (in FIG. 9, three sets each including T20, T21, and T22), V _DD is supplied to the gate, and D-type transistor T23 and gate having CGn connected to the drain side The transistor T27 to which the signal DISCHARGE_B is supplied is connected in series to a plurality of sets (two sets each including T23 and T24 in FIG. 9), V _DD is supplied to the gate, and CGn is connected to the drain side. The signal DISCHARGE_C is supplied to the D-type transistor T25 and the gate. Transistor T31 is composed of the units connected in series.

In this circuit, the D-type transistors T20 to T25 whose gates are supplied with V _DD are always on, and the number of DISCHARGE_A to C signals input to the transistors T26 to T31 becomes the V _DD level. The discharge capacity at the CGn level changes.

For example, during a normal write operation, all DISCHARGE_A and B signals are set to the V _DD level. Thus, the transistors T26 to T30 are turned on. On the other hand, the DISCHARGE_C signal to _{V SS} level. As a result, the transistor T31 is turned off. As described above, the potential of CGn is discharged at a speed determined by the dimensions of the transistors T26 to T30.

In the flash write mode, only the DISCHARGE_C signal is set to the V _DD level. As a result, only the transistor T31 is turned on. On the other hand, the DISCHARGE_A signal and DISCHARGE_B signal to _{V SS} level. As a result, the transistors T26 to T30 are turned off. Therefore, the potential of CGn is discharged at a speed determined by the size of the transistor T31.

  According to this configuration, by setting the size of the transistor T31 to be smaller than the total size of T26 to T30, the discharge rate of the selected word line potential during the flash write operation can be reduced compared to the normal write operation. it can. FIG. 10 shows the flash write operation of this embodiment, and up to T2 ″ is the same as the conventional flash write operation shown in FIG. At time T <b> 2 ″, the selected word line potential starts to drop, but this way of falling is different from the conventional one.

  Conventionally, the word lines are discharged at the same speed as the normal write operation (T2 to T3 = T2 ′ to T3 ′). However, in this embodiment, the speed is slower than the normal write operation (T2 to T3 <T2 ″). ~ T3 ″), the word line is discharged. For example, it is effective if T3 ″ is about 23 μs while T3 ′ is after 21 μs.

As a result, there is no situation in which the select gates SGD and SGS during negative line discharge, which may occur in the conventional flash write operation, drop to a negative potential.

    In the second embodiment of the present invention, the switching of the word line discharging method in two cases in the normal block write operation and the flash write operation has been described. However, the configuration of the present invention is not limited to this switching. For example, when a predetermined number of word lines in the block are simultaneously selected, or a predetermined number of word lines in the block are simultaneously selected, and the predetermined number is selected. This may also be applied to the case where a plurality of blocks are simultaneously selected.

  In this case, any configuration may be used as long as it has a plurality of word line discharge control circuits, a plurality of DISCHARGE signals, and can switch a desired word line discharge method.

  It is sufficient that at least a plurality of word line discharging methods are provided.

  As described above, according to this embodiment, it is possible to provide a nonvolatile semiconductor memory device in which invalid current does not increase even when the size of the nonvolatile memory is reduced.

It is a figure which shows an example of the chip layout in 1st Embodiment of this invention. It is a figure which shows an example of a structure of the NAND row | line in 1st Embodiment of this invention. It is a figure which shows an example of the circuit block in 1st Embodiment of this invention. It is a figure which shows an example of the write-in timing chart in 1st Embodiment of this invention. It is a figure which shows an example of the write-in timing chart at the time of the flash write in 1st embodiment of this invention. It is a conceptual diagram which shows the electric potential relationship in the cell part cross section at the time of the flashlight in 1st embodiment of this invention. It is a circuit diagram which shows the electric potential relationship at the time of the flash write in 1st embodiment of this invention. It is a figure which shows an example of the circuit block in 2nd embodiment of this invention. It is a circuit diagram which shows an example of the discharge circuit in 2nd Embodiment of this invention. It is a figure which shows an example of the write-in timing chart at the time of the flash write in 2nd embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Decoder 2 ... VT driver 3 ... V _PP pump 4 ... V _PASS pump 5 ... SGD driver 6 ... CG driver 7 ... SGS driver 8, 15 ... Word line discharge control circuit 9 ... Transfer transistor 11, 12, 13 ... Cell block

Claims (5)

A memory cell array in which electrically rewritable nonvolatile memory cells are arranged in a matrix;
A plurality of word line selection circuits for selecting a word line of the memory cell according to an address input;
A potential supply circuit for supplying a predetermined potential to the word line;
A plurality of discharge circuits for discharging the word line in a write operation;
And the discharge circuit is capable of switching discharge conditions. A memory cell array in which electrically rewritable nonvolatile memory cells are arranged in a matrix;
A plurality of word line selection circuits for selecting a word line of the memory cell according to an address input;
A potential supply circuit for supplying a predetermined potential to the word line;
A plurality of discharge circuits for discharging the word line in a write operation;
And the discharge circuit is composed of a plurality of circuit groups that can be controlled independently of discharge. 3. The discharge time of the discharge circuit for the word line can be set to different desired times in a plurality of types of write operations for the memory cell. Nonvolatile semiconductor memory device. The plurality of types of write operations are performed in units of predetermined blocks constituting the memory cell array;
Are performed in units of a plurality of the predetermined blocks, and
The discharge time of the discharge circuit of the word line for the write operation performed simultaneously in the plurality of the predetermined block units is longer than the discharge time of the discharge circuit of the word line performed in the predetermined block unit. Item 4. The nonvolatile semiconductor memory device according to Item 3. The plurality of types of write operations simultaneously select a predetermined number of word lines in the block and a predetermined number of word lines in the block, and simultaneously select a predetermined number of blocks. things and,
The nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory device is included.

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