JP2006324425A - Manufacturing method of memory element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a memory element which is capable of easily and stably manufacturing the memory element. <P>SOLUTION: Upon manufacturing the memory element whose respective memory cells are constituted of a resistance changing element, consisting of a recording layer 2 between two sets of electrodes 1, 3 and the resistance value of the recording layer 2 is changed reversibly by impressing different potentials of two electrodes 1, 3, the resistance changing element is worked employing a soluble organic material as a mask 11, and an insulating layer 4 is formed by covering the mask 11 of the organic material. Further, the mask 11 and the insulating layer 4 on the mask 11 are removed selectively by lift-off method. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a memory element.

With the rapid spread of communication devices such as small mobile terminals and the spread of information processing devices such as personal computers, the memory that constitutes these devices has higher integration, higher speed, lower power consumption, etc. There is a need for performance.
In particular, increasing the density and capacity of memories has become an increasingly important issue, and process technology that will support future multi-layering such as further miniaturization and wiring is required.

  In information devices such as computers, DRAMs with high speed and high density are widely used as random access memories.

However, a DRAM has a higher manufacturing cost because a manufacturing process is more complicated than a general logic circuit LSI or signal processing used in an electronic device.
The DRAM is a volatile memory in which information disappears when the power is turned off, and it is necessary to frequently perform a refresh operation, that is, an operation of reading, amplifying, and rewriting the written information (data).

Thus, for example, FeRAM (ferroelectric memory), MRAM (magnetic memory element), and the like have been proposed as nonvolatile memories whose information does not disappear even when the power is turned off.
In the case of these memories, it is possible to keep the written information for a long time without supplying power.
In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

However, with the above-described nonvolatile memory, it is difficult to ensure characteristics as a memory element as the memory elements constituting each memory cell are reduced.
For this reason, it is difficult to reduce the element to the limit of the design rule and the limit of the manufacturing process.

As a large-capacity nonvolatile memory, resistance change type memories such as RRAM and PMC (Programmable Metallization Cell) have been proposed.
In these variable resistance nonvolatile memories such as RRAM and PMC, a material having a characteristic that a resistance value is changed by applying a voltage or current is used for a recording layer for storing and holding information.
Therefore, since the two electrodes are provided with the recording layer interposed therebetween and a voltage or current is applied to the two electrodes, the memory element can be easily miniaturized.

As a configuration of the RRAM, for example, when a polycrystalline PrCaMnO ₃ thin film is sandwiched between two electrodes and a voltage pulse or a current pulse is applied to the two electrodes, the resistance value of PrCaMnO ₃ as a recording film changes greatly. The configuration is introduced (see Non-Patent Document 1).

As another configuration of the RRAM, for example, the resistance of the recording film is changed by sandwiching SrZrO ₃ (single crystal or polycrystal) doped with a small amount of Cr between two electrodes and passing a current from these electrodes. The structure which performs is introduced (refer nonpatent literature 2).

PMC has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes, and two electrodes can be obtained by including a metal contained in the ionic conductor in one of the two electrodes. When a voltage is applied between them, a characteristic that changes electrical characteristics such as resistance or capacitance of the ionic conductor is used (for example, see Patent Document 1).
Specifically, the ionic conductor is made of a solid solution of chalcogenide and metal (for example, amorphous GeS or amorphous GeSe), and one of the two electrodes contains Ag, Cu, or Zn (patent) Reference 1).

The material constituting these devices is, for example, (Pr _0.7 Ca _0.3 ) MnO ₃ in RRAM, GeSe / AgGeSe, etc. in PMC, both of which are inexperienced materials in conventional semiconductor manufacturing processes.

In semiconductor devices, generally, an RIE (Reactive Ion Etching) method, which is one of etching methods, is used to process cells.
Using a processing technique such as RIE, all adjacent cells, or cells connected to the same selected line, and cells connected to adjacent non-selected lines are electrically and physically separated. As a result, electrical mutual interference can be reduced and unnecessary atomic diffusion of impurity elements can be prevented.

  In particular, the RIE method is ideally used because the constituent film elements are removed by etching in a gas phase by reaction with an etching gas, so that there is no fear of a decrease in yield due to reattachment of the etching target elements. ing.

Special Table 2002-536840 Publication W. W. Zhuang et al., “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, Technical Digest “International Electron Devices Meeting”, 2002, p. 193 A. Beck et al., “Reproducible switching effect in thin oxide films for memory applications”, Applied Physics Letters, 2000, vol. 77, p. 139-141

However, when the RIE method is performed on a memory element using a new material, vaporization may be difficult depending on the constituent elements.
In addition, even when vaporization is possible, a very long development period is required to optimize the conditions such as selection of reaction gas and optimization of etching conditions in order to improve the yield. .

Further, in the memory element using a new material, there is a problem in the method of connecting the upper wiring after forming the memory element of each memory cell in a predetermined shape.
As a method of connecting the element and the upper wiring, a method of forming an insulating layer such as SiO _{2 on} the entire surface by a CVD method and then opening the insulating layer by a lithography technique and an RIE technique is common.

  However, when connecting to the upper wiring by the above method, it is necessary to design a margin in consideration of misalignment and size variation among the three layers of the memory element (memory cell), the connection hole, and the upper wiring. It becomes an impediment to improvement.

  As a technique for solving this problem, there is a method in which the upper electrode of the memory element is exposed by polishing by a CMP (Chemical Mechanical Polishing) method.

  However, in this method, since the margin of the upper electrode determines the margin in the polishing process by the CMP method, the upper electrode needs to be formed relatively thick.

  However, if the upper electrode is formed thick, when the upper electrode is patterned using a mask, the variation of the planar pattern becomes large, and the pattern accuracy deteriorates. This is because the side wall of the patterned electrode is not completely perpendicular to the film surface but slightly inclined, so that the bottom surface of the upper electrode (ie, the surface in contact with the recording layer) is larger than the mask pattern. This is because the shift between the mask pattern and the electrode bottom pattern increases as the thickness of the upper electrode increases.

  In the resistance change type memory element, the current path may be restricted by the surface where the electrode and the recording layer are in contact with each other, and variations in the pattern of the bottom surface of the electrode may cause variations in characteristics of each memory cell. become.

In addition, if the upper electrode is lost due to excessive polishing, or if the upper electrode is not exposed due to insufficient polishing, the device does not operate as a memory element, and high-precision polishing is an essential condition.
For this reason, it is preferable to use a standard insulating material in a semiconductor process such as SiO ₂ whose polishing rate is known. If an insulating material suitable for a memory element having a new configuration is to be used, the polishing accuracy is reduced. This is accompanied by technical difficulty.

  In order to solve the above-described problems, the present invention provides a method for manufacturing a memory element that can easily and stably manufacture a memory element having good characteristics such as electrical characteristics.

  The method for manufacturing a memory element according to the present invention includes a recording layer between two electrodes, and a resistance whose resistance value of the recording layer changes reversibly by applying potentials having different polarities to the two electrodes. When manufacturing a memory element in which each memory cell is configured by a change element, a process of processing the resistance change element using a soluble organic material as a mask, and an electrical connection between the memory cells covering the organic material mask And a step of selectively removing the insulating layer on the mask by dissolving the organic material of the mask.

  The memory element manufactured by the manufacturing method of the present invention has a recording layer between two electrodes, and the resistance value of the recording layer changes reversibly by applying potentials having different polarities to these two electrodes. Since each memory cell is configured by a resistance change element, the resistance value of the resistance change element can be reversibly changed between a high resistance and a low resistance, and the resistance state of the resistance change element is Information can be stored in a memory cell.

According to the above-described method for manufacturing a memory element of the present invention, the step of processing the resistance change element using a soluble organic material as a mask, and the insulation for covering the organic material mask and electrically separating the memory cells A step of forming a layer, and a step of dissolving the organic material of the mask and selectively removing the insulating layer on the mask (that is, selectively removing the insulating layer on the mask by a so-called lift-off method). Have.
Since the insulating layer on the mask for processing the variable resistance element is selectively removed, in the variable resistance element processed by the mask, on the electrode (upper electrode) on the recording layer of the two electrodes. The existing mask and insulating layer are removed, and this electrode is exposed.
As a result, if a wiring layer is formed in a portion where the electrode is exposed and connected to the electrode, the wiring layer can be connected in self-alignment with the electrode.

Compared with the method of exposing the electrode by opening the insulating layer by the RIE method and the method of exposing the electrode by polishing by the CMP method, it is not necessary to set conditions according to the material of the memory element, and it is easy. The electrode can be exposed to and connected to the wiring layer.
Thus, since the electrode and the wiring layer can be easily connected, it is not necessary to form the electrode thickly, and it is possible to reduce the variation in the pattern of the electrode bottom by forming the electrode thinly.
Therefore, even if a new material is used for the memory element, the memory element can be easily manufactured with a high yield.

According to the above-described present invention, it is possible to reduce variations in the pattern on the bottom surface of the electrode, so that variations in the characteristics of the resistance change element of each memory cell can be reduced.
In addition, even if a new material is used for the memory element, it is possible to easily manufacture the memory element with a high yield, so that the memory element can be configured using a specific material having good recording characteristics. Become.

  Therefore, according to the present invention, it is possible to easily and stably manufacture a memory element having favorable characteristics such as electric characteristics.

In the present invention, a resistance change element that has a recording layer between two electrodes and reversibly changes the resistance value of the recording layer by applying potentials having different polarities to the two electrodes. A memory element in which each memory cell is configured is manufactured.
In the memory element configured as described above, the resistance value of the resistance change element can be reversibly changed between high resistance and low resistance, and the resistance state of the resistance change element is stored in the memory cell as information. be able to.
As a form of such a memory element, for example, a configuration shown in cross-sectional views in FIGS. 3A and 3B can be given.

  3A has a single-layer recording layer 2 between two electrodes, a lower electrode 1 and an upper electrode 3, and is composed of a laminated film of these three layers 1, 2, and 3. The change element 10 constitutes each memory cell. The resistance change elements 10 of each memory cell are separated by an insulating layer 4.

The recording layer 2 has a configuration in which the resistance value is reversibly changed by applying different polarities to the lower electrode 1 and the upper electrode 3.
As a material of the single recording layer 2, for example, (Pr _0.7 Ca _0.3 ) MnO ₃ described above can be used.

In the memory element shown in the sectional view in FIG. 3B, the recording layer 2 is a laminated film of two layers 2A and 2B.
The two layers 2A and 2B have a configuration in which, for example, the resistance value is reversibly changed by applying potentials having different polarities in both of the two layers or only one of the layers.
In the configuration in which the resistance values of the two layers 2A and 2B change, for example, two layers having different compositions and materials are stacked. For example, the aforementioned GeSe / AgGeSe or the like can be used.
In the configuration in which only one layer changes its resistance value, the other layer supplies carriers for changing the resistance value, improves the characteristics of the layer whose resistance value changes, and the electrodes 1 and 3 It is provided for the purpose of suppressing reaction and element diffusion.

Further, as a storage element manufactured by the manufacturing method of the present invention, for example, as in the configuration described in Patent Document 1 described above, the recording layer 2 is made of Ag, Cu, Zn or the like between the two electrodes 1 and 3. It is also possible to adopt a configuration including the variable resistance element 10 having a structure in which an ionic conductor containing a metal element serving as an ion source is sandwiched.
In this configuration, when the recording layer 2 is configured to include a metal element (Ag, Cu, Zn, or the like) that serves as an ion source, a metal that serves as an ion source when a voltage is applied between the two electrodes 1 and 3. Since the element diffuses as ions, this changes the electrical characteristics such as the resistance value or capacitance of the recording layer 2, so that information can be recorded using this characteristic.

  In the case of the memory element having this configuration, for example, one or two of the two layers 2A and 2B of the recording layer 2 shown in FIG. 3B include a metal element (Ag, Cu, Zn, etc.) serving as an ion source. In addition, one of the two layers 2A and 2B of the recording layer 2 can be configured such that the resistance value changes as ions of the metal element move.

The layer whose resistance value changes due to movement of ions of the metal element is preferably a high resistance layer made of an insulator or a semiconductor and having a relatively high resistance value.
As this high resistance layer, for example, a configuration made of an oxide or nitride containing a rare earth element can be considered.

  Then, one of the two layers 2A and 2B of the recording layer 2 shown in FIG. 3B is a layer containing a metal element (Ag, Cu, Zn, etc.) serving as an ion source (hereinafter referred to as an ion source layer), and the other is a high layer. As a resistance layer, it can be set as the structure which laminated | stacked these ion source layers and high resistance layers.

The ion source layer preferably contains one or more elements (chalcogenide elements) selected from S, Se, and Te.
More preferably, the ion source element includes Cu and the chalcogenide element includes Te, that is, the ion source layer includes CuTe. By including Cu and Te, the resistance value of the ion source layer can be reduced as compared with the case where other ion source elements (Ag, Zn) and chalcogenide elements (S, Se) are used.

As a material of the insulating layer 4 that separates the resistance change element 10 of each memory cell, an oxide or nitride of Al or Ta can be used in addition to SiO ₂ used in a general semiconductor device. .

  Next, a method for manufacturing the memory element shown in FIGS. 3A and 3B will be described as an embodiment of the method for manufacturing the memory element of the present invention.

First, as shown in FIG. 1A, the lower electrode 1, the recording layer 2, and the upper electrode 3 are sequentially formed to form a laminated film of resistance change elements constituting a memory element.
Next, a photoresist is deposited on the upper electrode 3, and this photoresist is exposed and developed, thereby forming a resist mask 11 corresponding to the pattern of the memory cell as shown in FIG. 1B.

  Next, the upper electrode 3 and the recording layer 2 are sequentially etched by the ion milling method or the RIE method using the resist mask 11. Thus, the upper electrode 3 and the recording layer 2 are patterned as shown in FIG. 1C.

  In FIG. 1C, the upper electrode 3 and the recording layer 2 are patterned. However, depending on the configuration of the memory element, part or all of the lower electrode 1 may be patterned or only the upper electrode 3 may be patterned. .

  Subsequently, as shown in FIG. 2D, the insulating layer 4 is deposited over the entire surface covering the resist mask 11.

Next, the resist mask 11 and the insulating layer 4 on the resist mask 11 are removed by a lift-off method.
At this time, a liquid that dissolves the resist mask 11 such as an organic solvent is used, and an ultrasonic cleaning machine, a jet cleaning machine that jets the solution at high pressure, or a cleaning method that combines an ultrasonic cleaning machine and a jet cleaning machine. Use.
As a result, as shown in FIG. 2E, the insulating layer 4 remains only outside the patterned recording layer 2 and upper electrode 3.

Subsequently, although not shown, after a wiring layer is formed so as to be connected to the upper electrode 3, the wiring layer is patterned to form a wiring connected to the upper electrode 3.
In this way, a memory element can be manufactured.

According to the manufacturing method of the present embodiment described above, after patterning the upper electrode 3 and the recording layer 2 using the resist mask 11, the insulating layer 4 is deposited so as to cover the resist mask 11, and then the resist is formed by a lift-off method. By dissolving the mask 11 and removing the insulating layer 4 on the resist mask 11, the insulating layer 4 remains only outside the patterned recording layer 2 and upper electrode 3, and the upper electrode 3 can be exposed.
As a result, it is possible to form a wiring layer in a portion where the upper electrode 3 is exposed and connect the wiring layer to the upper electrode 3 in a self-aligned manner.

Compared with the method of exposing the upper electrode 3 by opening the insulating layer 4 by the RIE method and the method of exposing the upper electrode 3 by polishing by the CMP method, conditions are set according to the material of the memory element. There is no need, and the upper electrode 3 can be easily exposed and connected to the wiring layer.
Since the upper electrode 3 and the wiring layer can be easily connected in this way, it is not necessary to form the upper electrode 3 thick, and the upper electrode 3 is formed thin to reduce variations in the pattern of the electrode bottom surface. Is possible. Even if the film thickness of the upper electrode 3 is reduced to, for example, 20 nm or less, the memory element can be manufactured without any problem.
Since variations in the pattern of the electrode bottom surface of the upper electrode 3 can be reduced, variations in the characteristics of the resistance change element in each memory cell can be reduced.

Therefore, even if a new material is used for the memory element, the memory element can be easily manufactured with a high yield. This makes it possible to configure the memory element using a specific material having good recording characteristics.
In addition, it is possible to easily and stably manufacture a memory element having high reliability and favorable characteristics such as electrical characteristics.

  Here, FIG. 4 shows a schematic configuration diagram (cross-sectional view) of an embodiment of a storage device (memory) including a storage element manufactured by the manufacturing method of the present invention.

This memory device (memory) has a configuration in which a memory cell is configured by a memory element using a resistance change element, and a large number of the memory cells are arranged.
As shown in FIG. 4, a variable resistance element including a lower electrode 1, a recording layer 2, and an upper electrode 3 is formed immediately above the contact layer 21 connected to the MOS transistor (not shown). A wiring layer 22 is connected on the upper electrode 3.

  In manufacturing a memory device (memory) having this configuration, each memory cell is applied by applying a photolithography technique and a lift-off method to the laminated film (lower electrode 1, recording layer 2, upper electrode 3) of the resistance change element. The variable resistance element is separated.

  The advantage of this structure is that the laminated film of the resistance change elements constituting the memory cell is arranged immediately above the contact layer 21, so that the area occupancy of each memory cell can be reduced, and many resistance change elements can be obtained. It is possible to mount it, and a large-capacity memory can be manufactured.

FIG. 5 shows a schematic configuration diagram (cross-sectional view) of another embodiment of a memory device (memory) including a memory element manufactured by the manufacturing method of the present invention.
As shown in FIG. 5, this memory device (memory) differs from the configuration shown in FIG. 4 in that the lower electrode 1 is routed from the contact layer 21 connected to the MOS transistor to another portion. Yes.
In manufacturing the memory device having this configuration, the photolithography technique and the lift-off method are applied to the recording layer 2 and the upper electrode 3 in the laminated film (lower electrode 1, recording layer 2, upper electrode 3) of the resistance change element. The resistance change element of each memory cell is isolated by application. The lower electrode 1 is patterned in advance from the recording layer 2 and the upper electrode 3 so as to extend from the contact layer 21 to the memory cell portion.

  The advantage of this structure is that the lower electrode 1 directly below the recording layer 2 is on a surface having good flatness that is out of the contact layer 21, so that the lower electrode 1 and the recording layer 2 are formed in a better state. Is what you can do.

By the way, as described above, the recording layer 2 is configured by laminating an ion source layer containing an element serving as an ion source and a high resistance layer having a high resistance value and a resistance value changing as ions move. In some cases, the high resistance layer does not conduct in the film surface direction.
From this, it is possible to form one or more layers including at least the high resistance layer among the laminated films of the resistance change elements in common with the resistance change elements of adjacent memory cells.
In this case, if at least one of the two electrodes 1 and 3 of the laminated film of the resistance change element is separated for each memory cell by the insulating layer, each memory cell can be operated independently.

A schematic configuration diagram (cross section) of another mode of a memory device (memory) having a configuration in which a high resistance layer or the like is commonly formed in adjacent memory cells and including a memory element manufactured by the manufacturing method of the present invention. Figure) is shown in FIG.
In this memory device (memory), as shown in FIG. 6, the lower electrode 1 and the recording layer 2 are formed in common in the memory cells of the entire portion shown in the drawing.
When manufacturing a memory device having this configuration, a photolithography technique and a lift-off method are applied only to the upper electrode 3 of the laminated film (lower electrode 1, recording layer 2, upper electrode 3) of the resistance change element. The resistance change element of each memory cell is separated.
In this case, since the lower electrode 1 and the recording layer 2 are formed in common, the layers 1 and 2 do not need to be finely patterned for each memory cell, and can be easily patterned with a large area. Therefore, the memory element can be easily manufactured with a high yield.
Therefore, even when the size of the memory cell is reduced, the memory element can be easily manufactured with a high yield, and the density of the memory cell can be increased. As a result, the storage capacity of the storage element can be increased and the memory can be downsized.

In the embodiment shown in FIGS. 1A to 2E, the insulating layer 4 is formed to be slightly thicker than the total thickness of the recording layer 2 and the upper electrode 3, but the insulating layer is formed to be thicker. The connection holes may remain after the selective removal by the lift-off method.
The case is shown below.

Another embodiment of the method for manufacturing a memory element of the present invention will be described.
First, in the same manner as shown in FIGS. 1A to 1C, the upper electrode 3 and the recording layer 2 are patterned using the resist mask 11.
Next, as shown in FIG. 7A, the insulating layer 4 is formed thicker than the step shown in FIG. 2D.
That is, the insulating layer 4 is formed sufficiently thicker than the total thickness of the recording layer 2 and the upper electrode 3 in the laminated film of the resistance change element.

Thereafter, the resist mask 11 and the insulating layer 4 on the resist mask 11 are removed by a lift-off method.
As a result, as shown in FIG. 7B, the insulating layer 4 remains only outside the patterned recording layer 2 and the upper electrode 3, and the insulating layer 4 has an opening on the upper electrode 3.
In the present embodiment, the opening of the insulating layer 4 is used as a connection hole between the upper electrode 3 and the wiring layer.

Next, a wiring layer is formed so as to fill the opening (connection hole) of the insulating layer 4 and connect to the upper electrode 3.
Thereafter, the wiring layer is patterned to form a wiring connected to the upper electrode 3.
In this way, a memory element can be manufactured.

According to the manufacturing method of the present embodiment described above, as in the manufacturing method of the previous embodiment, the wiring layer is formed in the portion where the upper electrode 3 is exposed, and the wiring layer is self-aligned with the upper electrode 3. Can be connected.
Compared with the method of exposing the upper electrode 3 by opening the insulating layer 4 by the RIE method and the method of exposing the upper electrode 3 by polishing by the CMP method, conditions are set according to the material of the memory element. There is no need, and the upper electrode 3 can be easily exposed and connected to the wiring layer.
Thereby, it is possible to reduce the variation in the pattern of the bottom surface of the electrode by forming the upper electrode 3 thin. Even if the film thickness of the upper electrode 3 is reduced to, for example, 20 nm or less, the memory element can be manufactured without any problem.
Since variations in the pattern of the electrode bottom surface of the upper electrode 3 can be reduced, variations in the characteristics of the resistance change element in each memory cell can be reduced.

Therefore, even if a new material is used for the memory element, the memory element can be easily manufactured with a high yield. This makes it possible to configure the memory element using a specific material having good recording characteristics.
In addition, it is possible to easily and stably manufacture a memory element having high reliability and favorable characteristics such as electrical characteristics.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

A to C are manufacturing process diagrams of an embodiment of a method for manufacturing a memory element of the present invention. D and E are manufacturing process diagrams of an embodiment of a method for manufacturing a memory element of the present invention. A and B are schematic cross-sectional views showing the form of a memory element to which the manufacturing method of the present invention is applied. It is a schematic block diagram (sectional drawing) of one form of the memory | storage device (memory) provided with the memory element manufactured by this invention manufacturing method. It is a schematic block diagram (sectional drawing) of the other form of the memory | storage device (memory) provided with the memory element manufactured by this invention manufacturing method. It is a schematic block diagram (sectional drawing) of further another form of the memory | storage device (memory) provided with the memory element manufactured by this invention manufacturing method. A and B are manufacturing process diagrams of another embodiment of the method for manufacturing a memory element of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Lower electrode, 2 Recording layer, 3 Upper electrode, 4 Insulating layer, 10 Resistance change element, 11 Resist mask, 21 Contact layer

Claims (6)

Each memory cell has a recording layer between two electrodes, and each of the memory cells has a resistance change element that reversibly changes the resistance value of the recording layer by applying potentials having different polarities to the two electrodes. When manufacturing a memory element configured with
Processing the variable resistance element using a soluble organic material as a mask;
Then, forming an insulating layer that covers the mask of the organic material and electrically isolates the memory cells;
And a step of selectively removing the insulating layer on the mask by dissolving the organic material of the mask.   After the step of selectively removing the insulating layer, a step of forming a wiring layer by connecting to the upper electrode on the recording layer of the two electrodes of the variable resistance element is performed. A method for manufacturing a memory element according to claim 1.   The recording layer of the variable resistance element has a laminated structure of an ion source layer containing one or more elements selected from Ag, Cu, and Zn and a high resistance layer made of an insulator or a semiconductor. The method for manufacturing a memory element according to claim 1.   3. The memory element according to claim 2, wherein the variable resistance element is configured such that the ion source layer includes CuTe and the high resistance layer includes an oxide film or a nitride film containing a rare earth element. Manufacturing method.   2. The method for manufacturing a memory element according to claim 1, wherein an oxide or nitride of Al or Ta is used as a material of the insulating layer.   By selecting the thickness of the insulating layer to be formed, the insulating layer remaining after selective removal is made higher than the laminated film of the variable resistance element so that the insulating layer on the variable resistance element The method for manufacturing a memory element according to claim 1, wherein a connection hole with the upper wiring is formed using the opening.

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