JP2006318303A - Memory controller, flash memory system, and control method for flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method for a flash memory for detecting data which is rewritten by an illegal means, and also to provide a memory controller, and a flash memory system equipped with the memory controller. <P>SOLUTION: The memory controller comprises a writing means of writing data to the flash memory in response to an instruction from a host system using the flash memory as a storage medium, a reading means of reading the data written to the flash memory by the writing means in response to an instruction from the host system, and a check sum calculating means of finding a check sum value by sectioning the data read by the reading means into specified numbers of bits and adding them one after another in response to an instruction from the host system. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory controller and a flash memory system including the memory controller.

  An apparatus having a CPU (Central Processing Unit) such as a personal computer stores data such as a program that defines its operation in a nonvolatile recording medium. When the apparatus is started, a predetermined operation is realized by reading and executing a program stored in the recording medium. Conventionally, ROM (Read Only Memory) and hard disks are often used as recording media for such applications.

  However, in recent years, the performance (storage capacity, reliability, operation speed, etc.) of flash memory has been improved, and it is being used for the purpose of storing programs and the like as a nonvolatile recording medium as described above.

  By the way, when a flash memory is used for the above-mentioned application, if a situation occurs in which data is not normally written due to a trouble such as a power cut during data rewriting, a device that operates according to the data cannot perform a desired operation. There is a fear.

To avoid such problems, after rewriting data, check whether the checksum matches the expected value, and if it does not match, perform a predetermined operation so that an unintended program is not executed. A method has been proposed (see, for example, Patent Document 1).
JP 2004-355064 A

  However, when the data stored in the flash memory is rewritten illegally, a device that operates according to the data may perform an unintended operation.

  The present invention has been made in view of the above circumstances, and provides a flash memory control method, a memory controller, and a flash memory system including the memory controller, which can detect that data has been rewritten by unauthorized means. Objective.

A memory controller according to a first aspect of the present invention writes data in a user area of the flash memory in response to an instruction from a host system that uses the flash memory as a storage medium, and stores the data in a redundant area of the flash memory. Write additional data used to manage the recorded data, writing means, and data recorded in the user area and the redundant area by the writing means in response to an instruction from the host system A read means for reading data, and in response to a command from the host system, the data recorded in the user area and the data recorded in the redundant area read by the read means in a predetermined bit Checksum calculation means that obtains a checksum value by dividing and adding each item sequentially Characterized constructed, that from.
In the present invention, the host system refers to a device that uses a flash memory as a recording medium.
In the present invention, the user area refers to an area where data used by the host system is recorded, and the redundant area refers to an area where additional information used for managing data recorded in the user area is recorded. Shall be pointed to.

  The memory controller further includes a checksum collating unit that collates a predetermined expected checksum value with a checksum value calculated by the checksum calculating unit and outputs collation result information to the host system. Good.

The memory controller stores a predetermined password, and further includes a password verification unit that determines whether or not the predetermined password matches the password supplied from the host system, and the checksum calculation unit includes: The checksum value may be calculated when the password verification unit determines that the predetermined password matches the password supplied from the host system.
This can prevent the checksum value from being obtained illegally.

  The checksum calculation means replaces the data written in a specific area of the data in the redundant area with a predetermined value, and sequentially adds the data after being divided into predetermined bits. A sum value may be calculated.

  The checksum calculation means may change a predetermined number of bits separating the data in accordance with an instruction from the host system.

  The writing means writes data with an error correction code added to a flash memory, the reading means corrects an error based on an error correction code added to the read data, and the checksum calculation means The checksum value may be calculated by dividing the corrected data into predetermined bits and sequentially adding the data.

  A flash memory system according to a second aspect of the present invention includes a memory controller having at least one of the above characteristics and a flash memory.

  A flash memory control method according to a third aspect of the present invention includes a read step for reading data from a flash memory, and a checksum value obtained by sequentially adding the data read in the read step in a predetermined bit interval And a determination step for determining whether or not the data has been rewritten based on the checksum value calculated in the checksum calculation step.

  According to the present invention, it is possible to detect that data has been rewritten by an illegal means by using a checksum value obtained by dividing and adding data read from the flash memory every predetermined bit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Description of flash memory system 1]
FIG. 1 is a block diagram schematically showing a flash memory system 1 according to the present invention. As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a controller 3 that controls the flash memory 2.

  The flash memory system 1 is connected to the host system 4 via the external bus 13. The host system 4 includes a CPU (Central Processing Unit) for controlling the entire operation of the host system 4, a companion chip for transferring information to and from the flash memory system 1, and the like. The host system 4 may be various information processing apparatuses such as a personal computer and a digital still camera that process various types of information such as characters, sounds, and image information.

  The controller 3 includes a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, an ECC (Error Collection Code) block 11, and a ROM (Read Only Memory) 12. And. The controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Each functional block will be described below.

  The microprocessor 6 controls the overall operation of the controller 3 according to the program recorded in the ROM 12. Specifically, the microprocessor 6 performs a write process for writing data to the flash memory 2, a read process for reading data, a checksum process for calculating a checksum value, creation of an address conversion table, and erased Each unit is controlled to execute processing such as creation of a block search table.

  The host interface block 7 exchanges data, address information, status information, external command information, and the like with the host system 4. That is, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. In such a state, the data supplied from the host system 4 to the flash memory system 1 is taken into the controller 3 through the host interface block 7 and the data supplied from the flash memory system 1 to the host system 4 is The host interface block 7 is supplied to the host system 4 as an exit.

  More specifically, the host interface block 7 includes a command register that temporarily stores an external command supplied from the host system 4, a sector number register that stores the size of data to be written or read, and data to be written or read. And an LBA (Logical Block Addressing) register for storing the logical block address. Information is exchanged with the host system 4 via these registers.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2.

  The flash memory interface block 10 exchanges data, address information, status information, internal command information, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code added to data to be written to the flash memory 2 and detects and corrects an error included in the read data based on the error correction code added to the read data.

  The ROM 12 is a non-volatile storage element that stores a program that defines a processing procedure performed by the microprocessor 6. In addition to the above program, the ROM 12 stores a password used in the checksum process.

[Description of flash memory]
Next, the flash memory 2 will be described. FIG. 2 is a diagram schematically showing a memory structure of the flash memory 2. As shown in FIG. 2, the flash memory 2 includes a page that is a processing unit for reading and writing data and a block that is a data erasing unit.

  The page is composed of a 512-byte user area 25 and a 16-byte redundant area 26, for example. The user area 25 is an area mainly storing data supplied from the host system 4, and the redundant area 26 stores additional information such as an error collection code, a block status, a corresponding logical block address, and old and new identification information. It is an area to be done.

  The error collection code is additional information for correcting an error included in the data stored in the user area 25 and the redundant area 26 and is generated by the ECC block 11. Based on the error collection code, if the number of errors included in the data stored in the user area 25 and the redundant area 26 is equal to or less than a predetermined number, the error is corrected.

  The block status is a flag indicating whether or not the block is a bad block (a block in which data cannot be normally written). If it is determined that the block is a bad block, the block status is bad. A flag indicating a block is set.

  The corresponding logical block address indicates to which logical block address the block corresponds when data is stored in the block. If no data is stored in the block, the corresponding logical block address is not stored, so whether the corresponding logical block address is stored or not is determined whether the block is an erased block. Judgment can be made. That is, when the corresponding logical block address is not stored, it can be determined that the block is an erased block.

  The old and new identification information is information for identifying the update order of data written to the corresponding logical block address of the block. For example, the new / old identification information is incremented by one each time the data of the block corresponding to the same logical block address is updated. Then, when blocks having the same corresponding logical block address coexist due to the power being cut off during the data update, the data of the block having a large new / old identification information value is identified as the latest data.

  In the flash memory 2 of the present embodiment, each information is assigned as shown in FIG. That is, the most significant 1 byte is assigned to the new and old identification information. Further, the next 2 bytes are assigned to the corresponding logical block address. The next 1 byte is assigned to the block status. Further, the next 10 bytes are assigned to an error collection code for correcting an error included in the data written in the user area 25. Further, the next two bytes are assigned to the error correction code for detecting and correcting the error included in the corresponding logical block address written in the redundant area 26.

[Description of logical block address and physical block address]
Since the flash memory 2 cannot overwrite data, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data (data before rewriting) is written. A two-stage process of erasing the written block must be performed. At this time, since erasure is processed in units of blocks, data of all pages in a block including a page in which old data (data before rewriting) is written is erased. Therefore, when data is rewritten, it is necessary to perform processing for moving the data of other pages of the block including the page to be rewritten to the erased block.

  When data is rewritten as described above, since the data after rewriting is written in a different block from that before rewriting, a logical block address given from the host system 4 side and a physical block address which is a block address in the flash memory 2 The correspondence relationship changes dynamically every time data is rewritten. For this reason, an address conversion table showing the correspondence between logical block addresses and physical block addresses is required. This address conversion table is created based on the corresponding logical block address written in the redundant area 26 of the flash memory 2, and each time data is rewritten, the correspondence relationship of the part involved in the rewriting is updated. .

[Description of zone configuration]
Next, zone management for assigning a zone composed of a plurality of blocks in the flash memory 2 to a logical block address space will be described with reference to the drawings. FIG. 4 shows an example in which a zone is configured by 512 blocks. In the example shown in FIG. 4, the zone is composed of 512 blocks B0000 to B0511 (physical block addresses 0000 to 0511), and each block is composed of 32 pages P00 to P31 which are units of read and write processing. Has been. Here, the block is a unit of erasing processing, and the page is a unit of reading and writing processing.

In addition, when this zone is allocated to a logical block address space, it is allocated to a logical block address space having a smaller number of blocks than the number of blocks constituting the zone in consideration of the occurrence of defective blocks. This allocation is normally performed according to the specifications of the flash memory 2. For example, a zone composed of 512 blocks is allocated to a logical block address space of 500 blocks, or a logical block address of 490 blocks. Can be assigned to the space. At this time, if the number of blocks allocated to the space of the logical block address is increased, the use efficiency of the flash memory is improved, but the allowable amount for the generation of defective blocks (the allowable number of defective blocks generated) is reduced.
In the flash memory system 1 according to the present embodiment, as shown in FIG. 5, a zone composed of 512 blocks is assigned to a space of logical block addresses for 496 blocks.

[Description of address translation table]
Next, the address conversion table will be described. The address conversion table collectively manages the correspondence between logical block addresses and physical block addresses and the correspondence between logical block addresses and old / new identification information.
FIG. 6 shows an example of an address conversion table for the zone 0 shown in FIG. 5, and the physical block address in the flash memory 2 in which data corresponding to each logical block address is stored, and the physical The old and new identification information of the data stored in the block address is described in the order of the logical block address. For a logical block address in which no data is stored in the flash memory 2, a flag indicating that no data is stored in the portion corresponding to the logical block address in the address translation table (not a physical block address) , A flag indicating that the corresponding data is not stored is referred to as an unstored flag).

  For example, when the address conversion table for zone 0 shown in FIG. 5 is created, the microprocessor 6 secures an area where the physical block addresses for 496 blocks can be described on the SRAM, and the area where the physical block addresses are described. The unstored flag is set as an initial setting. Thereafter, the microprocessor 6 controls the flash memory interface block 10 to sequentially read the redundant areas 26 of the blocks constituting the zone 0 of the flash memory 2, and writes the logical block addresses (corresponding to the corresponding logical block addresses) in the redundant areas 26. In the address conversion table, the physical block address of the block in which the logical block address is described is described in the portion corresponding to the logical block address. Also, the old and new identification information described together with the logical block address is described in the part corresponding to the logical block address of the table.

  It should be noted that the unstored flag described in the initial setting remains as it is for the part where the physical block address is not described in the address conversion table creation process.

[Identification by old and new identification information]
When a situation occurs in which blocks with the same corresponding logical block address coexist due to the power being cut off during the data update, when creating the address conversion table, the physical block address is assigned to one logical block address. Two will coexist.
At this time, the microprocessor 6 compares the new and old identification information written in the redundant areas 26 of the two coexisting physical block addresses, and writes the new data (true data) with the larger value of the old and new identification information. It is determined that the block is a block, and an address conversion table is created.

[Description of erased block search table]
Next, the erased block search table will be described with reference to the drawings. The erased block search table is a table for searching for erased blocks that can be data write destinations.

  First, a method for searching for an erased block using the erased block search table will be described. For example, when searching for erased blocks in the zone shown in FIG. 5, the microprocessor 6 secures a 512-bit area on the SRAM, and erased blocks in which each block constituting the zone is assigned to each bit in the area. Create a block search table.

  FIG. 7 is a conceptual diagram conceptually showing the erased block search table for zone 0 and zone 1 shown in FIG. Here, bits on the erased block search table for zone 0 correspond to blocks B0000 to B0511 (physical block addresses 0000 to 0511), and bits on the erased block search table for zone 1 correspond to block B0512. To B1023 (physical block addresses 0512 to 1023).

  For the correspondence between the bits on the erased block search table and the blocks constituting the zone, the bits on the erased block search table shown in FIG. 7 are changed from the upper row to the lower row. Each row is associated from left to right in the order of physical block addresses. Therefore, in the erased block search table for zone 0, the upper left bit corresponds to the block B0000 (physical block address 0000) and the lower right bit corresponds to the block B0511 (physical block address 0511). To do.

  The bit on the erased block search table indicates whether the block is an erased block by “0” and “1”. For example, when data is written (or it is a defective block) Is set to “0” in the bit, and “1” is set in the bit when data is not written (in the case of an erased block).

  The erased block search table can be created together when creating the address conversion table. For example, the microprocessor 6 sets “0” in the area on the SRAM for creating the erased block search table, and indicates that the corresponding logical block address in the redundant area 26 of each block is also a bad block. When the status is not described, if the bit corresponding to the block is set to “1”, the address conversion table can be created together. In other words, if this process is performed when data described in the redundant area 26 of the block constituting the zone is read, only “1” is set to the bit corresponding to the erased block, and the block is not an erased block. The corresponding bit remains “0” set in advance.

  Further, when data is written in the erased block, the microprocessor 6 changes the bit corresponding to the block from “1” to “0”, and the block in which the data is written is erased. In addition, the erased block search table is updated as needed by changing the bit corresponding to the block from “0” to “1”.

  Next, a case where an erased block is searched using this erased block search table will be described with reference to FIG. FIG. 8 shows an erased block search table for zone 0. For example, each bit in the top row corresponds to blocks B0000 to B0007 (physical block addresses 0000 to 0007), and the bottom row corresponds to blocks B0504 to B0511 (physical block addresses 0504 to 0511). To do.

  The microprocessor 6 scans the erased block search table from the upper row to the lower row. The microprocessor 6 scans each row in the erased block search table from left to right. That is, the microprocessor 6 starts from the bit corresponding to the block B0000 (physical block address 0000) (the leftmost bit in the top row) to the bit corresponding to the block B0511 (physical block address 0511) ( The rightmost bit in the bottom row is scanned, and the bit “1” corresponding to the erased block is searched.

  When searching the erased block search table shown in FIG. 8, since the third bit from the left in the second row from the top is “1”, the microprocessor 6 ends the search here, and this bit The block B0010 (physical block address 0010) corresponding to is specified as the data write destination block.

  The next search starts scanning from the fourth bit from the left in the second row from the top. Since the fifth bit from the left in the fourth row from the top is “1”, the microprocessor 6 The search ends here, and the block B0028 (physical block address 0028) corresponding to this bit is specified as the data write destination block. Thereafter, such a search is continued, and when the scanning proceeds to the rightmost bit in the bottom row, the processing returns to the leftmost bit in the top row.

[Description of writing process]
The writing process is executed in response to a command from the host system 4.
A command requesting execution of write processing from the host system 4 is written to the command register of the host interface block 7. The logical block address to which data is written and the size of the data to be written are written to the LBA register and the sector number register of the host interface block 7, respectively.

  In response to the instruction written in the command register, the microprocessor 6 writes data to the block specified by searching the erased block search table. In this writing process, the microprocessor 6 controls the flash memory interface block 10 to write data to a page in the write destination block via the internal bus 14. The microprocessor 6 writes an error correction code, a logical block address, new / old identification information, and the like in the redundant area 26 of the block in which data is written.

  Further, in the above write processing, when old data corresponding to the logical block address supplied from the host system 4 side exists (when overwriting), the old data is erased after the new data write processing. It is. The physical block address of the block in which the old data to be erased is stored can be obtained based on the address conversion table shown in FIG. In this erasing process, the microprocessor 6 controls the flash memory interface block 10 to erase the data in the block in which the old data of the flash memory 2 is stored.

[Description of read processing]
The read process is executed in response to a command from the host system 4.
A command requesting execution of read processing from the host system 4 is written in the command register of the host interface block 7. Further, the logical block address of the data to be read is written in the LBA register of the host interface block 7.

  In response to the instruction written in the command register, the microprocessor 6 converts the logical block address written in the LBA register into a physical block address (data corresponding to the logical block address is based on the address conversion table shown in FIG. 6). Converted to the physical block address of the stored block).

  Subsequently, the microprocessor 6 controls the flash memory interface block 10 and stores it in the page in the block in which data corresponding to the logical block address given from the host system 4 side is stored via the internal bus 14. The read data is read out to the buffer 9.

  The ECC block 11 corrects an error in the data read out to the buffer 9 based on an error correction code added to the data. Then, the microprocessor 6 controls the host interface block 7 to supply the corrected data to the host system 4 via the external bus 13.

[Explanation of checksum processing]
The checksum process is a process for confirming whether or not the data written in the flash memory 2 has been rewritten, and is executed in response to a command from the host system 4.
For example, the host system 4 sends a command requesting execution of the checksum process to the flash memory system 1 when the power is turned on or when a user performs a predetermined operation. A command requesting execution of checksum processing from the host system 4 is written in the command register of the host interface block 7. Also, the number of bits used as a delimiter when calculating the checksum (hereinafter referred to as delimiter bit number) is written in the sector number register. The microprocessor 6 receives the logical block address and the number of delimiter bits together with the command requesting execution of the checksum process, and executes the checksum process based on these.
Hereinafter, the procedure of the checksum process will be described with reference to the flowchart shown in FIG.

When receiving a command requesting execution of the checksum process, the microprocessor 6 requests a password from the host system 4 (step S100). In response to this, the host system 4 transmits a predetermined password to the flash memory system 1, and the microprocessor 6 receives the password via the host interface block 7 (step S110). The password may be written in the LBA register.
The microprocessor 6 collates the received password with the password stored in the ROM 12 and determines whether or not they match (step S120).
If the passwords do not match (step S120; No), the checksum process ends.

  On the other hand, if the passwords match (step S120; Yes), the microprocessor 6 calculates the checksum values of all the blocks in which the corresponding logical block addresses are written in the redundant area 26, so that the microprocessor 6 performs the process in step S140. Proceed to It should be noted that a range of logical blocks for which a checksum value is to be calculated may be specified from the host system 4 side.

  When calculation of the checksum value is started, the microprocessor 6 controls the flash memory interface block 10 and stores it in the page in the block in which the corresponding logical block address is written via the internal bus 14. The read data is read out to the buffer 9 (step S140).

  The microprocessor 6 corrects the error included in the data read out to the buffer 9 based on the error collection code added to the data (step S150).

Next, the microprocessor 6 executes a calculation process for calculating a checksum value from the data whose error has been corrected (step S160).
In the calculation process, the checksum value is calculated by dividing the error-corrected data for each delimiter bit number and sequentially adding the data. For example, when the number of delimiter bits is 8 bits, as shown in FIG. 10, the data for one page is divided every 8 bits and added sequentially.

  Next, the microprocessor 6 determines whether or not the page on which the calculation process has been performed is the last page of the last block (step S161). If it is determined that the page is not the last page of the last block (step S161; No), data reading (step S140), error correction (step S150), and calculation process (step S160) are repeated for the subsequent pages (step S160). S161). When the calculation process of the final page of the final block is completed (step S161; Yes), the addition result is supplied to the host system 4 as a checksum value (step S170).

Note that the microprocessor 6 also adds data written in the redundant area 26 in the calculation process. At this time, addition is performed after error correction and data replacement processing.
In this data replacement process, values are not replaced for data written in the redundant area 26, such as the corresponding logical block address, with no individual difference. On the other hand, for data in which individual differences occur due to data rewrite history (hereinafter referred to as replacement target data), such as new and old identification information, the data is replaced with a predetermined value (for example, all bits are 0). Further, data that is not subjected to error correction is also replaced with predetermined data (data that is not subjected to error correction is also included in the replacement target data). Then, the data after such processing is divided for each number of delimiter bits and sequentially added.

  FIG. 11 is a flowchart specifically illustrating the procedure of the calculation process. When the calculation process is started, the microprocessor 6 resets the count value for dividing the target data (data read into the buffer 9) of the checksum process to 0 (step S200).

  Next, the microprocessor 6 delimits and cuts out the data to be added based on the count value and the number of delimiter bits (step S210). For example, the microprocessor 6 specifies the first bit of data to be added from the product of the number of delimiter bits and the count value, and adds data corresponding to the number of delimiter bits from the first bit (hereinafter referred to as addition data). Extract as

  Next, the microprocessor 6 determines whether or not the extracted addition data includes replacement target data (step S220). If it is determined that the data to be replaced is not included (step S220; No), the process proceeds to step S240.

  On the other hand, when it is determined that the replacement target data is included (step S220; Yes), the replacement target data included in the addition data is replaced with 0 (step S230), and the process proceeds to step S240.

  In step S240, the microprocessor 6 adds the addition data to the checksum value (step S240). Then, the microprocessor 6 determines whether or not the end of the checksum processing target data has been reached (step S250).

If it is determined that the end of the target data for the checksum process has been reached (step S250; Yes), the microprocessor 6 ends the calculation process.
On the other hand, when it is determined that the end of the target data for the checksum processing has not yet been reached (step S250; No), the microprocessor 6 increments the count value by 1 (step S260) and returns the processing to step S210.

  When the microprocessor 6 adds up to the end of the target data, it ends the calculation process. After that, when the target data for the checksum process is newly read out to the buffer 9, the added data is added to the checksum value at the end of the previous calculation process. In the checksum process, only a predetermined number of bits are treated as valid data (checksum value), and the data of higher bits overflowing is ignored.

When the host system 4 receives the checksum value, it compares the checksum value with the expected checksum value acquired in advance, and if the two match, it can be determined that unauthorized rewriting has not been performed.
For example, the host system 4 may be given a predetermined expected checksum value when rewriting data. Further, after the data writing is completed, a checksum process may be executed to obtain a checksum value, and the checksum value obtained at that time may be used as the expected checksum value.

  As described above, the flash memory system 1 of the present embodiment can detect fraudulent rewriting by performing checksum processing.

  Further, the flash memory system 1 according to the present embodiment collates the password when executing the checksum process. If the passwords do not match, the process ends without outputting the checksum value. For this reason, it is difficult to obtain a checksum value illegally.

  Further, the flash memory system 1 of the present embodiment uses the data written in the redundant area 26 to which the user cannot freely write data for calculating the checksum value, so that the checksums are matched. Unauthorized writing is even more difficult.

  Further, the flash memory system 1 according to the present embodiment calculates a checksum after replacing the data written in the redundant area 26 with the predetermined value for the data depending on the individual difference of the flash memory 2. To do. As a result, when the same data is written in a plurality of flash memory systems 1, the same checksum value can be obtained regardless of the data rewriting history, so that the management of the flash memory system 1 is facilitated.

  In addition, since the flash memory system according to the present embodiment can specify the number of delimiter bits, the degree of difficulty for performing illegal writing that matches the checksums increases, and illegal writing can be suppressed.

  In the above embodiment, the case where the flash memory system supplies the calculated checksum value to the host system has been described as an example. However, the flash memory system holds the expected checksum value itself (for example, ROM) and calculates it. It may be determined whether or not the checksum value matches the expected checksum value, and the determination result may be supplied to the host system.

1 is a block diagram schematically showing a flash memory system according to the present invention. It is a figure which shows roughly the structure of the address space of flash memory. It is a figure shown about allocation of the data with respect to a redundant area. It is a figure which shows the example which comprised the zone by the block of 512. FIG. It is a figure which shows the structural example of a zone. It is the figure which showed the example of the address conversion table. It is a conceptual diagram which shows the example of the erased block search table. It is a figure for demonstrating the search method of the erased block using the erased block search table. It is a flowchart which shows the procedure of a checksum process. It is a figure which shows the calculation method of a checksum value. It is a flowchart which shows the procedure of the calculation process for calculating a checksum value.

Explanation of symbols

1 Flash memory system 2 Flash memory 3 Controller 4 Host system 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 ROM
13 External bus 14 Internal bus 25 User area 26 Redundant area

Claims (8)

In response to an instruction from the host system that uses the flash memory as a storage medium, the data is written to the user area of the flash memory and additional data used for managing the data recorded in the redundant area of the flash memory. Writing, writing means,
In response to a command from the host system, reading means for reading the data recorded in the user area and the data recorded in the redundant area by the writing means;
In response to a command from the host system, the data recorded in the user area read by the reading unit and the data recorded in the redundant area are sequentially added by being divided into predetermined bits and checked. Checksum calculation means for obtaining a sum value,
A memory controller characterized by that. A checksum verification unit that collates a predetermined expected checksum value with a checksum value calculated by the checksum calculation unit and outputs verification result information to the host system;
The memory controller according to claim 1. A password verification unit that stores a predetermined password and determines whether or not the predetermined password matches the password supplied from the host system;
The checksum calculation unit calculates a checksum value when the password verification unit determines that the predetermined password matches the password supplied from the host system.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The checksum calculation means replaces data written in a specific area of the data in the redundant area with a predetermined value, and sequentially adds the data after the replacement after dividing the data into a predetermined number of bits. Calculate the sum value,
The memory controller according to claim 1, wherein the memory controller is a memory controller. The checksum calculation means changes a predetermined number of bits delimiting data in accordance with an instruction from the host system.
The memory controller according to claim 1, wherein the memory controller is a memory controller. The writing means writes data with an error correction code added to the flash memory,
The reading means corrects an error based on an error correction code added to the read data,
The checksum calculation means calculates the checksum value by sequentially adding the data in which the error has been corrected, divided into predetermined bits.
The memory controller according to any one of claims 1 to 5, wherein:   A flash memory system comprising: the memory controller according to claim 1; and a flash memory. A read step for reading data from the flash memory; and
A checksum calculation step for obtaining a checksum value by dividing the data read in the reading step into predetermined bits and sequentially adding the data;
A determination step of determining whether data has been rewritten based on the checksum value calculated in the checksum calculation step;
Composed of,
A method for controlling a flash memory.

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