JP2006318115A - Semiconductor storage device, semiconductor storage device functional test method, and electronic device comprising semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately detect crosstalk and garbled data under the influence of noise by using an address and data created by random numbers in verification of address, data bus and system bus in a semiconductor storage device and an electronic device comprising the semiconductor storage device. <P>SOLUTION: The semiconductor storage device which detects a functional disorder produced in specific bit array by writing data of random number address written by pseudo-random number generator 2 in a semiconductor storage devices A-1, A-2, A-XXX, B-1, B-2, B-XXX, X-1, X-2, X-XXX, reading data of random number address written in the semiconductor storage devices A-1, A-2, A-XXX, B-1, B-2, B-XXX, X-1, X-2, X-XXX, and comparing read data and written data through compare means, the semiconductor storage device functional test method therefor, and an electronic device having the semiconductor storage device are provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to address randomization, and in particular, addresses and data are randomly specified using a random number from a pseudo-random number generation means to detect functional failures such as defects and data corruption that occur in a specific bit array. The present invention relates to a semiconductor memory device, a semiconductor memory device function inspection method, and an electronic apparatus having the semiconductor memory device.

  Conventionally, in the normal operation mode, the address of the execution microinstruction (execution instruction address) generated according to the microprogram by the microsequencer is input to the program counter. In the test mode, the program counter uses the random number generated by the pseudo random number generator as the address. In the test mode, instructions from the micro-sequence are randomly read out, allowing transitions between all instructions during the acceleration test, enabling detection of failure modes in these transitions, and increasing the failure detection rate. An integrated circuit that can be improved is disclosed in Patent Document 1.

  FIG. 4 shows an integrated circuit (LSI) disclosed in Patent Document 1. In FIG. FIG. 4 is a functional system diagram of an LSI instruction control unit that functions in accordance with a microprogram. In the circuit of FIG. 4, the microinstruction is composed of 16 bits, and is read from the instruction ROM 12 by designating an 8-bit address.

  In normal operation, the microsequencer 14 gives the address of the next execution instruction to the program counter 13 according to the program as shown by the broken line, and the next execution instruction is read from the address area of the instruction ROM 12 indicated by the value of the program counter 13. After being written to the instruction register 11, the instruction is actually executed. During the test, by inputting a control signal from the control signal input line 21, the microsequencer 14 operates as an incrementer that simply counts outputs one by one regardless of the microprogram. Therefore, since consecutive addresses are given to the instruction ROM 12, instructions are executed according to the order of the addresses. A dynamic acceleration test is performed by operating the circuit in such an execution mode.

  In this way, the microsequencer instructions are executed in the order of the addresses in the instruction ROM 12. However, when the LSI is operated by the microprogram during the actual normal operation, the instructions are not executed in the order of addresses, but jump instructions. In the case of an instruction such as a subroutine call, an instruction at a discontinuous address is executed. As described above, there is a problem that the above-described conventional circuit cannot sufficiently detect the failure mode that occurs at the time of the instruction transition in which the address changes discontinuously in the acceleration test.

  Therefore, by causing the LSI to perform dynamic operations such that instructions with discontinuous addresses are continuously executed during accelerated tests, it is easy to detect failure modes specific to transitions between instructions and improve failure detection rates. For this purpose, in FIG. 4, the address selection selector 15 is connected to the operation mode control signal input terminal 22, and the address output of the microsequencer 14 and the random number output of the pseudo random number generator 16 are supplied to the input of the address selection selector 15, The output of the selection selector 15 is supplied to the input of the program counter 13.

  In the functional system diagram of FIG. 4, when performing a normal operation, a control signal corresponding to the normal operation mode is input to the operation mode control signal input terminal 22, and the address selection selector 15 is used as a data input to the program counter 13. The address output of the microsequencer 14 generated according to a microprogram (not shown) is selected. On the other hand, during the test, a control signal corresponding to the test mode is input to the operation mode control signal input terminal 22, and the address selection selector 15 selects the output of the pseudo random number generator 16 as the input of the program counter 13. As a result, the random number generated by the pseudo-random number generation circuit 16 is read into the program counter 13, and a microinstruction having the random value as an address is read from the instruction ROM 12 and executed.

  Accordingly, the next instruction to be read out is completely random by the pseudo random number generator 16, and the instruction is executed randomly regardless of the address value (address order). By operating in this test mode, the internal state of the LSI can be dynamically changed regardless of the order of the address of the instruction, and between the instructions that could not be in the conventional test mode where the address is simply incremented Transitions can also be made. A technology that enables a specific failure mode for an LSI internal state transition that cannot be detected by a conventional test method to be detected by operating a circuit in such a test mode during an LSI accelerated test. Is disclosed.

  The technique disclosed in Patent Document 1 described above has a selector 15 that selects an input to the program counter 13 in order to improve a failure detection rate in an LSI acceleration test, and a pseudo-random number generation circuit 16 connected to the selector 15. When the random number generated by the pseudo random number generator 16 is input to the program counter 13 during the acceleration test of the LSI, the microprogram is executed randomly regardless of the order of the addresses. The present invention relates to an LSI in which a failure mode is detected.

  In addition, by selecting the output of the pseudo random number generator as random data or the opposite data as the data to be written to the semiconductor memory device, rewriting from 0 to 1, 1 to 0, reading is facilitated, and the number of test patterns is reduced. A semiconductor integrated circuit with a test function configured as described above is disclosed in Patent Document 2.

  The configuration of Patent Document 2 is shown in FIG. In FIG. 5, 23 is a memory, 24 is a write or read address for the memory 23, 25 is a pseudo random number generator for generating a random number signal to be the write or read address 24, 26 is a random number signal, and 27 is a random number signal 26. A pseudo random number generator, 28 is an inverted signal of the random number signal 26, 29 is an inverting circuit that inputs the random number signal 26 and outputs an inverted signal 28 of the random number signal, 30 is write data to be written in the memory 23, and 31 is the random number signal 26. And a selection circuit for selecting one of the inverted signal 28 of the random number signal as the write data 30, 32 a read data from the memory 23, 33 a data compressor for sequentially compressing the read data 32 read from the memory 26 , 34 is a compression result output from the data compressor 33, 35 is a control signal for controlling each circuit operation, and 36 is a control signal. A control circuit for outputting issue 35.

  In the operation of the above-described semiconductor integrated circuit with a test function, first, a test mode is set to select the output signal 26 of the pseudo random number generator 27 or the inverted signal 28 as the write data 30 to the memory 23. In the first procedure, the test mode 1 is selected when the output signal 26 of the pseudo random number generator 27 is selected as the write data 30 to the memory 23, and the test mode 2 is selected when the inverted signal 28 is selected. In the next second procedure, when the self-test operation of the memory 23 is started, the contents of the pseudo random number generators 25 and 27 and the data compressor 33 are initialized. Thereafter, the data in the area of the memory 23 indicated by the address 24 is read, the read data 32 is compressed by the data compressor 33, the write signal 30 according to the test mode setting is written in the area of the memory 23 indicated by the address 24, The contents of the random number generators 25 and 27 are updated. In the third procedure, the read, data compression, write, and update operations are repeated to write to all memory cells. Thereafter, as a fourth procedure, failure diagnosis is performed based on the contents of the data compressor 33. By performing the above steps 1 to 4 four times in the test mode, the rewriting operation from 1 to 0, the rewriting operation from 0 to 1, and the reading operation of 0 and 1 can be confirmed for all the memory cells. There is a disclosure that the number of required test patterns at this time (the sum of the number of all write data and the number of all read data) is about 5 to 8 times the number of words in the memory 23.

The self-test circuit of the memory 23 disclosed in Patent Document 2 described above is configured to be able to select either random number data 26 that is an output of the pseudo random number generator 27 or inverted data 28 of the random number data as write data A case where random number data 26 is selected as write data to the memory 23 and a case where reverse data 28 of random number data is selected, a test when writing as the write data 26 of pseudo random number data, and inversion of random data A test is performed when a signal is written as write data 28, and all memory cells are easily rewritten from 1 to 0, rewritten from 0 to 1, and read operation of 0 and 1 can be easily confirmed. A few self-test circuits are to be realized. Conventional system bus (address, data), semiconductor memory address, detection of functional issues (defects, garbled data) due to crosstalk generated in the data bus are difficult to detect even in continuous long-term operation inspection, and the state is over time With regard to changing reliability, it is often impossible to detect at present.
JP-A-6-194422 JP-A-5-250900

  The present invention has been made to solve the above-described problems. The present invention is a semiconductor memory device, a semiconductor memory device function inspection method, and a semiconductor memory capable of easily detecting a function problem occurring in these system buses and memory buses. The purpose is to propose an electronic device having a device

  According to a first aspect of the present invention, there is provided a semiconductor memory device in which an address or data from a processor is randomly written to or read from a semiconductor memory device via a system bus or a memory bus through random number generation means. An address or data generated by crosstalk or the like generated on the bus is detected.

  According to a second aspect of the present invention, there is provided a semiconductor memory device in which an address or data from a processor is randomly written to or read from a semiconductor memory device via a system bus or a memory bus through random number generation means. The random number address data written by the random number generator is written and the random address data written to the semiconductor memory device is read, and the write data and the read data are compared via a comparing means to thereby generate a specific bit arrangement. This is intended to detect functional failures that occur in

  The semiconductor memory device function testing method of the third aspect of the present invention is a semiconductor memory device function testing method in which an address or data from a processor is randomly written to or read from a semiconductor memory device via a system bus or a memory bus through random number generation means. The random number address data written by the random number generator is written to the semiconductor memory device, and the random address data written to the semiconductor memory device is read, and the write data and read data are compared via the comparison means. In this case, a malfunction occurring in a specific bit arrangement is detected.

  According to a fourth aspect of the present invention, there is provided an electronic device having a semiconductor memory device having a conductor memory device in which an address or data from a processor is randomly written to or read from the semiconductor memory device via a system bus or a memory bus through random number generation means. In an electronic device, the random address data written by the random number generator is written to the semiconductor memory device, and the random address data written to the semiconductor memory device is read. The write data and the read data are compared via the comparison means. By doing so, it is possible to detect a malfunction occurring in a specific bit arrangement.

  According to the semiconductor memory device, the semiconductor memory device function detecting method, and the electronic device having the semiconductor memory device of the present invention, a system that occurs in a specific bit arrangement during the manufacturing process or design verification of the semiconductor memory device or the electronic device equipped with the semiconductor memory device Functional issues such as noise and garbled data such as crosstalk on printed wiring boards and devices (CPU, memory controller, memory) or electronic devices generated on buses (addresses, data) and memory buses (addresses, data) in a short time This produces an effect that can be detected.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a system diagram showing one embodiment of the semiconductor memory device of the present invention, FIG. 2 is a flowchart of one embodiment of the semiconductor memory device of the present invention, and FIG. 3 is one embodiment of electronic equipment having the semiconductor memory device of the present invention. It is a systematic diagram which shows an example.

  The present invention will be described below with reference to FIG. FIG. 1 is applied to a semiconductor memory device. In FIG. 1, reference numeral 1 denotes a processor of a computer. Input data and control data are given to the processor 1 from an operation unit 4. The processor 1 reads a predetermined random number address and / or predetermined random number data from the pseudo random number generator 2 by the operation of the operation unit 4, and this pseudo random number generator 2 has a hardware configuration as shown in FIG. It may be constituted by software stored in a ROM or the like in the processor 1 constituting the above.

  The random number address and / or random number data output from the processor 1 is supplied to the semiconductor memory device control means (hereinafter referred to as a memory controller) 3 via the system bus SB. Random number addresses and / or random number data from the memory controller 3 are sent via a memory bus MB to semiconductor storage devices (hereinafter referred to as memories) A-1, A-2, A-XXX, B-1, B-2, B -It is supplied to XXX, X-1, X-2, X-XXX.

  Also, the memories A-1, A-2, A-XXX, B-1, B-2, B-XXX, X-1, X-2, X-XXX and the system bus SB do not pass through the memory controller 3. Alternatively, it may be directly connected to the processor 1. Several different operating systems run on such memory 1, A-2, A-XXX, B-1, B-2, B-XXX, X-1, X-2, X-XXX. ing.

  An executable program is created based on the algorithm shown in FIG. 2 from the predetermined operating system having the above-described configuration. The operation of this program will be described with reference to the flowchart of FIG. In the first step S1, the processor 1 is provided with memories A-1, A-2, A-XXX, B-1, B-2, B-XXX, X-1, X-2, X-XXX. An address and bus width data of an arbitrary bus width in the address space (YYYYYYYYh to XXXXXXXXXh, where h is a hexadecimal notation) are generated using random numbers from the pseudo random number generator 2.

  Next, in the second step S2, arbitrary data created by using random numbers at arbitrary addresses generated is written to the memory A-1, for example, via the memory controller 3. In the third step S3, the data written in the memory is read.

  In the fourth step S4, a comparison is made as to whether the write data and the read data are equal to each other. If they are not equal, the process proceeds to a fifth step S5 to enter error processing. If the fourth step S4 is equal, a loop that returns to the first step S1 through the sixth step S6 causes a necessary number of times and a time loop to distort the data due to the influence of crosstalk or noise generated in a specific bit arrangement, etc. Detect functional issues instantly with high accuracy.

  If necessary, the memories A-1, A-2, A-XXX, B-1, B-2, B-XXX, C-1, C-2, C-XXX, X-1, X- 2, X-XXX can be replaced. Furthermore, random numbers can be used for either address or data.

  FIG. 3 is a functional system diagram of one embodiment of an electronic apparatus having the semiconductor memory device of the present invention. In FIG. 3, an electronic device 10 has basic blocks such as a processor 1, a memory controller 3, semiconductor memories A and B, and a pseudo random number generator 2 stored in the memory of the processor 1, as in FIG. Mobile phone 10A, PAD 10B, disc recording / reproducing apparatus 10C, digital camera, handy cam, or the like.

  The memories A and B are connected to the memory controller 3 via an address and data memory bus MB, and are connected to the processor 1 via an address and data system bus SB. Electronic devices (10A, 10B, 10C... 10N) are connected to the system bus SB. In some cases, the memories A and B are directly connected to the address and the data system bus SB. Several different operating systems are running on these electronic devices.

  The operating system described with reference to FIG. 3 is implemented as an executable program created based on the algorithm of FIG. On the processor 1, an arbitrary address in the address space (YYYYYYYYh to XXXXXXXXXh) in which electronic devices (10A, 10B, 10C... 10N) connected to the memories A and B and the system bus SB are arranged is Created using random numbers, write arbitrary data created using random numbers to the arbitrary address, read the written data, and compare. By looping this as many times as necessary, data due to crosstalk and noise on each electronic device (10A, 10B, 10C... 10N) connected to the system bus SB generated in a specific bit arrangement. It is also possible to detect a functional problem such as a garble in a short time, or to use a random number in one of address or data.

1 is a system diagram illustrating one embodiment of an electronic apparatus having a semiconductor memory device, a logic circuit function inspection method, and a semiconductor memory device according to the present invention. It is a systematic diagram which shows the other structure of the electronic device which has the semiconductor memory device of this invention, a logic circuit function test | inspection method, and a semiconductor memory device. 6 is a flowchart of an electronic apparatus having a semiconductor memory device, a logic circuit function inspection method, and a semiconductor memory device according to the present invention. It is a systematic diagram of the conventional integrated circuit. It is a systematic diagram of the conventional integrated circuit with a test function.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Processor, 2, 16, 25, 27 ... Pseudo random number generator, 3 ... Semiconductor memory device control means 8 Memory controller), 4 ... Operation part, 10A ... Mobile phone, 10B ... PDA, 10C ... disc recording / playback device, SB ... system bus, MB ... memory bus, A, B, A-1, A-2, A-XXX, B-1, B- 2, B-XXX, C-1, C-2, C-XXX, X-1, X-2, X-XXX ... Memory

Claims (4)

In a semiconductor memory device in which an address or data from a processor is written to or read from a semiconductor memory device randomly via a system bus or a memory bus through random number generation means,
A semiconductor memory device characterized in that an address or data generated by crosstalk or the like generated in the system bus or memory bus is detected. In a semiconductor memory device in which an address or data from a processor is written to or read from a semiconductor memory device randomly via a system bus or a memory bus through random number generation means,
The random address data written by the random number generator is written to the semiconductor memory device, and the random address data written to the semiconductor memory device is read. The write data and the read data are passed through a comparing means. A semiconductor memory device characterized by detecting a functional failure caused by a specific bit arrangement by comparison. In a semiconductor memory device function inspection method in which an address or data from a processor is randomly written or read to / from a semiconductor memory device via a system bus or a memory bus through random number generation means,
The random address data written by the random number generator is written to the semiconductor memory device, and the random address data written to the semiconductor memory device is read. The write data and the read data are passed through a comparing means. A method of testing a function of a semiconductor memory device, comprising detecting a functional failure caused by a specific bit arrangement by comparing. In an electronic apparatus having a conductor storage device in which an address or data from a processor is randomly written to or read from a semiconductor storage device via a system bus or a memory bus through random number generation means,
The random address data written by the random number generator is written to the semiconductor memory device, and the random address data written to the semiconductor memory device is read. The write data and the read data are passed through a comparing means. An electronic apparatus having a semiconductor memory device, wherein a functional failure caused by a specific bit arrangement is detected by comparison.

Images