JP2006313427A - Packet processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further improve process performance relating to a short packet. <P>SOLUTION: The device comprises an SDRAM 16 for storing transmitted and received data for packet transmission, a descriptor 15 for memorizing storage location information of the transmitted and received data, Ethernet (R) controllers 11a, 11b for accessing the transmitted and received data, and a CPU core 10 for controlling the descriptor and the Ethernet (R) controllers at the time of transmitting and receiving the packet. The descriptor and the Ethernet (R) controllers are directly connected via a bus 22, while the descriptor, the SDRAM, the CPU core, and the Ethernet (R) controllers are connected via a bus 21. The Ethernet (R) controllers 11a, 11b access the transmitted and received data via the bus 21 based on the storage location information read via the bus 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a packet processing device, and more particularly to a packet processing device that performs internal data transfer by DMA (Direct Memory Access).

  In recent years, broadband lines led by ADSL (Asymmetric Digital Subscriber Line) have spread widely to homes, and as of the end of September 2004, have reached 17 million lines. In the future, it is considered that FTTH (Fiber-To-The-Home) will become popular in order to achieve various communications at higher speeds. Since optical fiber is used, it is possible to flow various data by using its high speed, and it is possible to realize triple play that simultaneously performs video distribution, IP phone with VoIP (Voice over Internet Protocol) and Internet connection. . In order to realize this, a higher-speed router and a line termination device are required, and a network processor mounted on such a packet processing device is required to have a high processing performance. By increasing the processing performance, packet loss is reduced to improve throughput, and high-speed and stable communication is possible.

  A configuration example of such a packet processing apparatus is shown in FIG. In FIG. 4, a CPU 100 is a one-chip CPU, and includes a CPU core 110, an Ethernet (registered trademark) controller 111, an IPsec engine 112, and an SDRAM controller 113. The CPU core 110 controls the entire LSI and has a data bus 121. The Ethernet (registered trademark) controller 111 performs line control, has a DMA controller therein, and enables data transfer to a memory connected to the data bus 121 without depending on the CPU. The IPsec engine 112 performs IP packet encryption and authentication processing, has an internal DMA controller (DMAC), and enables data transfer to a memory connected to the data bus 121 without depending on the CPU. Yes. The SDRAM controller 113 controls an SDRAM (Synchronous Dynamic Random Access Memory) 114 connected to the outside. The SDRAM 114 is connected to the outside of the CPU 100, and the SDRAM 114 has a data area 115 to be processed and a descriptor 116 used in DMA processing. The descriptor 116 configured in the SDRAM 114 includes a transmission descriptor and a reception descriptor for the Ethernet (registered trademark) controller 111. The data area 115 stores data to be transmitted / received.

  Next, operations in data transmission / reception will be described. When data transmission is executed, the following operations (1) to (4) are performed.

  (1) The CPU core 110 sets a transmission data pointer and status in the descriptor 116. The data flow at this time is: CPU core 110 → CPU data bus 121 → SDRAM controller 113 → descriptor 116 in SDRAM 114.

  (2) The Ethernet (registered trademark) controller 111 reads the data pointer in the descriptor 116. The data flow at this time is as follows: descriptor 116 in SDRAM 114 → SDRAM controller 113 → CPU data bus 121 → Ethernet (registered trademark) controller 111.

  (3) The Ethernet (registered trademark) controller 111 extracts data from the SDRAM 114 using the DMA function. The data flow at this time is as follows: data area 115 in SDRAM 114 → SDRAM controller 113 → CPU data bus 121 → Ethernet (registered trademark) controller 111.

  (4) The Ethernet (registered trademark) controller 111 stores the status in the descriptor 116 using the DMA function. The data flow at this time is Ethernet (registered trademark) controller 111 → CPU data bus 121 → SDRAM controller 113 → descriptor 116 in SDRAM 114.

  First, the CPU data bus 121 is used to make various settings for the descriptor 116 in the SDRAM 114. It is then used to read various settings. It is used when transmission data is transferred from the data area 115 in the SDRAM 114 to the Ethernet (registered trademark) controller 111. Further, it is used to write the status to the descriptor 116 in the SDRAM 114 again. The CPU data bus 121 is used four times for a series of data transfers, such as setting the descriptor 116, reading the descriptor 116, transferring data, and writing the status to the descriptor 116, and the bus usage rate is high.

  On the other hand, when data reception is performed, the following operations (5) to (8) are performed.

  (5) The CPU core 110 sets the received data pointer and status in the descriptor 116. The data flow at this time is: CPU core 110 → CPU data bus 121 → SDRAM controller 113 → descriptor 116 in SDRAM 114.

  (6) The Ethernet (registered trademark) controller 111 reads the received data pointer in the descriptor 116. The data flow at this time is as follows: descriptor 116 in SDRAM 114 → SDRAM controller 113 → CPU data bus 121 → Ethernet (registered trademark) controller 111.

  (7) The Ethernet (registered trademark) controller 111 stores the received data in the SDRAM 114. The data flow at this time is the Ethernet (registered trademark) controller 111 → the CPU data bus 121 → the SDRAM controller 113 → the data area 115 in the SDRAM 114.

  (8) The Ethernet (registered trademark) controller 111 stores the status in the descriptor 116 for reception. The data flow at this time is Ethernet (registered trademark) controller 111 → CPU data bus 121 → SDRAM controller 113 → descriptor 116 in SDRAM 114.

  First, the CPU data bus 121 is used to access the reception descriptor 116 in the SDRAM 114 and make various settings for the DMA operation. It is then used to read various settings. The received data is used when the Ethernet (registered trademark) controller 111 is stored in the data area 115 in the SDRAM 114. Furthermore, it is used to access the descriptor 116 in the SDRAM 114 again to write the status. As described above, the CPU data bus B1 is used four times in the series of data reception as in the transmission, and the bus usage rate is high.

As described above, the packet processing apparatus shown in FIG. 4 has a high usage rate of the CPU data bus 121, and the data transfer processing capability by the bus is limited to be low. Therefore, Patent Document 1 discloses a packet processing apparatus that distributes DMAs and descriptors on separate buses to improve packet processing performance. As shown in FIG. 5, the packet processing apparatus stores a program of the CPU 210 and is connected to the bus B1, and a first memory 212 that stores a descriptor for performing DMA processing and is connected to the bus B3. A second memory 214 and a third memory 218 for storing packet data and connected to the bus B2, and the first bus control unit 213 and the second memory are respectively connected between the first, second and third memories. The bus control unit 215 is configured to be separated. Further, to the bus B2, DMA controller 216, is connected to the line control unit ₂₁₇ 1 _{~217 n,} DMA controller 216 controls DMA master operation and a slave operation in the line control unit ₂₁₇ 1 _{~217 n.} The packet processing apparatus having such a configuration improves the packet processing performance by separating the buses and operating each bus independently.

Japanese Patent Laid-Open No. 10-341257

  By the way, in video distribution and VoIP transmission, real-time processing is important, and further, it is required that processing delay is small. For data for which delay is a problem, it is necessary to provide services at certain intervals. Usually, the payload in an Ethernet (registered trademark) frame is 64 bytes to 1500 bytes. In the case of a 1500-byte frame, the data portion occupies the majority, and the rate of access to the descriptor for data transfer is small. However, in transmission such as VoIP, it is required to transmit and receive by shortening the packet length as much as possible (short packet) so as to prevent voice loss. For example, even if a short packet having a small payload such as 64 bytes is used, it is necessary to prevent the throughput from being lowered. In this case, when a 64-byte frame is continuously transmitted and received, the descriptor is frequently accessed.

Here, the rate of access to the descriptor will be described using specific numerical examples. In a 64-byte frame, a preamble (8 bytes) and an interpacket gap (96 bits) are added,
64 bytes + 8 bytes + 96 bits = (64 + 8) * 8 bits + 96 bits = 576 bits + 96 bits = 672 bits
It becomes the data of. Now, assuming 100BASE-TX as Ethernet (registered trademark), the time required for transmission is 6.72 μsec. If all processing can be performed within this time, a throughput of 100 Mbps can be realized.

  The number of clocks required to execute this transmission processing is 67 clocks on the transmission side of the Ethernet (registered trademark) controller, 17 clocks for reading the descriptor, 38 clocks for reading the data, and 12 clocks for writing the descriptor. It is. At this time, since the receiving side generally operates at the same time, the receiving side of the Ethernet (registered trademark) controller has a total of 61 clocks of 17 clocks for descriptor read, 32 clocks for data write, and 12 clocks for descriptor write. Necessary.

  Here, it is assumed that a predetermined protocol is required for accessing the bus, and that 13 clocks for reading and 8 clocks for writing are required for accessing the SDRAM. If the descriptor is data of 4 bytes, a total of 17 clocks are required for access of 4 bytes (assuming that 1 clock is required for access of 1 byte).

  In addition, in a high-speed packet processing device, two channels of Ethernet (registered trademark) are mounted on the LAN side and the WAN side, and two controllers are configured to operate. Another Ethernet (registered trademark) controller also requires 67 clocks (transmission) and 61 clocks (reception) in executing transmission / reception. Therefore, a total of 256 clocks is required for the two channels of the Ethernet (registered trademark) controller.

  Assuming that the speed of the CPU data bus is 133 MHz, when 256 clocks are expressed in time, it becomes 1.92 μsec. When the bus occupancy is calculated, 1.92 μsec is used in 6.72 μsec. Therefore, 1.68 / 6.72 = 0.285 = 28.5%. On the other hand, if the descriptor is not accessed, the total number of clocks is reduced to 140 clocks, excluding 116 (= (17 + 12) × 2 × 2) clocks corresponding to the descriptor access from 256 clocks. Thus, the occupation ratio is 1.05 / 6.72 = 0.156 = 15.6%.

  Further, although not described here, the IPsec engine 112 also has a DMAC, which also performs access to the descriptor and DMA to the SDRAM, as in the Ethernet (registered trademark) controller. In this case, the bus occupancy rate further increases.

  When processing with a short packet is performed in this way, descriptor access processing that is almost similar to data access is required. In addition to the Ethernet (registered trademark) controller, the CPU bus of the actual processor executes a number of processes such as access to the CPU itself, encryption macro, and PCI controller. Decreases.

By the way, in the packet processing device of Patent Document 1, the DMA control unit 216 occupies the bus B2 when accessing the second memory 214 storing the descriptor. Therefore, the bus B2 is occupied in the access to the descriptor and the DMA transfer between the line control units 217 _{1 to} 217 _n and the third memory 218, and the bus occupancy rate is extremely high.

  Further, in order to perform packet processing, it is necessary for the CPU 210 to read out data stored in the third memory unit 218 and execute frame processing, so the work data of the CPU 210 is stored from the third memory unit 218. Data transfer to the first memory unit 212 occurs. In this case, since the CPU 210 occupies the buses B2 and B3, the DMA control unit 216 cannot access the descriptor for the next DMA or DMA termination.

  Furthermore, when the CPU 210 and the DMA control unit 216 access the second memory unit 214 at the same time, one of them enters an access waiting state.

  As described above, in the conventional packet processing apparatus, the DMA controller cannot access the descriptor at the same time as the data transfer, so that the performance at the time of short packet processing is deteriorated.

  In order to solve the above problem, a packet processing device according to one aspect of the present invention includes a peripheral processing unit having a DMA function for performing data transfer with a storage unit that stores transmission / reception data for packet transmission, A first bus that connects a descriptor storage unit that stores storage location information in DMA by function, and a second bus that connects the storage unit and the peripheral processing unit to perform data transfer.

  A packet processing device according to another aspect of the present invention stores a storage unit for storing transmission / reception data for packet transmission, a peripheral processing unit having a DMA function for accessing the storage unit, and storage destination information in the DMA by the DMA function. A descriptor storage unit that controls the descriptor storage unit and the peripheral processing unit when transmitting and receiving packets, a first bus that directly connects the descriptor storage unit and the peripheral processing unit, and descriptor storage A second bus that connects the storage unit, the storage unit, the control unit, and the peripheral processing unit, and the peripheral processing unit uses the second bus based on the storage location information read through the first bus. To access the storage unit.

  According to the present invention, by providing a dedicated bus for connecting the descriptor and the peripheral circuit, the peripheral circuit can simultaneously access the descriptor even when the main bus is in use. Therefore, the main bus traffic is reduced, and the packet processing performance can be further improved.

  A packet processing apparatus according to an embodiment of the present invention includes an SDRAM (16 in FIG. 1) that stores transmission / reception data for packet transmission, a descriptor (15 in FIG. 1) that stores storage destination information of transmission / reception data, and transmission / reception data. And an Ethernet controller (11a and 11b in FIG. 1) for accessing the CPU and a CPU core (10 in FIG. 1) for controlling the descriptor and the Ethernet (registered trademark) controller when transmitting and receiving packets. The descriptor and the Ethernet (registered trademark) controller are directly connected by a first bus (22 in FIG. 1), and the descriptor, SDRAM, CPU core, and Ethernet (registered trademark) controller are connected to the second bus (in FIG. 1). 21). The Ethernet (registered trademark) controller accesses transmission / reception data via the second bus based on the storage location information read via the first bus.

  The packet processing apparatus configured as described above allows the Ethernet (registered trademark) controller to simultaneously access the descriptor via the first bus even when the second bus, which is the main bus, is in use. It becomes. Therefore, the traffic on the second bus is reduced, and the processing performance in the transmission / reception of short packets is improved. Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a block diagram showing a configuration of a packet processing apparatus according to an embodiment of the present invention. In FIG. 1, the packet processing apparatus includes a CPU 5 and an SDRAM 16. The CPU 5 is a one-chip LSI, and includes a CPU core 10, Ethernet (registered trademark) controllers 11a and 11b, an IPsec engine 12, an SDRAM controller 13, a descriptor controller 14, an on-chip descriptor 15, an SDRAM 16, a CPU data bus 21, A bus 22 is provided. Although the packet processing apparatus has other various processing functions, the description thereof is omitted because it is not related to the present invention.

  The CPU core 10 is a central processing unit that controls the entire CPU. The Ethernet (registered trademark) controllers 11a and 11b are connected to a network outside the apparatus, perform Ethernet (registered trademark) MAC (Media Access Control) processing, and use an external data memory via a built-in DMAC (DMA controller). The data transfer of a certain SDRAM 16 is controlled. The IPsec engine 12 is a peripheral circuit that incorporates a DMAC and performs cryptographic processing. The SDRAM controller 13 controls the SDRAM 16 connected to the outside. The descriptor controller 14 in the SDRAM controller 13 controls the descriptor 15 and addresses the SDRAM 16 and the on-chip descriptor in the LSI. The descriptor 15 stores a pointer of data used in the DMA and a communication status. The SDRAM 16 is connected to the CPU via the SDRAM controller 13 and stores data and programs to be processed. The CPU data bus 21 connects the CPU core 10 to the Ethernet (registered trademark) controllers 11a and 11b, the IPsec engine 12, and the SDRAM controller 13. The bus 22 is a dedicated bus for peripheral circuits and descriptors, and directly connects the descriptor 15 to the Ethernet (registered trademark) controllers 11 a and 11 b and the IPsec engine 12.

  FIG. 2 is a diagram illustrating a data structure in the descriptor 15. The descriptor 15 has a plurality of sets of statuses, sizes, and address pointers for a series of data transfers. The address pointer points to the position of data in the SDRAM 16, and the size represents the size of this data. The status represents a state such as whether data has been set or transfer has been completed. Further, when the address pointer is a link pointer, it indicates that the data structure in the descriptor 15 is not continuous and the data structure continues after the destination indicated by the link pointer. Further, when the address pointer is a NULL descriptor, it means that the data structure is not continuous any more. Here, only the descriptor for one side of transmission or reception of the Ethernet (registered trademark) controller 11a is shown, but the descriptor 15 also includes descriptors for the Ethernet (registered trademark) controller 11b and the IPsec engine. ing.

  Next, operations related to data transmission / reception of the Ethernet (registered trademark) controller will be described. FIG. 3 is a diagram illustrating a sequence related to data transmission in the packet processing apparatus. In FIG. 3, when the Ethernet (registered trademark) controller 11a performs data transmission, the following steps S11 to S14 are executed.

  In step S11, the CPU core 10 sets a pointer indicating an address in the SDRAM 16 in which data to be transmitted is stored, a data size, and a status in the descriptor for transmission of the descriptor 15. The data flow at this time is as follows: CPU core 10 → CPU data bus 21 → descriptor 15. Although not shown, the CPU core 10 notifies the transmission descriptor that necessary information has been written by accessing the Ethernet (registered trademark) controller 11a.

  In step S12, the Ethernet (registered trademark) controller 11a accesses the descriptor for transmission of the descriptor 15 and reads the address pointer and size of data to be transmitted. The data flow at this time is as follows: descriptor 15 → bus 22 → Ethernet (registered trademark) controller 11a.

  In step S13, the Ethernet (registered trademark) controller 11a takes out data to be transmitted from the SDRAM 16 using the DMA function. The data flow at this time is SDRAM16 → SDRAM controller 13 → CPU data bus 21 → Ethernet (registered trademark) controller 11a. Since the bus 22 is open during this period, the Ethernet (registered trademark) controller 11 b or the IPsec engine 12 can access the descriptor 15 via the bus 22.

  In step S14, after the data transmission is completed, the status as the transmission result is stored in the descriptor 15. The data flow at this time is Ethernet (registered trademark) controller 11a → bus 22 → descriptor 15.

  Thereafter, if there is more data to be transmitted, steps S12 to S14 are repeated.

  On the other hand, when data reception is performed, the following steps S16 to S19 are executed.

  In step S <b> 16, the CPU core 10 previously sets a pointer indicating an address in the SDRAM 16 storing the received data, a data size, and an area for storing the reception status in the reception descriptor of the descriptor 15. The data flow at this time is as follows: CPU core 10 → CPU data bus 21 → descriptor 15.

  In step S17, the Ethernet (registered trademark) controller 11a accesses the descriptor for reception of the descriptor 15 and reads an address pointer and a size indicating the storage destination of the received data. The data flow at this time is as follows: descriptor 15 → bus 22 → Ethernet (registered trademark) controller 11a.

  In step S18, the Ethernet (registered trademark) controller 11a stores the received data from the Ethernet (registered trademark) controller 11a in the SDRAM 16 using the DMA function. The data flow at this time is Ethernet (registered trademark) controller 11a → CPU data bus 21 → SDRAM controller 13 → SDRAM 16. Since the bus 22 is open during this period, the Ethernet (registered trademark) controller 11 b or the IPsec engine 12 can access the descriptor 15 via the bus 22.

  In step S19, the Ethernet (registered trademark) controller 11a stores the reception status in the descriptor 15. The data flow at this time is Ethernet (registered trademark) controller 11a → bus 22 → descriptor 15.

  Thereafter, if there is more data to be received, steps S17 to S19 are repeated.

  As described above, when the Ethernet (registered trademark) controller 11 a accesses the descriptor 15, it operates so as to use the bus 22. Therefore, the CPU data bus 21 is not used for accessing the descriptor 15 of the Ethernet (registered trademark) controller 11a, and the occupancy rate of the CPU data bus 21 is reduced.

  In the above description, only the Ethernet (registered trademark) controller 11 a has been described. However, the Ethernet (registered trademark) controller 11 b and the IPsec engine 12 also operate to use the bus 22 when accessing the descriptor 15. In these cases as well, the occupancy rate of the CPU data bus 21 is similarly reduced.

  The packet processing apparatus of the present invention reduces the number of external accesses and improves the processing speed by mounting the descriptor 15 in the LSI without using an external memory in the above transmission / reception operation. When accessing an external memory such as the SDRAM 16, the access speed and cycle speed of the memory itself are often slow. In an SDRAM usually mounted on a broadband router device for home use, the operation is about 133 MHz (7.5 ns per clock). In order to compensate for this, improvement is possible by using a high-speed memory (SSRAM or the like), but the apparatus becomes expensive. Further, when the SDRAM is connected to the SSRAM for the descriptor, the number of LSI signal pins increases, leading to an increase in the size and cost of the device. Therefore, by incorporating the descriptor 15 in the LSI, it is possible to reduce the number of accesses to the low-speed external memory. Then, the access time to the descriptor is shortened, and by reducing the access occupancy rate to the descriptor of the bus, other processing can be executed, which leads to improvement in processing performance.

  Further, by using the internal memory, high speed access is possible, and the processing speed can be improved. When a memory is installed inside the LSI and used, the built-in memory itself is also fast, and if it is configured to allow direct access from the CPU core, the number of operating clocks can be greatly reduced. It leads to improvement of processing speed. As a result of a trial calculation using a certain CPU as an example, when a descriptor is configured in the SDRAM and data is read from the descriptor, 13 clocks are required. However, if a descriptor is configured in the built-in RAM, 1 to 2 clocks are required. Data can be read.

  When the CPU core 110, the Ethernet (registered trademark) controller 111, and the SDRAM controller 113 transmit / receive data when the conventional technology as shown in FIG. 4 is used, the CPU data bus 121 is occupied by the data transmission / reception. ing. Accordingly, for example, when the Ethernet (registered trademark) controller 111 is executing processing for fetching the descriptor 116 existing in the external SDRAM 114 into the DMA controller, the CPU core 110 cannot access the data area 115 existing in the SDRAM 114. Can not.

  On the other hand, in the packet processing apparatus of this embodiment, the descriptor 15 is in the LSI, and a dedicated bus 22 is provided between the Ethernet (registered trademark) controllers 11a and 11b, the IPsec engine 12 and the descriptor. For this reason, even if the Ethernet (registered trademark) controller 11 a captures the data of the descriptor 15 via the bus 22, the CPU data is transmitted between the Ethernet (registered trademark) controller 11 b or the IPsec engine 12 and the SDRAM 16. Data transfer is possible via the bus 21. Further, it becomes possible for the CPU core 10 to access data existing in the SDRAM 16 using the CPU data bus 21. In contrast, while the Ethernet (registered trademark) controller 11 a performs data transfer via the CPU data bus 21, the Ethernet (registered trademark) controller 11 b or the IPsec engine 12 transmits the descriptor 15 via the bus 22. It is possible to access the data. As described above, by providing the bus 22 that directly connects the peripheral circuit such as the Ethernet (registered trademark) controller 11a and the descriptor 15, the peripheral circuits can access the CPU data bus 21 and the bus 22 simultaneously. The processing performance can be improved by reducing the access waiting time.

  According to the present invention, in a broadband device (broadband router device or optical line termination device) connected to a broadband network (FTTH, ADSL, etc.) for homes and businesses, a device with improved processing performance compared to the conventional devices. Realized. In particular, it is possible to improve processing performance when simultaneously processing video / audio / data communication, and it is possible to realize a high-performance home gateway device that does not cause loss of video / audio.

It is a block diagram which shows the structure of the packet processing apparatus which concerns on the Example of this invention. It is a figure which shows the data structure in a descriptor. It is a figure showing the sequence which concerns on the data transmission in a packet processing apparatus. It is a block diagram which shows the structure of the conventional packet processing apparatus. It is a block diagram which shows the structure of the other conventional packet processing apparatus.

Explanation of symbols

5 CPU
10 CPU cores 11a and 11b Ethernet (registered trademark) controller 12 IPsec engine 13 SDRAM controller 14 Descriptor controller 15 Descriptor 16 SDRAM
21 CPU data bus 22 bus

Claims (6)

A peripheral processing unit having a DMA (Direct Memory Access) function for transferring data to and from a storage unit for storing transmission / reception data for packet transmission; a descriptor storage unit for storing storage destination information in the DMA by the DMA function; A first bus connecting
A second bus connecting the storage unit and the peripheral processing unit to perform the data transfer;
A packet processing apparatus comprising: A storage unit for storing transmission / reception data for packet transmission;
A peripheral processing unit having a DMA (Direct Memory Access) function for accessing the storage unit;
A descriptor storage unit for storing storage location information in DMA by the DMA function;
A control unit that controls the descriptor storage unit and the peripheral processing unit when transmitting and receiving packets; and
A first bus connecting the descriptor storage unit and the peripheral processing unit;
A second bus connecting the descriptor storage unit, the storage unit, the control unit, and the peripheral processing unit;
With
The packet processing device, wherein the peripheral processing unit accesses the storage unit via the second bus based on the storage location information read via the first bus.   The packet processing apparatus according to claim 1, wherein there are a plurality of the peripheral processing units.   4. The packet processing apparatus according to claim 3, wherein at least one of the plurality of peripheral processing units includes a communication interface unit that performs packet transmission with the outside. The storage location information includes a status indicating a storage state of the transmission / reception data, and a pointer indicating a storage location of the transmission / reception data,
When accessing the storage unit, the peripheral processing unit reads the status and the pointer before the access, accesses the storage unit based on the pointer, and rewrites the status after the access of the transmission / reception data is completed. The packet processing device according to claim 1 or 2.   3. The packet according to claim 2, wherein the descriptor storage unit, the peripheral processing unit, the control unit, the first bus, and the second bus are configured to be included in the same chip. Processing equipment.

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