JP2006311074A - Signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precisely match an output voltage with a target voltage while securing a proper rise/fall time. <P>SOLUTION: A reference voltage generation circuit 18 generates a reference voltage Vt1 which rises toward a reference voltage Vr1 as the target voltage with a constant gradient. A comparator 20 reduces an output current of a current output circuit 14 when an output voltage Vo exceeds the reference voltage Vt1. Further, a comparator 19 turns off a switch circuit 15 when the output voltage Vo exceeds the reference voltage Vr1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal generation circuit that generates a trapezoidal signal.

  FIG. 6 shows a configuration of a conventional trapezoidal wave signal generation circuit. The constant current circuit 1, the switch circuit 2 and the capacitor 3 are connected in series, and the comparator 4 turns off the switch circuit 2 when the voltage of the capacitor 3 exceeds the reference voltage Vr generated by the reference voltage generation circuit 5. It is like that. FIG. 7 shows the waveform of the output voltage Vo and the waveform of the output signal of the comparator 4.

In Patent Document 1, in order to reduce harmonic components caused by the edges appearing at the increase / decrease start point and the increase / decrease end point of the trapezoidal wave signal, the voltage between the terminals of the capacitor and a plurality of threshold voltages are set. Based on the comparison, a trapezoidal wave signal generation circuit is disclosed that performs control so that the charge / discharge current to the capacitor decreases as the voltage difference between the terminal voltage and the power supply line decreases.
JP 2004-289597 A

  In the trapezoidal wave signal generation circuit shown in FIG. 6, the output voltage Vo greatly exceeds the reference voltage Vr, which is the target voltage, due to the operation delay of the comparator 4, as shown in FIG. In the figure, td is a delay time, and ΔV is an excess voltage with respect to the reference voltage Vr. The problem of excess output voltage appears more markedly as the rate of change (slew rate) of the output voltage Vo increases.

  To cope with this, it is conceivable to set the reference voltage Vr lower than the target voltage in anticipation of the delay time of the comparator 4. However, when the load of the trapezoidal wave signal generation circuit fluctuates or when there is a manufacturing variation in the capacitance of the capacitor 3, the slew rate of the output voltage Vo changes, so the reference voltage Vr is accurately determined. It becomes very difficult. If the setting of the reference voltage Vr is not appropriate, the output voltage Vo stops changing at a voltage that deviates from the target voltage.

  On the other hand, in the trapezoidal wave signal generation circuit described in Patent Document 1, the charge / discharge current to the capacitor is controlled to be smaller as the voltage difference between the capacitor voltage and the target voltage is smaller. According to this current reduction control, the effect of reducing the excess voltage ΔV can be obtained. However, when the slew rate of the output voltage Vo is large, the output voltage Vo may still exceed the target voltage. Further, if the start voltage of the current reduction control is lowered in order to reduce the excess voltage ΔV, the rise time is abnormally increased when the slew rate of the output voltage Vo is small.

  The present invention has been made in view of the above circumstances, and its purpose is a signal that can accurately match the output voltage to the target voltage while ensuring appropriate rise and fall times regardless of the slew rate. It is to provide a generation circuit.

  According to the first aspect of the present invention, when the switch circuit is switched to the current non-cutoff state (ON state), the charging current flows from the current output circuit to the capacitor, and the voltage across the capacitor (output signal) is To increase. When the voltage between the terminals of the capacitor exceeds the second reference voltage, the charging current flowing from the current output circuit to the capacitor is reduced by a command from the second comparison circuit (current reduction control). After that, when the voltage between the terminals of the capacitor exceeds the first reference voltage corresponding to the target value, the switch circuit is switched to the current cutoff state (off state) by a command from the first comparison circuit. Stops changing.

  Here, the second reference voltage changes at a predetermined change rate so that the voltage difference from the target value gradually decreases. When such a second reference voltage is used, when the slew rate of the capacitor terminal voltage is large, the capacitor terminal voltage exceeds the second reference voltage at a voltage value far from the target value. The output current of the current output circuit decreases from a relatively early point. On the other hand, when the slew rate of the capacitor terminal voltage is small, the capacitor terminal voltage exceeds the second reference voltage at a voltage value close to the target value. Output current decreases.

  As a result, when the slew rate is large and the change time until reaching the target value is short, the output current of the current output circuit can be decreased from the earlier point to eliminate the influence of the delay time of the comparison circuit. In addition, when the slew rate is small and the change time until reaching the target value is long, the output current of the current output circuit is decreased from that later point to prevent the rise time from becoming long. As a result, regardless of the slew rate, the capacitor terminal voltage (output signal) can be accurately matched to the target value while ensuring an appropriate rise time. The operation and effect when the voltage between the terminals of the capacitor decreases are the same.

  According to the means described in claim 2, since the second reference voltage changes with a constant slope toward the target value after the switch circuit is switched to the current non-cutoff state, the voltage across the terminals of the capacitor is reduced. The current decrease start point of the current output circuit is accelerated in proportion to the rate.

  According to the means described in claim 3, the second reference voltage changes from an intermediate value between the terminal voltage of the capacitor and the target value when the switch circuit is switched to the current non-cutoff state toward the target value. To start. Therefore, before the voltage between the terminals of the capacitor reaches the intermediate value, the current of the current output circuit does not start to decrease, and the rise time (fall time) can be prevented from becoming longer.

  According to the means described in claim 4, since a predetermined margin value is secured between the target value and the second reference voltage, even if the slew rate of the voltage across the terminals of the capacitor is small The current of the current output circuit decreases before the terminal voltage reaches the target value. Thereby, even when the slew rate is small, the current reduction control by the second comparison circuit can be effectively functioned.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 shows a schematic configuration related to a signal rising operation in a trapezoidal wave signal generation circuit that generates a trapezoidal wave signal, and FIG. 2 shows an overall configuration of the trapezoidal wave signal generation circuit. The trapezoidal wave signal generation circuit 11 shown in these drawings is used, for example, in the in-vehicle LAN interface standard Safe-by-Wire constituting the airbag system of the vehicle. This standard Safe-by-Wire is realized by connecting a master for controlling bus operations and a slave provided in an airbag or sensor in the form of a parallel, daisy chain, tree or ring.

  The bus is composed of two differential signal lines, and has a ternary data level and one power level. Here, the ternary data levels are L0 (data level 0) having a differential voltage of 6V, L1 (data level 1) having a differential voltage of 3V, and L1 (special data level 0) having a differential voltage of 0V. Yes, data is transmitted in the data phase. The power level has a differential voltage of 11V. In the power phase, the slave is supplied with power by a 50% duty pulse supplied from the master to the bus. The trapezoidal wave signal generation circuit 11 described in the present embodiment generates a trapezoidal wave signal that drives the bus in response to changes in the power phase and the data phase. The reason why the trapezoidal wave signal is used instead of the square wave signal is to suppress the generation of noise.

  In FIG. 1, a current output circuit 14, a switch circuit 15, and a capacitor 16 are connected in series between the power supply line 12 and the power supply line 13 (ground), and the voltage between terminals of the capacitor 16 is the output voltage. Vo (trapezoidal wave signal). The reference voltage generation circuit 17 generates a reference voltage Vr1 equal to the target voltage that is the upper base voltage of the trapezoidal wave signal, and the reference voltage generation circuit 18 is lower than the target voltage and increases with a constant slope toward the target voltage. The reference voltage Vt1 is generated.

  The comparator 19 compares the output voltage Vo with the reference voltage Vr1, and opens and closes the switch circuit 15 according to the comparison result. The comparator 20 compares the output voltage Vo with the reference voltage Vt1, and changes the output current of the current output circuit 14 according to the comparison result.

  FIG. 2 shows a specific circuit configuration of the trapezoidal wave signal generation circuit 11 that can perform not only a signal rising operation but also a signal falling operation. The trapezoidal wave signal generation circuit 11 includes a signal drop operation in addition to the above-described current output circuit 14, switch circuit 15 (15a and 15b in FIG. 2), capacitor 16, reference voltage generation circuits 17 and 18, and comparators 19 and 20. And a switch control circuit 25 for controlling the comparators 23 and 24 and the switch circuits 15a and 15b. Here, the reference voltage generation circuits 17 and 21 and the reference voltage generation circuits 18 and 22 correspond to the first reference voltage generation circuit and the second reference voltage generation circuit of the present invention, respectively, and the comparators 19 and 23 and the comparator 20 , 24 correspond to the first comparison circuit and the second comparison circuit of the present invention, respectively.

  The current output circuit 14 is a variable current source that supplies a charging current or a discharging current to the capacitor 16 based on the signals S1, S6, and S7. The signal S1 is a signal for switching the direction of the output current of the current output circuit 14, that is, the charge operation and the discharge operation of the capacitor 16, and the signal S6 indicates whether the switch circuits 15a and 15b are opened or closed, that is, whether or not the current output circuit 14 outputs current. This is a switching signal. When the signal S6 is at L level, the switch circuits 15a and 15b are turned on, and when the signal S6 is at H level, the switch circuits 15a and 15b are turned off. The signal S7 is a current command signal for switching whether to reduce the output current of the current output circuit 14.

  The current output circuit 14 includes two independent current output circuits 26 and 27. Among them, the current output circuit 26 is for supplying a constant charging current or discharging current to the capacitor 16 in a state where the switch circuit 15a is turned on. A transistor Q11, a switch circuit 15a and a constant current circuit 28 are connected in series between the power supply lines 12 and 13, and the transistor Q11 and the transistors Q12 and Q13 constitute a current mirror circuit.

  On the other hand, the current output circuit 27 is for supplying a charging current or a discharging current corresponding to the voltage across the capacitor 29 to the capacitor 16 in a state where the switch circuit 15b is turned on. A transistor Q14 and a constant current circuit 30 are connected in series between the power supply lines 12 and 13, and the transistor Q14 and transistors Q15, Q16, and Q17 constitute a current mirror circuit. The collectors of the transistors Q16 and Q17 are connected in common, and the transistor Q18 connected between the collector and the power supply line 13 and the transistor Q19 connected between the terminals of the capacitor 29 constitute a current mirror circuit. Yes. The transistor Q18 is connected in parallel with a transistor Q20 that operates using the signal S7 as a base signal, and the capacitor 29 is connected in parallel with a Zener diode 31.

  A transistor Q22, a switch circuit 15b, a transistor Q21, and a resistor 32 are connected in series between the power supply lines 12 and 13. Here, the base of the transistor Q21 is connected to the collector of the transistor Q15, and the transistor Q22 and the transistors Q23 and Q24 constitute a current mirror circuit.

  The collectors of the transistors Q12 and Q23 are connected in common, and the capacitor 16 is connected between the collector and the power supply line 13. The collectors of the transistors Q13 and Q24 are connected in common, and the transistor Q25 connected between the collector and the power supply line 13 and the transistors Q26 and Q27 connected between the terminals of the capacitor 16 are current mirror circuits. Is configured. The transistor Q25 is connected in parallel with a transistor Q28 that operates using the signal S1 as a base signal.

  As described above, the comparator 19 compares the output voltage Vo with the reference voltage Vr1 generated by the reference voltage generation circuit 17 and outputs the signal S2. The comparator 20 and the inverter 33 that follows the comparator 20 output the output voltage Vo and the reference voltage. The reference voltage Vt1 generated by the voltage generation circuit 18 is compared and a signal S3 is output. Similarly, the comparator 23 compares the output voltage Vo with the reference voltage Vr2 generated by the reference voltage generation circuit 21 and outputs a signal S4. The comparator 24 and the subsequent inverter 34 generate the output voltage Vo and the reference voltage. The reference voltage Vt2 generated by the circuit 22 is compared and a signal S5 is output. These comparators 19, 20, 23, 24, inverters 33, 34 and switch control circuit 25 operate by receiving supply of power supply voltage Vcc from power supply lines 12 and 13.

  The switch control circuit 25 includes AND gates 35 and 36 that generate a signal S6 from the signals S2 and S4 and an OR gate 37, AND gates 38 and 39 that generate a signal S7 from the signals S2 to S5, and OR gates 40, 41, and 42; The inverter 43 is configured.

FIG. 3 shows a specific circuit configuration of the reference voltage generation circuit 18.
A constant voltage circuit 45 that outputs a constant voltage VH1 is connected between the power supply lines 44 and 13. A current mirror circuit composed of transistors Q29 and Q30 and a current mirror circuit composed of transistors Q31 and Q32 are connected to the power supply line 44, and a capacitor 46 is connected between the collector of the transistor Q30 and the power supply line 13. Has been. The collectors of the transistors Q29 and Q31 are respectively connected to terminals a and b of the switch circuit 47, and a constant current circuit 48 is connected between the terminal c of the switch circuit 47 and the power supply line 13.

  Transistors Q33 and Q34 constitute a current mirror circuit, and a constant voltage circuit 49 for outputting a constant voltage VL1 is connected between the emitters of the commonly connected transistors Q33 and Q34 and the power supply line 13. Yes. The collectors of the transistors Q33 and Q34 are connected to the collectors of the transistors Q32 and Q39, respectively. The voltage between the terminals of the capacitor 46 is output as the reference voltage Vt1. The reference voltage generation circuit 22 is similarly configured.

Next, the operation of the present embodiment will be described with reference to FIGS.
FIG. 4 is a waveform diagram of each signal, voltage, and current of the trapezoidal wave signal generation circuit 11. From top to bottom, the signals S1 to S7, the voltage Vp between terminals of the capacitor 29, the current I3 that flows through the transistor Q21, and the capacitor 16 flow. The current Ic and the terminal voltage Vo (output voltage Vo) of the capacitor 16 are shown. However, a delay time td of a comparator, which will be described later, is not taken into account in the change timing of each signal.

  The period from time t1 to time t6 when the signal S1 becomes H level is a signal rising period, and ideally, the voltage Vr1 is maintained after the output voltage Vo rises from Vr2 to Vr1. On the other hand, the period from time t6 to time t11 when the signal S1 becomes L level is a signal falling period, and ideally, the output voltage Vo is maintained from Vr1 to Vr2, and then the voltage Vr2 is maintained. That is, the reference voltages Vr1 and Vr2 are the upper and lower base voltages of the trapezoidal wave signal, respectively.

  In the switch control circuit 25, when the signal S1 is at the H level, only the AND gates 35 and 38 among the AND gates 35, 36, 38, and 39 are in a signal passing state, and when the signal S1 is at the L level, only the AND gates 36 and 39 are in the state. A signal passing state is entered. Therefore, in the signal rising period in which the signal S1 is at the H level, the logical expressions S6 = S2 and S7 = S2 + S3 are established, and in the signal falling period in which the signal S1 is at the L level, the logical expressions S6 = S4 and S7 = S4 + S5. Is established.

The operation during the signal rising period when the signal S1 is at the H level and the operation during the signal falling period when the signal S1 is at the L level are exactly the same. Therefore, the operation during the signal rising period will be described in detail below.
At time t1, the output voltage Vo (voltage between terminals of the capacitor 16) is Vr2. When the signal S1 becomes H level, the signal S6 changes from H level to L level, and the switch circuits 15a and 15b are turned on. At the same time, since the transistor Q28 is turned on, the transistors Q26 and Q27, which are discharge paths of the capacitor 16, are turned off, and the transistor Q12 of the current output circuit 26 and the transistor Q23 of the current output circuit 27 each output a charging current to the capacitor 16. To do.

  During a period from time t1 to time t3 when the output voltage Vo exceeds the reference voltage Vt1, both the current output circuits 26 and 27 output a constant current, and the output voltage Vo rises with a constant slope. When the output voltage Vo exceeds Vt1 at time t3, the signal S3 changes from the H level to the L level, and the output current of the current output circuit 27 decreases with a constant slope, so the rate of increase of the output voltage Vo gradually decreases. To do. When the output voltage Vo exceeds Vr1 at time t4, the signal S2 changes from L level to H level, and the switch circuits 15a and 15b are turned off. As a result, the current output circuits 26 and 27 both stop outputting current, and the output voltage Vo maintains the voltage Vr1 at that time.

  In this series of operations, the current output circuit 26 outputs the output current I1 of the constant current circuit 28 as it is through the transistor Q12 while the switch circuit 15a is on. On the other hand, the current output circuit 27 charges and discharges the capacitor 29 by the output current I2 of the constant current circuit 30, and outputs a current I3 proportional to the terminal voltage Vp of the capacitor 29 via the transistor Q23. If the current output circuit 27 is configured in this way, the output current can be changed by switching charging / discharging of the capacitor 29 using the signal S7.

  That is, during the period from time t1 to time t3, since Vo <Vt1 <Vr1, the signal S2 is at the L level, the signal S3 is at the H level, and the signal S7 is at the H level. As a result, the transistor Q20 is turned on, the transistors Q18 and Q19 are turned off, and the output current I2 of the constant current circuit 30 becomes the charging current of the capacitor 29 via the transistors Q14 and Q15. However, since the inter-terminal voltage Vp of the capacitor 29 is clamped by the Zener voltage Vz of the Zener diode 31, a constant current I3 corresponding to the Zener voltage Vz flows through the transistors Q21, Q22, and Q23.

  In the period from time t3 to time t4, since Vt1 <Vo <Vr1, both the signals S2 and S3 are at the L level and the signal S7 is at the L level. Thereby, the transistor Q20 is turned off and the transistors Q18 and Q19 are turned on, and a discharge current equal to the current I2 flows from the capacitor 29 via the transistor Q19. As a result, the inter-terminal voltage Vp of the capacitor 29 decreases with a constant slope, and accordingly, the current I3 flowing through the transistors Q21, Q22, and Q23 and hence the charging current Ic flowing through the capacitor 16 decreases with a constant slope.

Next, the reference voltage Vt1 that is a feature of the present embodiment will be described with reference to FIG. 5 showing a detailed waveform in the signal rise period. Since the reference voltage Vt2 used in the signal falling period is the same as the reference voltage Vt1 used in the signal rising period, description thereof is omitted.
The comparators 19, 20, 23, and 24 have a delay from the change of the input voltage to the output of the comparison result. When this delay time is td [sec], when the rate of change (slew rate) of the output voltage Vo is R [V / sec], the output is already output when the output signal S2 of the comparator 19 changes from L level to H level. The voltage Vo exceeds the target voltage Vr1 by R · td [V]. Therefore, a reference voltage generation circuit 18 for generating a reference voltage Vt1 lower than Vr1 and a comparator 20 are provided, and the charging current Ic to the capacitor 16 is gradually reduced from the time when the output voltage Vo reaches the voltage Vt1 lower than Vr1. ing. When the charging current Ic decreases, the slew rate of the output voltage Vo decreases, so that excess voltage due to the delay time can be reduced.

  The reference voltage Vt1 of the present embodiment rises with a constant slope from VL1 to Vr1 (target value) when the signal S1 changes from L level to H level, and holds the voltage VH1 when reaching the voltage VH1. Here, the voltage VL1 is an intermediate voltage between the reference voltages Vr2 and Vr1, and the voltage VH1 is a voltage lower than the target voltage Vr1 by a predetermined margin voltage. The slope is set smaller than the maximum slew rate of the output voltage Vo.

  Specifically, when the signal S1 changes from the L level to the H level, the switch circuit 47 is turned on between a and c in FIG. 3, and a charging current equal to the output current I4 of the constant current circuit 48 flows through the capacitor 46. . As a result, the reference voltage Vt1 rises with the above-described constant slope, and when the voltage VH1 is reached, the voltage VH1 is held.

  When such a reference voltage Vt1 is used as a comparison reference for the output voltage Vo, when the slew rate of the output voltage Vo is large (indicated by M1 in FIG. 5), a voltage value that is far from the target voltage Vr1 (that is, low). In the voltage value), the output voltage Vo exceeds the reference voltage Vt1 (time t1a). Thereafter, the slew rate of the output voltage Vo gradually decreases from time t1b when the delay time td of the comparator 20 has elapsed. As a result, when the output voltage Vo reaches the voltage Vr1, the slew rate of the output voltage Vo is greatly reduced, and the voltage excess due to the delay time of the comparator 19 can be greatly reduced.

  On the other hand, when the slew rate of the output voltage Vo is small (indicated by M2 in FIG. 5), the output voltage Vo exceeds the reference voltage Vt1 at a voltage value close to the target voltage Vr1 (that is, a high voltage value) ( Time t1c). Thereafter, the slew rate of the output voltage Vo gradually decreases from time t1d when the delay time td has elapsed. In this case, the slew rate reduction start time is delayed as compared with the case indicated by M1, but since the slew rate is originally small, the slew rate of the output voltage Vo is sufficiently high when the output voltage Vo reaches the voltage Vr1. is decreasing. Therefore, also in this case, it is possible to reduce the excess voltage due to the delay time of the comparator 19.

  Since the reference voltage Vt1 is clamped by the voltage VH1, even when the slew rate of the output voltage Vo is further reduced (indicated by M3 in FIG. 5), the output voltage Vo starts from the time when the voltage VH1 is reached (time t1e). The slew rate begins to decrease at time t1f when the delay time td has elapsed. Voltage VH1 (ie, margin voltage Vr1−VH1) is determined based on the minimum value of the slew rate of output voltage Vo and the delay time td of the comparator.

  As described above, the trapezoidal wave signal generation circuit 11 of the present embodiment includes the comparator 19 that compares the reference voltage Vr1 that is the target value and the output voltage Vo, and the reference voltage Vt1 that is lower than the target value, for the signal rising operation. And a comparator 20 that compares the output voltage Vo with each other, and when the output voltage Vo becomes higher than the reference voltage Vt1, the slew rate of the output voltage Vo is reduced. Similarly, for the signal falling operation, a comparator 23 that compares the reference voltage Vr2 that is the target value and the output voltage Vo, and a comparator 24 that compares the reference voltage Vt2 that is higher than the target value and the output voltage Vo are provided. When the voltage Vo falls below the reference voltage Vt2, the slew rate of the output voltage Vo is reduced. As a result, it is possible to reduce excess voltage due to the delay time td of the comparators 19 and 23.

  Further, when the signal rises, the reference voltage Vt1 rises from VL1 to VH1 with a constant slope. Therefore, when the change time from the output voltage Vo to the target voltage Vr1 is short, the slew rate of the output voltage Vo is short. The charging current Ic decreases from a point earlier by the amount. In addition, when the change time to the voltage Vr1 at which the slew rate is small and the target value is long, the charging current Ic is reduced from the later time. Thereby, regardless of the size of the slew rate (for example, capacitance variation of the capacitor 16), it is possible to further reduce the voltage excess due to the delay time of the comparator 19 while preventing the rise time from becoming long. The same applies when the signal falls.

  In the standard Safe-by-Wire, voltage values are defined in the data phase and the power phase. By using the trapezoidal wave signal generation circuit 11 of the present embodiment, a highly accurate trapezoidal wave signal conforming to the standard can be generated. In addition, since the waveform change at the end of rising and falling ends of the trapezoidal wave signal becomes smooth, the amount of noise generated due to communication is also reduced.

  The reference voltages Vt1 and Vt2 are clamped by the voltages VH1 and VH2, respectively, and a marginal voltage is secured between the voltages Vr1 and Vr2. Thereby, even when the slew rate of the output voltage Vo is small, the charge / discharge current Ic is controlled to be reduced before the target voltage is reached, and a highly accurate trapezoidal wave signal can be generated.

The present invention is not limited to the embodiment described above and shown in the drawings. For example, the present invention can be modified or expanded as follows.
The reference voltages Vt1 and Vt2 need only have characteristics that change so that the voltage difference from the reference voltages Vr1 and Vr2 gradually decreases, and need not always change with a constant slope.
The marginal voltages Vr1-VH1 and VL2-Vr2 may be zero as necessary.
The trapezoidal wave signal generation circuit 11 may be composed of an FET instead of a bipolar transistor.

The schematic block diagram regarding the signal rise operation | movement of the trapezoidal wave signal generation circuit which shows one Embodiment of this invention Specific configuration diagram of trapezoidal wave signal generation circuit Specific configuration diagram of the reference voltage generation circuit Diagram showing trapezoidal wave signal generation circuit signal, voltage, and current waveforms The figure which shows the detailed waveform of the output voltage Vo and the reference voltage Vt1 in a signal rise period 1 equivalent diagram showing the prior art The figure which shows the waveform of the output signal Vo and the output signal of a comparator

Explanation of symbols

  In the drawing, 11 is a trapezoidal wave signal generation circuit (signal generation circuit), 14 is a current output circuit, 15, 15 a and 15 b are switch circuits, 16 is a capacitor, 17 and 21 are reference voltage generation circuits (first reference voltage generation circuit) Circuit), 18, 22 reference voltage generation circuit (second reference voltage generation circuit), 19, 23 are comparators (first comparison circuit), and 20, 24 are comparators (second comparison circuit).

Claims (4)

A capacitor that outputs a voltage between terminals as a signal;
A current output circuit for outputting a current corresponding to the current command signal to the capacitor;
A switch circuit that cuts off a current flowing from the current output circuit to the capacitor;
A first reference voltage generation circuit for generating a first reference voltage corresponding to a target value of the voltage across the capacitors;
The first reference voltage is compared with the voltage between the terminals of the capacitor, and a current interruption operation is performed on the switch circuit according to a comparison result that the voltage between the terminals of the capacitor exceeds the first reference voltage. A first comparator circuit to command;
A second reference voltage generation circuit that generates a second reference voltage that changes at a predetermined rate of change so that a voltage difference from the target value gradually decreases after the switch circuit is switched to a current non-cutoff state. When,
The second reference voltage is compared with the voltage across the terminals of the capacitor, and the current is reduced with respect to the current output circuit according to the comparison result that the voltage across the terminals of the capacitor exceeds the second reference voltage. And a second comparison circuit for outputting a current command signal for commanding the signal.   2. The signal generation circuit according to claim 1, wherein the second reference voltage generation circuit generates a second reference voltage that changes with a constant slope toward the target value.   The second reference voltage generation circuit starts changing from the intermediate value between the terminal voltage of the capacitor and the target value toward the target value when the switch circuit is switched to the current non-cutoff state. 3. The signal generation circuit according to claim 1, wherein the reference voltage of 2 is generated. 4. The second reference voltage generation circuit according to claim 1, wherein the second reference voltage generation circuit generates the second reference voltage so that a voltage difference from the target value is ensured by at least a predetermined margin value. A signal generation circuit according to claim 1.

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