JP2006285823A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption in a waiting mode in a semiconductor integrated circuit capable of promptly returning to a normal mode from the waiting mode. <P>SOLUTION: This semiconductor integrated circuit is provided with: a clock generation circuit 10 having a self-traveling mode and a multiplication mode; an internal circuit 40 capable of operating in synchronization with a clock signal generated by the clock generation circuit; an oscillation circuit 30 generating a reference clock signal; and an operation mode control circuit 20 capable of controlling changeover between the normal mode and the waiting mode. The clock signal by the self-traveling mode is generated before the oscillation operation of the oscillation circuit becomes stable, so that the internal circuit can operate in the normal mode in synchronization therewith, and a return time to the normal mode from the waiting mode is reduced. In the waiting mode, the oscillation operation of the oscillation circuit is stopped to reduce the power consumption. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and further to a clock generation technique therefor, and particularly to a technique effective when applied to a microcontroller.

  There is a strong demand for portable devices to reduce power consumption during standby as well as during operation. In general, a portable device is equipped with a microcontroller for controlling the device and an oscillation circuit for supplying an operation clock signal to the entire system including the microcontroller. Among portable devices, there are devices that stop the operation of an oscillation circuit that supplies a clock signal in order to reduce standby power consumption to the limit. Of course, since the microcontroller cannot operate unless a clock is supplied, it is necessary to restart the operation of the oscillation circuit and supply the clock to the microcontroller in order to return from the standby state. Since it takes time to start up the oscillation circuit, a system that reduces the standby power consumption, such as stopping clock oscillation, is adopted for a system in which the microcontroller must respond immediately to some stimulus and perform processing. It is not possible. In other words, the startup time of the microcontroller and the power consumption for maintaining the clock oscillation are in a trade-off relationship. This will be described in more detail below.

  The standby current consumption required for a microcontroller mounted on a portable device is less than several tens of μA, and of course, the lower the better. On the other hand, such a microcontroller is required to have high processing performance, and a clock generation circuit that internally multiplies a reference clock generated by an oscillation circuit using a crystal oscillator may be mounted. . In addition, the microcontroller is provided with an operation mode and a standby mode. Normally, the standby mode is a standby mode, and the microcontroller is in a standby state in order to change to the operation mode by some stimulus. The stimulus is, for example, a user's key operation or an incoming call. For the microcontroller, a signal input to a general-purpose input / output port or an activation request from a connected device via a serial communication interface, etc. Detected as a command received.

  In order to keep the current consumption during standby to a low level of less than several tens of μA, it is not enough to stop the operation by setting the microcontroller to standby mode, and it is also necessary to stop the operation of the oscillation circuit that generates the reference clock. is there. According to a circuit using a crystal resonator, the current consumption when maintaining clock oscillation is 8 mA MAX, and it is 20 μA MAX even in a standby state where oscillation output is stopped. The crystal oscillator of several MHz to several tens of MHz that is the reference clock for the microcontroller is mounted on the same chip, and even if it suppresses the power to excite the outside, the current consumption during standby can be maintained simply by maintaining the oscillation operation. This is because a current of several tens of μA is consumed.

  When a stimulus is detected during standby, some means for starting the oscillation circuit first and then transitioning the microcontroller from the standby mode to the operation mode is required separately from the microcontroller. This is because the microcontroller itself does not receive a clock when the stimulus is sensed, and cannot perform operations such as controlling other devices. When a stimulus is detected and the oscillation circuit is activated, the time until the oscillation stabilizes is usually several ms. For example, Non-Patent Document 1 describes 3 ms MAX as the startup time of the clock crystal oscillator. In the portable device, when the stimulus is detected, the clock oscillation is resumed, and after the clock generation circuit mounted on the microcontroller generates the operation clock, the program processing responding to the stimulus can be started. For example, as described in Patent Document 1 and Patent Document 2, the clock generation circuit generates a clock obtained by multiplying the frequency of the input reference clock by a predetermined frequency and supplies the generated clock to the microcontroller. In order to multiply the reference clock, a phase locked loop (abbreviated as PLL) or a delay locked loop (abbreviated as DLL) is used. The PLL adjusts the oscillation frequency of the oscillation circuit according to the output of the oscillation circuit that can control the oscillation frequency, the phase comparator that compares the phase of the output clock of the oscillation circuit and the input reference clock. It consists of a control circuit. The DLL can control the delay amount of the output pulse with respect to the input pulse. The oscillation circuit that oscillates by feeding back the output pulse to the input pulse is compared with the oscillation cycle and the reference clock cycle. It consists of a control circuit that adjusts the amount of delay. In either case, the oscillation circuit clock and the reference clock are compared and synchronized. When the reference clock starts to be input, the oscillation circuit clock does not coincide with the reference clock, and the difference is fed back. The pull-in time to match gradually is required. In order to multiply the frequency, the frequency can be multiplied by the number of divisions by controlling the waveform obtained by dividing the oscillation clock and the reference clock so as to match. In both cases, it is assumed that the reference clock is supplied. When the reference clock is stopped during standby, it takes time to wait for the reference clock to resume when returning from the standby state. Cannot be resolved.

  The known example described in Patent Document 1 generates a clock signal having a high frequency from a reference clock signal having a low frequency. The delay line circuit sequentially delays the reference clock signal, and the output of the delay line circuit. And a logic circuit that generates a clock having an integer multiple frequency. Comparing the output of the delay line circuit with the reference clock, and controlling the delay value of the delay line circuit, the frequency of the generated high frequency clock is set to an exact integer multiple of the reference clock frequency, and abnormal Reduce locks and phase jitter. According to Patent Document 1, it is assumed that the reference clock signal is stably supplied, and when the supply of the reference clock is also stopped in the standby state, the oscillation of the reference clock is stabilized upon recovery. After the supply is resumed, the above-described delay value adjusting mechanism based on the phase comparison is operated to obtain a clock having a high required frequency. Therefore, a considerable amount of oscillation stabilization time is required for returning from the standby state.

  The known example described in Patent Document 2 is a waveform generator that supplies a clock to a microprocessor or the like, and includes a delay chain and a control circuit that matches the propagation delay of the delay chain to the period of the input timing signal. The problem is to quickly start and stop the internal clock to reduce power. In this specification, the known example points out that it is difficult to quickly stop and restart the clock in the specification, and proposes a waveform generator using the delay chain. However, similarly to the known example according to Patent Document 1, it is assumed that the input timing signal is stably supplied, and when the supply of the input timing signal is also stopped in the standby state, After the oscillation of the input timing signal is stabilized and the supply is resumed, the necessary clock is obtained by operating the delay value adjusting mechanism by the control circuit. Therefore, even with the technique according to Patent Document 2, a considerable amount of oscillation stabilization time is required to return from the standby state.

  As described above, in the conventional portable device, when the reference clock is stopped in order to reduce the power consumption during standby, the start-up time of the oscillation circuit starts from the standby state to return to the normal operation state. A time of several ms is required.

  On the other hand, in a portable device, there are various stimuli for requesting a transition from a standby state to a normal state, and there are some that cannot allow a time of several ms until a response to the stimulus. For example, when returning from standby by a key operation by a person, it is generally considered that several ms is allowed, but when a start command is transmitted by serial communication transmitted at a predetermined baud rate. The acceptable time is very short. Assuming that the baud rate is 9600 bps here, the period of 1 bit is about 0.1 ms, and when the first bit is inputted, about 0.1 ms is triggered by the input of the first bit. A means to capture the second bit is necessary. Accordingly, the number of milliseconds required to activate the reference clock oscillation circuit and supply it to the microcontroller and generate the internal clock by the internal clock generation circuit is not an allowable time. Therefore, in such a system, the clock of the microcontroller cannot be stopped completely, and at least the oscillation operation of the reference clock is maintained, so that it is difficult to suppress the power consumption during standby to tens of μA or less. .

  In general, power consumption during standby of a semiconductor integrated circuit is clock oscillation power, power of a circuit operating with the clock, power due to an analog DC steady current, and power due to leakage current. The analog DC steady-state current can be devised as a circuit that stops during standby. Leakage current has become more prominent with recent miniaturization of integrated circuits, but various techniques for suppressing leakage current have been developed by selectively shutting off power to fine circuit portions. When the clock oscillation is stopped, the power consumption of the semiconductor integrated circuit during standby can be reduced to almost zero by suppressing the clock oscillation power and the power of the circuit operated by the clock.

  Patent Document 3 discloses a technique for extracting a sampling clock from received data and capturing the received data in a data communication system. A sampling rate that matches the transmission data rate of the communication partner can be reproduced on the receiving side. Although not suggested in the specification of the patent document, it is considered that according to this technique, it is possible to sample received data without external clock supply. However, the technique is intended for sampling of communication data, and the generated sampling clock cannot be used for processing the received data after sampling. This is because, in this technology, the communication data defines a maximum bit length that does not change the value of bit data during serial data input, and is equipped with hardware that can absorb the maximum bit length. Therefore, since the generation of the clock is stopped when the communication data is interrupted, the processing of the received data is interrupted together with the interruption of the communication data. Therefore, generally, the sampling clock and the clock for subsequent data processing are separated.

Crystal oscillator FXO2520F for surface mount type clocks manufactured by Kyocera Corporation JP-A-6-61849 JP-A-6-252717 JP 2003-258771 A

  In a portable device equipped with a microcontroller and an oscillation circuit that supplies a clock to the microcontroller, if the oscillation of the clock is stopped during standby, it takes time to start the oscillation circuit, so it can respond immediately to any stimulus generated during standby. Can not. Therefore, in a system where the microcontroller must perform processing immediately in response to some stimulus generated during standby, it is not possible to employ a standby power consumption reduction method that stops clock oscillation. The power consumption during standby cannot be reduced sufficiently. In other words, the startup time of the microcontroller and the power consumption to maintain clock oscillation are in a trade-off relationship, with no waiting time such as waiting for clock oscillation resumption while making standby power consumption almost zero, It is considered difficult to recover from the standby state.

  An object of the present invention is to provide a technique for reducing power consumption in the standby mode in a semiconductor integrated circuit capable of quickly returning from the standby mode to the normal mode.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] An oscillation circuit that generates a reference clock signal using a vibrator, a free-running mode in which a clock signal having a predetermined pulse width is continuously generated by an internal logic circuit, and a frequency by multiplying the frequency of the reference clock signal A clock generation circuit having a multiplication mode for generating a signal, an internal circuit operable in synchronization with the clock signal generated by the clock generation circuit, and a normal mode in which the internal circuit operates in synchronization with the clock signal And an operation mode control circuit that can control switching between the standby mode in which the oscillation operation of the oscillation circuit is stopped, and the semiconductor integrated circuit is configured, the operation mode control circuit in the standby mode, When the oscillation operation of the oscillation circuit is stopped and an event of transition from the standby mode to the normal mode is detected, the oscillation circuit is Together with resumes the oscillating operation, the clock generating circuit is operated in the free-running mode, then switch from the free-running mode to the multiplication mode.

  According to the above means, when returning from the standby mode to the normal mode, the self-running mode is first selected, and after the oscillation operation is stabilized for generating the reference clock using the oscillator by the oscillation circuit, the multiplication mode is set. Let them choose. Even when the reference clock signal is stopped in the standby mode, the clock signal in the free-running mode is generated before the oscillation operation of the oscillation circuit is stabilized. It can operate, and the return time from the standby state to the normal operation is shortened. In addition, in the standby mode, the oscillation operation of the oscillation circuit is stopped, so that power consumption is greatly reduced. This achieves a reduction in power consumption in the standby mode in the semiconductor integrated circuit that can quickly return from the standby mode to the normal mode.

  [2] An oscillation circuit that generates a reference clock signal using a vibrator, a free-running mode in which a clock signal having a predetermined pulse width is continuously generated by an internal logic circuit, and a frequency by multiplying the frequency of the reference clock signal A clock generation circuit having a multiplication mode for generating a signal, an internal circuit operable in synchronization with the clock signal generated by the clock generation circuit, and a normal mode in which the internal circuit operates in synchronization with the clock signal And an operation mode control circuit capable of controlling switching between a standby mode in which the oscillation operation of the oscillation circuit is stopped, and a serial communication interface circuit enabling serial communication between the internal circuit and the outside. When the semiconductor integrated circuit is configured, the operation mode control circuit controls the oscillation operation of the oscillation circuit in the standby mode. When the event that causes the serial communication interface circuit to transition from the standby mode to the normal mode is detected, the oscillation operation of the oscillation circuit is resumed and the clock generation circuit is operated in the free-running mode. Thereafter, the self-running mode is switched to the multiplication mode.

  According to the above means, when returning from the standby mode to the normal mode, the self-running mode is first selected, and the multiplication mode is selected after the oscillation operation in the multiplication mode is stabilized. Even when the reference clock signal is stopped in the standby mode, the clock signal in the free-running mode is generated before the oscillation operation of the oscillation circuit is stabilized. It can operate, and the return time from the standby state to the normal operation is shortened. In addition, in the standby mode, the oscillation operation of the oscillation circuit is stopped, so that power consumption is greatly reduced. This achieves a reduction in power consumption in the standby mode in the semiconductor integrated circuit that can quickly return from the standby mode to the normal mode.

  [3] In the above [1] and [2], the clock generation circuit is capable of realizing the pulse generation for the free-running mode and the pulse generation for the multiplication mode, and the operation According to the control of the mode control circuit, a selection circuit capable of selecting the pulse generation in the self-running mode and the pulse generation in the multiplication mode can be configured.

  [4] In the above [3], the semiconductor integrated circuit further includes a pulse width control circuit having a pulse width setting unit that determines a pulse width of a clock signal generated by the clock generation circuit, and the pulse width control circuit includes: The pulse width determined by the pulse width setting unit is set to be equal to the cycle of the reference clock signal by a value obtained by multiplying the clock cycle based on the pulse width determined by the pulse width setting unit by the multiplication number in the multiplication mode. Allows adjustment.

  [5] In the above [4], when the internal circuit includes a central processing unit that can operate in synchronization with the clock signal generated by the clock generation circuit, in response to an event of transition from the standby mode to the normal mode. Thus, an interrupt control circuit capable of executing interrupt control for the central processing unit can be provided.

  [6] A clock generation circuit for generating a clock signal, an internal circuit capable of operating in synchronization with the clock signal generated by the clock generation circuit, an oscillation circuit for generating a reference clock signal, and the internal circuit being connected to the reference signal A semiconductor integrated circuit includes an operation mode control circuit capable of controlling switching between a normal mode operated in synchronization with a clock signal and a standby mode in which the oscillation operation of the oscillation circuit is stopped, and a USB interface circuit The operation mode control circuit stops the oscillation operation of the oscillation circuit in the standby mode, and detects an event that causes the USB interface circuit to transition from the standby mode to the normal mode. The oscillation operation of the oscillation circuit is resumed and the clock generation circuit is operated in the free-running mode. To work, then, it is switched from the free-running mode to the multiplication mode.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to achieve a reduction in power consumption in the standby mode in the semiconductor integrated circuit that can quickly return from the standby mode to the normal mode.

  FIG. 1 shows a microcontroller as an example of a semiconductor integrated circuit (LSI) according to the present invention. The microcontroller 1 shown in FIG. 1 includes a clock generation circuit 10, an operation mode control circuit 20, an oscillation circuit 30, a CPU (central processing unit) 40, an interrupt control circuit 50, a pulse width control circuit 80, and a multiplication number setting circuit 90. Although it is not particularly limited, it is formed on one semiconductor substrate such as a single crystal silicon substrate.

  The clock generation circuit 10 generates a clock signal CLK1. The generated clock signal CLK1 is supplied to an internal circuit represented by the CPU 40 and the interrupt control circuit 50. Signals for notifying the occurrence of exceptions such as an interrupt signal and a reset signal to the microcontroller 1 are provided from outside the microcontroller 1 or are generated in another internal circuit, and interrupt control is performed in either case. It is input to the circuit 50 and controlled based on the mask and priority order for the interrupt. In this example, such an interrupt signal or reset signal is supplied to the operation mode control circuit 20 as a return request signal as shown in FIG. The operation mode control circuit 20 monitors the operation mode of the CPU 40 and controls the oscillation circuit 30. Even if the CPU 40 is about to enter the standby mode, if the clock is stopped before all the pipeline operations realizing the operation of the CPU 40 are completed, normal operation cannot be guaranteed, so the CPU 40 actually enters the standby state. It is desirable to stop the clock oscillation after confirming that this is the case with the CPU operation mode signal.

  The CPU 40 and the interrupt control circuit 50 are not necessarily essential components, and can be replaced by any circuit as long as the simple operation mode control circuit 20 is provided. Also, interrupts and resets are not necessarily used as return request signals, and may be limited to request signals from a circuit that generates a return request.

  The operation of the above configuration will be described below.

  When the activation signal is input, the clock generation circuit 10 outputs a clock pulse CLK1 having a width set by the pulse width setting unit 12 according to the operation mode. The operation modes include a free-running mode and a multiplication mode, and the operation will be described with reference to FIG.

  In the free-running mode, as shown in FIG. 2A, clock output is started in response to the level change of the activation signal STA. The clock cycle at this time is determined based on the value given by the pulse width setting unit 12. In contrast, in the multiplication mode, as shown in FIG. 2B, the reference clock signal CLK0 is input as the activation signal STA, and the multiplication number setting circuit 90 synchronizes with the rising edge of the reference clock signal CLK0. A clock pulse having the set number and the pulse width set by the pulse width setting unit 12 is output as the clock signal CLK1.

  In FIG. 3, the entire microcontroller 1 shifts from the normal mode to the standby mode, and in order to keep the power consumption during the standby to the minimum, the return request signal RET is also stopped in a state where the oscillation of the reference clock CLK0 is also stopped. In response to the change in, the transition from standby mode to normal mode is shown. In FIG. 3, the microcontroller 1 is initially in the normal mode, and the oscillation circuit 30 supplies the reference clock CLK0 to the clock generation circuit 10. The clock generation circuit 10 receives the reference clock CLK0 applied to the activation signal input STA. It operates by outputting a clock with a frequency four times that of the clock. At this time, the multiplication number is set to 4, and the pulse width setting unit 12 sets the pulse width of the output clock to 4 minutes that is just the reciprocal of the multiplication number 4 of the period of the reference clock applied to the activation signal input STA. It is adjusted to 1.

  In the standby mode of the microcontroller 1, not only stopping the supply of the reference clock signal CLK0 but also stopping the operation of the oscillation circuit 30 is indispensable for suppressing standby power consumption to the limit of the μW order. This is because the power consumption by the oscillation operation of the oscillation circuit 30 is as large as mW. Power consumption includes power consumption corresponding to signal changes and power consumed simply by applying a power supply voltage. In the CMOS circuit, the former is charge / discharge power, and the latter is power due to leakage current. The former can be made zero by eliminating the signal change in the microcontroller 1, and the latter can be made zero by turning off the power supply or by using the substrate bias effect to increase the threshold voltage of the transistor. By reducing the leakage current, a remarkable reduction effect can be obtained, and it can be sufficiently suppressed to 1 μA or less. In this example, there is no signal change during standby, and transient power typified by charge / discharge power in the CMOS circuit is made zero. In this example, during standby, the clock generation circuit 10 stops the clock output CLK1 because the reference signal input CLK0 stops. The operation mode control circuit 20 outputs the oscillation stop of the oscillation circuit 30 and causes the signal to be propagated to the start signal input terminal of the clock generation circuit 10 when there is a next return request by the return request signal RET. The selection circuit 21 is switched. The operation mode control circuit 20 switches the operation mode of the clock generation circuit 10 from the multiplication mode to the free-running mode. Since the oscillation circuit 30 is not operating when a return request is made by the return request signal RET, the reference clock signal CLK0 is not supplied, and the clock generation circuit 10 can resume its operation from the free-running mode. This is desirable.

  When there is a return request, the operation mode control circuit 20 detects it by the edge detection circuit 22, and cancels the oscillation stop by the oscillation control signal OCNT and starts the supply of the reference clock to the oscillation circuit 30. Control. The return request signal RET may be generated inside the microcontroller 1 or may be supplied from the outside. It is supplied as an interrupt signal or reset signal. Here, if the oscillation circuit 30 uses an external crystal resonator 31, the time until the reference clock signal is stably supplied is about the same as the startup time of the crystal oscillator of 3ms. The operation clock frequency of recent microcontrollers often exceeds 100 MHz, and 3 ms is a period corresponding to 300,000 clocks when converted to a clock cycle. During this period, the clock generation circuit 10 operates in the free-running mode, and continuously sends out a clock signal having a pulse width given by the pulse width setting unit 12. Therefore, the microcontroller 1 can start processing responding to the return request before the reference clock is stabilized. Thereafter, when the reference clock signal CLK0 starts to be stably supplied, the operation mode control circuit 20 performs control to return the operation mode of the clock generation circuit 10 to the multiplication mode. Strictly speaking, another time or frequency reference is necessary to detect that the oscillation circuit 30 performs a stable oscillation operation. However, in practice, a sufficient waiting time is provided with an appropriate margin. The oscillation is determined to be stable. The oscillation circuit 30 is different from the resonance frequency of the crystal unit 31 at the time of starting oscillation. Therefore, the oscillation circuit 30 outputs a clock signal having an unpredictable frequency, gradually approaches the target frequency, and eventually reaches the resonance frequency of the crystal unit 31. Stable oscillation. Even if it is different from the target oscillation frequency, the clock signal is actually stable if the oscillation of the reference clock is treated as stable after waiting for a sufficient number of clock pulses. A point in time can be indicated. For example, when the startup time is 3 ms max with a 10 MHz crystal resonator, 3 ms ÷ 1/10 MHz = 30000. Therefore, if the crystal oscillation clock is counted with a counter of 60000 to 100,000 with a margin of 2 to 3 times, It is possible to determine when the oscillation is stabilized by sufficiently guaranteeing the passage of time of 3 ms or more.

  When the reset signal RST is used as a return request signal, another effect can be expected. That is, when the reset is a power-on reset and is a reset immediately after the power is turned on, the clock is often not supplied at the time of reset. On the other hand, when past design resources are reused or introduced from the outside, many adopt a so-called synchronous reset method that expects a clock to be supplied during reset. The synchronous reset circuit expects more than a certain number of clock pulses until the reset information is confirmed, and in the indeterminate state until the reset information, the microcontroller may be caused by signal collision or the presence of a floating node. There is a possibility of causing a through current in other circuits in the circuit 1. In the microcontroller 1 that employs the conventional clock generation circuit, there are cases in which this state is unavoidable for several milliseconds until the clock oscillation is stabilized, which has been a bottleneck for adoption in portable devices. According to this example, since the clock signal can be supplied immediately after detecting the reset signal, the clock signal is supplied immediately after the power is turned on even if a synchronous reset method circuit is adopted to solve such a problem. Thus, the entire circuit can be reset in the shortest time.

  In the case shown in FIG. 3, the multiplication number is changed in an example where the standby mode is the multiplication mode of the multiplication number 4 and the standby mode is switched from the free-running mode to the multiplication mode of the multiplication number 2 after the standby. The pulse width in the normal mode before entering the standby state is different from the pulse width when returning from the standby state. When the pulse width in the normal mode before entering the standby state is the maximum operating frequency as the circuit operation of the microcontroller 1, and the pulse width cannot be faithfully reproduced without the reference clock signal at the time of return. For this reason, it is effective to change the setting of the pulse width longer as a safety measure. For example, before entering the standby state, the temperature is high during operation at the maximum frequency, while the temperature of the microcontroller 1 decreases during standby, and the pulse width setting unit 12 Therefore, there is a possibility that a clock having a shorter pulse width is supplied and a malfunction occurs in the microcontroller 1 to which the clock signal is supplied. At this time, the pulse width setting is lengthened in consideration of the shortening of the clock pulse width due to the temperature drop. However, if the multiplication number is 4, the value obtained by multiplying the pulse width by the multiplication number 4 is the period of the reference clock. Since it becomes longer and the multiplication operation is not performed, it is necessary to reduce the multiplication number as appropriate. On the other hand, the pulse generation circuit 11 is provided with a temperature compensation circuit, a means for compensating for the influence of power supply voltage fluctuation, and the like, so that the clock output of the same frequency can be obtained with the same pulse width and the same multiplier setting before and after the standby mode. If so, it is more preferable.

  After the reference clock signal CLK0 stabilizes and shifts to the multiplication mode of the multiplication number 2, the pulse width control circuit 80 is operated so as to coincide with the cycle of the reference clock when the multiplication number is 4, and the pulse width is gradually increased. You may perform control to shorten. For example, when operating at a multiplication factor of 2, two clock pulses are output corresponding to the rising edge of the reference clock CLK0. At this time, the fourth and fifth clock pulses are generated in the clock generation circuit 10. The pulse width value is gradually changed so that the period from the rising edge of the first clock pulse synchronized with the rising edge of the reference clock signal CLK0 to the rising edge of the fifth clock pulse matches the cycle of the reference clock pulse. You can reduce it to. Finally, if the period from the first to the fifth output clock pulse rises below the cycle of the reference clock signal CLK0, it is possible to return to the multiplication operation of the multiplication number 4.

  When a return is requested by the return request RET as described above, first, the clock output is started in the free-running mode, so that the operation clock can be supplied with a delay of only the gate delay from the return request signal RET. Without waiting for the oscillation of the circuit 30 to stabilize, the processing when returning from the standby mode to the normal mode can be started immediately. While the clock stabilization time is on the order of ms, the gate delay is on the order of ns, and a waiting time reduction of about 6 digits can be realized. Incidentally, in the prior art, the clock oscillation is continued during standby, and a method of returning to normal operation by a method of shortening the synchronization time of the multiplier circuit such as PLL is used. In this case, the recovery time is on the order of μs. . In the present invention, it is possible to return to normal operation in a shorter period of ns order while stopping clock oscillation during standby. Therefore, even in a system in which some processing must be performed in a very short period when returning from the standby state, clock oscillation can be stopped during standby. That is, it is possible to suppress power consumption to the utmost with no immediate return from the standby state and no signal change during the standby period.

  FIG. 4 shows a configuration example of the pulse generation circuit 11, and FIG. 5 shows an operation timing in the configuration shown in FIG.

  As shown in FIG. 4, the pulse generation circuit 11 includes a set / reset flip-flop circuit 101, an edge detection circuit 102, a counter 103, a comparison circuit 104, a variable delay line 105, NAND gates 106 and 108, and a delay element 107. The set-reset flip-flop circuit 101 detects the activation signal STA when set by the activation signal STA. The output signal of the set / reset flip-flop circuit 101 is transmitted to the subsequent edge detection circuit 102. The edge detection circuit 102 performs edge detection of the input signal. The edge detection result is transmitted to the counter 103 at the subsequent stage. The counter 103 counts the output signal of the variable delay line 105, and the count result is reset by the output signal of the edge detection circuit 102. The output signal count of the counter 103 is transmitted to the comparison circuit 104 at the subsequent stage. The comparison circuit 104 compares the output signal count of the counter 103 with the multiplication number. The comparison result eq is transmitted to the set / reset flip-flop circuit 101 via the selection circuit 13, and the set / reset flip-flop circuit 101 is reset by the comparison result eq. The amount of delay in the variable delay line 105 is controlled by the pulse width setting unit 12. The NAND gate 106 obtains a NAND logic between the output signal dck of the variable delay line 105 and the output signal of the set / reset flip-flop circuit 101. The output signal nck of the NAND gate 106 is fed back to the variable delay line 105 and transmitted to the NAND gate 108 and the delay element 107. The NAND gate 108 obtains a NAND logic between the output signal nck of the NAND gate 106 and the output signal of the delay element 107. The output signal of the NAND gate 108 is the clock signal CLK1.

  When the output Q of the set-reset flip-flop circuit 101 is a logical value “1”, the output signal dck of the variable delay line 105 is inverted and nck is fed back. However, when the output Q of the set-reset flip-flop circuit 101 is the logical value “0”, nck is fixed to the logical value “1” and is not fed back. The edge detection 102 detects that the output Q of the set-reset flip-flop circuit 101 has been set from the logical value “0” to the logical value “1”, resets the counter 103, and determines the number of occurrences of the delay clock dck. When counted by the counter 103 and coincides with a desired multiplication number, the comparison circuit 104 outputs a coincidence signal eq. The coincidence signal eq resets the set / reset flip-flop circuit 101 in the multiplication mode. As a result, feedback from the NAND gate 106 to the variable delay line 105 is stopped, the output of the clock pulse is stopped, and the input of the next start signal STA is awaited.

  FIG. 5 shows an operation example in the free-running mode and the multiplication mode in the clock generation circuit 10 shown in FIG. The multiplication number is 3, and the gate delay is exaggerated from the actual size. The free-running mode shown in FIG. 4A can be designated by setting the mode designation signal to a logical value “0”, and the set-reset flip-flop circuit 101 is set by changing the activation signal input. Since it is not reset later, the clock generation circuit 10 continues to generate clocks continuously. When the clock generation is stopped in the free-running mode, the set / reset flip-flop may be reset as described above. The multiplication mode shown in FIG. 4B can be designated by setting the mode designation signal to a logical value “1”. When the counter 103 counts the number of occurrences of the output dck of the variable delay line 105 and the value matches the predetermined multiplication number 3, the coincidence signal eq becomes the logical value “1”. Since the mode designation signal is the logical value “1”, the coincidence signal eq is propagated to reset the set / reset flip-flop circuit 101 and forcibly set the output nck of the NAND gate 106 to the logical value “1” to the variable delay line 105. Stop feedback. However, as shown in FIG. 5B, since the output nck of the NAND gate 106 is forcibly changed from the logical value “0” to the logical value “1”, a narrow pulse is generated. This pulse also appears at the output of the variable delay line 105 and increases the output of the counter 103 by 1 and changes it to 4. At this time, the counter output count does not coincide with the predetermined multiplication number 3, and the coincidence signal eq becomes the logical value “0”. The period from when the set-reset flip-flop circuit 101 is set to when it is reset, that is, the period during which the output Q of the set-reset flip-flop circuit 101 is the logical value “1” is three clock pulses. This signal is output as an oscillation period signal. As described above, a narrow pulse is generated in the output nck of the NAND gate 106, and it is not preferable to use it as it is as a clock of the external circuit. The delay element 107 and the NAND gate 108 are combined to erase a narrow pulse and output it as a clock. The delay amount of the delay element 107 is set larger than the width of the pulse to be erased.

  The oscillation period signal CYC is a signal having a high level period obtained by multiplying the clock pulse period by a multiple and a low level period of the rest period. If the period of the inputted reference clock signal is controlled to be the same as the high level period, in other words, if the period of the low level is controlled to be as short as possible, the period of the clock output is the same as that of the reference clock signal. It becomes 1 / multiple of the cycle, and it becomes an accurate multiplier circuit. On the other hand, the remaining low level period is clock jitter generated in the cycle of the reference clock signal. Even if there is jitter in the operation clock, the microcontroller 1 operates normally if the shortest cycle is equal to or greater than the maximum delay (critical path) of the microcontroller 1. However, some circuits that require synchronization with other devices, such as peripheral circuits, do not allow jitter. In that case, as described above, a clock signal without jitter can be generated by controlling and appropriately controlling the clock pulse width.

  FIG. 6 shows a configuration example of the variable delay line 105 in the clock generation circuit 10. The variable delay line 105 can be controlled by a digital signal, and is designed so that no through current flows. The variable delay line 105 suppresses the current consumption to only the leakage current of the device when the clock output is stopped. In addition, since the delay amount may be stored in a register or the like as a digital value, it does not change with time. In the variable delay line shown in FIG. 6, the delay amount is designated by a 3-bit digital value dly. In order to limit the current for delaying the signal, p-channel MOS transistors Tdp1 to Tdp8 are connected to the power supply Vcc side, and n-channel MOS transistors Tdn1 to Tdn8 are connected to the ground Vss side, and the former stage composed of Tip1 and Tin1 Tdp1 to Tdp4 and Tdn1 to Tdn4 are connected to this inverter, and Tdp5 to Tdp8 and Tdn5 to Tdn8 are connected to the subsequent inverter composed of Tip2 and Tin2, respectively. The p-channel MOS transistors Tdp1 and Tdp5, Tdp2 and Tdp6, and Tdp3 and Tdp7 for current limitation have the same size, and are a power of 2 of the reference gate width / gate length ratio Wp0 / Lp0, 4Wp0 / The sizes are Lp0, 2Wp0 / Lp0, and Wp0 / Lp0. Tdp4 and Tdp8 have a gate width / gate length ratio Wp1 / Lp1. Similarly, the p-channel MOS transistors for current limiting have the same size, Tdn1 and Tdn5, Tdn2 and Tdn6, Tdn3 and Tdn7, and Tdn4 and Tdn8, respectively. Lp0 and Wn1 / Ln1.

  The delay amount dly includes dly [2], dly [1], and dly [0] in order from the most significant bit to current limiting n-channel MOS transistors Tdn1 and Tdn5, Tdn2 and Tdn6, and Tdn3 and Tdn7, respectively. Inverted signals are respectively connected to the current limiting p-channel MOS transistors Tdp1 and Tdp5, Tdp2 and Tdp6, and Tdp3 and Tdp7. Since these current limiting MOS transistors have a power size of 2 of the reference sizes Wn0 / Ln0 and Wp0 / Lp0, the current limiting is proportional to the delay amount dly expressed in a 3-bit binary number. It can be carried out. Tdp4 and Tdp8, and Tdn4 and Tdn8 are current limiting transistors that determine a delay amount that is not controlled by the delay amount dly. When adding or subtracting the delay amount dly to control the clock frequency, etc., the delay amount dly is zero because the dly value becomes zero and the clock output cannot be recovered when it is stopped. In this case, the minimum oscillation frequency can be guaranteed so that the clock output does not stop.

The variable delay line in this example changes the current supply capability by digitally turning on and off the current limiting MOS transistor, and is a steady current in a current mirror circuit frequently used in a voltage-controlled oscillation circuit of a PLL. Therefore, unless a pulse is input from the input terminal, no transition current and through current other than the junction leakage current of the transistor are consumed. Therefore, the current consumption during standby can be suppressed to a level much smaller than 1 μA. A minute transistor constituting the internal circuit has a remarkable junction leakage, but a transistor having a relatively high breakdown voltage and threshold voltage used in the input / output circuit has a junction leakage on the order of pA / cm ² . By using these high voltage transistors, the leakage current can be suppressed to almost zero. Since the delay amount is digitally stored in the register, the held value does not change with the passage of time. On the other hand, an analog method that is frequently used in a voltage-controlled oscillation circuit of a PLL, in which a control voltage is stored in a capacitor and controlled by a charge pump, the accumulated charge for storing the oscillation frequency etc. It is difficult to keep such information while waiting because it is lost. It is possible to return to the same state as just before the clock is stopped by entering the standby mode. The operating environment such as temperature and power supply voltage changes at the time of starting the standby mode and at the time of return, and the oscillation frequency may be different even with the same set value. In this example, temperature compensation and stabilization of the power supply voltage are omitted, but if these technologies are used together, it is possible to avoid fluctuations in the clock frequency due to changes in the operating environment before and after the standby mode. .

  In this example, a circuit for controlling the delay amount control with 3 bits and 8 gradations is illustrated, but control is performed so that the clock pulse width is accurately adjusted to 1 / multiple of the cycle of the reference clock signal CLK0. In this case, it is effective to increase the number of bits to make the gradation finer. Further, in this example, only an example in which the same circuit is used in the former stage and the latter stage is shown, but it may be changed as appropriate. If the delay amount of the front stage and the rear stage can be controlled independently, the duty of the clock signal can be adjusted.

  In addition, Tdp4 and Tdp8, and Tdn4 and Tdn8 determine the delay amount that is not controlled by the delay amount dly, and an example of a fixed value is shown. However, this is controlled by increasing or decreasing the delay amount using another register. You may be able to. At this time, the inclination can be controlled by dly and the intercept can be controlled by the other register, thereby enabling precise control with a higher degree of freedom.

  In this example, the method of controlling the number of pulses generated using a variable delay line and a counter has been described, but many circuits that realize the same function are conceivable. For example, a circuit configuration in which the number of variable delay lines corresponding to the maximum number of pulses to be generated is appropriately masked can be considered. Although the circuit scale increases, it is effective when the control is simple and is incorporated in a complicated control system.

  In the case of a microcontroller that does not require accuracy in the clock frequency, it is sufficient to realize only the free-running mode. At that time, the activation signal inputs a power-on reset. Since it is not necessary to provide a clock oscillation source, it is possible to realize an inexpensive control system that consumes very little power.

  In the microcontroller equipped with the clock generation circuit 10 having only the free-running mode, the function of stopping the clock signal in the standby mode can be realized. In that case, a signal indicating that the microcontroller has entered the standby mode is input to the reset terminal R of the set-reset flip-flop circuit 101, and an interrupt signal and a return time in addition to the reset signal are input to the start signal. Input the return request signal from the set timer. The clock generation circuit 10 of this example has a very short waiting time until the clock is generated, and can be designed to be much shorter than one cycle of the operation clock as shown in the timing chart of FIG. In the input microcontroller, even if the clock is stopped in the standby state, interrupt processing can be started immediately without waiting for the clock oscillation to stabilize after the return request is generated. It is possible to achieve both a reduction in power consumption and an immediate return process.

  FIG. 7 shows another configuration example of the microcontroller 1.

  The microcomputer 1 shown in FIG. 7 is greatly different from that shown in FIG. 1 in that a serial communication interface circuit 60 is included. The serial communication interface circuit 60 is coupled to the CPU 40 via the bus BUS and enables serial communication under the control of the CPU 40. The serial communication interface circuit 60 includes a start bit detection circuit 61 for detecting a start bit from a captured serial signal, a clock generation circuit 610 for generating a clock signal, a latch circuit 62 capable of latching data, serial data Includes a serial / parallel conversion circuit (S / P conversion circuit) 63 capable of converting data into parallel data, a FIFO (First In First Out) 64 serving as a first-in first-out buffer, and a start command detection circuit 65 capable of detecting a start command. It consists of

  A start bit is detected by the start bit detection circuit 61, and a start signal STA2 of the clock generation circuit 610 is formed based on the detection result. The serial signal is taken into the latch circuit 62, converted into parallel data by the serial / parallel conversion circuit 63, and stored in the FIFO 64. A series of these operations are performed in synchronization with the clock signal CLK2 generated by the clock generation circuit 610.

  The clock generation circuit 10 is a circuit different from the clock generation circuit 610 provided in the serial communication interface circuit 60. The clock generation circuits 10 and 610 employ the configuration shown in FIG. As described above, when the clock oscillation to the CPU 40 is completely stopped during standby, a circuit for returning the CPU 40 in the standby mode when receiving a command can be configured by serial communication. The parallel data obtained by the serial / parallel conversion circuit 63 is analyzed to detect a start command, and is connected to the interrupt circuit as an interrupt signal, and is also connected as a clock start signal of the clock oscillation circuit 30. In this example, the start command detection circuit 65 detects a predetermined start command, and based on this, restarts clock oscillation and can generate an interrupt.

  On the other hand, when a serial signal is input during the standby mode without negotiating the start command, it is effective to return to the normal mode unconditionally. In that case, the signal detected by the start bit detection circuit 61 may be the oscillation control signal OCNT of the clock oscillation circuit 30 or the interrupt signal INT. During normal operation, if it is not desired to detect the start bit every time a serial signal is received and generate an interrupt, the interrupt is masked by return processing from standby mode, and before transitioning to standby mode again. It is recommended to cancel the interrupt mask by processing.

  FIG. 8 shows a data format of asynchronous serial communication as an example of the serial signal. The initial state without communication is a high level, and a low level of 1 bit is transmitted as a start bit. This is followed by data bits, parity bits, and stop bits. The detailed format is set in advance before starting communication. The length of the data bit is set to 7 bits or 8 bits. The parity bit sets whether to add even parity, odd parity, or no parity bit. The stop bit defines a minimum high level period until the start bit of the next frame arrives, and is set from 1 bit to 2 bits. A frame from the start bit to the stop bit is called one frame.

  FIG. 9 shows the operation timing when the serial signal shown in FIG. 8 is received.

  When the start bit detection circuit 61 detects that the start bit of the serial signal has been received, the start bit detection circuit 61 sets the start signal STA2 to a high level. The clock generation circuit 610 starts clock generation in response to the activation signal STA2 becoming high. The operation of the clock generation circuit 610 is a multiplication mode shown in FIG. The multiplication number is set to 10 bits so as to receive a start bit of 1 bit, data of 8 bits, and parity bit of 1 bit. As described with reference to FIG. 8, the data bits may be 7 bits, and the parity bit may not be added. Therefore, the multiplication number is appropriately set according to the format. The delay amount given by the pulse width setting unit 12 is set based on the cycle per bit obtained from the baud rate of serial communication. For example, if the baud rate is 9600 bps, the 1-bit period is 1/9600 [s] = 0.104 [ms], and the delay amount is set to 0.052 [ms], which is half of that. The clock generation circuit 610 counts the number of clock pulses generated by the internal counter 103 shown in FIG. 4, and when the multiplication number is reached, the clock generation is stopped. At this time, the start bit detection circuit 61 is also reset. The start bit detection circuit 61 is realized by a circuit that detects a change in the serial signal from a high level to a low level. However, the same change may be sufficiently present in the data, so that the clock generation circuit erroneously changes the change. The activation signal is configured to remain high during one frame so that the activation signal of 610 is not used. By resetting at the end of one frame, it is guaranteed that the low level signal received next is always a start bit. The generated clock is synchronized with the received serial signal, but the delay amount set in the pulse width setting unit 12 does not always correspond to the baud rate of the serial signal. For this, an inverted signal of the generated clock is used. FIG. 7 shows an example in which operation is performed using an inverted clock from the S / P conversion circuit 63 to the FIFO 64 in the subsequent stage. According to this example, the serial communication reception clock starts to be generated only after receiving the start bit and stops upon completion of frame reception, so it is sufficient to supply the minimum necessary clock pulses, reducing power consumption. can do. Especially when waiting, it was necessary to continue to supply the clock signal constantly to wait for the reception of the start bit, but even if this is stopped completely, the clock supply can be restarted from the moment the start bit is received, The power consumption during standby can be reduced to zero, and the effect of reducing standby power is significantly great.

  As described above, the delay amount given by the pulse width setting unit 12 is set based on the cycle per bit obtained from the baud rate of serial communication. However, the operating temperature and the power supply voltage are different from those assumed, or the communication partner The baud rate may include an error, and data cannot always be captured at an ideal timing. The center of the next change point from the change point of the serial signal is the ideal data capture timing. In FIG. 10, the delay amount set by the pulse width setting unit 12 is less than ideal and the clock cycle is short. The case is illustrated. Unlike the PLL and the like, the clock generation circuit 610 of this example does not have a feedback unit that reduces the error, so that the error gradually accumulates. However, error accumulation is limited to the period of one frame and is reset when the next start bit is detected. Normally, in asynchronous serial communication as in this example, the frame length is 10 bits at most, so the accumulation of errors between the ideal data capture timings 201 to 213 and the actual data capture timings 301 to 313 is not large. It is possible to avoid such a large shift that the target bit cannot be taken in by appropriately setting the pulse width.

  In order to realize the ideal data capture timings 201 to 213, a pulse width control circuit 80 as shown in FIG. 1 is further provided, and by performing a pull-in operation in accordance with the reference clock, the received serial signal is converted into a received serial signal. It becomes possible to obtain a completely synchronized clock signal. The reference clock signal CLK0 may be input from the outside or generated by including an oscillation circuit inside. Further, it may be generated based on the output clock of the clock oscillation circuit 30 for supplying a clock signal to the CPU 40. In the initialization operation, it is effective to obtain a value to be set in the pulse width setting unit 12 by performing a pull-in operation when performing baud rate matching with the communication partner. With respect to fluctuations in the operating environment, it is possible to follow by performing a pull-in operation as appropriate.

  In this example, the clock for receiving 1-bit serial data has been described as a pulse, but so-called oversampling in which data is taken in multiple times per bit can also be applied. In that case, it is only necessary to set the multiplication number to the oversampling multiple and simultaneously reduce the pulse width set by the pulse width setting unit 12 to 1 / oversampling number. By performing oversampling, it is possible to realize a circuit configuration that can remedy even if the sampling point is shifted to a bit other than the target bit due to the accumulation of the error of the data fetch timing described above.

  FIG. 11 shows another configuration example of the microcontroller 1. The circuit shown in FIG. 11 is greatly different from that shown in FIG. 7 in that a USB (Universal Serial Bus) interface 70 is provided instead of the serial communication interface 60. The microcontroller 1 in this example is basically realized based on the configuration shown in FIG. 7, but includes a differential amplification circuit 72, a suspend return detection circuit 71, a clock transmission stability determination circuit 77 as a configuration block unique to USB. A clock transmission circuit 78 is provided. Since USB communicates with complementary signals called D + and D−, it receives using the differential amplifier circuit 72. Communication is performed between devices in a master-slave relationship called a host and a function. For example, a personal computer has a host function, and a USB device having a function function can be connected. When there is no need for communication, the USB function device can be placed in a standby state called “suspend” to suppress power consumption as a system. This example is suitable for a function device because power consumption in a standby state can be suppressed. The USB suspend state is defined in a special state such as D + and D−, which should be complementary and should always take the opposite logic levels, both have the same logic level. By monitoring the states of D + and D−, A return from the suspended state can be detected. In order to maintain communication quality, the accuracy of the clock frequency is defined by the standard. Taking the data rate mode called full speed of 12 Mbps, which is the most widely used, as an example, the USB function clock is required to have an accuracy of 2500 ppm. In this example, in order to realize this clock accuracy, a clock oscillation circuit 78 that oscillates by a crystal resonator is provided separately from the clock generation circuit 710. Further, a clock oscillation stability determination circuit 77 is provided for determining whether or not the oscillation in the clock oscillation circuit 78 is stable.

  When the suspend return detection circuit 71 detects that a suspend return request has been given, it immediately starts clock output from the clock generation circuit 710, receives the transmitted data, and stores it in a buffer such as the FIFO 64. Accumulate sequentially. In parallel with this, the clock oscillation circuit 78 is controlled to start the clock oscillation operation. Since the clock oscillation stabilizes in a few ms, the supplied clock is switched after detecting the stability.

  A USB function device has its own power supply. Some of them receive power supply from the host, and the former is called self-powered and the latter is called bus-powered. In the case of a bus-powered device, the power allowed to be consumed in the suspended state is limited to 500 μA or less. Therefore, it is very important to stop the clock oscillation in the suspended state. On the other hand, strict regulations are also provided regarding the time constraint from the receipt of a return request from suspend until the response to the host. According to this example, the clock oscillation can be stopped during standby, that is, during suspend, so that power consumption can be reduced to almost zero, and the clock supply is resumed immediately upon return from suspend. You can respond as quickly as you would.

  In this example, in order to satisfy the clock accuracy defined by the USB standard, an example in which a clock oscillation circuit 78 is separately provided is shown. The clock generation circuit 710 can be provided with a reference power supply that is not affected by fluctuations in the power supply voltage, and a temperature compensation circuit can be provided to improve the setting accuracy of the pulse width by the pulse width setting unit 12 and satisfy the standard. . In this case, the clock generation circuit 710 is operated in the free-running mode. Therefore, the circuit necessary for the multiplication mode may be deleted from the clock generation circuit 10 shown in FIG. Further, in the case where the clock oscillation circuit 30 is provided for supplying the clock of the CPU 40, the operation is performed in the free-running mode for the return from the suspend, and after the operation of the clock oscillation circuit 30 of the CPU 40 is stabilized, It is also possible to switch to the multiplication mode based on the clock. Further, timing information, that is, bit rate information may be extracted from a USB signal received from the host, and a pull-in operation may be performed on the timing information.

  The clock oscillation circuit 30 that supplies a clock to the CPU 40 and the USB clock oscillation circuit 78 can be shared. In this case, when either one of them has a return request signal, control is performed so that the oscillation operation is resumed, and the oscillation may be stopped after both oscillations become unnecessary. By sharing, not only the circuit scale can be reduced, but also an external crystal resonator can be saved, and power consumption can be reduced.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, the polarity of the signal, the number of bits, and the setting of the multiplication number are not limited to the above embodiment. In addition, the clock generation circuit is not limited to supplying a clock only to a circuit such as a CPU on the same chip, and even if it is supplied to other LSIs constituting the system, the entire system The same effect is obtained.

  In the above description, the case where the invention made by the present inventor is applied to a microcontroller, which is the field of use behind it, has been described. However, the present invention is not limited to this and is widely applied to various semiconductor integrated circuits. Can be applied.

  The present invention can be applied on condition that at least a clock generation circuit for generating a clock signal is included.

1 is a block diagram illustrating a configuration example of a microcontroller as an example of a semiconductor integrated circuit according to the present invention. It is an operation | movement timing diagram of the principal part in the said microcontroller. It is an operation | movement timing diagram of the principal part in the said microcontroller. FIG. 2 is a circuit diagram illustrating a configuration example of a main part in the microcontroller. FIG. 5 is an operation timing chart of the circuit shown in FIG. 4. FIG. 2 is a circuit diagram illustrating a configuration example of a main part in the microcontroller. It is another example block diagram of a configuration of the microcontroller. FIG. 8 is an operation timing chart of main parts in the microcontroller shown in FIG. 7. FIG. 8 is an operation timing chart of main parts in the microcontroller shown in FIG. 7. FIG. 8 is an operation timing chart of main parts in the microcontroller shown in FIG. 7. It is another example block diagram of a configuration of the microcontroller.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Microcontroller 10 Clock generation circuit 11 Pulse generation circuit 12 Pulse width setting part 13 Mode selection circuit 20 Operation mode control circuit 21 Selection circuit 22 Edge detection circuit 30 Oscillation circuit 40 CPU
50 interrupt control circuit 60 serial communication interface circuit 61 start bit detection circuit 62 latch circuit 63 serial / parallel conversion circuit 64 FIFO
65 Startup command detection circuit 610 Clock generation circuit 70 USB interface circuit 71 Suspend return detection circuit 72 Differential amplifier circuit 76 Startup command detection circuit 77 Clock oscillation stability determination circuit 78 Clock oscillation circuit 710 Clock generation circuit

Claims (5)

An oscillation circuit that generates a reference clock signal using an oscillator;
A clock generation circuit having a free-running mode for continuously generating a clock signal having a predetermined pulse width by an internal logic circuit, and a multiplication mode for generating a clock signal by multiplying the frequency of the reference clock signal;
An internal circuit capable of operating synchronously with the clock signal generated by the clock generation circuit;
An operation mode control circuit capable of controlling switching between a normal mode in which the internal circuit is operated in synchronization with the clock signal and a standby mode in which the oscillation operation of the oscillation circuit is stopped,
In the standby mode, the operation mode control circuit stops the oscillation operation of the oscillation circuit and restarts the oscillation operation of the oscillation circuit when detecting an event of transition from the standby mode to the normal mode. A semiconductor integrated circuit which operates the clock generation circuit in the free-running mode and then switches from the free-running mode to the multiplication mode. An oscillation circuit that generates a reference clock signal using an oscillator;
A clock generation circuit having a free-running mode for continuously generating a clock signal having a predetermined pulse width by an internal logic circuit, and a multiplication mode for generating a clock signal by multiplying the frequency of the reference clock signal;
An internal circuit capable of operating synchronously with the clock signal generated by the clock generation circuit;
An operation mode control circuit capable of controlling switching between a normal mode in which the internal circuit is operated in synchronization with the clock signal and a standby mode in which the oscillation operation of the oscillation circuit is stopped;
A serial communication interface circuit that enables serial communication between the internal circuit and the outside,
The operation mode control circuit stops the oscillation operation of the oscillation circuit in the standby mode, and detects an event of transition from the standby mode to the normal mode in the serial communication interface circuit. A semiconductor integrated circuit which restarts the oscillation operation, operates the clock generation circuit in the free-running mode, and then switches from the free-running mode to the multiplication mode. The clock generation circuit is capable of realizing pulse generation for the free-running mode and pulse generation for the multiplication mode;
3. The semiconductor integrated circuit according to claim 1, further comprising a selection circuit capable of selecting pulse generation in the free-running mode and pulse generation in the multiplication mode in accordance with control of the operation mode control circuit. The semiconductor integrated circuit further includes a pulse width control circuit having a pulse width setting unit that determines a pulse width of a clock signal generated by the clock generation circuit,
The pulse width control circuit determines the pulse width setting unit so that a value obtained by multiplying the clock cycle based on the pulse width determined by the pulse width setting unit by the multiplication number in the multiplication mode matches the cycle of the reference clock signal. 4. The semiconductor integrated circuit according to claim 3, wherein said pulse width can be adjusted. When the internal circuit includes a central processing unit that can operate synchronously with the clock signal generated by the clock generation circuit, interrupt control for the central processing unit is performed in response to an event of transition from the standby mode to the normal mode. 5. The semiconductor integrated circuit according to claim 4, further comprising an executable interrupt control circuit.

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