JP2006270621A - Solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device, capable of suppressing FPN which is generated in a picture signal, by reducing the variations in the characteristics of a readout circuit. <P>SOLUTION: When a picture signal is outputted from an output signal line 4, MOS transistors T10, T14 are turned on, and a voltage signal, corresponding to the image signal is sampled and held in a capacitor C1. When noise signal is outputted from the signal line 4, MOS transistors T11, T15 are turned on, and a voltage signal, corresponding to the noise signal, are sampled and held in a capacitor C2. MOS transistors T16, T17 are turned on, and the image signal and the noise signal appearing at the sources of MOS transistors T12, T13 are outputted to a correction circuit 6. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device that outputs an electrical signal corresponding to the amount of incident light, and more particularly, to a solid-state imaging device including a CDS (Correlated Double Sampling) circuit that removes sensitivity variations among pixels.

  Conventionally used solid-state imaging devices are roughly classified into a CCD type and a CMOS type by means for reading out photoelectric charges generated by a photoelectric conversion element. The CCD type transfers photocharges while accumulating them in the potential well, and the CMOS type reads out the charges accumulated in the pn junction capacitance of the photodiode through a MOS transistor. For the CMOS type solid-state imaging device, the applicant can switch between a solid-state imaging device configured to perform a logarithmic conversion operation and a linear conversion operation and a logarithmic conversion operation in order to widen the dynamic range. A solid-state imaging device has been proposed (see Patent Document 1 and Patent Document 2).

  Such a solid-state imaging device samples an image signal output from each pixel arranged in the same row as a voltage signal for each row and outputs the sampled image signal for one row to the outside of the device for each column. A CDS circuit is provided. That is, in the CDS circuit, an image signal from one row of pixels is read and sampled, and a noise signal indicating sensitivity variation of each pixel of one row is read and sampled. The sampled image signal and noise signal are read out for each pixel, and the image signal from which noise has been removed is output to the outside of the apparatus.

  FIG. 1 shows a general configuration of a solid-state imaging device including such a CDS circuit. The solid-state imaging device of FIG. 1 includes pixels G11 to Gmn arranged in a matrix (matrix arrangement), and the vertical scanning circuit 1 gives signals to the pixels G11 to Gmn through rows (lines) 3-1 to 3-n. Thus, scanning is sequentially performed in the vertical direction. Further, by driving the readout circuits 5-1 to 5-m by the horizontal scanning circuit 2, the photoelectric conversion signals derived from the pixels to the output signal lines 4-1 to 4-m are sequentially arranged in the horizontal direction for each pixel. read out. Since each of the output signal lines 4-1 to 4-m is connected to a constant current load by MOS transistors Q1 to Qm to which constant DC voltages VD and VSS are applied to the gate and the source, respectively, the pixel G11 The photoelectric conversion signals from .about.Gmn are output as voltage signals.

  In the readout circuits 5-1 to 5-m, image signals (electrical signals including imaging information and noise components) and noise signals (electrical signals including noise components) output from each pixel in one row are output. Is sampled and held. Thereafter, the reading circuits 5-1 to 5-m sequentially send the sampled and held image signals and noise signals to the correction circuit 6. Thus, in the correction circuit 6, when an image signal is given from the readout circuit 5-a (a: a natural number of 1 ≦ a ≦ m), the noise signal given from the readout circuit 5-a is applied to the image signal. Based on the correction processing, the image signal from which noise has been removed is output to the outside. At this time, a CDS circuit is constituted by the read circuits 5-1 to 5-m and the correction circuit 6.

  In the solid-state imaging device of FIG. 1, the conventional readout circuit 5 (corresponding to readout circuits 5-1 to 5-m in FIG. 1) is replaced with an output signal line 4 (output signal line 4 in FIG. 1) as shown in FIG. MOS transistors T10, T11 whose drains are connected to (-1 to 4-m), capacitors C10, C11 having one ends connected to the sources of the MOS transistors T10, T11, and MOS transistors T10, T11, respectively. MOS transistors T102 and T103 having gates connected to the sources, and MOS transistors T16 and T17 having drains connected to the sources of the MOS transistors T102 and T103, respectively.

  Further, the DC voltage VDD is applied to the drains of the MOS transistors T102 and T103, and the DC voltage VSS is applied to the other ends of the capacitors C10 and C11. Then, signals φVs and φVn are applied to the gates of the MOS transistors T10 and T11, and a signal φH is applied to the gates of the MOS transistors T16 and T17. Signals φVs and φVn are supplied from the vertical scanning circuit 1 and a signal φH is supplied from the horizontal scanning circuit 2. At this time, the signal φH is applied to each column, and the signals φH1 to φHm are applied to the MOS transistors T16 and T17 provided in the read circuits 5-1 to 5-m, respectively.

  The correction circuit 6 includes MOS transistors T20 and T21 whose drains are connected to the sources of the MOS transistors T16 and T17 provided in the readout circuits 5-1 to 5-m, respectively, and an inverting input terminal at the drain of the MOS transistor T20. And a differential amplifier 60 having a non-inverting input terminal connected to the drain of the MOS transistor T21. In this correction circuit 6, DC voltages VD and VSS are applied to the gates and sources of the MOS transistors T20 and T21, respectively.

  According to the solid-state imaging device in which the CDS circuit is configured by the readout circuits 5-1 to 5 -m and the correction circuit 6 having such a configuration, first, each of the pixels G 1 b to Gmb (b: a natural number of 1 ≦ b ≦ n) When a noise signal indicating pixel sensitivity variation is output, the signal φVn becomes high, whereby the MOS transistor T11 in the readout circuits 5-1 to 5-m is turned on, and the noise signal is sampled and held in the capacitor C11. The Next, when an image signal corresponding to the amount of incident light is output from the pixels G1b to Gmb, the signal φVs goes high, whereby the MOS transistor T10 in the readout circuits 5-1 to 5-m is turned on, and the image signal Is sampled and held in the capacitor C10.

  In this manner, the image signals from the pixels G1b to Gmb are sampled and held in the capacitors C10 in the readout circuits 5-1 to 5-m, and the pixels in the capacitors C11 in the readout circuits 5-1 to 5-m. When a noise signal from each of G1b to Gmb is sampled and held, it is set to high in the order of the signals φH1, φH2,. Therefore, the MOS transistors T16 and T17 in the readout circuits 5-1 to 5-m are turned on in the order of 5-1, 5-2,..., 5-m, and the image signals and noise signals of the pixels G1b to Gmb are Each pixel is input to the differential amplifier 60 of the correction circuit 6. Then, the differential amplifier 60 performs a subtraction process between the image signal and the noise signal, and outputs the noise-removed image signal in the order of the pixels G1b, G2b,.

JP-A-11-313257 JP 2002-77733 A

  In the solid-state imaging device of FIG. 1 described above, in the CDS circuit constituted by the readout circuits 5-1 to 5 -m and the correction circuit 6, the image signal is handled by the MOS transistors T 10, T 102, T 16, T 20 and the capacitor C 10. A signal output circuit unit is configured, and a noise signal output circuit unit that handles a noise signal is configured by the MOS transistors T11, T103, T17, and T21 and the capacitor C11. As described above, in the CDS circuit, the image signal output circuit unit and the noise signal output circuit unit are configured. The difference in characteristics between the image signal output circuit unit and the noise signal output circuit unit is different for each column. If present, the image signal output from the correction circuit 6 includes fixed pattern noise (FPN) that becomes vertical streak noise. Further, the difference in characteristics generated for each column is greatly influenced by the threshold voltages of the MOS transistors T102 and T103.

  In view of such a problem, an object of the present invention is to provide a solid-state imaging device capable of suppressing FPN generated in an image signal by reducing variation in characteristics of a readout circuit.

  In order to achieve the above object, a plurality of pixels including a photoelectric conversion unit that outputs an electrical signal corresponding to the amount of incident light, an output signal line that is connected to the pixel and outputs an electrical signal from the pixel, A readout circuit that reads out an electrical signal from the pixel and samples and holds the electrical signal through the output signal line, and the readout circuit receives an input of the electrical signal from the pixel. An output terminal, and a negative feedback circuit connected to the input / output terminal and having a feedback loop and a signal holding unit that holds a signal appearing on the feedback loop, and the electrical signal from the pixel is When input to the input / output terminal of the readout circuit, the feedback loop of the negative feedback circuit is closed, and a signal having a value corresponding to the electrical signal from the pixel is transmitted in advance. After giving to the signal holding unit, the feedback loop is opened, and a signal having a value corresponding to the electric signal from the pixel is sampled and held in the signal holding unit, and then from the input / output terminal of the readout circuit An electrical signal from the pixel obtained based on the signal sampled and held in the signal holding unit is output.

  The solid-state imaging device according to the present invention includes a plurality of pixels including a photoelectric conversion unit that outputs an electric signal corresponding to an incident light amount, and an output signal line that is connected to the pixel and outputs an electric signal from the pixel. A readout circuit that reads out an electrical signal from the pixel and samples and holds the electrical signal via the output signal line, and the readout circuit receives an electrical signal from the pixel. An input / output terminal, a first switch connected between the output signal line and the input / output terminal, a feedback loop formed by connecting a first electrode and a control electrode, and the input / output A first transistor including a second electrode connected to the terminal; a second switch connected between the first electrode of the first transistor and the control electrode; and control of the first transistor A signal holding unit connected to a connection node between the pole and the second switch and holding a signal appearing on the feedback loop, and a third switch having one end connected to the input / output terminal, When the first switch is turned on and an electrical signal from the pixel is input to the input / output terminal of the readout circuit, the second switch is turned on and the feedback loop of the first transistor is closed. After applying a signal having a value corresponding to the electrical signal from the pixel to the signal holding unit, the second switch is turned off to open the feedback loop of the first transistor, and the electrical signal from the pixel The signal holding value is sampled and held in the signal holding unit, and then the third switch is turned on, before the input / output terminal of the readout circuit. And outputs an electrical signal from the pixels obtained on the basis of the signal holding unit to the sampled and held the signals.

  In such a solid-state imaging device, the solid-state imaging device further includes a first constant current load connected to the other end of the third switch of the readout circuit and causing a constant current to flow through the first electrode of the first transistor. A second constant current load that supplies a constant current substantially equal to a constant current generated by the first constant current load to the transistor, and when the first switch is turned on, the second constant current load is the first constant current load. When a constant current is flowed by being connected to one transistor and the third switch is turned on, the first constant current load is connected to the first transistor and a constant current is allowed to flow.

  Further, in such a solid-state imaging device, the first electrode is connected to the output signal line, and one end of the first switch is connected to the control electrode while being installed between the output signal line and the first switch. A second constant transistor connected to the second electrode of the second transistor; and a third constant current load connected to the second electrode of the second transistor, and suppressing signal deterioration in the transistors used as output portions of the pixels. It does n’t matter. At this time, the second switch may be connected between the control electrode of the first transistor and the second electrode of the second transistor.

  Furthermore, in the above-described solid-state imaging device, the control electrode is connected to the first electrode of the first transistor, and the current that flows to the capacitive load by the other readout circuit when flowing when the third switch is turned on And a fourth switch connected between the first or second electrode of the third transistor and the input / output terminal, and the input / output terminal is turned on by turning on the third switch. When the electric signal from the pixel is output, the fourth switch is turned on, and the influence of the capacitive load by the other readout circuit that is connected to another column and is not performing the output operation is suppressed. It does n’t matter.

  The readout circuit includes a voltage shift circuit for setting a voltage value between the control electrode and the first electrode of the first transistor, and the first transistor is a depletion type transistor. In some cases, a voltage for driving the first transistor may be secured. At this time, the voltage shift circuit includes a fourth transistor having a first electrode connected to the control electrode of the first transistor and a control electrode connected to the first electrode of the first transistor; It may be configured by a load connected to the first electrode.

  In addition, the plurality of pixels output a noise signal indicating variation of each pixel and an image signal on which noise due to the variation is superimposed, and the noise that becomes an electric signal from the pixel as the readout circuit It comprises at least two systems of circuits: a first readout circuit in which a signal is input to the input / output terminal, and a second readout circuit in which the image signal to be an electrical signal from the pixel is input to the input / output terminal.

  Further, at this time, the noise signal output from the input / output terminal of the first readout circuit and the noise signal output from the input / output terminal of the first readout circuit are input, and the A correction circuit is provided that removes the noise from the image signal based on the noise signal and outputs the noise signal.

  According to the present invention, the signal holding circuit for sampling and holding the electric signal from the pixel in the readout circuit is configured on the feedback loop of the negative feedback circuit, and the electric signal held from the terminal to which the electric signal from the pixel is input. The signal output terminal is the same input / output terminal. Therefore, as in a conventional readout circuit that amplifies and outputs an electrical signal from a pixel that is input to and held at the gate of the transistor by the transistor, it depends on the characteristics of the readout circuit such as variations due to elements that perform an amplification operation. The influence on the signal can be suppressed, and FPN generated by the reading circuit can be suppressed.

  Further, by providing the second transistor provided between the output signal line and the first switch, it is possible to suppress signal deterioration in the transistor used as the output portion of each pixel. In addition, by providing a third transistor for passing a current flowing through a capacitive load by another readout circuit, the influence of the capacitive load by another readout circuit that is connected to another column and is not performing an output operation is suppressed. Can do. Further, by providing the voltage shift circuit, when the first transistor is a depletion type transistor, a voltage for driving the first transistor can be secured.

<Configuration of solid-state imaging device>
First, an outline of a configuration of a solid-state imaging device in each embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing an outline of the configuration of a two-dimensional MOS solid-state imaging device (hereinafter referred to as “area sensor”) that is common in each embodiment of the present invention.

  As described in [Background Art], the solid-state imaging device shown in FIG. 1 includes pixels G11 to Gmn that output image signals and noise signals, and a vertical scanning circuit that operates the pixels G11 to Gmn by giving signals to each row. 1, a horizontal scanning circuit 2 that operates so that an image signal and a noise signal from the pixels G 11 to Gmn are output for each column, and a line 3 for supplying signals to the pixels from the vertical scanning circuit 1 in units of rows. 1-3-n, output signal lines 4-1 to 4-m for outputting image signals and noise signals from the pixels G11 to Gmn, and readout for sampling and holding the image signals and noise signals from the pixels G11 to Gmn. A correction circuit 6 that removes noise of the image signal by receiving the image signal and the noise signal sampled and held by the circuits 5-1 to 5-m and the readout circuits 5-1 to 5-m, and an output signal line; 4-1 to 4-m Comprises a MOS transistor Q1~Qm to be connected constant current load Le, a. As will be described later, each of the lines 3-1 to 3-n includes a plurality of signal lines.

  In such a solid-state imaging device, an image signal and a noise signal that are output from the pixel Gab are respectively output via the output signal line 4-a and the MOS connected to the output signal line 4-a. The voltage is amplified by the transistor Qa. That is, the DC voltage VD, VSS is applied to the gate and the source of the MOS transistor Qa whose drain is connected to the output signal line 4-a, so that the MOS transistor Qa functions as a constant current load. The pixels G11 to Gmn are provided with a MOS transistor T3 that outputs a signal based on the photocharge generated in these pixels, as will be described later. When the MOS transistor T3 and the MOS transistor Qa are connected via the output signal line 4-a, the MOS transistor Qa is equivalent to a constant current load, and the circuit formed by the MOS transistors T3 and Qa is a source follower type amplifier. It becomes a circuit.

  By configuring the source follower type amplifier circuit in this way, a larger signal can be amplified and outputted than the case where there is no amplification from the output signal line 4-a. Therefore, when the pixel naturally converts the photocurrent generated from the photosensitive element to expand the dynamic range, the output signal is small as it is, but the amplification circuit is provided as a result by providing this amplification circuit. Since a large signal can be obtained as compared with the case where there is no signal, processing in a subsequent signal processing circuit (not shown) is facilitated. Further, the MOS transistors Q1 to Qm constituting the load resistance portion of the amplifier circuit are not provided in the pixel, but are provided for each of the output signal lines 4-1 to 4-m to which a plurality of pixels arranged in the column direction are connected. As a result, the number of constant current loads can be reduced, and the area occupied by the amplifier circuit on the semiconductor chip can be reduced.

  The image signal and noise signal output from the pixel Gab are sequentially sent to the readout circuit 5-a, and the sent image signal and noise signal are sampled and held in the readout circuit 5-a. Thereafter, the sampled and held image signal is sent from the readout circuit 5-a to the correction circuit 6, and then the sampled and held noise signal is sent to the correction circuit 6. The correction circuit 6 corrects the image signal given from the readout circuit 5-a based on the noise signal also given from the readout circuit 5-a, and outputs the image signal from which noise has been removed to the outside.

  An example of a pixel circuit included in each pixel in FIG. 1 is shown in FIG. In the pixel shown in FIG. 2, the source of the MOS transistor T1 is connected to the anode of the photodiode PD to which the DC voltage VSS is applied to the cathode, and the source of the MOS transistor T4 and the gate of the MOS transistor T2 are connected to the drain of the MOS transistor T1. Connected. The drain of the MOS transistor T3 is connected to the source of the MOS transistor T2, and the source of the MOS transistor T3 is connected to the output signal line 4 (corresponding to the output signal lines 4-1 to 4-m in FIG. 1). The

  A DC voltage VDD is applied to the drains of the MOS transistors T2 and T4. The gates of the MOS transistors T1, T3, and T4 are connected to the drains of the MOS transistors T5 to T7 whose sources are connected to the signal lines 31 to 33 from the vertical scanning circuit 1, respectively. Signal φX is applied to the gates of MOS transistors T5 to T7. Therefore, when the signal φX is set high and the MOS transistors T5 to T7 are turned on, the signal lines 31 to 33 (the three signal lines 31 to 33 are connected to the signal lines 3-1 to 3- (corresponding to each of n), signals φTX, φV, φRS are applied to the gates of the MOS transistors T1, T3, T4. The MOS transistors T1 to T7 are N-channel MOS transistors whose back gates are grounded (DC voltage VSS is applied). When the MOS transistors T1 to T7 are P-channel MOS transistors, a power supply voltage is applied.

  The pixels G11 to Gmn configured as described above operate according to the timing chart of FIG. 3 to output an image signal and a noise signal. Note that the timing chart of FIG. 3 shows a signal state in one horizontal period. Now, when the pixels G1b to Gmb in the b-th row output noise signals and image signals, the signals φTX, φV, and φRS of the signal lines 31 to 33 corresponding to the signal line 3-b of FIG. Is made effective, the signal φX given to the MOS transistors T5 to T7 from the vertical scanning circuit 2 is set to high. Therefore, the MOS transistors T5 to T7 are turned ON, and the signal lines 31 to 33 are electrically connected to the gates of the MOS transistors T1, T3, and T4.

  Then, a high signal φV is applied to the gate of the MOS transistor T3 through the signal line 32 and the MOS transistor T6, thereby turning on the MOS transistor T3. In the photodiode PD, a photoelectric conversion operation is performed to generate and store charges corresponding to the exposure amount. Thereafter, a high signal φRS is applied to the gate of the MOS transistor T4 through the signal line 33 and the MOS transistor T7, thereby turning on the MOS transistor T4. Therefore, the charges stored at the gate of the MOS transistor T2 are recombined, and the gate voltage of the MOS transistor T2 is reset.

  At this time, a drain current corresponding to the gate voltage of the reset MOS transistor T2 flows to the MOS transistor T2. Therefore, a noise signal that becomes a voltage signal proportional to the gate voltage of the reset MOS transistor T2 appears on the output signal lines 4-1 to 4-m. Thereafter, the signal φRS is set to low and the MOS transistor T4 is turned off, and then the signal φTX that goes high is applied to the gate of the MOS transistor T1 through the signal line 31 and the MOS transistor T5 until the MOS transistor T1 is turned on. A voltage signal that becomes a noise signal appears on the output signal lines 4-1 to 4-m.

  When the signal φTX is set high and the MOS transistor T1 is turned on, the charge stored in the photodiode PD is transferred to the gate of the MOS transistor T2. Therefore, even after the signal φTX is set to low and the MOS transistor T1 is turned off, the charge obtained by photoelectric conversion by the photodiode PD is accumulated in the gate of the MOS transistor T2, so that the gate voltage of the MOS transistor T2 is accumulated. Becomes a voltage corresponding to the exposure amount in the photodiode PD. Therefore, since a drain current corresponding to the gate voltage held in the MOS transistor T2 flows, an image signal that is a voltage signal linearly proportional to the exposure amount in the photodiode PD is output to the output signal lines 4-1 to 4-m. appear.

  Thereafter, by setting the signal φX to low, the MOS transistors T5 to T7 are turned OFF, and the signals φTX, φV, and φRS are prohibited from being supplied from the vertical scanning circuit 1 to the pixels G1b to Gmb in the b-th row. . As described above, the pixels G1b to Gmb in the b-th row are operated to output pixel signals and noise signals, which are sampled and held in the readout circuits 5-1 to 5-m, and then read out circuits 5-1 and 5--5. The image signals and noise signals of the pixels G1b, G2b,..., Gmb are given to the correction circuit 6 in order from 2, ..., 5-m, so that the image signals from which the pixels G1b, G2b,. Are output in order.

  Then, in order to validate the signal lines 31 to 33 corresponding to the line 3- (b + 1) connected to the pixels G1 (b + 1) to Gm (b + 1) in the (b + 1) th row, the line 3- The signal φX applied to the gates of the MOS transistors T5 to T7 connected to the signal lines 31 to 33 corresponding to (b + 1) is set to high. Thereafter, each element in the pixels G1 (b + 1) to Gm (b + 1) operates in accordance with the timing chart of FIG. 3, so that the pixels G1 (b + 1) to Gm (b + 1) An image signal is output.

  The configuration of the solid-state imaging device shown in FIG. 1, the configuration of the pixel shown in FIG. 2, and the operation of the pixel shown in FIG. 3 are common configurations and operations in the following embodiments. Therefore, in each embodiment shown below, the readout circuits 5-1 to 5-m and the correction circuit 6 that have different configurations and operations in each embodiment will be described. The readout circuits 5-1 to 5-m and the correction circuit 6 constitute a CDS circuit in the solid-state imaging device of FIG.

<First Embodiment>
A first embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram illustrating an internal configuration of the readout circuit and the correction circuit in the solid-state imaging device according to the present embodiment. In the configuration of the readout circuit and the correction circuit shown in FIG. 4, the same reference numerals are given to the same components as those in FIG. 11, and detailed description thereof is omitted.

  As shown in FIG. 4, the readout circuit 5x (corresponding to the readout circuits 5-1 to 5-m shown in FIG. 1) in the solid-state imaging device of the present embodiment has an output signal line 4 (output signal line shown in FIG. 1). MOS transistors T10, T11 to which the drains are connected, MOS transistors T12, T13 whose sources are connected to the sources of the MOS transistors T10, T11, and MOS transistors T12, T13, respectively. Capacitors C1 and C2 having one ends connected to the respective gates, MOS transistors T14 and T15 having sources connected to the gates of the MOS transistors T12 and T13, and drains connected to the sources of the MOS transistors T10 and T11, respectively. MOS transistors T16 and T17 and MOS transistor T12 MOS transistor T18 having a drain connected to the drain at the node T13, comprises a T19, the.

  The MOS transistors T10 to T17 are N-channel MOS transistors whose back gates are grounded (DC voltage VSS is applied), and the MOS transistors T18 and T19 have power supply potentials applied to the back gates (DC voltage). It is composed of a P-channel MOS transistor to which VDD is applied. A DC voltage VSS is applied to the other ends of the capacitors C1 and C2. A DC voltage VD1 is applied to the gate of the MOS transistor T18, and a DC voltage VDD is applied to the sources of the MOS transistors T18 and T19.

  Further, similarly to the readout circuit 5 of FIG. 11, the signals φVs and φVn are inputted to the gates of the MOS transistors T10 and T11, and the signal φH (readout circuits 5-1 to 5-m is inputted to the gates of the MOS transistors T16 and T17. (Corresponding to signals φH1 to φHm given to each of them). Signals φSs and φSn are input to the gates of the MOS transistors T14 and T15, and a signal φS is input to the gate of the MOS transistor T19. Then, the signals φVs, φVn, φSs, and φSn are supplied from the vertical scanning circuit 1, and the signals φH (φH1 to φHm) are supplied from the horizontal scanning circuit 2.

  The correction circuit 6 has the same configuration as the circuit shown in FIG. 11, and includes MOS transistors T20 and T21 whose drains are connected to the sources of the MOS transistors T16 and T17, and inverting input terminals and drains of the MOS transistors T20 and T21, respectively. And a differential amplifier 60 to which a non-inverting input terminal is connected. DC voltages VD and VSS are applied to the gates and sources of the MOS transistors T20 and T21, respectively. The MOS transistors T20 and T21 are composed of N-channel MOS transistors whose back gates are grounded (DC voltage VSS is applied).

  The readout circuits 5-1 to 5-m having the circuit configuration shown in FIG. 4 and the correction circuit 6 constitute a CDS circuit in the solid-state imaging device shown in FIG. The operations of the readout circuits 5-1 to 5-m and the correction circuit 6 constituting the CDS circuit will be described with reference to the timing chart of FIG. 5 together with the operations of the pixels G11 to Gmn.

  As described above, when the pixels G1b to Gmb operate in accordance with the timing chart of FIG. 3, first, a pulse that goes high while the signal φV is applied to the gate of the MOS transistor T3 and the MOS transistor T3 is turned on. The MOS transistor T4 is turned on by the signal φRS, and the gate voltage of the MOS transistor T2 is reset. When the signal φRS is turned low and the MOS transistor T4 is turned off, the signals φVn and φSn are turned high, so that the MOS transistors T11 and T15 are turned on. At this time, the signals φVs and φSs are made low and the signal φS is made high, and the MOS transistors T10, T14 and T19 are turned off.

  Therefore, the output signal line 4 is electrically connected to the source of the MOS transistor T13 via the MOS transistor T11, and the connection node between the gate of the MOS transistor T13 and the capacitor C2 is connected to the MOS transistor via the MOS transistor T15. It is electrically connected to the connection node of the drains of the transistors T13 and T18. When the output signal line 4, the MOS transistors T11, T13, T15, T18 and the capacitor C2 have such a connection relationship, the MOS transistor T18 operates as a constant current load, and a negative feedback loop is formed by the MOS transistors T13, T15. Is configured.

  At this time, the gate-source voltage Vgs of the MOS transistor T13 is determined by the drain current Id of the MOS transistor T13 based on the characteristics of the gate-source voltage Vgs versus the drain current Id in the MOS transistor shown in FIG. . Now, the gate-source voltage Vgs versus drain current Id characteristic of the MOS transistor T13 is shown by the dotted line in FIG. 6B, and the threshold voltage which is the gate-source voltage Vgs when the drain current Id becomes zero. Is assumed to be Vthn. Since the current Ih determined by the MOS transistor T18 serving as a constant current load flows as a drain current through the MOS transistor T13 having such characteristics, the voltage between the gate and the source of the MOS transistor T13 is a value shown in FIG. Vgsnh.

  When the voltage value representing the noise signal appearing on the output signal line 4 becomes VN, the source voltage of the MOS transistor T13 electrically connected to the output signal line 4 via the MOS transistor T11 becomes VN. Therefore, since the gate-source voltage of the MOS transistor T13 is Vgsnh, the gate voltage of the MOS transistor T13 becomes (VN + Vgsnh), and the voltage Vcn (= VN + Vgsnh) is sampled and held in the capacitor C2.

  Thereafter, the signal φSn is set to low to turn off the MOS transistor T15, thereby disconnecting the electrical connection between the drain and gate of the MOS transistor T13 and holding the voltage Vcn sampled and held in the capacitor C2. Further, the signal φVn is set low to turn off the MOS transistor T11, thereby disconnecting the electrical connection between the output signal line 4 and the source of the MOS transistor T13.

  When the voltage Vcn based on the noise signal is sampled and held in the capacitor C2 in this way, next, in each of the pixels G1b to Gmb, the MOS transistor T3 is turned on by the high pulse signal φTX, and the phototransistor is applied to the gate of the MOS transistor T2. The charge stored in the diode PD is transferred. Therefore, an image signal that becomes a voltage signal linearly proportional to the exposure amount in the photodiode PD appears on the output signal line 4. When the signal φTX is set low and the MOS transistor T3 is turned off, the signals φVs and φSs are set high so that the MOS transistors T10 and T14 are turned on.

  Therefore, the output signal line 4 is electrically connected to the source of the MOS transistor T12 via the MOS transistor T10, and the connection node between the gate of the MOS transistor T12 and the capacitor C1 is connected to the MOS transistor via the MOS transistor T14. It is electrically connected to the connection node of the drains of the transistors T12 and T18. That is, the MOS transistor T18 operates as a constant current load, and a negative feedback loop is configured by the MOS transistors T12 and T14.

  At this time, the gate-source voltage Vgs vs. drain current Id characteristics of the MOS transistor T12 are shown by the solid line in FIG. 6B, and the threshold value is the gate-source voltage Vgs when the drain current Id becomes zero. Assume that the voltage is Vths. Since the current Ih determined by the MOS transistor T18 serving as a constant current load flows as a drain current in the MOS transistor T12 having such characteristics, the voltage between the gate and the source of the MOS transistor T12 is a value shown in FIG. Vgssh. When the voltage value representing the image signal appearing on the output signal line 4 is VS, the source voltage of the MOS transistor T12 electrically connected to the output signal line 4 via the MOS transistor T10 is VS. Therefore, the gate voltage of the MOS transistor T12 becomes (VS + Vgssh), and the voltage Vcs (= VS + Vgssh) is sampled and held in the capacitor C1.

  Thereafter, the signal φSs is set to low to turn off the MOS transistor T14, thereby disconnecting the electrical connection between the drain and gate of the MOS transistor T12, and then the signal φVs to be set low to turn off the MOS transistor T10 to output the signal. The electrical connection between the signal line 4 and the source of the MOS transistor T12 is cut off. In this way, the sampled and held voltage Vcs is held in the capacitor C2. In each of the pixels G1b to Gmb, the signal φV is set low and the MOS transistor T3 is turned OFF. While the MOS transistor T3 is ON, a vertical blank period is set.

  Each element in the readout circuits 5-1 to 5-m performs the above-described operation in the vertical blank period, so that voltage values corresponding to the image signals of the pixels G1b to Gmb are read out from the readout circuits 5-1 to 5-m. Each capacitor C1 is sampled and held, and voltage values corresponding to the noise signals of the pixels G1b to Gmb are sampled and held in the capacitors C2 of the readout circuits 5-1 to 5-m. Thereafter, when a low signal φV is applied to each of the pixels G1b to Gmb, the signal φS applied to the readout circuits 5-1 to 5-m is set to low and the high pulse signals φH1 to φHm are changed to φH1. , .Phi.H2,..., .Phi.Hm are given to the read circuits 5-1 to 5-m, respectively.

  At this time, by setting the signal φS applied to the read circuits 5-1 to 5-m to low, the MOS transistor T19 provided in each of the read circuits 5-1 to 5-m is turned on, and the voltage is applied to the MOS transistors T12 and T13. VDD is applied. Then, high-level pulse signals φH1, φH2,..., ΦHm are sequentially input to the gates of the MOS transistors T16, T17 of the read circuits 5-1, 5-2,. The MOS transistors T16, T17 of -1,5-2,..., 5-m are turned on in order.

  That is, in the read circuit 5x, the signal φS is turned low to turn on the MOS transistor T19, and the high signal φH is given to turn on the MOS transistors T16 and T17. Therefore, the DC voltage VDD is applied via the MOS transistor T19 to the drain of the MOS transistor T12 whose gate is connected to the capacitor C1 holding the voltage Vcs, and the constant current load is applied to the source via the MOS transistor T16. A MOS transistor T20 is connected. Further, the DC voltage VDD is applied to the drain of the MOS transistor T13 whose gate is connected to the capacitor C2 holding the voltage Vcn via the MOS transistor T19, and the constant current load is applied to the source via the MOS transistor T17. The MOS transistor T21 is connected.

  Since the MOS transistors T12 and T13 are connected in this way, the MOS transistors T12 and T13 constitute a source follower amplifier with the MOS transistors T20 and T21, respectively. At this time, the current Ir flowing through the MOS transistor T20 serving as the constant current load flows through the MOS transistor T12 as the source current, and the current Ir flowing through the MOS transistor T21 serving as the constant current load flows through the MOS transistor T13 as the source current.

  Therefore, from the gate-source voltage Vgs vs. drain current Id characteristic indicated by the solid line in FIG. 6B, the drain current flowing through the MOS transistor T12 is Ir, so that the gate-source voltage Vgs of the MOS transistor T12 is The value Vgssr shown in FIG. Since the voltage Vcs held in the capacitor C1 is applied to the gate of the MOS transistor T12, the voltage appearing at the source of the MOS transistor T12 becomes (Vcs−Vgssr), and is applied to the inverting input terminal of the differential amplifier 60. The voltage Vsr (= Vcs−Vgssr = VS + Vgssh−Vgssr) is input.

  Similarly, from the gate-source voltage Vgs vs. drain current Id characteristic indicated by the dotted line in FIG. 6B, the drain current flowing in the MOS transistor T13 is Ir, so that the gate-source voltage Vgs of the MOS transistor T13. Becomes the value Vgsnr shown in FIG. Since the voltage Vcn held in the capacitor C1 is applied to the gate of the MOS transistor T13, the voltage appearing at the source of the MOS transistor T13 becomes (Vcn−Vgsnr), and is applied to the inverting input terminal of the differential amplifier 60. The voltage Vsn (= Vcn−Vgsnr = VN + Vgsnh−Vgsnr) is input.

  When operating in this way, the drain current Ih flowing through the MOS transistors T12 and T13 when the MOS transistor T18 is a constant current load and the MOS transistors T12 and T13 when the MOS transistors T20 and T21 are each a constant current load. The flowing drain current Ir is set to a substantially equal current value. At this time, the source-gate voltages Vgssh and Vgssr of the MOS transistor T12 when the drain currents Ih and Ir flow can be made substantially equal, and the MOS transistor T13 of the MOS transistor T13 when the drain currents Ih and Ir flow. The source-gate voltages Vgsnh and Vgsnr can be made substantially equal.

  Therefore, the signal φH is given by setting the drain current Ih when the MOS transistor T18 is a constant current load and the drain current Ir when the MOS transistors T20 and T21 are each a constant current load to substantially equal current values. Thus, the source voltages of the MOS transistors T12 and T13 when the MOS transistors T16 and T17 are turned on can be set to VS and VN, respectively. The voltages VS and VN are input to the non-inverting input terminal and the inverting input terminal of the differential amplifier 60 in the correction circuit 6, and an image signal having a voltage value α × (VS−VN) is differential amplifier. 60.

  When operating in this way, as described above, the drain current Ih when the MOS transistor T18 is a constant current load and the drain current Ir when the MOS transistors T20 and T21 are each a constant current load are substantially equal to each other. By setting the value, it is possible to reduce the influence of variations in threshold voltages of the MOS transistors T12 and T13 in the image signal and noise signal input to the differential amplifier 60. Further, it can be equivalent to a state in which an image signal and a noise signal are sampled and held at the sources of the MOS transistors T12 and T13. Therefore, as in conventional MOS transistors T102 and T103 (see FIG. 11), signal degradation such as gain loss and distortion that occurs while transmitting the image signal and noise signal sampled and held at the gate to the source is also suppressed. can do.

  Thus, when the read circuits 5-1 to 5-m operate, the signal φS is set low, and after all the MOS transistors T19 of the read circuits 5-1 to 5-m are turned on, the signal φS is set low. .., ΦHm are sequentially supplied to the MOS transistors T16, T17 of the read circuits 5-1, 5-2,. 60, image signals and noise signals of the pixels G1b, G2b,..., Gmb are given, and an image signal from which noise has been removed is output.

  When the pulse signal φHm is supplied to the readout circuit 5-m and the image signal of the pixel Gmb is output from the differential amplifier 60, the signal φS is set high, and all the readout circuits 5-1 to 5-m The MOS transistor T19 is turned off, and the signal φX in the b-th row is set low to turn off the MOS transistors T5 to T7 connected to the pixels G1b to Gmb. At this time, the signal φX in the (b + 1) th row is set to high, the MOS transistors T5 to T7 connected to the pixels G1 (b + 1) to Gm (b + 1) are turned on, and the pixel G1 (b + 1) in the b + 1th row is turned on. The imaging operation by .about.Gm (b + 1) is performed, and the image signals of the pixels G1 (b + 1) to Gm (b + 1) are output in order. By repeating such an operation for each of the pixels G11 to Gm1, G12 to Gm2,..., G1n to Gmn, an image signal for one frame is output.

<Second Embodiment>
A second embodiment of the present invention will be described below with reference to the drawings. FIG. 7 is a circuit diagram illustrating an internal configuration of the readout circuit and the correction circuit in the solid-state imaging device according to the present embodiment. In the configuration of the readout circuit and the correction circuit shown in FIG. 7, parts that are the same as the configuration of FIG. 4 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The readout circuit 5y (corresponding to the readout circuits 5-1 to 5-m shown in FIG. 1) in the solid-state imaging device of the present embodiment has a negative threshold voltage in the MOS transistors T12 and T13 as shown in FIG. A depletion type MOS transistor is used, and the circuit configuration of the readout circuit 5x (see FIG. 4) includes a MOS transistor T22 having a source connected to the drains of the MOS transistors T14 and T15, and a drain connected to the source of the MOS transistor T22 A connected MOS transistor T23 is added.

  In the readout circuit 5y configured as described above, the MOS transistor T22 has its gate connected to the connection node of the respective drains of the MOS transistors T12 and T13, and the DC voltage VDD is applied to its drain, whereby the MOS transistor T12. , T13 operate as voltage shift means for setting the voltage difference between the drain and gate. The MOS transistor T23 acts as a constant current load for setting a source current flowing in the MOS transistor T22 by applying DC voltages VD2 and VSS to the gate and source thereof. The MOS transistors T22 and T23 are N-channel MOS transistors, and their back gates are grounded (DC voltage VSS is applied).

  The read circuit 5y operates in accordance with the flowchart of FIG. 5 like the read circuit 5x in the first embodiment. At this time, a noise signal is output from the output signal line 4, and when the MOS transistors T11 and T15 are turned on, the gate and source of the MOS transistor T22 are connected to the drain and gate of the MOS transistor T13, respectively. Therefore, even in the depletion type MOS transistor T13, a voltage difference is generated between the drain and source of the MOS transistor T13. Therefore, the MOS transistor T13 is operated to sample and hold the voltage Vcn corresponding to the noise signal in the capacitor C2. be able to.

  Similarly, when an image signal is output from the output signal line 4 and the MOS transistors T10 and T14 are turned on, the gate and source of the MOS transistor T22 are connected to the drain and gate of the MOS transistor T12, respectively. Therefore, even in the depletion type MOS transistor T12, a voltage difference is generated between the drain and source of the MOS transistor T12. Therefore, the MOS transistor T12 is operated to sample and hold the voltage Vcs corresponding to the noise signal in the capacitor C1. be able to.

<Third Embodiment>
A third embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a circuit diagram showing an internal configuration of the readout circuit and the correction circuit in the solid-state imaging device according to the present embodiment. In the configuration of the readout circuit and the correction circuit shown in FIG. 8, the same reference numerals are given to the same components as those in FIG. 4, and detailed description thereof is omitted.

  The readout circuit 5z (corresponding to readout circuits 5-1 to 5-m shown in FIG. 1) in the solid-state imaging device of the present embodiment is in the circuit configuration of the readout circuit 5x (see FIG. 4) as shown in FIG. Instead of the MOS transistors T18 and T19, MOS transistors T18a and T18b whose drains are connected to the drains of the MOS transistors T12 and T13, and MOS transistors T24 and T25 whose gates are connected to the drains of the MOS transistors T18a and T18b, The MOS transistors T26 and T27 have drains connected to the drains of the MOS transistors T24 and T25, respectively.

  The DC voltage VDD is applied to the sources of the MOS transistors T18a, T18b, T24, and T25, and the sources of the MOS transistors T12 and T13 are connected to the sources of the MOS transistors T26 and T27, respectively. A signal φS1 is applied to the gates of the MOS transistors T26 and T27. The MOS transistors T18a, T18b, T24, and T25 are P-channel MOS transistors whose back gates are supplied with a power supply potential (DC voltage VDD is applied). The MOS transistors T26 and T27 are N-channel MOS transistors whose back gates are grounded (DC voltage VSS is applied).

  In the readout circuit 5z configured as described above, the signal φS1 operates at the same timing as the signal φS in the first embodiment. The relationship between the high and low is that the MOS transistor T19 and the MOS transistors T26 and T27 Since the MOS transistor has a reverse polarity, the reverse occurs. That is, during the horizontal blank period, the signal φS1 is set to low and the MOS transistors T26 and T27 are turned OFF. When the signal φV is set to low and the MOS transistor T5 (see FIG. 2) of the pixel performing the reading operation is turned off, the signal φS1 is set to high and the MOS transistors T26 and T27 are turned on. Thereafter, the pulse signals φH1 to φHm that become high are sequentially supplied to the readout circuits 5-1 to 5-m, the image signal and the noise signal are supplied to the differential amplifier 60, and when the signal φHm becomes low, the signal φS1 Is turned low to turn off the MOS transistors T26 and T27.

  In the readout circuit 5z operating in this way, the operation when reading out the image signal and the noise signal from each pixel is connected to the gates of the MOS transistors T12 and T13 by performing the same operation as the readout circuit 5x. Voltages Vcs and Vcn corresponding to the image signal and noise signal are sampled and held in the capacitors C1 and C2, respectively. At this time, the MOS transistor T18a functions as a constant current load for setting the drain current Ir flowing in the MOS transistor T12, and the MOS transistor T18b functions as a constant current load for setting the drain current Ir flowing in the MOS transistor T13.

  When the MOS transistors T10, T11, T14, and T15 are OFF and the signal φS1 is high and the MOS transistors T26 and T27 are ON, the drains of the MOS transistors T24 and T25 are the sources of the MOS transistors T12 and T13, respectively. Is electrically connected. Therefore, when the MOS transistors T16 and T17 are turned on and connected to the MOS transistors T20 and T21 of the correction circuit 6, a current also flows through the MOS transistors T24 and T25.

  That is, when the MOS transistor T20 serving as a constant current load is connected to the source of the MOS transistor T12, the MOS transistor T20 is also connected to the drain of the MOS transistor T24. At this time, m−1 MOS transistors T22 which are in the OFF state of the other readout circuit 5z whose φH is set to low are connected to the source of the MOS transistor T12 and the drain of the MOS transistor T24.

  For this reason, a large capacity load is connected to the source of the MOS transistor T12 and the drain of the MOS transistor T24 by the (m−1) MOS transistors T22 that are turned off, and a large current tends to flow. Flowing through. Therefore, the drain current Ir from the MOS transistor T18a serving as a constant current load flows through the MOS transistor T12. As a result, the image signal in which the gate and source of the MOS transistor T12 are canceled is input to the inverting input terminal of the differential amplifier 60. Will be input.

  Similarly, when the MOS transistor T21 serving as a constant current load is connected to the source of the MOS transistor T13, the MOS transistor T21 is also connected to the drain of the MOS transistor T25. Therefore, since a large current tends to flow through the MOS transistor T25, the drain current Ir from the MOS transistor T18b serving as a constant current load flows through the MOS transistor T13. As a result, a noise signal canceled between the gate and the source of the MOS transistor T13 is input to the non-inverting input terminal of the differential amplifier 60.

<Fourth Embodiment>
A fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 9 is a circuit diagram illustrating an internal configuration of the readout circuit and the correction circuit in the solid-state imaging device according to the present embodiment. In the configuration of the readout circuit and the correction circuit shown in FIG. 9, parts that are the same as the configuration of FIG. 4 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The readout circuit 5s (corresponding to readout circuits 5-1 to 5-m shown in FIG. 1) in the solid-state imaging device of the present embodiment has a circuit configuration of the readout circuit 5x (see FIG. 4) as shown in FIG. The MOS transistor T28 to which the source of the output signal line 4 is connected and the MOS transistor T29 to which the gate, drain and drain of the MOS transistor T28 are connected are added. The drains of the MOS transistors T10 and T11 are connected to the gate of the MOS transistor T28, and DC voltages VD3 and VDD are applied to the gate and source of the MOS transistor T29, respectively. The MOS transistor T28 is an N-channel MOS transistor whose back gate is grounded (DC voltage VSS is applied), and the MOS transistor T29 is that the back gate is applied with a power supply potential (DC voltage VDD). Is a P-channel MOS transistor.

  In the readout circuit 5s configured as described above, the MOS transistors T10 to T19 operate according to the timing chart of FIG. 5 as in the readout circuit 5x (see FIG. 4) of the first embodiment. Therefore, in the present embodiment, the operation of the newly added MOS transistors T28 and T29 will be described below.

  In this read circuit 5s, a current equivalent to the drain current flowing through the MOS transistor T2 flows from the MOS transistor T29 serving as a constant current load as the drain current of the MOS transistor T28, and the drain and gate of the MOS transistor 28 are connected. Thus, a negative feedback circuit is configured. By configuring the MOS transistor T28 as a MOS transistor having characteristics equivalent to those of the MOS transistor T2, a voltage equivalent to the voltage between the gate and source of the MOS transistor T2 is obtained between the gate and source of the MOS transistor T28. Can appear in

  Therefore, a voltage equivalent to the voltage appearing at the gate of the MOS transistor T2 appears at the gate of the MOS transistor T28. That is, when the image signal is output, the voltage appearing at the gate of the MOS transistor T2 appears at the gate of the MOS transistor T28, and when the MOS transistor T10 is turned ON, the source voltage of the MOS transistor T12 is equal to the voltage appearing at the gate of the MOS transistor T2. It can be. Further, when the noise signal is output, the voltage appearing at the gate of the MOS transistor T2 appears at the gate of the MOS transistor T28, and when the MOS transistor T11 is turned on, the source voltage of the MOS transistor T13 is equal to the voltage appearing at the gate of the MOS transistor T2. Can be a value.

<Fifth Embodiment>
A fifth embodiment of the present invention will be described below with reference to the drawings. FIG. 10 is a circuit diagram illustrating the internal configuration of the readout circuit and the correction circuit in the solid-state imaging device according to the present embodiment. In the configuration of the readout circuit and the correction circuit shown in FIG. 10, parts that are the same as the configuration of FIG. 9 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The readout circuit 5t (corresponding to the readout circuits 5-1 to 5-m shown in FIG. 1) in the solid-state imaging device of the present embodiment has a circuit configuration of the readout circuit 5s (see FIG. 9) as shown in FIG. On the other hand, instead of the MOS transistors T18 and T19, a MOS transistor T30 having a drain connected to the gate of the MOS transistor T28 is added, and a DC voltage VDD is applied to the drains of the MOS transistors T12 and T13. The drain of the transistors T14 and T15 is connected to the drain of the MOS transistor T29. At this time, the MOS transistor T30 is an N-channel MOS transistor whose back gate is grounded (DC voltage VSS is applied), and DC voltages VD4 and VSS are applied to the gate and source, respectively.

  In the readout circuit 5t configured as described above, the MOS transistors T10, T11, T14 to T17 operate according to the timing chart of FIG. 5 as in the readout circuit 5x (see FIG. 4) of the first embodiment. That is, by turning on the MOS transistors T11 and T15, the voltage Vcn corresponding to the noise signal is sampled and held in the capacitor C2, and then the MOS transistors T10 and T14 are turned on so that the capacitor C1 corresponds to the noise signal. Sample and hold the voltage Vcs. Then, by turning on the MOS transistors T16 and T17, an image signal and a noise signal are simultaneously sent to the differential amplifier 60.

  When operating in this way, first, when a noise signal is output from the pixel from the output signal line 4, the MOS transistors T11 and T15 are turned ON. Therefore, the connection node between the gate of the MOS transistor T13 and the capacitor C2 is electrically connected to the connection node between the drains of the MOS transistors T28 and T29, and the source of the MOS transistor T13 is connected to the gate of the MOS transistor T28 and the MOS transistor T30. Electrically connected to a connection node with the drain of

  At this time, a drain current having a current value substantially equal to the drain current of the MOS transistor T2 in the pixel flows through the MOS transistor T28 by the MOS transistor T29 serving as a constant current load. Therefore, the voltage appearing at the gate of the MOS transistor T2 in the pixel appears as a noise signal as the source voltage of the MOS transistor T13. Further, the drain current Ir flows to the MOS transistor T13 by the MOS transistor T30 serving as a constant current load, and the voltage Vcn corresponding to the noise signal appearing at the source of the MOS transistor T13 is sampled and held in the capacitor C2.

  After that, after turning off the MOS transistors T11 and T15, when an image signal is output from the pixel from the output signal line 4, the MOS transistors T10 and T14 are turned on. Therefore, the connection node between the gate of the MOS transistor T12 and the capacitor C1 is electrically connected to the connection node between the drains of the MOS transistors T28 and T29, and the source of the MOS transistor T12 is connected to the gate of the MOS transistor T28 and the MOS transistor T30. Electrically connected to a connection node with the drain of

  At this time, a drain current having a current value substantially equal to the drain current of the MOS transistor T2 in the pixel flows through the MOS transistor T28 by the MOS transistor T29 serving as a constant current load, as in the case where the image signal is output. Therefore, the voltage that appears at the gate of the MOS transistor T2 in the pixel appears as a noise signal as the source voltage of the MOS transistor T12. The drain current Ir flows to the MOS transistor T12 by the MOS transistor T30 serving as a constant current load, and the voltage Vsn corresponding to the image signal appearing at the source of the MOS transistor T12 is sampled and held in the capacitor C1.

  Thereafter, after turning off the MOS transistors T10 and T14, turning on the MOS transistors T16 and T17, the drain of the MOS transistor T20 is connected to the source of the MOS transistor T12, and the drain of the MOS transistor T21 is connected to the source of the MOS transistor T13. Is connected. Therefore, the drain current Ir determined by the MOS transistor T20 serving as the constant current load flows through the MOS transistor T12, and the drain current Ir determined by the MOS transistor T21 serving as the constant current load flows through the MOS transistor T13. In this manner, an image signal and a noise signal that appear as source voltages of the MOS transistors T12 and T13 can be sent to the differential amplifier 60.

  In the third to fifth embodiments, similarly to the second embodiment, when a depletion type MOS transistor is provided as the MOS transistors T12 and T13, a voltage difference is generated between the gate and drain of each of the MOS transistors T12 and T13. A MOS transistor that shifts the voltage for generation may be provided. At this time, two MOS transistors T22 and T23 provided in the readout circuit 5y are provided, and each is provided in each circuit unit that samples and holds each of the image signal and the noise signal.

  In the fourth and fifth embodiments, as in the third embodiment, the MOS transistors T22 and T22 of other readout circuits that are turned off when outputting the image signal and the noise signal to the differential amplifier 60 are provided. A configuration for reducing the influence of a current flowing through a large-capacity load due to T23 may be used. At this time, similarly to the read circuit 5z, in the read circuits 5s and 5t, the MOS transistors T24 and T25 whose gates are connected to the drains of the MOS transistors T12 and T13, and the sources are connected to the sources of the MOS transistors T12 and T13, respectively. MOS transistors T26 and T27 are provided.

  Furthermore, in the first to fifth embodiments described above, the configuration of each pixel included in the solid-state imaging device is configured as shown in FIG. 3, and the image signal is a value that changes linearly with respect to the integral value of the incident light amount. However, the present invention is not limited to such a configuration. For example, as described in Patent Document 1, an image signal that has a value that naturally varies logarithmically with respect to the amount of incident light. Or a pixel configuration capable of switching between a linear conversion operation and a logarithmic conversion operation as described in Patent Document 2. In addition, among the MOS transistors constituting each part of each solid-state imaging device described above, a transistor configured with an N channel may be configured with a P channel, and a transistor configured with a P channel may be configured with an N channel.

These are block diagrams which show the internal structure of a solid-state imaging device. These are circuit diagrams which show the structure of the pixel with which the solid-state imaging device of FIG. 2 is equipped. FIG. 4 is a timing chart showing an imaging operation by the pixel of FIG. 3. FIG. 2 is a circuit diagram illustrating an internal configuration of each of a readout circuit and a correction circuit in the solid-state imaging device according to the first embodiment. These are timing charts showing the operation of the readout circuit of FIG. These are graphs showing the relationship between the gate-source voltage and the drain current of the MOS transistors T12, T13. These are circuit diagrams which respectively show the internal structure of the read-out circuit and correction | amendment circuit in the solid-state imaging device in 2nd Embodiment. These are the circuit diagrams which each show the internal structure of the read-out circuit and correction | amendment circuit in the solid-state imaging device in 3rd Embodiment. These are the circuit diagrams which each show the internal structure of the read-out circuit and correction circuit in the solid-state imaging device in 4th Embodiment. These are the circuit diagrams which each show the internal structure of the read-out circuit and correction circuit in the solid-state imaging device in 5th Embodiment. These are circuit diagrams which show an internal structure of each of the readout circuit and the correction circuit in the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Vertical scanning circuit 2 Horizontal scanning circuit 3-1 to 3-n line 4-1 to 4-m Output signal line 5-1 to 5-m Reading circuit 6 Correction circuit Q1-Qm MOS transistor G11-Gmn Pixel

Claims (10)

A plurality of pixels including a photoelectric conversion unit that outputs an electric signal corresponding to the amount of incident light, an output signal line that is connected to the pixel and outputs an electric signal from the pixel, and the output signal line through the output signal line In a solid-state imaging device including a readout circuit that reads out an electrical signal from a pixel and samples and holds the electrical signal,
The readout circuit is
An input / output terminal to which an electrical signal from the pixel is input;
A negative feedback circuit connected to the input / output terminal and having a feedback loop and a signal holding unit for holding a signal appearing on the feedback loop;
With
When the electrical signal from the pixel is input to the input / output terminal of the readout circuit, the feedback loop of the negative feedback circuit is closed, and a signal having a value corresponding to the electrical signal from the pixel is After giving to the signal holding unit, the feedback loop is opened, and a signal having a value corresponding to the electrical signal from the pixel is sampled and held in the signal holding unit,
Thereafter, an electric signal from the pixel obtained based on the signal sampled and held in the signal holding unit is output from the input / output terminal of the readout circuit. A plurality of pixels including a photoelectric conversion unit that outputs an electrical signal corresponding to the amount of incident light, an output signal line that is connected to the pixel and outputs an electrical signal from the pixel, and the output signal line through the output signal line In a solid-state imaging device including a readout circuit that reads out an electrical signal from a pixel and samples and holds the electrical signal,
The readout circuit is
An input / output terminal to which an electrical signal from the pixel is input;
A first switch connected between the output signal line and the input / output terminal;
A first transistor comprising: a feedback loop formed by connecting the first electrode and the control electrode; and a second electrode connected to the input / output terminal;
A second switch connected between the first electrode and the control electrode of the first transistor;
A signal holding unit connected to a connection node between the control electrode of the first transistor and the second switch and holding a signal appearing on the feedback loop;
A third switch having one end connected to the input / output terminal;
With
When the first switch is turned on and an electrical signal from the pixel is input to the input / output terminal of the readout circuit, the second switch is turned on and the feedback loop of the first transistor is closed. After applying a signal having a value corresponding to the electrical signal from the pixel to the signal holding unit, the second switch is turned off to open the feedback loop of the first transistor, and the electrical signal from the pixel Sample and hold the signal corresponding to the value in the signal holding unit,
Thereafter, the third switch is turned on, and an electric signal from the pixel obtained based on the signal sampled and held in the signal holding unit is output from the input / output terminal of the readout circuit. Solid-state imaging device. A first constant current load connected to the other end of the third switch of the readout circuit and configured to flow a constant current to the first electrode of the first transistor;
The readout circuit includes a second constant current load that supplies a constant current substantially equal to a constant current by the first constant current load to the transistor,
When the first switch is turned on, the second constant current load is connected to the first transistor, and a constant current is passed,
3. The solid-state imaging device according to claim 2, wherein when the third switch is turned on, the first constant current load is connected to the first transistor and a constant current is passed. 4. A second transistor installed between the output signal line and the first switch, a first electrode connected to the output signal line, and one end of the first switch connected to a control electrode;
A third constant current load connected to the second electrode of the second transistor;
The solid-state imaging device according to claim 2, further comprising:   The solid-state imaging device according to claim 4, wherein the second switch is connected between a control electrode of the first transistor and a second electrode of the second transistor. A third transistor having a control electrode connected to the first electrode of the first transistor and flowing a current flowing through the capacitive load of the other readout circuit when flowing when the third switch is turned ON;
A fourth switch connected between the first or second electrode of the third transistor and the input / output terminal;
With
6. The solid state according to claim 2, wherein when the third switch is turned on and an electric signal from the pixel is output from the input / output terminal, the fourth switch is turned on. 6. Imaging device.   The said read-out circuit is equipped with the voltage shift circuit for setting the voltage value between the control electrode of a said 1st transistor, and a 1st electrode, The Claim 2 characterized by the above-mentioned. Solid-state imaging device.   The voltage shift circuit includes a fourth transistor having a first electrode connected to a control electrode of the first transistor and a control electrode connected to a first electrode of the first transistor, and a first electrode of the fourth transistor The solid-state imaging device according to claim 7, wherein the solid-state imaging device is configured to include a load connected to the load. The plurality of pixels output a noise signal indicating variation of each pixel and an image signal on which noise due to the variation is superimposed,
As the readout circuit, a first readout circuit in which the noise signal that is an electrical signal from the pixel is input to the input / output terminal, and the image signal that is an electrical signal from the pixel is input to the input / output terminal. The solid-state imaging device according to claim 1, further comprising at least two circuits of a second readout circuit.   The noise signal output from the input / output terminal of the first readout circuit and the noise signal output from the input / output terminal of the first readout circuit are input and based on the noise signal The solid-state imaging device according to claim 9, further comprising a correction circuit that removes the noise from the image signal and outputs the signal.

Images