JP2006269769A - Semiconductor composite device, print head, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor composite device which reduces deterioration in characteristics even when a large current flows into a conduction layer supplying a common potential, and also to provide a print head and an image forming apparatus. <P>SOLUTION: The semiconductor composite device 100 comprises: an integrated circuit board 110; a metal layer 140 formed on the integrated circuit board 110; a pad 150 provided on the integrated circuit board 110 and connected electrically with the metal layer 140 at a plurality of points in order to supply a common potential to the metal layer 140; and a semiconductor thin film 160 having one or more semiconductor elements 166 and a semiconductor layer connected electrically with one or more semiconductor elements and provided on the integrated circuit board 110 to connect the semiconductor layer electrically with the metal layer 140. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor composite device including a semiconductor thin film having a semiconductor element on a circuit board that supplies a driving potential and a common potential, a print head on which the semiconductor composite device is mounted, and an image on which the print head is mounted. The present invention relates to a forming apparatus.

  For example, Patent Document 1 proposes a semiconductor composite device including a semiconductor thin film having a semiconductor element on an integrated circuit substrate. This semiconductor composite device includes a common electrode layer (metal layer) formed on an integrated circuit substrate, a semiconductor thin film (semiconductor epitaxial film) provided thereon, and a region from the semiconductor thin film to the integrated circuit substrate. The common electrode layer is connected to the ground.

JP 2004-179641 A (FIG. 1, FIG. 2, paragraph 0016)

  However, in order to achieve a significant reduction in the cost of semiconductor materials (ie, integrated circuit substrate materials and semiconductor thin film materials), it is required to reduce the width of the semiconductor material and reduce the thickness of the semiconductor material. The When the width of the semiconductor material is reduced and the thickness is reduced, it is necessary to reduce the width of the common electrode layer and reduce the thickness. As a result, the application of each semiconductor element due to the voltage drop in the common electrode layer There is a problem that the characteristics of the semiconductor composite device deteriorate due to a difference in voltage. This problem becomes conspicuous when the number of semiconductor elements included in the semiconductor thin film is large and a large current needs to flow through the common electrode layer.

  Therefore, the present invention has been made to solve the above-described problems of the prior art, and even when a large current flows through a conductive layer that supplies a common potential, the deterioration of the characteristics of the device is reduced. It is an object of the present invention to provide a semiconductor composite device, a print head, and an image forming apparatus that can be used.

  The semiconductor composite device of the present invention includes a circuit board, a conductive layer provided on the circuit board, a common electrode portion that is electrically connected to a plurality of locations of the conductive layer and supplies a common potential to the conductive layer, And a semiconductor thin film having one or more semiconductor elements which are provided on the circuit board and electrically connected to the conductive layer.

  The print head according to the present invention includes the semiconductor composite device and an optical element mounted to face the semiconductor composite device.

  Furthermore, the image forming apparatus of the present invention includes the print head and an image carrier on which an electrostatic latent image is formed by light irradiation from the print head.

  According to the present invention, even when a large current flows through a conductive layer that supplies a common potential, it is possible to reduce the deterioration of the characteristics of the device.

<First Embodiment>
FIG. 1 is a plan view schematically showing a semiconductor composite device 100 according to the first embodiment of the present invention. 2 is a cross-sectional view schematically showing a cross section of FIG. 1 taken along line S ₂ -S _2. FIG. 3 is provided on a conductive layer (metal layer) 140 on the integrated circuit substrate 110. 2 is an enlarged cross-sectional view of a semiconductor thin film 160. FIG.

  As shown in FIGS. 1 and 2, the semiconductor composite device 100 according to the first embodiment includes an integrated circuit substrate 110, a metal layer 140 provided on the integrated circuit substrate 110, and an integrated circuit substrate 110. And a plurality of bonding pads (electrode pads) 150 for supplying a common potential to the metal layer 140, and a semiconductor thin film (semiconductor epitaxial film) 160 bonded (bonded) on the metal layer 140. The semiconductor composite device 100 also includes an interlayer insulating film 170 covering the semiconductor thin film 160 and an individual wiring layer 180 connected to the semiconductor element 166 of the semiconductor thin film 160 through the opening 171 of the interlayer insulating film 170. Yes.

  The integrated circuit substrate 110 includes a substrate (for example, a Si substrate) 111 including an integrated circuit region 112 on which transistors and the like constituting the integrated circuit are formed, a multilayer wiring region 113 on the integrated circuit region 112 of the substrate 111, a substrate 111 has a multilayer film region 114 having a multilayer film structure similar to that of the multilayer wiring region 113. The laminated film region 114 is formed at a position adjacent to the integrated circuit region 112. Further, the integrated circuit board 110 has an individual wiring pad 115 on the laminated film region 114, a connection wiring 116 connected to the individual wiring pad 115, and an individual output pad 117 connected to the connection wiring 116. have. Further, the integrated circuit board 110 has an input pad 118 on the multilayer wiring region 113 to which various drive signals, drive power supply potential, and ground (GND) potential of the integrated circuit in the integrated circuit region 112 are input.

  The integrated circuit region 112 and the multilayer wiring region 113 include a driving integrated circuit for driving a semiconductor element 166 (an LED array including a plurality of LEDs in the first embodiment) included in the semiconductor thin film 160, and is supplied from the outside. Circuits such as a circuit for digitally processing a drive control signal to be processed and a transistor circuit for outputting a current for driving the semiconductor element 166 are integrated. When supplying an electric signal from the outside of the chip (that is, the semiconductor composite device 100), for example, the external circuit and the input pad 118 are connected by wire bonding. Further, the input pad 118 and the individual output pad 117 can be used for probing the operation of the chip in the wafer state (in the manufacturing process).

  The connection wiring 116 is, for example, a wiring that is formed in a part of the multilayer wiring layer and is not exposed on the chip surface. The individual wiring pad 115, the connection wiring 116, and the individual output pad 117 are, for example, a layer made of one material selected from Al, Cu, Si, Ni, Cr, Ti, and W, or It can be formed as a layer composed of a laminated material including a plurality of materials selected from various materials, an alloy material, or a mixed material.

  The individual wiring 180 for connecting the individual wiring connection pad 115 and the semiconductor element 166 forms an ohmic contact with the semiconductor element 166 and the region 167 (shown in FIG. 2). The individual wiring 180 is, for example, a laminated film in which thin films of one or more elements selected from Au, Ge, Ni, Pt, Ti, Pd, In, Al, Cu, Cr, and Si are laminated, Alternatively, the thin film is made of an alloy containing the one or more elements.

  Further, the structure of the integrated circuit substrate 110 is not limited to the illustrated example. For example, an integrated circuit region including a driving integrated circuit (a region corresponding to the region 112 in FIGS. 1 and 2) can be formed under the bonding area of the semiconductor thin film 160. When such a configuration is adopted, the semiconductor integrated device 100 can be highly integrated. In this case, a multilayer wiring region (a region corresponding to the region 113 in FIGS. 1 and 2) is provided under the metal layer 140 under the semiconductor thin film 160. Further, without forming the integrated circuit region under the metal layer 140, the metal layer 140 is formed on the multilayer insulating film formed of a plurality of interlayer insulating films formed when the multilayer wiring region is formed on the substrate 111. May be. In this case, since the adhesion region of the semiconductor thin film 160 becomes flat, the adhesion strength of the semiconductor thin film 160 to the adhesion region increases.

  The metal layer 140 is, for example, a stacked film in which thin films of one or more elements selected from Au, Ge, Ni, Pt, Ti, Pd, and In are stacked, or the one or more It is comprised by the thin film which consists of an alloy containing an element. The metal layer 140 is desirably formed in a region similar to the semiconductor thin film 160 over the entire area under the semiconductor thin film 160 and slightly larger than the semiconductor thin film 160.

  The bonding pad 150 is an electrode pad connected to the metal layer 140 or integrally formed with the metal layer 140. The bonding pad 150 is an electrode pad for wire connection with a common potential region outside the chip (semiconductor composite device 100). A plurality of bonding pads 150 are provided in electrical connection with the metal layer 140. The metal layer 140 to which the bonding pad 150 is connected serves as a common potential supply electrode of the semiconductor element 166 formed on the semiconductor thin film 160.

  Here, when the number of bonding pads 150 is N and the length of the long side of the metal layer 140 is 1, the n-th bonding pad 150 (n is an arbitrary integer from 1 to N) is connected to the chip. It is preferable to arrange at a position of about (2n-1) / 2N from one short side. The bonding pad 150 is provided on the opposite side of the metal layer 140 from the input pad 118 and the individual output pad 117.

The semiconductor thin film 160 is, for example, a single layer selected from GaAs, AlGaAs, AlGaInP, InP, GaP, GaInP, GaN, AlGaN, InGaN, and AlGaInAs, or a laminated structure composed of various mixed crystal ratios of the plurality of materials. It is. As shown in FIGS. 2 and 3, the semiconductor thin film 160 includes, for example, a lower contact layer 161 in contact with the metal layer 140 on the integrated circuit substrate 110, a lower cladding layer 162 formed thereon, and a lower contact layer 161 thereon. The active layer 163 is formed, an upper clad layer 164 formed thereon, and an upper contact layer 165 formed thereon. For example, the lower contact layer 161 is an n-GaAs layer, the lower cladding layer 162 is an n-Al _x Ga _1-x As layer, the active layer 163 is an n-Al _y Ga _1-y As layer, cladding layer 164 is a _{p-Al z Ga 1-z} as layer, the upper contact layer 165 may be a p-GaAs layer. Here, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, and 0 ≦ z ≦ 1, for example, y <x and y <z. In the example of FIG. 3, the active layer 163 of the semiconductor thin film 160 and the region above the active layer 163 are element-isolated into a plurality of individual island regions (individual element regions). The upper contact layer 165 that is the uppermost layer of each individual element region is a layer for forming an ohmic contact with the individual electrode 180. The lower contact layer 161, which is the lowest layer, is a layer for forming an ohmic contact with the metal layer 140.

  As shown in FIG. 1, a plurality of bonding pads 150 connected to the metal layer 140 are provided in the region of the metal layer 140 to which the semiconductor thin film 160 is bonded. For this reason, the semiconductor composite device 100 according to the first embodiment performs drive control by supplying a large amount of current to each semiconductor element 166, or the current flowing to each semiconductor element 166 is small, but the total number of semiconductor elements is large. Even when the current is large, the current flowing in the metal layer 140 does not cause a voltage drop that has an influence on device driving.

  Next, an example of a method for manufacturing the semiconductor composite device 100 according to the first embodiment will be described. First, the driving integrated circuit 112 is formed on the substrate (for example, Si substrate) 111, and the multilayer wiring region 113 and the laminated film region 114 are further formed. Next, a metal layer 140 and a plurality of bonding pads 150 are formed on the substrate 111. The metal layer 140 and the plurality of bonding pads 150 may be formed simultaneously in the same process, or may be formed in separate processes.

Separately from the manufacturing process of the integrated circuit substrate 110 described above, as shown in FIG. 4, a semiconductor thin film layer 160a (before the peeling, the semiconductor thin film layer 160a and the semiconductor thin film layer 160a are formed on a semiconductor thin film forming substrate (for example, a GaAs substrate). After the peeling, it is written as a semiconductor thin film 160). When forming the semiconductor thin film layer 160a, for example, MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy) can be used. As shown in FIG. 4, on the GaAs substrate 190, for example, a GaAs buffer layer 191 and a release layer for peeling the semiconductor thin film layer 160 a from the GaAs substrate 190 (for example, an AlAs layer or Al _t Ga _1-t An As layer (0 ≦ t ≦ 1) 192 is provided. The release layer 192 may be appropriately selected from materials that can be selectively removed by etching depending on the semiconductor thin film layer 160a to be used. The semiconductor thin film layer 160a formed on the GaAs substrate 190 is separated into a desired size and shape by mesa etching so that at least the peeling layer 192 is exposed in the mesa etching region. Next, the peeling layer 192 is selectively etched using, for example, diluted acid such as hydrofluoric acid or hydrochloric acid, and the semiconductor thin film layer 160a is peeled from the GaAs substrate 190. In this step, a support (not shown) that supports the semiconductor thin film layer 160a can be used as appropriate so that the semiconductor thin film layer 160a can be easily handled. The peeled semiconductor thin film 160 is moved onto the integrated circuit substrate 110 and bonded onto the metal layer 140.

  Next, an interlayer insulating film 170 is formed so as to cover the semiconductor thin film 160 bonded on the metal layer 140. The interlayer insulating film 170 can be, for example, PCVD-SiN (SiN formed by Plasma Chemical Vapor Deposition method). After forming an opening 171 for electrode contact in the interlayer insulating film 170, an individual wiring layer 180 for connecting the semiconductor element 166 and the pad 115 is formed, and sintering for forming a good contact is performed. Thereafter, it is separated into individual chips as appropriate by dicing or the like.

  Next, the operation of the semiconductor composite device 100 according to the first embodiment will be described. A power supply and a drive signal are input from the input pad 118 to the drive integrated circuit 112 to drive each semiconductor element 166. A common potential of each semiconductor element 166, for example, a GND potential, is supplied from a plurality of bonding pads 150. Each semiconductor element (for example, light emitting element) 166 is driven by passing a current of 1 mA to several mA, for example. Since the current flowing through each individual element flows into the nearest bonding pad 150 via the metal layer 140, even if the number of elements is very large, the common potential of each individual element is unlikely to vary. .

  According to the first embodiment, the semiconductor thin film 160 including the semiconductor element 166 is bonded on the metal layer 140, and the semiconductor thin film 160 is bonded to the bonding pad 150 connected to the metal layer 140 that supplies the common potential. A common potential is supplied by providing a plurality in the region. Therefore, even when the sum of currents flowing through one or more semiconductor elements 166 included in the semiconductor thin film 160 is large, the voltage drop is reduced so as not to affect the driving of the semiconductor element 166, and the semiconductor element 166 is reduced. The variation in the common potential due to the position of can be reduced. Therefore, when the semiconductor element 166 is an LED and the semiconductor composite device 100 is an LED array, it is possible to reduce variations in the light emission luminance of each LED constituting the LED array.

  Further, since the individual output pad 117, the input pad 118, and the like are provided on the opposite side of the bonding pad 150 connected to the metal layer 140, bonding for connecting to the individual output pad 117, the input pad 118, and the bonding pad 150 is performed. The wires are dispersed on both sides of the semiconductor thin film 160, and the arrangement density of the bonding wires can be lowered.

In the above description, the example of the semiconductor element 166 included in the semiconductor thin film 160 has been described by taking the element isolation form by mesa etching shown in FIG. 3, but as shown in FIG. The thin film layer may be selectively doped with a second conductivity type impurity, for example, selectively diffused. In the case of a semiconductor thin film structure including selective impurity doping as shown in FIG. 5, the semiconductor thin film layer 160b is, for example, a lower contact layer 161b (for example, n-GaAs), and a lower cladding formed thereon. layer 162b _{(e.g., n-Al x Ga 1-} x as), and thereon formed active layer _{163b (n-Al y Ga 1} -y as), the top upper cladding layer 164b formed on the (p -al _z and Ga _1-z as), may be formed from its top on the contact layer 165b formed on the (n-GaAs). In this case, a p-type impurity (eg, Zn) may be selectively diffused to form the selective diffusion region 168. Here, the diffusion front 169 may be formed so as to be located in the active layer 163b.

  In FIG. 5, the semiconductor thin film layer 160b does not necessarily have a double hetero structure, and may have a single hetero structure or a homo structure.

  Furthermore, in the above description, an LED array in which LEDs are arranged in a row as the semiconductor element 166 is specifically described as an example. However, the arrangement of elements and the number of elements are not limited to the illustrated example.

  Further, the semiconductor element 166 may be another element such as a light emitting element (for example, a laser diode) other than an LED, a light receiving element, and a drive circuit element such as a transistor circuit.

<Second Embodiment>
FIG. 6 is a plan view schematically showing a semiconductor composite device 200 according to the second embodiment of the present invention. FIG. 7 is a cross-sectional view schematically showing a plane taken along line S ₇ -S ₇ in FIG.

  6 and 7, in the semiconductor composite device 200 according to the second embodiment, the connection wiring 219 extending from the drive integrated circuit region 212 side is provided on the metal layer 240 to which the semiconductor thin film 260 is bonded. It differs from the semiconductor composite device 100 according to the first embodiment in that it is provided at a plurality of locations and a common potential is supplied from the plurality of connection wirings 219 to the metal layer 240.

  In the second embodiment, the configurations 210 to 218 correspond to the configurations 110 to 118 in the first embodiment, respectively. In the second embodiment, the configurations 240, 260, 266, 270, 271, and 280 correspond to the configurations 140, 160, 166, 170, 171, and 180 in the first embodiment, respectively.

  The connection wiring 219 is, for example, a wiring that is formed in a part of the multilayer wiring layer and is not exposed on the chip surface. The connection wiring 219, the individual wiring pad 215, the connection wiring 216, and the individual output pad 217 are layers made of one material selected from, for example, Al, Cu, Si, Ni, Cr, Ti, and W. Alternatively, it can be formed of a layer composed of a laminated material including a plurality of materials selected from the above materials, an alloy material, or a mixed material.

  The semiconductor thin film 260 has the same structure as that of the first embodiment. In addition, the method for manufacturing the semiconductor composite device 200 according to the second embodiment can use the same method as in the first embodiment.

  As shown in FIG. 6, a plurality of connection wirings 219 connected to the metal layer 240 are provided. For this reason, the semiconductor composite device 200 according to the second embodiment performs drive control by supplying a large amount of current to each semiconductor element 266, or the number of semiconductor elements 266 even if the current flowing to each semiconductor element 266 is small. Even when the total current is large, the current flowing through the metal layer 240 does not cause a voltage drop that may affect device driving.

  As described above, according to the second embodiment, in the configuration in which the semiconductor thin film 260 including the semiconductor element 266 is bonded on the metal layer 240, the connection region 220 connected to the metal layer 240 supplying the common potential is provided. A plurality of semiconductor thin films 260 are provided in the bonded region, and are connected to the connection wiring 219 so as to supply a common potential. Since the connection pad 218a for supplying the common potential is provided on the side of the driving integrated circuit region 212 with respect to the semiconductor thin film 260, in addition to the effects obtained in the first embodiment, the chip of the semiconductor composite device 200 The effect that a width | variety can be made narrower can be acquired.

  Further, according to the second embodiment, since the wire bonding portion is integrated on one side of the semiconductor thin film 260, the bonding operation is facilitated.

  In FIG. 6, the connection wiring 219 and the connection area 220 having the common potential are provided by using regions other than the individual wiring pad 215, the individual output pad 217, or the connection wiring 216. By providing an appropriate interlayer insulating structure depending on the structure, the connection wiring 219 and the connection region 220 may be formed so as to overlap with the connection wiring 216 in the vertical direction of the stacked structure.

  6 shows the case where the common potential connection pad 218a is provided in the end region of the chip, it can be provided in an appropriate position as appropriate.

  In the second embodiment, points other than those described above are the same as in the case of the first embodiment.

<Third Embodiment>
FIG. 8 is a plan view schematically showing a semiconductor composite device 300 according to the third embodiment of the present invention. FIG. 9 is a cross-sectional view schematically showing a plane taken along line S ₉ -S ₉ in FIG.

  As shown in FIGS. 8 and 9, the semiconductor composite device 300 according to the third embodiment includes a plurality of connection wirings 319 extending from the drive integrated circuit region 312 side to the metal layer 340 bonding the semiconductor thin film 360. The semiconductor integrated device 100 according to the first embodiment is different from the first embodiment in that a common potential is supplied from the plurality of connection wirings 319.

  In the third embodiment, the configurations 310 to 318 correspond to the configurations 110 to 118 in the first embodiment, respectively. In the third embodiment, the configurations 340, 360, 366, 370, 371, and 380 correspond to the configurations 140, 160, 166, 170, 171 and 180 in the first embodiment, respectively.

  The connection wiring 319 is, for example, a wiring that is formed in a part of the multilayer wiring layer and is not exposed on the chip surface. The connection wiring 319, the individual wiring pad 315, the connection wiring 316, and the individual output pad 317 are layers made of one material selected from, for example, Al, Cu, Si, Ni, Cr, Ti, and W. Alternatively, it can be formed of a layer composed of a laminated material including a plurality of materials selected from the above materials, an alloy material, or a mixed material.

  In the third embodiment, the bonding area of the semiconductor thin film 360 is provided in an area on the Si substrate 311 where the integrated circuit is not formed, and the lower metal layer 341 is formed by the wiring layer of the integrated circuit. Since the lower metal layer 341 uses a wiring layer used when forming an integrated circuit on the Si substrate 311, for example, an Al wiring is used. A metal layer 340 having a shape similar to that of the upper semiconductor thin film 360 and slightly larger is formed.

  Here, since the lower metal layer 341 and the metal layer (the metal layer made of a material such as Au) 340 are in electrical contact with each other in a connection area having a large area, the connection failure is eliminated and the space between them is reduced. It becomes possible to connect with resistors, and the number of connection points and pads can be reduced.

  The semiconductor thin film 360 has the same structure as that of the first embodiment. Moreover, the manufacturing method of the semiconductor composite device 300 according to the third embodiment can use the same method as in the first embodiment.

  As shown in FIG. 8, a plurality of connection wirings 319 connected to the metal layer 340 are provided. When driving and controlling a large amount of current through each semiconductor element 366, or a current flowing through each semiconductor element 366 is small. Even if the number of individual elements is large and the total current is large, the semiconductor composite device 300 according to the third embodiment does not generate a voltage drop that has an influence on element driving due to the current flowing through the metal layer 340. It has become.

  As described above, according to the third embodiment, in the form in which the semiconductor thin film 360 provided with the semiconductor element 366 is bonded on the metal layer 340, the connection wiring 319 connected to the metal layer 340 supplying the common potential is provided. A plurality of semiconductor thin films 360 are provided in a region where the semiconductor thin film 360 is bonded so as to supply a common potential. Since the common electrode pad 318a connected to the connection wiring 319 for supplying the common potential is provided on the side of the driving integrated circuit region 312 with respect to the semiconductor thin film 360, in addition to the effect obtained in the first embodiment. Thus, the effect that the chip width of the semiconductor composite device 300 can be further reduced can be obtained.

  In the third embodiment, the lower metal layer 341 that forms the common potential connection region is continuously provided with respect to the metal layer 340, and the layer of the connection region (lower metal layer 341) is, for example, a multi-layer. It can be included in a part of the wiring layer. Further, since the connection region layer can be formed thick, the resistance of the connection layer can be reduced.

  In the third embodiment, points other than the above are the same as those in the first or second embodiment.

<Fourth Embodiment>
FIG. 10 is a plan view schematically showing a semiconductor composite device 400 according to the fourth embodiment of the present invention. FIG. 11 is a cross-sectional view schematically showing a plane taken along line S ₁₁ -S ₁₁ in FIG.

  The semiconductor composite device 400 according to the fourth embodiment supplies a common potential via a wiring connected to the back surface of the substrate 411 formed using a through hole penetrating the Si substrate 411 in a form in which a common potential is supplied. This is different from the semiconductor composite device 100 according to the first embodiment.

  In the fourth embodiment, the configurations 410 to 418 correspond to the configurations 110 to 118 in the first embodiment, respectively. In the fourth embodiment, the configurations 440, 460 to 466, 470, 471, and 480 correspond to the configurations 140, 160 to 166, 170, 171, and 180 in the first embodiment, respectively.

  In the fourth embodiment, the conductive layer 452 on the back surface side of the Si substrate 411, the plurality of through wirings 451 provided in the plurality of through holes of the Si substrate 411, and the conductive layer 450 on the surface side of the Si substrate 411 are used. A common potential is supplied to the metal layer 440. The plurality of through holes of the Si substrate 411 can be formed by, for example, reactive ion etching. Further, the plurality of through wires 451 can be formed by, for example, a Cu-CVD method so as to fill the plurality of through holes. The through wiring 451 may be made of a metal other than Cu, or may be formed by a method other than the CVD method.

  As described above, according to the fourth embodiment, since the common potential is supplied from the back surface of the substrate 411, in addition to the effects obtained in the first embodiment, the connection form with the external circuit is changed to wire bonding or the like. Thus, it is possible to easily form the structure without connection, to save the connection process, and to improve the reliability of the connection.

  In the fourth embodiment, points other than the above are the same as those in the first to third embodiments.

<Fifth Embodiment>
FIG. 12 is a plan view schematically showing a semiconductor composite device 500 according to the fifth embodiment of the present invention. FIG. 13 is a cross-sectional view schematically showing a plane taken along line S ₁₃ -S ₁₃ of FIG.

  In the semiconductor composite device 500 according to the fifth embodiment, the common electrode of the semiconductor element 566 of the semiconductor thin film 560 is provided on the surface side (upper surface in FIG. 13) of the semiconductor thin film 560, and the conductive layer 590, the metal layer 540, The difference from the semiconductor composite device 100 according to the first embodiment is that a common potential is supplied using the connection region 520, the connection wiring 519, and the common electrode pad 518a.

  In the fifth embodiment, the configurations 510 to 518 correspond to the configurations 510 to 518 in the first embodiment, respectively. In the fifth embodiment, the configurations 540, 560, 566, 570, 571, and 580 correspond to the configurations 140, 160, 166, 170, 171, and 180 in the first embodiment, respectively.

  In the fifth embodiment, the conductive layer 590 is, for example, a laminated film including one or more elements selected from Au, Ge, Ni, Pt, Ti, Pd, ln, Al, Cu, Cr, and Si. Or it is the material which consists of an alloy. The form of the other region can be the same as the form described in the first to fourth forms.

  In the fifth embodiment, a strip-like conductive layer (metal layer) 590 is provided on the surface side of the semiconductor thin film 560 (upper surface in FIG. 13) in the common potential region of the semiconductor element 566 of the semiconductor thin film 560. . This is preferably provided continuously along the longitudinal direction of the semiconductor thin film 560. The conduction paths at this time are the surface of the semiconductor thin film 560, the band-shaped conductive layer 590 along the surface of the semiconductor thin film, the band-shaped metal layer 540 on the lower surface of the semiconductor thin film 560, and the common electrode wiring 519 of the multilayer wiring layer.

  A region for forming a contact with the conductive layer 590 on the semiconductor thin film 560 (the upper surface of the semiconductor thin film 560 in FIG. 13) is a semiconductor layer made of a material in which a metal layer and a low-resistance contact are formed. GaAs layer.

  As described above, according to the fifth embodiment, since the contact with the electrode (conductive layer 590) is formed on a surface different from the bonding surface of the semiconductor thin film 560, the bonding configuration and state of the back surface of the semiconductor thin film 560 are formed. Therefore, the electrical characteristics of the semiconductor element 566 included in the semiconductor thin film 560 can be controlled. For example, characteristic variations caused by variations in driving voltages of a large number of semiconductor elements can be reduced.

  FIG. 14 is a cross-sectional view showing a modification of the semiconductor composite device according to the fifth embodiment of the present invention. The modification of FIG. 14 is different from the case of FIG. 13 in that an insulating layer 591 such as a dielectric thin film is provided between the metal layer 540 and the semiconductor thin film 560.

  Although not shown, the wiring layer 519 may be extended below the conductive layer 590 so that the conductive layer 590 and the wiring layer 519 are connected without using the metal layer 40.

  Furthermore, the form in which the common contact region is formed on the upper surface of the semiconductor thin film as in the fifth embodiment can be applied to other embodiments.

  In the fifth embodiment, the points other than the above are the same as those in the first to fourth embodiments.

<Sixth Embodiment>
FIG. 15 is a plan view schematically showing a semiconductor composite device 600 according to the sixth embodiment of the present invention. 16 is a cross-sectional view schematically showing a plane cut along line S ₁₆ -S ₁₆ in FIG. 15. FIG. 17 is a cross-sectional view schematically showing a plane cut along line S ₁₇ -S _{17 in} FIG. FIG.

  As shown in FIGS. 15 to 17, in the semiconductor composite device 600 according to the sixth embodiment, a plurality of metal layers 640 are arranged on the integrated circuit substrate 610, and each of the plurality of metal layers 640 is disposed on the integrated circuit substrate 610. A semiconductor thin film 660 (having one semiconductor element) is bonded to the metal layer 640, the metal layer 640 is connected to the connection wiring 615 and the individual input pad 617, and the metal layer 640 is used as an individual electrode layer for supplying a driving potential. On the integrated circuit substrate 610, a connection region 650 for supplying a common potential from the outside, an interlayer insulating film 670 having a contact opening on the semiconductor thin film 660, a semiconductor thin film 660, and a connection region 650 are provided. A transparent electrode layer 680 that is electrically connected is provided. The transparent conductive film 680 having a contact with the upper surface of each semiconductor thin film is an oxide conductive film layer such as an indium tin oxide film layer (ITO) or a zinc oxide layer (Zn0).

  As shown in FIG. 15, the metal layers 640 are individually divided and connected to the individual outputs of the drive integrated circuit 612 via conduction paths 615, 616, 617, and 617a as shown in FIG. The semiconductor thin film 660 is also divided for each semiconductor element 666. Thus, in the sixth embodiment, the common electrode 680 is provided on the upper surface of the semiconductor thin film 660 (the upper surface in FIG. 16), and a plurality of connection regions 650 for supplying a common potential to the common electrode (transparent electrode) 680 are provided. Provided.

  About another form, it can be set as the form equivalent to the said other embodiment. About a semiconductor thin film, it can be set as the desired element structure suitably about the element structure which a semiconductor thin film contains except having set it as the form divided | segmented separately.

  As described above, according to the sixth embodiment, since the transparent electrode 680 for supplying a common potential is provided on the upper surface of the semiconductor thin film 660 and the plurality of common potential connection regions 650 are provided, the influence of the voltage drop is reduced. In addition, the drive control of the semiconductor element can be performed satisfactorily.

  In this way, by using the transparent electrode as a common electrode, it is possible to connect to the electrode of the semiconductor thin film with a wide wiring layer and to connect with the bonding pad in a wide area, so that it is connected to the semiconductor thin film with a low resistance value. Is possible.

<Modifications of First to Sixth Embodiments>
The semiconductor thin film described in the first to sixth embodiments is not necessarily peeled off from the substrate for forming the semiconductor thin film and bonded to the integrated circuit substrate. The semiconductor thin film is not formed on the substrate constituting the semiconductor composite device. It may be manufactured by another method capable of forming a semiconductor thin film. The semiconductor thin film may be formed by etching or polishing and removing after bonding. Therefore, the present invention is not limited to the semiconductor thin film manufacturing method described in the first embodiment.

<Seventh Embodiment>
FIG. 18 is a plan view schematically showing a semiconductor composite device 700 according to the seventh embodiment of the present invention.

  As shown in FIG. 18, the semiconductor composite apparatus 700 according to the seventh embodiment includes a mounting board (for example, a glass epoxy laminated board) 701 and a mounting board for inputting an input signal for driving control and a power source. A connection region 702 provided on the substrate 701, a connection region 703 provided on the mounting substrate 701 for supplying a common potential (for example, a GND potential) of the semiconductor thin film, and a semiconductor composite chip (first or sixth embodiment). (The semiconductor composite device of the first or second embodiment is shown in FIG. 18.) Bonding for connecting the input pad 705 and the connection region 702 of the semiconductor composite chip 704 to each other. A wire 706 and a bonding wire 708 for connecting the common electrode pad 707 of the semiconductor composite chip 704 and the connection region 703 are provided.

  According to the semiconductor composite device 700 according to the seventh embodiment, the semiconductor composite chip 704 is mounted on the mounting substrate 701 and the common potential is supplied to the semiconductor elements of the semiconductor composite chip 704 from a plurality of locations. Even when the total current flowing through the element is large, fluctuations and variations in the common potential due to a voltage drop in the chip can be reduced, and the effect that the element can be driven and controlled satisfactorily can be obtained.

<Eighth Embodiment>
FIG. 19 is a plan view schematically showing a semiconductor composite device 800 according to the eighth embodiment of the present invention.

  As shown in FIG. 19, the semiconductor composite apparatus 800 according to the eighth embodiment includes a mounting board (for example, a glass epoxy laminated board) 801 and a mounting board for inputting an input signal and power supply for driving control. A connection region 802 provided on 801, a connection region 803 provided on a mounting substrate 801 for supplying a common potential (for example, a GND potential) of the semiconductor thin film, and a semiconductor composite chip (second or third implementation). 804, a bonding wire 806 that connects the input pad 805 and the connection region 802 of the semiconductor composite chip 804, and a bonding wire that connects the common electrode pad 807 and the connection region 803 of the semiconductor composite chip 804. 808.

  According to the semiconductor composite device 800 according to the eighth embodiment, the semiconductor composite chip 804 is mounted on the mounting substrate 801 and the common potential is supplied to the semiconductor elements of the semiconductor composite chip 804 from a plurality of locations. Even when the total current flowing through the element is large, fluctuations and variations in the common potential due to a voltage drop in the chip can be reduced, and the effect that the element can be driven and controlled satisfactorily can be obtained.

<Ninth Embodiment>
FIG. 20 is a plan view schematically showing a semiconductor composite device 900 according to the ninth embodiment of the present invention.

  As shown in FIG. 20, the semiconductor composite device 900 according to the ninth embodiment includes a mounting substrate (for example, a glass epoxy laminated substrate) 901 and a mounting substrate for inputting an input signal and power supply for driving control. A connection region 902 provided on the mounting substrate 901; a connection region 903 provided on the mounting substrate 901 for supplying a common potential (for example, a GND potential) of the semiconductor thin film; and a semiconductor composite chip (semiconductor of the fourth embodiment). Composite device) 904, and bonding wires 906 that connect the input pads 905 and the connection regions 902 of the semiconductor composite chip 904. As described in the fourth embodiment, the semiconductor composite chip 904 includes a conductive layer on the back surface thereof, and the conductive layer is connected to the common electrode pad 907 by wiring in the through hole.

  According to the semiconductor composite device 900 according to the ninth embodiment, the semiconductor composite chip 904 is mounted on the mounting substrate 901 and the common potential is supplied to the semiconductor elements of the semiconductor composite chip 904 from a plurality of locations. Even when the total current flowing through the element is large, fluctuations and variations in the common potential due to a voltage drop in the chip can be reduced, and the effect that the element can be driven and controlled satisfactorily can be obtained.

  Further, the common potential can be taken from the back surface of the semiconductor composite chip, and it is not necessary to form a separate wire connection for the connection for the common potential.

  In addition, it can replace with the semiconductor compound apparatus of 4th Embodiment, and can also provide the semiconductor compound apparatus of 5th Embodiment.

<Tenth Embodiment>
FIG. 21 is a cross-sectional view schematically showing an LED head 1000 incorporating a semiconductor composite device according to the tenth embodiment of the present invention.

  As shown in FIG. 21, the LED print head 1000 has a base member 1001, an LED unit (printed circuit board) 1002 fixed to the base member 1001, and an LED chip 1002a fixed thereon, and a large number of columnar optical elements. It has a rod lens array 1003, a lens holder 1004 that holds the rod lens array 1003, and a clamper 1005 that fixes these components 1001 to 1004. An LED chip 1002a according to the tenth embodiment includes the LED array according to any one of the first to sixth embodiments. The lens holder 1004 is formed so as to cover the base member 1001 and the LED unit 1002. The base member 1001, the LED unit 1002, and the lens holder 1004 are sandwiched and integrated by a clamper 1005 provided through openings 1001a and 1004a formed in the base member 1001 and the lens holder 1004.

  Therefore, the light generated by the LED unit 1002 is applied to a predetermined external member through the rod lens array 1003. This LED head can be used as an exposure apparatus such as an electrophotographic printer or an electrophotographic copying apparatus.

  As described above, according to the LED head according to the tenth embodiment, the fluctuation and variation of the common potential due to the voltage drop in the chip can be reduced, and the element can be driven and controlled satisfactorily. As a result, luminance variation for each element can be reduced.

<Eleventh embodiment>
FIG. 22 is a block diagram schematically showing an image forming apparatus according to the eleventh embodiment of the present invention.

  As shown in FIG. 22, an image forming apparatus 1100 according to the eleventh embodiment uses an electrophotographic method for images of each color of yellow (Y), magenta (M), cyan (C), and black (K). The four process units 1101 to 1104 are formed. The process units 1101 to 1104 are arranged in tandem along the conveyance path of the recording medium 1105. Each of the process units 1101 to 1104 includes a photosensitive drum 1103a as an image carrier, a charging device 1103b that is disposed around the photosensitive drum 1103a and charges the surface of the photosensitive drum 1103a, and a charged photosensitive drum. And an exposure device 1103c that forms an electrostatic latent image by selectively irradiating light on the surface of 1103a. As the exposure apparatus 1103c, the LED print head 1000 described with reference to FIG. 21 is used, and the LED print head 1000 includes the semiconductor composite apparatus described in the first to ninth embodiments. Yes.

  In the image forming apparatus 1100, a developing device 1103d that conveys toner to the surface of the photosensitive drum 1103a on which the electrostatic latent image is formed, and a cleaning device 1103e that removes toner remaining on the surface of the photosensitive drum 1103a. have. The photosensitive drum 1103a is rotated in the direction of the arrow by a driving mechanism (not shown) including a driving source and a gear. In addition, the image forming apparatus 1100 includes a paper cassette 1106 for storing a recording medium 1105 such as paper, and a hopping roller 1107 for separating and transporting the recording medium 1105 one by one. The pinch rollers 1108 and 1109 and the recording medium 1105 are sandwiched downstream of the hopping roller 1107 in the recording medium 1105 conveyance direction, and the skew of the recording medium 1105 is corrected together with the pinch rollers 1108 and 1109 and conveyed to the process units 1101 to 1104. Registration rollers 1110 and 1111 are provided. The hopping roller 1107 and the registration rollers 1110 and 1111 rotate in conjunction with a driving source (not shown).

  Further, the image forming apparatus 1100 includes a transfer roller 1112 disposed to face the photosensitive drum 1103a. The transfer roller 1112 is made of semiconductive rubber or the like. The potential of the photosensitive drum 1103a and the potential of the transfer roller 1112 are set so that the toner image on the photosensitive drum 1103a is transferred onto the recording medium 1105. Further, the image forming apparatus includes a fixing device 1113 for fixing the toner image on the recording medium 1105 by heating and pressing, and rollers 1114, 1116, 1115, and 1117 for discharging the recording medium 1105 that has passed through the fixing device 1113. Is provided.

  The recording media 1105 loaded on the paper cassette 1106 are separated and conveyed one by one by a hopping roller 1107. The recording medium 1105 passes through the registration rollers 1110 and 1111 and the pinch rollers 1108 and 1109 and passes through the process units 1101 to 1104 in this order. In each of the process units 1101 to 1104, the recording medium 1105 passes between the photosensitive drum 1103 a and the transfer roller 1112, and the toner images of each color are sequentially transferred and overheated and pressurized by the fixing device 1113, and the toner of each color. The image is fixed on the recording medium 1105. Thereafter, the recording medium 1105 is discharged to the stacker unit 1118 by the discharge roller. The structure of the image forming apparatus including the first to ninth semiconductor devices or the optical print head of FIG. 21 is not limited to that shown in FIG.

  According to the image forming apparatus 1100 of the eleventh embodiment, since the LED print head 1000 of FIG. 21 is used, a high-quality image can be formed with excellent light emission characteristics with small variations in luminance for each element. Further, the space efficiency can be improved and the material cost can be greatly reduced by downsizing the exposure apparatus. Further, the present invention can be applied to a monochrome printer, but it can be particularly effective in a full color printer provided with a plurality of exposure apparatuses.

1 is a plan view schematically showing a semiconductor composite device according to a first embodiment of the present invention. The surface cut 1 in S ₂ -S ₂ line is a sectional view schematically showing. It is sectional drawing which expands and shows the semiconductor thin film with which the conductive layer on an integrated circuit board was equipped. It is sectional drawing for demonstrating the manufacturing method of a semiconductor thin film. It is sectional drawing for demonstrating the manufacturing method of another semiconductor thin film. It is a top view which shows roughly the semiconductor compound apparatus concerning the 2nd Embodiment of this invention. The surface cutting to Figure 6 S ₇ -S ₇ line is a sectional view schematically showing. It is a top view which shows roughly the semiconductor compound apparatus concerning the 3rd Embodiment of this invention. The surface cutting to Figure 8 S ₉ -S _9-wire is a sectional view schematically showing. It is a top view which shows roughly the semiconductor compound apparatus concerning the 4th Embodiment of this invention. A surface cut 10 in _S 11 _{-S 11} line is a sectional view schematically showing. FIG. 9 is a plan view schematically showing a semiconductor composite device according to a fifth embodiment of the present invention. A surface cut 12 in _S 13 _{-S 13} line is a sectional view schematically showing. It is sectional drawing which shows roughly the modification of the semiconductor compound apparatus which concerns on 5th Embodiment. FIG. 10 is a plan view schematically showing a semiconductor composite device according to a sixth embodiment of the present invention. A surface cut 15 in _S 16 _{-S 16} line is a sectional view schematically showing. A surface cut 15 in _S 17 _{-S 17} line is a sectional view schematically showing. FIG. 9 is a plan view schematically showing a semiconductor composite device according to a seventh embodiment of the present invention. It is a top view which shows roughly the semiconductor compound apparatus concerning the 8th Embodiment of this invention. It is a top view which shows roughly the semiconductor compound apparatus concerning the 9th Embodiment of this invention. It is sectional drawing which shows schematically the LED print head which concerns on the 10th Embodiment of this invention. It is a block diagram which shows schematically the image forming apparatus which concerns on the 11th Embodiment of this invention.

Explanation of symbols

100, 200, 300, 400, 500, 600 Semiconductor composite device (semiconductor composite chip),
111, 211, 311, 411, 511, 611 substrate,
112, 212, 312, 412, 512, 612 integrated circuit area,
113, 213, 313, 413, 513, 613 multilayer wiring region,
114, 214, 314, 414, 514, 614 laminated film region,
115, 215, 315, 415, 515, 615, pads for individual wiring,
116, 216, 316, 416, 516, 616 connection wiring,
117, 217, 317, 417, 517 individual output pads,
617 Individual input pad,
118, 218, 318, 418, 518, 618 input pads,
110, 210, 310, 410, 510, 610 integrated circuit board,
140, 240, 340, 440, 540, 640 conductive layer (metal layer),
150,650 bonding pad (electrode pad),
160, 160b Semiconductor thin film (semiconductor epitaxial film),
160a semiconductor thin film layer,
161, 161b, 461 Lower contact layer,
162, 162b, 462 Lower cladding layer,
163, 163b, 463 active layer,
164, 164b, 464 upper cladding layer,
165, 165b, 465 upper contact layer,
166, 266, 366, 466, 566, 666 semiconductor element,
167 region forming ohmic contact,
168 selective diffusion region,
169 Diffusion front,
170, 270, 370, 470, 570, 670 interlayer insulation film,
171 opening,
180 Individual wiring,
218a, 318a, 518a common electrode pad,
219, 319, 519 connection wiring,
220, 520 connection area,
341 Lower electrode layer,
451 through wiring,
452 Conductive layer on the back side,
590 strip-shaped conductive layer,
591 insulation layer,
650 connection area,
680 common electrode,
700, 800, 900 Semiconductor composite device,
701, 801, 901 glass epoxy substrate,
1000 print heads,
1100 Image forming apparatus.

Claims (22)

A circuit board;
A conductive layer provided on the circuit board;
A common electrode portion electrically connected to a plurality of portions of the conductive layer and supplying a common potential to the conductive layer;
A semiconductor composite device comprising: a semiconductor thin film having one or more semiconductor elements provided on the circuit board and electrically connected to the conductive layer. The semiconductor thin film is disposed on the conductive layer;
The semiconductor composite device according to claim 1, wherein the common electrode portion has a plurality of electrode pads electrically connected to a plurality of portions of the conductive layer. The semiconductor thin film is disposed on the conductive layer;
The common electrode part is
A plurality of electrode wirings electrically connected to a plurality of locations of the conductive layer;
The semiconductor composite device according to claim 1, further comprising: an electrode pad connected to each of the plurality of electrode wirings. The circuit board has a plurality of through holes,
The common electrode part is
A plurality of through wires provided in the plurality of through holes and electrically connected to a plurality of locations of the conductive layer;
The semiconductor composite device according to claim 1, further comprising: a back electrode provided on a surface of the circuit board opposite to the semiconductor thin film. The semiconductor thin film has a common potential region,
The common electrode part is
A wiring layer connecting the common potential region of the semiconductor thin film and the conductive layer;
A plurality of electrode wirings electrically connected to a plurality of locations of the conductive layer;
The semiconductor composite device according to claim 1, further comprising: an electrode pad connected to each of the plurality of electrode wirings.   6. The semiconductor composite device according to claim 5, further comprising an interlayer insulating film between the semiconductor thin film and the conductive layer. A plurality of the conductive layers;
A plurality of the semiconductor thin films;
Each of the plurality of semiconductor thin films has a common potential region,
The semiconductor composite device according to claim 1, wherein the common electrode section includes a plurality of electrode pads, and a wiring layer that connects a common potential region of the plurality of semiconductor thin films and the conductive layer.   The semiconductor composite device according to claim 1, wherein the conductive layer is a metal layer.   9. The metal layer according to claim 8, wherein the metal layer is made of a material containing one or more elements selected from Ti, Pt, Au, Ge, Ni, ln, and Cr. Semiconductor composite device.   5. The semiconductor composite device according to claim 2, wherein the semiconductor thin film has a common potential region on the conductive layer side.   8. The semiconductor composite device according to claim 5, wherein the semiconductor thin film has a common potential region on the opposite side of the conductive layer.   The semiconductor composite device according to claim 1, wherein the semiconductor thin film includes a heteroepitaxial laminated structure.   The semiconductor composite device according to claim 12, wherein the heteroepitaxial multilayer structure includes a heterojunction formed by epitaxial growth.   The semiconductor composite device according to claim 12, wherein the heteroepitaxial stacked structure includes a heterojunction formed by diffusing a second conductivity type impurity in the first conductivity type epitaxial layer.   15. The semiconductor composite device according to claim 1, wherein the semiconductor element is a light emitting element.   The semiconductor composite device according to claim 15, wherein the light emitting element is a light emitting diode. A plurality of the light emitting elements,
The semiconductor composite device according to claim 16, wherein the plurality of light emitting elements constitute a light emitting diode array.   18. The semiconductor composite device according to claim 1, wherein the circuit board includes a driving integrated circuit for driving and controlling the semiconductor element.   The semiconductor composite device according to claim 1, wherein the semiconductor element is a light receiving element. A mounting board;
A semiconductor composite device comprising: a semiconductor composite chip having the same configuration as that of the device according to any one of claims 1 to 19 mounted on the mounting substrate. A semiconductor composite device according to claim 20,
An optical element mounted so as to face the semiconductor composite device. A print head according to claim 21;
And an image carrier on which an electrostatic latent image is formed by light irradiation from the print head.

Images