JP2006261641A - Semiconductor package assembly - Google Patents

Semiconductor package assembly Download PDF

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Publication number
JP2006261641A
JP2006261641A JP2006013706A JP2006013706A JP2006261641A JP 2006261641 A JP2006261641 A JP 2006261641A JP 2006013706 A JP2006013706 A JP 2006013706A JP 2006013706 A JP2006013706 A JP 2006013706A JP 2006261641 A JP2006261641 A JP 2006261641A
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JP
Japan
Prior art keywords
bump
linear dimension
package assembly
semiconductor package
conductive pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006013706A
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Japanese (ja)
Inventor
Szu Wei Lu
思維 盧
Hsin-Hui Lee
新輝 李
Chuyu O
忠裕 王
Mirng-Ji Lii
明機 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of JP2006261641A publication Critical patent/JP2006261641A/en
Pending legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a bump pad for a flip chip that is resistant to occurrence of a crack even if a non-lead or high concentration lead bump is employed. <P>SOLUTION: The semiconductor package assembly 23 comprises a first conductive pad 8 on a semiconductor substrate 2, a second conductive pad 16 on a package board 12, and a bump 10 physically bound between the first conductive pad 8 and the second conductive pad 16. In this construction, the bump 10 is non-lead, or substantially contains a high concentration lead, and has a first contact surface with the first conductive pad 8, the first contact surface having a first linear size. Furthermore, the bump 10 has a second contact surface with the second conductive pad 16 which has a second linear size. The ratio of the first linear size and the second linear size is set to be between about 0.7 and about 1.7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、広く集積回路のパッケージ化に関するものであり、特にフリップ・チップ・パッケージ用の導電性バンプの形成方法に関するものである。   The present invention relates generally to integrated circuit packaging, and more particularly to a method of forming conductive bumps for flip chip packages.

フリップ・チップ超小型電子部品は、表面を下に向けた（すなわち、反転された）電子部品を、基板上に直接電気的接続をするものであり、この基板は、チップの導電性バンプ・ボンド・パッドを使用するセラミック基板，回路基板，或いは基材（キャリア）などである。フリップ・チップ技術は、配線がチップ上の各パッドに接続された状態で、上を向いたチップを使用する旧式のワイヤー・ボンディング技術に対して、急速に取って代わりつつある。   A flip chip microelectronic component is an electrical connection of a surface-down (ie flipped) electronic component directly onto a substrate, which is the conductive bump bond of the chip. -Ceramic substrates, circuit boards, or base materials (carriers) that use pads. Flip chip technology is rapidly replacing old wire bonding technology that uses chips facing up with wires connected to each pad on the chip.

フリップ・チップ超小型電子部品に使用されるフリップ・チップ部品は、大部分が半導体デバイスであるが、受動型フィルタや検出器アレイなどの部品や記憶装置も、またフリップ・チップ形式で使用されつつある。フリップ・チップは、他の組立方法の場合と比較した場合に、その高速電気性能の故に、有利性がある。ボンデイング・ワイヤを排除したことにより、配線のインダクタンスおよびキャパシタンスにおける遅れを減少させるとともに、電流経路を大幅に短縮して、高速のチップ外（オフ−チップ）配線を実現することになる。   Flip-chip components used for flip-chip microelectronic components are mostly semiconductor devices, but components and storage devices such as passive filters and detector arrays are also being used in flip-chip format. is there. Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. By eliminating the bonding wire, the delay in wiring inductance and capacitance is reduced, and the current path is greatly shortened to realize high-speed off-chip wiring.

フリップ・チップは、また最も厳格な機械的接続法を提供する。エポキシなどの接着剤でアンダーフィルされた場合、フリップ・チップは、最も厳しい耐久力テストに耐えることができる。さらに、フリップ・チップは、自動式大量生産の場合に、最低のコストで配線が可能である。   Flip chips also provide the most stringent mechanical connection method. When underfilled with an adhesive such as epoxy, flip chips can withstand the most demanding durability tests. Furthermore, flip chips can be wired at the lowest cost for automated mass production.

フリップ・チップは、一般的に、ソルダー・バンプをシリコン・チップ上に設置することより作成される。ソルダー・バンプ・フリップ・チップ工程は、一般的に、四つの連続する段階から成っている。１）ソルダー・バンプの作成のためのチップの用意、２）チップ上へソルダー・バンプの形成、或いは設置、３）ソルダー・バンプを形成されたチップの、ボード，基板，或いは基材への取り付け、４）接着用アンダーフィルの使用による部品の完成。フリップ・チップ部品のバンプは、数種の機能を有する。バンプは、チップ（またはダイ）から、チップが搭載される基板へ至る導電経路を提供する。熱伝導経路もまた、バンプにより設けられて、チップから基板に熱を伝達する。バンプはまた、チップの基板への機械的な取り付け部の一部を提供する。最終的に、バンプはリード線長が短いので、チップと基板間の機械的歪みを軽減する。   A flip chip is typically created by placing solder bumps on a silicon chip. The solder bump flip chip process generally consists of four successive stages. 1) Preparation of chip for creating solder bump 2) Formation or installation of solder bump on chip 3) Mounting of solder bump formed chip on board, substrate or base material 4) Completion of parts by use of adhesive underfill. The bumps of the flip chip component have several functions. The bumps provide a conductive path from the chip (or die) to the substrate on which the chip is mounted. A heat conduction path is also provided by the bumps to transfer heat from the chip to the substrate. The bumps also provide part of the mechanical attachment of the chip to the substrate. Finally, the bump has a short lead wire length, thus reducing mechanical distortion between the chip and the substrate.

通常、鉛（Pb）と錫（Sn）を含む共晶ソルダー材が、ソルダー・バンプとして使用される。共晶ソルダーを含んでいる通常使用される鉛は、約63％の錫（Sn）と37％の鉛（Pb）を有する。この組み合わせにより、適切な融点と低い電気抵抗を有するソルダー材が得られる。
特開２００５−１２９９５５号公報 Usually, a eutectic solder material containing lead (Pb) and tin (Sn) is used as a solder bump. Commonly used lead containing eutectic solder has about 63% tin (Sn) and 37% lead (Pb). By this combination, a solder material having an appropriate melting point and low electric resistance can be obtained.
JP 2005-129955 A

しかし、鉛は有毒材料である。法規および産業上の要件では、無鉛ソルダー・バンプを要求している。電子配線工業のサプライ・チェーンの会社は、Sn−Pbソルダーの代替を積極的に求めている。しかしながら、Sn―Ag、Sn―Ag―Cu、および、これらの金属間部材などの、一般的に既知となっている無鉛ソルダーは、非常に脆弱で、クラックに悩まされる。一方、高濃度鉛バンプは、また、高度の電子泳動性能における応用面で、業界で歓迎されている。鉛を追加すると、耐食性が増加し、純粋な錫におけるリフロー温度を下げ、純粋な錫の表面張力を下げる。高濃度鉛バンプは、また、脆弱で、それぞれクラックが生じ易い。   However, lead is a toxic material. Legal and industrial requirements require lead-free solder bumps. Electronic wiring industry supply chain companies are actively seeking an alternative to Sn-Pb solder. However, generally known lead-free solders such as Sn-Ag, Sn-Ag-Cu, and their intermetallic members are very fragile and plagued with cracks. On the other hand, high-concentration lead bumps are also welcomed in the industry for applications in advanced electrophoretic performance. Adding lead increases corrosion resistance, lowers the reflow temperature in pure tin, and lowers the surface tension of pure tin. High concentration lead bumps are also fragile and prone to cracking.

バンプのクラックは、主として、ストレスにより生じる。パッケージ・アセンブリにおける材料間の熱膨張係数（CTE）の不整合が、ストレス発生の主原因の１つである。例えば、シリコン基板は、通常、約３ppm/℃より高いCTEを有し、低誘電率体は、約20ppm/℃より高いCTEを有し、一方、パッケージ基板は約17ppm/℃より高いCTEを有する。CTEが著しく相違する場合に温度変化が起きると、構造に対してストレスを生じる。この問題に対する一つの解答は、チップと基板間の隙間を埋めるため、チップの片側または両側に液状エポキシを施す、アンダーフィル処理による方法がある。エポキシ・アンダーフィルは、ストレスを分散させ、ソルダー・バンプを保護する助けをする。   Bump cracks are mainly caused by stress. Mismatched coefficient of thermal expansion (CTE) between materials in the package assembly is one of the main causes of stress generation. For example, silicon substrates typically have a CTE greater than about 3 ppm / ° C, and low dielectric constants have a CTE greater than about 20 ppm / ° C, while package substrates have a CTE greater than about 17 ppm / ° C. . If temperature changes occur when the CTEs are significantly different, the structure is stressed. One solution to this problem is an underfill process in which liquid epoxy is applied to one or both sides of the chip to fill the gap between the chip and the substrate. Epoxy underfill helps disperse stress and protect solder bumps.

低誘電率体が集積回路に使用される場合、バンプと低誘電率体との両者を保護するにはジレンマが存在する。脆弱なバンプの保護には、強度の大きなアンダーフィルが必要とされる。しかし、低誘電率体は、強度の大きなアンダーフィル材料により悪影響を受け、層間剥離などの問題を生じる。   When a low dielectric constant is used in an integrated circuit, there is a dilemma to protect both the bump and the low dielectric constant. A strong underfill is required to protect fragile bumps. However, the low dielectric constant is adversely affected by a strong underfill material and causes problems such as delamination.

従って、低誘電率体が使用される場合には、好ましくは強度の大きなアンダーフィルを使用せずに、無鉛バンプと高濃度鉛バンプを保護する必要がある。バンプのクラック発生の問題に対する従来の解決法は、材料を中心に行われていた。従って、構造の観点からの解決法の検討は価値あるものとなる。本発明の好ましい実施例は、構造の変更による解決方法を提供するものである。   Therefore, when a low dielectric constant material is used, it is necessary to protect lead-free bumps and high-concentration lead bumps, preferably without using a strong underfill. Conventional solutions to the problem of bump cracking have been centered on materials. Therefore, consideration of the solution from a structural point of view is valuable. The preferred embodiment of the present invention provides a solution by changing the structure.

本発明の一つの特徴によれば、半導体パッケージアセンブリは、半導体基板上の導体パッド（第１の導電性パッド）或いはアンダー・バンプ・メタラージ（UBM）と、導体パッドの下部にあって、パッケージ基板の上部にあるバンプとから成り、このバンプは、このバンプと接触するバンプ・パッド（第２の導電性パッド）を有する。導体パッド／UBMとこのバンプ間には、上部接触面が存在し、このバンプとパッケージ基板のバンプ・パッド間に下部接触面が存在する。上部接触面および下部接触面の寸法は、ほぼ同程度である。バランスの取れた構造は、バンプ，中間金属部品と隣接材料に及ぼすストレスを軽減する。この結果得られるアセンブリの信頼性は、著しく改善される。   According to one aspect of the present invention, a semiconductor package assembly includes a conductive pad (first conductive pad) or an under bump metallurgy (UBM) on a semiconductor substrate and a lower portion of the conductive pad, the package substrate The bump has a bump pad (second conductive pad) in contact with the bump. An upper contact surface exists between the conductor pad / UBM and the bump, and a lower contact surface exists between the bump and the bump / pad of the package substrate. The dimensions of the upper contact surface and the lower contact surface are approximately the same. A balanced structure reduces stress on bumps, intermediate metal parts and adjacent materials. The reliability of the resulting assembly is significantly improved.

本発明の好ましい実施例には、無鉛および高濃度鉛含有バンプに対するクラック発生問題を解決するパッケージによる解決法を示すものである。この解決法は、現行のパッケージング処理と両立可能である。現行のパッケージング処理で行われている以上の取り組み、或いは、それ以上のコストは発生しない。また、バンプ保護のために、強度の高いアンダーフィルの使用を必要としないので、チップにおける低誘電率材料の損傷が回避される。   The preferred embodiment of the present invention shows a package solution that solves the cracking problem for lead-free and high-concentration lead-containing bumps. This solution is compatible with current packaging processes. There is no additional effort or cost beyond the current packaging process. Also, it is not necessary to use a strong underfill for bump protection, so that damage to the low dielectric constant material in the chip is avoided.

好ましい本実施例の製造および利用について、下記に詳述する。しかしながら、本発明は、さまざまな状況において具現され得る多くの発明の概念を、提供するものであることを理解されたい。検討する特定の実施例は、本発明を構成し利用するための特定の方法を、単に説明しているに過ぎず、本発明の範囲を限定するものではない。   The production and use of this preferred embodiment will be described in detail below. However, it should be understood that the present invention provides many inventive concepts that can be embodied in a variety of situations. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

本発明の好ましい実施例は、無鉛または高濃度鉛を含有するバンプを使用するパッケージ・アセンブリ構造を提示するものである。本発明の好ましい実施例は、図１から図４で説明する。本発明の種々の図および実施例の説明においては、一貫して同じ参照番号は同じ要素を示している。   The preferred embodiment of the present invention presents a package assembly structure that uses bumps containing lead-free or high-concentration lead. A preferred embodiment of the present invention is illustrated in FIGS. In the various figures and the description of the embodiments of the invention, like reference numerals designate like elements throughout.

好ましい実施例において、ソルダー・バンプは、集積回路を有しているチップ上に形成される。この他の実施例においては、ソルダー・バンプは、パッケージ基板上に形成される。図１は、導電性パッド上に形成されたソルダー・バンプ10を有する半導体基板２を示す。導電性パッドは、通常、アンダー・バンプ・メタライゼーション（UBM）８と称する。半導体基板２は、時には、チップ２と呼ぶ。半導体基板２は、通常、強度の低い低誘電率体から構成されるのが好ましい。約3.3未満のk値を有する少なくとも１つの低誘電率体層が、半導体基板２に含まれていることが好ましい。保護層４は、窒化物，酸化物，ポリイミドなどの誘電体材料から形成されるのが好ましく、これはチップ２の表面に形成される。導体パッド６は、半導体基板２における集積回路（図示なし）に電気的に接続され、銅、アルミニュウム、或いは、これらの合金などで形成されるのが好ましい。アンダー・バンプ・メタライゼーション層とも称せられ、導電性パッドであるアンダー・バンプ・メタライゼーション（UBM）８は、導体パッド６上に形成されるのが好ましい。UBM８は、導体パッド６とバンプ10間の良好な接着性を提供する。UBM８は、通常は、多数層から成る複合構造を有し、拡散阻止（バリア），ソルダー可溶性層，および酸化阻止としての機能を果たすものである。さらに、UBM８は、スパッタリング法，蒸発法，エレクトロ・プランティング法，或いはそれらに代わる方法で形成される。UBM８の多数層は、順次、蒸着により形成され、UBM８の最外部である可溶性層は、銅，ニッケル，パラディウム，或いはこれらの合金から成る導電性材料で、通常形成される。UBM８は、長さと幅がほぼ等しい正方形または長方形であるのが好ましい。UBM８における任意の２点間の最長距離は、直線寸法W1とも称し、約30μmと約200μmの間にあるのが好ましいが、約100μmであるのが、さらに好ましい。直線寸法を使用する場合、バンプ・パッドまたはUBMの形状は、正方形および長方形に限定はされず、任意の形状が可能である。直線寸法は、円の直径である。チップは、通常、多数の導体パッドと多数のバンプで構成される。バンプ間のピッチ、すなわち距離は、約100μmと300μmの間にあるのが好ましいが、約150μmと250μmであるのがさらに好ましい。 In the preferred embodiment, the solder bumps are formed on a chip having an integrated circuit. In other embodiments, the solder bumps are formed on the package substrate. FIG. 1 shows a semiconductor substrate 2 having solder bumps 10 formed on conductive pads. The conductive pad is usually referred to as under bump metallization (UBM) 8. The semiconductor substrate 2 is sometimes referred to as a chip 2. In general, the semiconductor substrate 2 is preferably composed of a low dielectric constant material having low strength. Preferably, the semiconductor substrate 2 includes at least one low dielectric constant layer having a k value less than about 3.3. The protective layer 4 is preferably formed from a dielectric material such as nitride, oxide or polyimide, which is formed on the surface of the chip 2. The conductor pad 6 is electrically connected to an integrated circuit (not shown) in the semiconductor substrate 2 and is preferably formed of copper, aluminum, or an alloy thereof. The under bump metallization (UBM) 8, which is also referred to as an under bump metallization layer and is a conductive pad, is preferably formed on the conductor pad 6. UBM 8 provides good adhesion between conductor pads 6 and bumps 10. The UBM 8 usually has a composite structure composed of multiple layers and functions as a diffusion barrier (barrier), a solder-soluble layer, and an oxidation barrier. Further, the UBM 8 is formed by a sputtering method, an evaporation method, an electro planting method, or a method in place of them. The multiple layers of UBM8 are sequentially formed by vapor deposition, and the soluble layer that is the outermost part of UBM8 is usually formed of a conductive material made of copper, nickel, palladium, or an alloy thereof. The UBM 8 is preferably a square or a rectangle having substantially the same length and width. The longest distance between any two points in UBM 8 is also referred to as linear dimension W 1 and is preferably between about 30 μm and about 200 μm, more preferably about 100 μm. When using linear dimensions, the shape of the bump pad or UBM is not limited to square and rectangular, and can be any shape. The linear dimension is the diameter of the circle. A chip is usually composed of a large number of conductor pads and a large number of bumps. The pitch, or distance, between the bumps is preferably between about 100 μm and 300 μm, more preferably about 150 μm and 250 μm.

UBM８を蒸着した後、ソルダー・バンプ10が、UBM８上に形成される。ソルダー・バンプ10は、蒸発法，エレクトロ・プランティング法，印刷法，ソルダー・トランスファー法，ボール・プレイスメント法などの、通常使用されている方法により形成できる。好ましい一実施例においては、無鉛バンプ10は、錫，銀と、状況によっては銅から成る。典型的な実施例においては、無鉛バンプ10は、約95％から約97％までの錫、約３％から約４％までの銀と、約0.5％から1.5％までの銅から成る。高濃度鉛バンプは、約95％から約97％の鉛、約３％から約５％の錫から成るのが好ましいが、約95％の鉛と５％の錫から成るのが、さらに好ましい。   After depositing UBM8, solder bumps 10 are formed on UBM8. The solder bump 10 can be formed by a commonly used method such as an evaporation method, an electro planting method, a printing method, a solder transfer method, or a ball placement method. In one preferred embodiment, the lead-free bump 10 is comprised of tin, silver, and in some cases copper. In a typical embodiment, the lead-free bump 10 comprises about 95% to about 97% tin, about 3% to about 4% silver, and about 0.5% to 1.5% copper. The high concentration lead bump preferably comprises about 95% to about 97% lead and about 3% to about 5% tin, but more preferably comprises about 95% lead and 5% tin.

図２は、パッケージ基板12を示す。パッケージ基板12は、ポリマー，セラミックおよびプリント基板などの材料から形成されるのが好ましい。バンプ・パッド16は、銅，アルミニュウムとこれらの合金から成るのが好ましい。ソルダー停止層14は、パッケージ基板12の好ましくない部分にソルダーが付着するのを防止するため、パッケージ基板12上に形成される。バンプ・パッド16を露出させるソルダー停止開口部（SRO）24が、ソルダー停止層14を貫通して形成される。SRO 24は、長さと幅がほぼ同じ正方形または長方形であることが好ましい。SRO 24の最長の長さ、すなわち直線寸法W2は、約 30μmと約200μmの間にあるのが好ましく、約100μmであればさらに好ましい。導電性パッドである保護層18は、バンプ・パッド16上に任意に形成される。保護層18は、約100Åから約10000Å間の厚さであるのが好ましく、ニッケル，金，または、これらの合金などの導電性材料から形成される。導電線22は、バンプ・パッド16ともう一つのバンプ・パッド20を電気的に結合する。バンプ・パッド20の機能は、以下の段落で検討する。 FIG. 2 shows the package substrate 12. The package substrate 12 is preferably formed from materials such as polymers, ceramics and printed circuit boards. The bump pad 16 is preferably made of copper, aluminum and alloys thereof. The solder stop layer 14 is formed on the package substrate 12 in order to prevent the solder from adhering to an undesirable portion of the package substrate 12. A solder stop opening (SRO) 24 exposing the bump pad 16 is formed through the solder stop layer 14. The SRO 24 is preferably a square or a rectangle having approximately the same length and width. Maximum length of the SRO 24, i.e. linear dimension W 2 is preferably between about 30μm and about 200 [mu] m, more preferably it is about 100 [mu] m. A protective layer 18 which is a conductive pad is optionally formed on the bump pad 16. The protective layer 18 is preferably between about 100 and about 10,000 inches thick and is formed from a conductive material such as nickel, gold, or alloys thereof. Conductive wire 22 electrically couples bump pad 16 and another bump pad 20. The function of the bump pad 20 will be discussed in the following paragraphs.

図１で参照される半導体基板２と図２で参照されるパッケージ基板12は、一体化され、図３に示す半導体パッケージ・アセンブリ23を形成する。半導体基板２は、表面を裏返しにして組み立てられる。両者を合体する前に、半導体基板２またはパッケージ基板12の何れか一方の表面に、フラックスが塗布される。ソルダー・バンプ10は、リフローして、２個の導電性パッド８，16間を結合する。好ましい実施例においては、導電性パッド８，16は、それぞれUMB８とバンプ・パッド16である（多分、保護層18と称せられる別の導電性パッドを介して）。   The semiconductor substrate 2 referenced in FIG. 1 and the package substrate 12 referenced in FIG. 2 are integrated to form the semiconductor package assembly 23 shown in FIG. The semiconductor substrate 2 is assembled with the surface turned upside down. Before combining the two, flux is applied to the surface of either the semiconductor substrate 2 or the package substrate 12. The solder bumps 10 are reflowed to bond the two conductive pads 8 and 16 together. In the preferred embodiment, conductive pads 8, 16 are UMB 8 and bump pad 16, respectively (possibly through another conductive pad, referred to as protective layer 18).

リフロー後、バンプ10は再成形され、バンプの直線寸法Wmは、約100μmと約300μmの間にあるのが好ましくなる。最大幅Wmに対する高さHの比率は、約0.5と1.0の間にあるのが好ましい。バンプ10とUBM８間の接触面である上部の接合部分26の寸法は、通常、UBM８の寸法により規定される。バンプ10と保護層18間の接触面である下部の接合部分28の寸法は、通常、SRO 24の寸法で規定される。上部の接合部分26と下部の接合部分28の寸法が大幅に異なる場合、バンプは不平衡であると考えられる。不平衡バンプ10は、寸法の小さな端部において、ストレスが高いので（上部の接合部分26か下部の接合部分28のどちらかで）、さらにクラックが生じ易い。従って、UBM８は、バランスが取れていることが好ましく、UBM８の寸法W1がSRO 24の寸法W2に十分に近ければ、バランスが取れていることになる。W1／W2の比率は、約0.7と1.7の間にあることが好ましく、約0.8と約1.5の間にあることがさらに好ましく、約0.9と約1.3の間にあることが、さらになお好ましい。バンプのリフロー後、金属間部分が（IMC）（図示なし）接合部分26，28で形成される。 After reflow, the bump 10 is reshaped and the bump linear dimension W m is preferably between about 100 μm and about 300 μm. The ratio of height H to maximum width W m is preferably between about 0.5 and 1.0. The dimension of the upper joint portion 26 that is a contact surface between the bump 10 and the UBM 8 is usually defined by the dimension of the UBM 8. The dimension of the lower joint portion 28 that is the contact surface between the bump 10 and the protective layer 18 is usually defined by the dimension of the SRO 24. A bump is considered unbalanced if the dimensions of the upper joint portion 26 and the lower joint portion 28 are significantly different. Since the unbalanced bump 10 has high stress at the small end portion (either the upper joint portion 26 or the lower joint portion 28), the unbalanced bump 10 is more likely to crack. Therefore, the UBM 8 is preferably balanced. If the dimension W 1 of the UBM 8 is sufficiently close to the dimension W 2 of the SRO 24, the UBM 8 is balanced. The ratio of W 1 / W 2 is preferably between about 0.7 and 1.7, more preferably between about 0.8 and about 1.5, and even more preferably between about 0.9 and about 1.3. . After the reflow of the bumps, an intermetallic part is formed at (IMC) (not shown) joints 26 and 28.

有機物基板を使用して形成される高濃度鉛バンプ体に対して、予備半田付け層を形成することが好ましい。図４は、別の好ましい実施例を示し、この実施例では、半田付け事前層36は、バンプ10とバンプ・パッド16間に形成される。予備半田付け層36は、63％の錫と37％の鉛などで構成される合金のような、共晶材料から形成されるのが好ましい。バンプ10の下部接合部は、従って、予備半田付け層36の寸法によって、通常は規定される。この前に検討した実施例と同様に、予備半田付け層36の直線寸法W2は、約30μmと約200μmの間にあるのが好ましく、約100μmであればさらに好ましい。バンプの平衡を取り、従って、上部接合部26と下部接合部28におけるストレスを低減するために、W1/W2の比率は、約0.7と約1.7の間にあるのが好ましく、約0.8と約1.5の間にあるのが、さらに、好ましく、約0.9と約1.3の間にあるのが、さらになお、好ましい。 It is preferable to form a preliminary soldering layer on the high-concentration lead bump body formed using the organic substrate. FIG. 4 shows another preferred embodiment, in which the soldering pre-layer 36 is formed between the bump 10 and the bump pad 16. The pre-soldering layer 36 is preferably formed from a eutectic material, such as an alloy comprised of 63% tin and 37% lead. The lower joint of the bump 10 is therefore usually defined by the dimensions of the pre-soldering layer 36. Similar to the embodiment discussed before this linear dimension W 2 of the preliminary soldering layer 36 is preferably between about 30μm and about 200 [mu] m, more preferably it is about 100 [mu] m. In order to balance the bumps and thus reduce stress in the upper joint 26 and the lower joint 28, the ratio of W 1 / W 2 is preferably between about 0.7 and about 1.7, and about 0.8 and More preferably, it is between about 1.5 and even more preferably between about 0.9 and about 1.3.

前に戻って図３を参照すると、パッケージ基板12は、通常、層状構造を有する。パッケージ基板12を通る金属線22を経由して、バンプ10は、ボール・グリッド・アレイ（BGA）ボール30の１つに電気的に接続されている。BGAボール30は、パッケージ基板12の下部に形成されており、プリント基板40のような外部部品に、基板上の集積回路（図示なし）を電気的に結合するために使用される。好ましい実施例においては、BGAボール 30は、ほとんど無鉛であり、鉛濃度が約５％未満のソルダー材から成る。代わりの実施例では、BGAボール30は、鉛と錫から成る共晶合金から構成される。   Referring back to FIG. 3, the package substrate 12 typically has a layered structure. The bumps 10 are electrically connected to one of the ball grid array (BGA) balls 30 via metal lines 22 that pass through the package substrate 12. The BGA ball 30 is formed under the package substrate 12 and is used to electrically couple an integrated circuit (not shown) on the substrate to an external component such as the printed circuit board 40. In the preferred embodiment, the BGA ball 30 is composed of a solder material that is almost lead free and has a lead concentration of less than about 5%. In an alternative embodiment, BGA ball 30 is composed of a eutectic alloy of lead and tin.

低誘電率材料が、金属間誘電体として集積回路に広く使用される。低誘電率体は、通常、強度が低く、時に多孔質であるので、強度の高い材料と併用される場合においては、特に破損または層間剥離を起こし易い。低誘電率体をチップ２に使用すると、強度の高いアンダーフィル材料の使用が制限され、このことは、バンプ10がアンダーフィルから受ける保護機能を制限することになる。この保護無しには、無鉛および高濃度鉛バンプとバンプのIMCは、さらにクラックを生じ易くなる。無鉛および高濃度鉛材料の信頼性に関する試験が実施された。この結果、バンプが不平衡である場合は、熱サイクル試験中にかなりの数のサンプルが不合格であった。クラックは、通常、接合部分の寸法が小さな端部に近い部分に発生する。不適切なアンダーフィル材料が使用された場合、障害は低誘電率体の層間剥離の原因、或いは、アンダーフィルの層間剥離の原因でも発生する。十分にバランスをとったバンプのサンプルで試験をおこなった場合は、著しい改善効果が見られた。熱サイクル試験中には、不合格のサンプルは、全く出なかった。   Low dielectric constant materials are widely used in integrated circuits as intermetallic dielectrics. Low dielectric constants are usually low in strength and sometimes porous, and therefore are particularly susceptible to breakage or delamination when used in combination with high strength materials. The use of a low dielectric constant for the chip 2 limits the use of a strong underfill material, which limits the protective function that the bump 10 receives from the underfill. Without this protection, lead-free and high-concentration lead bumps and bump IMCs are more susceptible to cracking. Tests were conducted on the reliability of lead-free and high-concentration lead materials. As a result, a significant number of samples failed during the thermal cycling test if the bumps were unbalanced. A crack usually occurs in a portion near the end where the size of the joint portion is small. If an inappropriate underfill material is used, the failure may also be due to low dielectric constant delamination or underfill delamination. When tested with a well-balanced bump sample, a significant improvement was seen. During the heat cycle test, no failed samples were found.

本発明の好ましい実施例では、無鉛および高濃度鉛のバンプに対するクラック発生の問題を解決するパッケージングによる解決法を示した。無鉛および高濃度鉛のバンプはクラックを発生し易いという従来の教唆に反して、得られた結果は、無鉛および高濃度鉛のバンプはクラックを発生し易く無いことを実証し、本発明の好ましい実施例で特定される寸法バランス要件が満たされたのである。本解決法は、現行のパッケージング工程と十分に一致し、特別な試みの必要が無く、或いは、余分なコストは発生しない。低誘電率体の破損を避けるために、バンプを保護する目的で、強度の大きなアンダーフィル材料は必要が無い。   In the preferred embodiment of the present invention, a packaging solution has been presented that solves the problem of cracking for lead-free and high concentration lead bumps. Contrary to the conventional teaching that lead-free and high-concentration lead bumps are prone to cracking, the results obtained demonstrate that lead-free and high-concentration lead bumps are not prone to cracking and are preferred for the present invention. The dimensional balance requirements specified in the examples were met. This solution is well consistent with current packaging processes and does not require special trials or extra costs. In order to avoid damage to the low dielectric constant material, there is no need for a strong underfill material for the purpose of protecting the bumps.

本発明とその利点を詳細に説明したが、添付の請求項で規定するように、本発明の精神と範囲を逸脱することなく、種々の変形、代替と代案が可能であることを理解されたい。
さらに、本願の範囲を、明細書で説明した工程、機械、製造、材料の組合せ、手段および方法について、この特別な実施例に限定する意図はない。本発明の開示から当業者が容易に理解するように、現存する、或いは、将来開発される、同一の機能を当業者が十分に実行し、或いは、ここに、説明した実施例に相当するとものと同じ機能を実行し、同じ結果を実現する工程、機械、製造、材料の組合せ、手段および方法は、本発明により利用される。従って、添付の請求項は、工程、機械、製造、材料の組合せ、手段および方法などの範囲内を包含するものである。 Having described the invention and its advantages in detail, it should be understood that various modifications, substitutions and alternatives may be made without departing from the spirit and scope of the invention as defined in the appended claims. .
Furthermore, there is no intention to limit the scope of the present application to this particular embodiment with respect to the processes, machines, manufacture, material combinations, means and methods described in the specification. As will be readily understood by those skilled in the art from the disclosure of the present invention, the same functions that exist or will be developed in the future are fully performed by those skilled in the art or correspond to the embodiments described herein. Processes, machines, manufacturing, material combinations, means and methods that perform the same functions and achieve the same results are utilized by the present invention. Accordingly, the appended claims are intended to cover within the scope of the process, machine, manufacture, combination of materials, means and methods.

ソルダー・バンプを有するチップを説明する図である。It is a figure explaining the chip | tip which has a solder bump. パッケージ基板を説明する図である。It is a figure explaining a package substrate. チップとパッケージ基板が一体化されたパッケージ・アセンブリの図である。It is a figure of the package assembly with which the chip | tip and the package board | substrate were integrated. チップとパッケージ基板が一体化されたパッケージ・アセンブリの図である。It is a figure of the package assembly with which the chip | tip and the package board | substrate were integrated.

符号の説明Explanation of symbols

2 半導体基板
8 UBM（第１の導電性パッド）
10 バンプ
12 パッケージ基板
16 バンプ・パッド（第２の導電性パッド）
23 半導体パッケージ・アセンブリ
30 BGAボール

2 Semiconductor substrate
8 UBM (first conductive pad)
10 Bump
12 Package substrate
16 Bump pad (second conductive pad)
23 Semiconductor package assembly
30 BGA balls

Claims (15)

半導体基板上の第１の導電性パッドと、
パッケージ基板上の第２の導電性パッドと、
前記第１の導電性パッドと前記第２の導電性パッド間を物理的に結合するほぼ無鉛のバンプと、から構成される半導体パッケージ・アセンブリにおいて、
前記バンプが、前記第１の導電性パッドとの第１の接触面を有し、前記第１の接触面が第１の直線寸法を有し、
前記バンプが、前記第２の導電性パッドとの第２の接触面を有し、前記第２の接触面が第２の直線寸法を有し、
前記第１の直線寸法に対する前記第２の直線寸法の比率が、約0.7と約1.7の間にあることを特徴とする半導体パッケージ・アセンブリ。 A first conductive pad on a semiconductor substrate;
A second conductive pad on the package substrate;
A semiconductor package assembly comprising: a substantially lead-free bump that physically couples between the first conductive pad and the second conductive pad;
The bump has a first contact surface with the first conductive pad, and the first contact surface has a first linear dimension;
The bump has a second contact surface with the second conductive pad, the second contact surface has a second linear dimension;
The semiconductor package assembly wherein the ratio of the second linear dimension to the first linear dimension is between about 0.7 and about 1.7. 前記半導体基板が、約3.3未満のｋ値を有する少なくとも１つの低誘電率体層から成ることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   The semiconductor package assembly of claim 1, wherein the semiconductor substrate comprises at least one low dielectric constant layer having a k value less than about 3.3. 前記第２の導電性パッドが、銅，アルミニュウム，およびこれらの組み合わせから主として成るグループから選択された材料から構成されることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   The semiconductor package assembly of claim 1, wherein said second conductive pad is comprised of a material selected from the group consisting primarily of copper, aluminum, and combinations thereof. 前記第２の導電性パッドが、ニッケル，金，およびこれらの組み合わせから主として成るグループから選択された材料から構成される保護層であることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   2. The semiconductor package assembly of claim 1, wherein the second conductive pad is a protective layer made of a material selected from the group consisting primarily of nickel, gold, and combinations thereof. 前記第１の直線寸法と前記第２の直線寸法が、約30μmと約200μmの間にそれぞれあることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   2. The semiconductor package assembly of claim 1, wherein the first linear dimension and the second linear dimension are between about 30 [mu] m and about 200 [mu] m, respectively. 前記半導体基板と前記パッケージの間に複数のバンプをさらに備え、前記複数のバンプが、約100μmと約300μmの間のピッチを有することを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   The semiconductor package assembly of claim 1, further comprising a plurality of bumps between the semiconductor substrate and the package, the plurality of bumps having a pitch between about 100 μm and about 300 μm. 前記バンプが、約30μmと約200μmの間の高さを有し、前記高さと前記第１の直線寸法が、約0.5と約1.0の間の比率を有し、前記高さの前記第２の直線寸法に対する比率が、約0.5と約1.0の間であることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   The bump has a height between about 30 μm and about 200 μm, and the height and the first linear dimension have a ratio between about 0.5 and about 1.0, and the second of the height The semiconductor package assembly of claim 1, wherein the ratio to the linear dimension is between about 0.5 and about 1.0. 前記第１の導電性パッドが、アンダー・バンプ・メタライゼーション（UBM）であることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   The semiconductor package assembly of claim 1, wherein the first conductive pad is under bump metallization (UBM). 前記パッケージ基板表面上に複数のボール・グリッド・アレイ（BGA）ボールをさらに備え、前記BGAボールは、主として共晶合金から構成されるグループから選択される材料と、約５％未満の鉛濃度を有する材料とから成ることを特徴とする請求項１記載の半導体パッケージ・アセンブリ。   A plurality of ball grid array (BGA) balls on the surface of the package substrate, wherein the BGA balls have a material selected from the group consisting primarily of eutectic alloys and a lead concentration of less than about 5%; The semiconductor package assembly according to claim 1, wherein the semiconductor package assembly comprises: 半導体基板上の第１の導電性パッドと、
パッケージ基板上の第２の導電性パッドと、
前記半導体基板と前記パッケージ基板間を物理的に結合する大幅な高濃度鉛を含有するバンプと、から構成される半導体パッケージ・アセンブリにおいて、
前記バンプが、前記第１の導電性パッドが第１の接触面を有し、前記第１の接触面は第１の直線寸法有し、
前記バンプが、前記第２の導電性パッドが第２の接触面を有し、前記第２の接触面は第２の直線寸法を有し、さらに
第１の直線寸法に対する第２の直線寸法の比率が、約0.7と約1.7の間にあることを特徴とする半導体パッケージ・アセンブリ。 A first conductive pad on a semiconductor substrate;
A second conductive pad on the package substrate;
In a semiconductor package assembly comprised of bumps containing significant high-concentration lead that physically bond between the semiconductor substrate and the package substrate,
The bump, the first conductive pad has a first contact surface, and the first contact surface has a first linear dimension;
The bump, the second conductive pad has a second contact surface, the second contact surface has a second linear dimension, and has a second linear dimension relative to the first linear dimension. A semiconductor package assembly characterized in that the ratio is between about 0.7 and about 1.7. 前記半導体基板が、約3.3未満のｋ値を有する少なくとも１つの低誘電率体層から成ることを特徴とする請求項10記載の半導体パッケージ・アセンブリ。   11. The semiconductor package assembly of claim 10, wherein the semiconductor substrate comprises at least one low dielectric constant layer having a k value less than about 3.3. 前記第２の導電性パッドが、銅，アルミニュウム，およびこれらの組み合わせから主として成るグループから選択される材料で構成されることを特徴とする請求項10記載の半導体パッケージ・アセンブリ。   11. The semiconductor package assembly of claim 10, wherein the second conductive pad is comprised of a material selected from the group consisting primarily of copper, aluminum, and combinations thereof. 前記第１の直線寸法と前記第２の直線寸法が、約30μmと約200μmの間にそれぞれあることを特徴とする請求項10記載の半導体パッケージ・アセンブリ。   11. The semiconductor package assembly of claim 10, wherein the first linear dimension and the second linear dimension are between about 30 [mu] m and about 200 [mu] m, respectively. 前記バンプが、約30μmと約200μmの間の高さを有し、前記高さの前記第１の直線寸法に対する比率が、約0.5と約1.0の間にあり、前記高さの前記第２の直線寸法に対する比率が、約0.5と約1.0の間にあることを特徴とする請求項10記載の半導体パッケージ・アセンブリ。   The bump has a height between about 30 μm and about 200 μm, and a ratio of the height to the first linear dimension is between about 0.5 and about 1.0, and the height of the second is The semiconductor package assembly of claim 10, wherein the ratio to the linear dimension is between about 0.5 and about 1.0. 半導体基板上にあって、第１の直線寸法を有する導体パッドと、
パッケージ基板上にあって、第２の直線寸法を有するバンプ・パッドと、
前記導体パッドと前記バンプ・パッドを物理的に接続し、約５％未満の鉛から成り、ほぼ無鉛であるか、さもなければ約80％を超える鉛から成り、ほぼ高濃度の鉛を含有するバンプと、から構成されるとともに、
前記第１の直線寸法に対する前記第２の直線寸法の比率が、約0.7と約1.7の間にあることを特徴とする半導体パッケージ・アセンブリ。

A conductor pad on a semiconductor substrate having a first linear dimension;
A bump pad on the package substrate and having a second linear dimension;
The conductor pad and the bump pad are physically connected and consisted of less than about 5% lead, almost lead-free, or else more than about 80% lead, containing almost a high concentration of lead. With bumps,
The semiconductor package assembly wherein the ratio of the second linear dimension to the first linear dimension is between about 0.7 and about 1.7.

JP2006013706A 2005-03-17 2006-01-23 Semiconductor package assembly Pending JP2006261641A (en)

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