JP2006251349A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that circuits such as an address generation circuit and a buffer for selecting an input/output data bus are required and circuit scale increases since frame rate of an input video signal is converted into twice as high as a high speed memory in the conventional manner. <P>SOLUTION: A double speed FIFO 15 outputs video signal data at frame rate twice as high as that of the input video signal by sequentially writing video signals for one line from an LM circuit 14 by synchronizing with a period twice as high as that of a dot clock MCLK of a liquid crystal device 17 and reading the written video signals in a writing order by synchronizing with the dot clock MCLK thereafter. Thus, the frame rate can be twice as high even without using an expensive image memory and the address generation circuit for image memory and a data bus selection circuit required in the conventional device are made unnecessary. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image display device, and more particularly to an image display device such as a projector that displays an image with a frame rate of an input video signal being doubled.

  In an image display apparatus such as a projector using a liquid crystal device, when the frame frequency of an input video signal is about 50 Hz to 60 Hz, it is necessary to convert the frame rate to a double frame rate of about 100 Hz to 120 Hz as a countermeasure against flicker. is there. In this case, an image display apparatus that displays an image by converting the frame rate using a low-speed frame memory has been conventionally known (for example, see Patent Document 1).

  FIG. 7 is a block diagram showing an example of the conventional image display apparatus. In the figure, a serial digital video signal is serial / parallel converted by an S / P circuit 21, converted into a parallel digital video signal, and supplied to a conversion FIFO (first in first out) 22, where it is synchronized with the parallel digital video signal. When the conversion FIFO 22 becomes full after being temporarily stored for a predetermined capacity based on the first clock, the data is read based on the second clock having the same rate as the image rate and supplied to the control circuit 23.

  The control circuit 23 writes the parallel digital video signal read from the conversion FIFO 22 into the image memory 24 for one frame in real time, and reads the written parallel digital video signal from the image memory 24. Here, the image memory 24 is an SDRAM (Synchronous Dynamic Random Access Memory), for example, and is a synchronous RAM that fetches instructions in synchronization with the second clock and inputs and outputs data.

  The control circuit 23 reads out the parallel digital video signal from the image memory 24 at a transfer rate twice as high as that at the time of writing, supplies it to the DA circuit 25 for D / A conversion, and supplies the analog video signal to the liquid crystal device 26. To display an image.

Japanese Patent No. 3359270

  However, in the above conventional image display device, since a high-speed memory such as SDRAM is used for the image memory 24, the control circuit 23 has a circuit for generating an address of the image memory 24, a buffer for selecting an input / output data bus, and the like. There is a problem that the circuit scale increases.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an image display apparatus capable of minimizing an increase in circuit scale and realizing functions necessary for a projector such as frame frequency conversion.

  In order to achieve the above object, the present invention provides an image display apparatus for displaying an image on a display device with a frame rate of an input video signal being doubled, after writing the input video signal in synchronization with a first clock signal. The clock conversion means for reading out in the writing order in synchronization with the second clock signal, and the video signal read from the clock conversion means are sequentially stored in synchronization with the second clock signal for each line, and then displayed. Line memory means that reads in synchronization with the dot clock of the device, and the video signal for one line read from the line memory means is written every other dot clock, and the video signal written every dot clock is written By sequentially reading out, it is a double configured with a FIFO that outputs a video signal that is twice the frame rate of the input video signal. Conversion means, in which a structure and an output means for displaying supplies the video signal output from the double speed converting means to the display device.

  In this invention, the video signal for one line is written to the FIFO every other dot clock, and the video signal written every dot clock is read out from the FIFO in the order of writing, thereby double the frame rate of the input video signal. Video signals can be output.

  According to the present invention, since the video signal twice the frame rate of the input video signal is output by the double speed conversion means using the FIFO, the frame rate is doubled by using an expensive image memory such as SDRAM. Compared with conventional devices that perform double speed conversion, the address generation circuit and data bus selection circuit can be eliminated, so that the increase in circuit scale can be minimized, and this makes it cheaper and easier than conventional devices. An image display apparatus having a simple structure can be realized.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of an image display apparatus according to the present invention. As shown in the figure, the image display apparatus of this embodiment converts a serial / parallel conversion circuit (S / P circuit) 11 that converts a digital video signal inputted as a serial signal into a parallel signal, and a synchronous clock. A conversion FIFO 12, a test circuit 13 for generating a test pattern, a line memory circuit (LM circuit) 14 having a capacity of one line (for example, 2048 pixels), a double speed FIFO 15 for converting a frame frequency, It comprises a DA converter circuit (DA circuit) 16 that generates a drive signal for the liquid crystal device 17 and a liquid crystal device 17 for displaying an image.

  In the S / P circuit 11 described above, when the video signal input serially is each primary color signal of the three primary colors R (red), G (green), and B (blue), and these are input in parallel. These are converted into 8-bit parallel video signals, and a horizontal synchronizing signal (HS), a vertical synchronizing signal (VS), a data enable signal (DE), and a first clock signal (DCLK) synchronized with the video signal are output. .

  The conversion FIFO 12 temporarily stores R, G, and B parallel video signals (primary color signals) input from the S / P circuit 11 in synchronization with the first clock signal DCLK, and then stores the on-board clock. Reading is performed in synchronization with a second clock signal (hereinafter referred to as SCLK) generated by a generator (not shown) and having extremely high frequency stability. As a result, the conversion FIFO 12 converts the video signal synchronized with the first clock signal DCLK into a video signal synchronized with the second clock signal SCLK.

  The test circuit 13 is a circuit block that generates test video signals such as color bars and cross hatches in synchronization with the second clock signal SCLK. The LM circuit 14 is composed of four line memories each having a capacity of one line, and is used as a ring buffer as will be described later. The LM circuit 14 writes the video signal (primary color signal) supplied from the conversion FIFO 12 or the test pattern supplied from the test circuit 13 for one line.

  At the time of writing, a horizontal inversion function is realized by preparing a mode for writing from the beginning of the address and a mode for writing from the last address. The LM circuit 14 reads the input video signal in synchronization with the second clock signal SCLK and the output signal in synchronization with the dot clock (hereinafter referred to as MCLK) of the liquid crystal device 17 which is the third clock signal. And

  The double-speed FIFO 15 sequentially writes the parallel video signal data output from the LM circuit 14 every 1 dot clock MCLK, and sequentially reads out the video signal data written first for each dot clock MCLK. Thus, the frame frequency is doubled and output.

  Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS. In the following description, the operation of an input video signal with respect to any one primary color signal among the three primary color signals will be described for convenience of description. The same operation is performed for the remaining two primary color signals.

  The serial input video signal is converted into, for example, an 8-bit parallel video signal by the S / P circuit 11, and then, together with the horizontal synchronization signal HS and the vertical synchronization signal VS, the data enable signal DE, and the first clock signal DCLK. Supplied to the conversion FIFO 12. The first clock signal DCLK is, for example, 74.25 MHz.

  The conversion FIFO 12 synchronizes the parallel video signal input from the S / P circuit 11 with the first clock signal DCLK shown in FIG. The parallel video signal data shown in FIG. 2C is temporarily stored during the period when the write control signal shown in FIG. Here, D0, D1,..., D26, D27,... In FIG. 2C indicate 8 bits of video signal data, and as shown in FIG. The conversion FIFO 12 accumulates 16 bits at a time in synchronization with the first clock signal DCLK. Note that this is processing for one primary color signal, and the entire three primary color signals of R, G, and B are stored 48 bits at a time.

  After starting the writing of the parallel video signal data, the second clock having an extremely high frequency stability, for example, 74.25 MHz, shown in FIG. 2D, which is generated by an on-board clock generator (not shown). As shown in FIG. 2E, after about 10 clocks of the signal SCLK, the read control signal becomes high level, and during this high level period, the conversion FIFO 12 displays the parallel video signal data in synchronization with SCLK. It is read as shown in 2 (F).

  The video signal read from the conversion FIFO 12 in synchronization with the second clock signal SCLK is supplied to the LM circuit 14. The LM circuit 14 shows the video signal supplied from the conversion FIFO 12 based on the write address shown in FIG. 3A during the period when the write control signal shown in FIG. Thus, one line of 1920 pixels is stored.

  Further, when performing normal display, the LM circuit 14 stores the video signal for one line stored during the period when the read control signal shown in FIG. 3E is at a high level based on the read address shown in FIG. Data D0 to D1919 are read out in the order in which they are written, as shown in FIG.

  On the other hand, when performing the horizontal inversion display, the LM circuit 14 stores the video for one line stored during the period when the read control signal shown in FIG. 3H is at a high level based on the read address shown in FIG. The signal data D0 to D1919 are read out in the reverse order to the order in which they are written as shown in FIG.

  The operation of the LM circuit 14 is shown in units of lines as shown in the timing chart of FIG. That is, the LM circuit 14 is composed of four line memories. As shown in FIGS. 4C to 4F, the individual write control signals write0 to write3 are sequentially supplied in time division to each line memory. Based on the write address shown in FIG. 4A, the input video signal shown in FIG. 4B is written in line units.

  Thereafter, as shown in FIGS. 4H, 4J, 4L, and 4N, individual read control signals read0 to read3 are stored in the four line memories constituting the LM circuit 14, respectively. As shown in (I), (K), (M), and (O) of each of the four line memories based on the read address shown in (G) of FIG. The stored video signal is read in line units in synchronization with MCLK.

  The double-speed FIFO 15 writes the video signal from the LM circuit 14 based on the write enable signal shown in one frame unit in FIG. 5A, and as shown in FIG. Based on the enable signal, the video signal of one frame is repeatedly read out twice at a double transfer rate. Note that F [0], F [1], F [2], and F [3] in FIG. 5B indicate video signals of one entire screen (one frame), respectively. Therefore, when the video signal is HDTV, the number of pixels is 2073600 pixels, which is 1920 pixels horizontally and 1080 pixels vertically.

  That is, the double-speed FIFO 15 performs LM as shown in FIG. 6C during the period when the write enable signal shown in FIG. 6B synchronized with the period twice the dot clock MCLK shown in FIG. 8 bits of the video signal from the circuit 14 are written, and then the 8 bits of the written video signal are synchronized with the dot clock MCLK as shown in FIG. 8E during the period when the read enable signal shown in FIG. Thus, the video signal data having a frame rate twice that of the input video signal is output.

  Note that DI [0] and the like in FIG. 6C indicate 8 bits of the input video signal data of the double speed FIFO 15. In addition, DO [0] and the like in FIG. 6E are output video signal data of the double speed FIFO 15, and are 8 bits like DI [0] and the like. However, all the three primary color signals are 24 bits.

  Video signal data having a frame rate twice that of the input video signal output from the double speed FIFO 15 is converted into an analog video signal by the DA circuit 16 shown in FIG. 1, and then supplied to the liquid crystal device 17 to display an image.

  As described above, according to the present embodiment, the input video signal data is sequentially written by the double speed FIFO 15 every 1 dot clock MCLK (that is, in a cycle of 2 clocks), and the dot is sequentially written from the video signal data written first. Since the frame frequency is doubled by continuously reading every clock MCLK (that is, in one clock cycle), the frame rate can be set without using an expensive image memory such as an SDRAM as in the prior art. The speed can be doubled, and the use of a FIFO eliminates the need for an image memory address generation circuit and data bus selection circuit that were required in the conventional apparatus. Therefore, it is cheaper and simpler than the conventional apparatus. It can be set as a simple structure.

  Further, in this embodiment, since the test circuit 13 is provided and the output signal of the test circuit 13 can be supplied to the circuit section after the LM circuit 14 instead of the output video signal of the conversion FIFO 12, the video signal is input. Even without this, test patterns such as color bars and cross hatches can be displayed as images. Furthermore, in this embodiment, as described with FIG. 3, the horizontal inversion function can be easily realized.

  It should be noted that the present invention is not limited to the above-described embodiment, and of course can be applied to video signals other than HDTV signals, for example.

It is a block diagram of one embodiment of an image display device of the present invention. 2 is a timing chart for explaining the operation of a conversion FIFO in FIG. 1. 3 is a timing chart (No. 1) for explaining the operation of the LM circuit in FIG. 1; 3 is a timing chart (part 2) for explaining the operation of the LM circuit in FIG. 3 is a timing chart (part 1) for explaining the operation of the double-speed FIFO in FIG. 3 is a timing chart (part 2) for explaining the operation of the double-speed FIFO in FIG. It is a block diagram of an example of the conventional image display apparatus.

Explanation of symbols

11 Serial / parallel conversion circuit (S / P circuit)
12 Conversion FIFO
13 Test circuit 14 Line memory circuit (LM circuit)
15 double speed FIFO
16 DA converter circuit (DA circuit)
17 Liquid crystal devices

Claims (1)

In an image display device for displaying an image on a display device by setting the frame rate of an input video signal to double speed,
Clock conversion means for writing the input video signal in synchronization with the first clock signal and then reading out the input video signal in order of writing in synchronization with the second clock signal;
Line memory means for sequentially storing the video signal read from the clock conversion means for each line in synchronization with the second clock signal, and for reading in synchronization with the dot clock of the display device;
The video signal for one line read from the line memory means is written at every other clock of the dot clock, and the video signal written at every dot clock is read in the order of writing, whereby the frame of the input video signal is read. A double speed conversion means composed of a FIFO that outputs a video signal of twice the rate;
An image display apparatus comprising: output means for supplying the video signal output from the double speed conversion means to the display device for display.

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