JP2006237674A - Patch antenna and rfid inlet - Google Patents
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Abstract
Description
本発明は、パッチアンテナ、並びに、パッチアンテナ及び送受信素子を有するRFIDインレットに関する。 The present invention relates to a patch antenna, and an RFID inlet having a patch antenna and a transmission / reception element.
パッチアンテナ及び送受信素子を有するRFIDインレットは、識別情報の正確且つ効率的な送受信を行えるものとして、物流管理や人の入出退管理等の種々の分野において非常に注目されている。 An RFID inlet having a patch antenna and a transmission / reception element has attracted a great deal of attention in various fields such as distribution management and human entry / exit management as being capable of transmitting and receiving identification information accurately and efficiently.
しかしながら、従来のRFIDインレットは、省サイズ化や、パッチアンテナと送受信素子との接続作業性に関して、十分な考慮がなされていなかった。
図8は、従来のRFIDインレットにおけるパッチアンテナの一例を示す斜視図である。
However, the conventional RFID inlet has not been sufficiently considered in terms of size reduction and connection workability between the patch antenna and the transmission / reception element.
FIG. 8 is a perspective view showing an example of a patch antenna in a conventional RFID inlet.
前記パッチアンテナ100は、導体によって形成されるグラウンド面110と、該グラウンド面110上に載置された誘電体120と、導体によって形成されたアンテナ面130であって、前記誘電体120上に載置されたアンテナ面130とを有している。
そして、前記送受信素子(図示せず)は、一対の接続端子の一方が給電点141において前記グラウンド面に接続され、且つ、他方が給電点142において整合回路150を介して前記アンテナ面130に接続されている。
The patch antenna 100 includes a ground surface 110 formed of a conductor, a dielectric 120 placed on the ground surface 110, and an antenna surface 130 formed of a conductor, and is mounted on the dielectric 120. And an antenna surface 130 placed thereon.
The transmitting / receiving element (not shown) has one of a pair of connection terminals connected to the ground plane at a feeding point 141 and the other connected to the antenna plane 130 via a matching circuit 150 at a feeding point 142. Has been.
詳しくは、図8に示すように、従来のRFIDインレットにおいては、前記整合回路150が前記アンテナ面130の外部に設けられている。
従って、RFIDインレット全体の縮小化を十分には図ることができなかった。
Specifically, as shown in FIG. 8, in the conventional RFID inlet, the matching circuit 150 is provided outside the antenna surface 130.
Therefore, the entire RFID inlet cannot be sufficiently reduced.
さらに、図8に示す従来例においては、前記送受信素子は、一対の接続端子の一方が前記誘電体120上に設けられた整合回路150を介して前記アンテナ面130に接続され、且つ、他方が前記誘電体120の下方に配置された前記グラウンド面110に接続されている。
即ち、従来の構成においては、前記送受信素子は、前記誘電体120の厚みに相当する段差が生じた状態で、前記アンテナ面及び前記グラウンド面に接続されており、かかる接続作業が極めて困難であった。
Further, in the conventional example shown in FIG. 8, the transmission / reception element has one of a pair of connection terminals connected to the antenna surface 130 via a matching circuit 150 provided on the dielectric 120, and the other is connected to the antenna surface 130. The dielectric 120 is connected to the ground plane 110 disposed below the dielectric 120.
That is, in the conventional configuration, the transmitting / receiving element is connected to the antenna surface and the ground surface in a state where a step corresponding to the thickness of the dielectric 120 is generated, and such connection work is extremely difficult. It was.
本発明は、前記従来技術に鑑みなされたものであり、可及的な小型化を図り得るパッチアンテナ及びRFIDインレットの提供を、一の目的とする。
又、本発明は、送受信素子とパッチアンテナとの接続作業の簡略化を図り得るパッチアンテナ及びRFIDの提供を、他の目的とする。
The present invention has been made in view of the above prior art, and an object thereof is to provide a patch antenna and an RFID inlet that can be made as small as possible.
Another object of the present invention is to provide a patch antenna and an RFID capable of simplifying the connection work between the transmitting / receiving element and the patch antenna.
本発明は、前記目的を達成するために、誘電体が介挿されたグラウンド面及びアンテナ面を有するパッチアンテナであって、前記アンテナ面には、前記誘電体を露出させる開口が設けられており、前記開口は、前記アンテナ面のうち該開口を介して露出する誘電体によって画される領域が送受信素子に対する整合回路を形成するように構成されたパッチアンテナを提供する。 In order to achieve the above object, the present invention provides a patch antenna having a ground surface and an antenna surface through which a dielectric is interposed, and the antenna surface is provided with an opening for exposing the dielectric. The opening provides a patch antenna configured such that a region defined by a dielectric exposed through the opening on the antenna surface forms a matching circuit for a transmitting / receiving element.
好ましくは、前記アンテナ面における前記領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接される。
前記開口が、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する態様においては、前記第2スリットを挟んだ一方側及び他方側が、前記送受信素子の一対の接続端子にそれぞれ接続される。
Preferably, one end of the region on the antenna surface is close to a portion of the antenna surface where the high-frequency voltage is low.
In an aspect in which the opening includes a pair of first slits extending in parallel so as to face each other and a second slit communicating the pair of first slits, one side and the other side sandwiching the second slit are , And a pair of connection terminals of the transmission / reception element, respectively.
又、本発明は、誘電体が介挿されたグラウンド面及びアンテナ面を有するパッチアンテナと、一対の接続端子を有する送受信素子とを備えたRFIDインレットであって、前記アンテナ面には、前記誘電体を露出させる開口であって、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する開口が形成され、前記アンテナ面のうち前記開口を介して露出する誘電体によって画される領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接されており、前記送受信素子は、前記一対の接続端子が前記第2スリットを挟んだ一方側及び他方側において前記アンテナ面に接続されているRFIDインレットを提供する。 The present invention also provides an RFID inlet comprising a patch antenna having a ground surface and an antenna surface through which a dielectric is inserted, and a transmission / reception element having a pair of connection terminals. An opening that exposes the body and has a pair of first slits extending in parallel so as to face each other and a second slit that communicates with the pair of first slits; One end of the region defined by the dielectric exposed through the opening is close to a portion of the antenna surface where the high-frequency voltage is low, and the transmitting / receiving element includes the pair of connection terminals that pass through the second slit. An RFID inlet is provided that is connected to the antenna surface on one side and the other side of the sandwich.
好ましくは、前記第2スリットが、前記高周波電圧の低い部位に近接される。
前記アンテナ面が、前記第1スリットと平行な長さ方向の距離がLで、且つ、前記第1スリットと直交する幅方向の距離がWの矩形とされた場合においては、例えば、前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置するように形成される。
これに代えて、前記アンテナ面が、前記第1スリットと平行な長さ方向の距離がLの円形又は楕円形とされる場合においては、例えば、前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置するように形成される。
Preferably, the second slit is close to a portion where the high-frequency voltage is low.
When the antenna surface is a rectangle whose length in the length direction parallel to the first slit is L and whose distance in the width direction perpendicular to the first slit is W, for example, the antenna surface The region is formed so that one end thereof is located within a range of ± L × 0.1 with respect to L / 2 with respect to the length direction.
Instead, in the case where the antenna surface is circular or elliptical with a length in the length direction parallel to the first slit, for example, the region of the antenna surface has one end portion, With respect to the length direction, it is formed so as to be located within a range of ± L × 0.1 with reference to L / 2.
本発明に係るパッチアンテナによれば、アンテナ面に、誘電体を露出させる開口を設け、前記アンテナ面のうち該開口を介して露出する誘電体によって画される領域が送受信素子に対する整合回路を形成するように構成したので、整合回路がアンテナ面の外部に設けられていた従来構成に比して、可及的な小型化を図ることができる。 According to the patch antenna of the present invention, an opening for exposing a dielectric is provided on the antenna surface, and a region defined by the dielectric exposed through the opening of the antenna surface forms a matching circuit for a transmitting / receiving element. Thus, as compared with the conventional configuration in which the matching circuit is provided outside the antenna surface, the size can be reduced as much as possible.
又、本発明に係るRFIDインレットによれば、アンテナ面に、誘電体を露出させる開口であって、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する開口を形成し、前記アンテナ面のうち前記開口を介して露出する誘電体によって画される領域を、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接させ、送受信素子の一対の接続端子を前記第2スリットを挟んだ一方側及び他方側において前記アンテナ面に接続させたので、整合回路がアンテナ面の外部に設けられていた従来構成に比して、可及的な小型化が図れると共に、前記送受信素子の一対の接続端子を同一平面内で接続させることができ、該送受信素子の接続作業を極めて効率化することができる。 In addition, according to the RFID inlet of the present invention, a pair of first slits, which are openings for exposing a dielectric on the antenna surface and extend in parallel so as to face each other, communicate with the pair of first slits. An opening having a second slit is formed, and a region defined by a dielectric exposed through the opening in the antenna surface is made close to a portion of the antenna surface where the high-frequency voltage is low, to transmit and receive Since the pair of connection terminals of the element are connected to the antenna surface on one side and the other side across the second slit, the matching circuit is possible as compared with the conventional configuration in which the matching circuit is provided outside the antenna surface. Thus, the pair of connection terminals of the transmission / reception element can be connected in the same plane, and the connection work of the transmission / reception element can be made extremely efficient.
以下に、本発明に係るパッチアンテナの好ましい実施の形態につき、添付図面を参照しつつ説明する。
図1は、本実施の形態に係るパッチアンテナ1の斜視図である。
又、図2は、図1におけるII部拡大平面図である。
Hereinafter, a preferred embodiment of a patch antenna according to the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a perspective view of a patch antenna 1 according to the present embodiment.
FIG. 2 is an enlarged plan view of a portion II in FIG.
前記パッチアンテナ1は、電気的に接続されるICチップ等の送受信素子(図示せず)と共働して、外部に対して信号を送受信するRFIDインレットを形成する。 The patch antenna 1 forms an RFID inlet for transmitting / receiving a signal to / from the outside in cooperation with a transmitting / receiving element (not shown) such as an IC chip that is electrically connected.
詳しくは、前記パッチアンテナ1は、導体によって形成されるグラウンド面10と、該グラウンド面10上に載置された誘電体20と、該誘電体20を挟んで前記グラウンド面10に対して略平行に配置されたアンテナ面30とを備えている。 Specifically, the patch antenna 1 includes a ground plane 10 formed of a conductor, a dielectric 20 placed on the ground plane 10, and substantially parallel to the ground plane 10 with the dielectric 20 interposed therebetween. The antenna surface 30 is provided.
前記グラウンド面10は、例えば、前記誘電体20中の電磁波の波長をλとした場合に、1λ以上の矩形より大きな面積を有するAl又はCu等の導体(好ましくは金属)によって形成される。
前記アンテナ面30は、例えば、前記誘電体20中の電磁波の波長をλとした場合に、0.5λ〜1.5λ×0.5λ〜1.5λの矩形状、若しくは、円形状又は楕円形状等の非矩形状に形成された厚さ0.001mm〜1mmのAL又はCu等の導体(好ましくは金属)によって形成される。
又、前記誘電体20は、例えば、厚さ0.1mm〜3mmのFR−4(比誘電率εr=4.2〜4.8)等の絶縁物によって形成される。
For example, when the wavelength of the electromagnetic wave in the dielectric 20 is λ, the ground surface 10 is formed of a conductor (preferably metal) such as Al or Cu having an area larger than a rectangle of 1λ or more.
The antenna surface 30 is, for example, a rectangular shape of 0.5λ to 1.5λ × 0.5λ to 1.5λ, or a circular shape or an elliptical shape when the wavelength of the electromagnetic wave in the dielectric 20 is λ. It is formed by a conductor (preferably metal) such as AL or Cu having a thickness of 0.001 mm to 1 mm formed in a non-rectangular shape.
The dielectric 20 is formed of an insulator such as FR-4 (relative permittivity εr = 4.2 to 4.8) having a thickness of 0.1 mm to 3 mm.
本実施の形態においては、図2に示すように、前記アンテナ面30には、前記誘電体20の一部を露出させる開口31が形成されている。
該開口31は、前記アンテナ面30のうち該開口31を介して露出する誘電体20によって画される領域(以下、整合領域35という)が、前記送受信素子に対する整合回路を形成するように構成されている。
詳しくは、図2に示すように、前記開口は、互いに対向するように平行に延びる一対の第1スリット31aと、該一対のスリット31aを連通する第2スリット31bとを有している。
In the present embodiment, as shown in FIG. 2, an opening 31 for exposing a part of the dielectric 20 is formed in the antenna surface 30.
The opening 31 is configured such that a region defined by the dielectric 20 exposed through the opening 31 in the antenna surface 30 (hereinafter referred to as a matching region 35) forms a matching circuit for the transmitting / receiving element. ing.
Specifically, as shown in FIG. 2, the opening includes a pair of first slits 31a extending in parallel so as to face each other, and a second slit 31b communicating with the pair of slits 31a.
前記開口31は、前記整合領域35の一端部が前記アンテナ面30のうち高周波電圧の低い部位(以下、低電圧部位という)に近接するように形成され、これにより、該整合領域35が前記整合回路を構成するようになっている。
前記低電圧部位は、例えば、前記アンテナ面30における高周波電圧の最大値をVmaxとし、且つ、最小値Vminとした場合に、電圧Vが、
Vmin≦V≦Vmin+(Vmax−Vmin)×α(但し、0<α<1)
の条件を満たす部位と定義することができる。
前記αはRFIDインレットに求められる性能に応じて決定されるが、0.2、より好ましくは、0.1とされる。
The opening 31 is formed so that one end portion of the matching region 35 is close to a portion of the antenna surface 30 where the high-frequency voltage is low (hereinafter, referred to as a low-voltage portion). A circuit is configured.
For example, when the maximum value of the high-frequency voltage on the antenna surface 30 is Vmax and the minimum value Vmin is used as the low voltage portion, the voltage V is
Vmin ≦ V ≦ Vmin + (Vmax−Vmin) × α (where 0 <α <1)
It can be defined as a part satisfying the condition.
The α is determined according to the performance required for the RFID inlet, but is preferably 0.2, more preferably 0.1.
これに代えて、本実施の形態におけるように、前記アンテナ面30が、前記第1スリット31aと平行な長さ方向Lに沿って延びる長さaの辺a1,a2と、前記第1スリット31aに直交する幅方向Wに沿って延びる長さbの辺b1,b2とを有する矩形状とされている場合には、前記低電圧部位は、長さ方向Lに関する中心線C(辺b1からa/2だけ離間され、且つ、該辺b1に平行な仮想線)を基準にして、長さaの±20%、より好ましくは、±10%の領域と、擬制することができる。
即ち、辺b1からの長手方向の距離Pが、
(a/2)−a×0.2≦P≦(a/2)+a×0.2
より好ましくは、
(a/2)−a×0.1≦P≦(a/2)+a×0.1
によって画される領域を、前記低電圧部位と擬制することができる。
Instead, as in the present embodiment, the antenna surface 30 has sides a1 and a2 having a length a extending along the length direction L parallel to the first slit 31a, and the first slit 31a. In the case of a rectangular shape having sides b1 and b2 having a length b extending along the width direction W orthogonal to the low-voltage portion, the low-voltage portion has a center line C (from the sides b1 to a in the length direction L). (An imaginary line separated by / 2 and parallel to the side b1) as a reference) can be assumed to be an area of ± 20%, more preferably ± 10% of the length a.
That is, the longitudinal distance P from the side b1 is
(A / 2) −a × 0.2 ≦ P ≦ (a / 2) + a × 0.2
More preferably,
(A / 2) −a × 0.1 ≦ P ≦ (a / 2) + a × 0.1
The region defined by the above can be simulated as the low voltage portion.
図示の形態においては、前記第2スリット31bは、前記一対の第1スリット31aの一端部に配置されている。
斯かる形態においては、前記一対の第1スリット31aの他端部と前記第2スリット31bとの間において、該一対の第1スリット31aに挟まれる領域が前記整合領域35を構成している。
In the illustrated form, the second slit 31b is disposed at one end of the pair of first slits 31a.
In such a form, a region sandwiched between the pair of first slits 31 a between the other end of the pair of first slits 31 a and the second slit 31 b constitutes the matching region 35.
なお、本実施の形態においては、前述の通り、前記アンテナ面30を矩形状としたが、当然ながら、該アンテナ面30は斯かる形態に限定されるものではない。
例えば、該アンテナ面30を円形状又は楕円形状とすることも可能である。
斯かる場合には、第1スリット31aと平行な長さ方向に関する中心線(円形又は楕円形の中心を通り、且つ、第1スリット31aと直交する直線)を基準にして、長さ方向の距離aの±20%(より好ましくは、±10%)の範囲内を、前記低電圧部位と擬制することができる。
In the present embodiment, as described above, the antenna surface 30 has a rectangular shape, but the antenna surface 30 is naturally not limited to such a form.
For example, the antenna surface 30 can be circular or elliptical.
In such a case, the distance in the length direction with reference to the center line (the straight line passing through the center of the circle or ellipse and perpendicular to the first slit 31a) in the length direction parallel to the first slit 31a. The range of ± 20% of a (more preferably ± 10%) can be assumed as the low voltage region.
前記送受信素子は、前記整合回路を介して前記アンテナ面30に接続される。
具体的には、前記送受信素子は、一対の接続端子が、前記第2スリット31bを挟んで一方側及び他方側にそれぞれ位置する第1給電点41及び第2給電点42(図2参照)において、前記アンテナ面30に接続されている。
The transmitting / receiving element is connected to the antenna surface 30 through the matching circuit.
Specifically, the transmission / reception element includes a pair of connection terminals at a first feeding point 41 and a second feeding point 42 (see FIG. 2), which are located on one side and the other side, respectively, across the second slit 31b. , Connected to the antenna surface 30.
このように本実施の形態に係るパッチアンテナ1においては、前記アンテナ面30に前記誘電体20を露出させる開口31を設け、該開口によって露出する誘電体20によって画される前記整合領域35を、送受信素子に対する整合回路として用いており、従って、整合回路がアンテナ面の外部に設けられた従来構成(図8参照)に比して、可及的な小型化を図ることができる。 Thus, in the patch antenna 1 according to the present embodiment, the antenna surface 30 is provided with the opening 31 for exposing the dielectric 20, and the matching region 35 defined by the dielectric 20 exposed by the opening is As a matching circuit for the transmission / reception element, the matching circuit can be miniaturized as much as possible as compared with the conventional configuration (see FIG. 8) in which the matching circuit is provided outside the antenna surface.
又、本実施の形態においては、前述の通り、前記第2スリット31bを挟んで一方側及び他方側にそれぞれ位置する第1及び第2給電点41,42において、前記送受信素子の一対の接続端子を前記アンテナ面30に接続可能としており、該送受信素子の一対の接続端子が同一平面内において接続されるようになっている。
従って、一対の接続端子が、それぞれ、誘電体の厚みに相当する距離だけ上下に離間されたグラウンド面及びアンテナ面に接続される従来構成(図8参照)に比して、送受信素子の接続作業を極めて簡略化及び効率化することができる。
Further, in the present embodiment, as described above, a pair of connection terminals of the transmitting / receiving element at the first and second feeding points 41 and 42 respectively located on one side and the other side across the second slit 31b. Can be connected to the antenna surface 30 and a pair of connection terminals of the transmitting and receiving elements are connected in the same plane.
Therefore, compared to the conventional configuration (see FIG. 8) in which the pair of connection terminals are connected to the ground plane and the antenna plane that are separated from each other by a distance corresponding to the thickness of the dielectric, the transmission / reception element connection operation is performed. Can be greatly simplified and made efficient.
さらに、本実施の形態においては、図2に示すように、前記第2スリット31bが、前記低電圧部位に近接するように、前記開口31を形成している。
斯かる構成によれば、前記第1給電点41が前記低電圧部位に位置することになり、該第1給電点41に接続される前記送受信素子における一方の接続端子が、グラウンド電圧に近い状態とされる。
従って、本実施の形態に係るパッチアンテナ1の性能を、従来のパッチアンテナが持つ性能と同等とすることができる。
Further, in the present embodiment, as shown in FIG. 2, the opening 31 is formed so that the second slit 31b is close to the low voltage region.
According to such a configuration, the first feeding point 41 is located in the low voltage region, and one connection terminal of the transmitting / receiving element connected to the first feeding point 41 is close to the ground voltage. It is said.
Therefore, the performance of the patch antenna 1 according to the present embodiment can be made equal to the performance of the conventional patch antenna.
なお、本実施の形態においては、前述の通り、前記第2スリット31bが前記低電圧部位に近接するように、該第2スリット31bをアンテナ面30の長手方向中心線Cの近傍に位置させたが(図2参照)、これに代えて、前記第2スリット31bを前記第一対の第1スリットの他端部(アンテナ面30の長手方向中心線Cから離間された側の端部)に位置させたり(図3参照)、前記第2スリット31bを前記一対の第1スリット31aの中間部に位置させることも可能である(図4参照)。 In the present embodiment, as described above, the second slit 31b is positioned in the vicinity of the longitudinal center line C of the antenna surface 30 so that the second slit 31b is close to the low voltage portion. (Refer to FIG. 2) Instead, the second slit 31b is connected to the other end of the first pair of first slits (the end on the side separated from the longitudinal center line C of the antenna surface 30). Alternatively, the second slit 31b can be positioned in the middle of the pair of first slits 31a (see FIG. 4).
図3に示す形態においては、前記一対の第1スリット31aの一端部と前記第2スリット31bとの間において、該一対の第1スリット31aによって挟まれる領域が、前記整合回路として作用する前記整合領域35となる。
又、図4に示す形態においては、前記一対の第1スリット31aの他端部と前記第2スリット31bとの間において、該一対の第1スリット31aによって挟まれる領域36と、前記一対の第1スリット31aの一端部と前記第2スリット31bとの間において、該一対の第1スリット31aによって挟まれる領域37とが、前記整合回路として作用する前記整合領域35となる。
なお、図3及び図4に示す何れの形態においても、前記第1及び第2給電点41,42は、前記第2スリット31bを挟んで両側に配置される。
In the form shown in FIG. 3, a region sandwiched between the pair of first slits 31a between the one end of the pair of first slits 31a and the second slit 31b functions as the matching circuit. Region 35 is formed.
In the embodiment shown in FIG. 4, the region 36 sandwiched between the pair of first slits 31a and the pair of first slits 31a between the other end of the pair of first slits 31a and the second slit 31b. Between one end of one slit 31a and the second slit 31b, a region 37 sandwiched between the pair of first slits 31a is the matching region 35 that functions as the matching circuit.
3 and 4, the first and second feeding points 41 and 42 are arranged on both sides of the second slit 31b.
ここで、本実施の形態に係るパッチアンテナ1の一実施例に関して電磁界シミュレータを用いて行った解析結果について説明する。
図5に、本解析に用いたアンテナ面30の平面寸法を示す。
該アンテナ面30は、ALによって形成されるものとし、長手方向Lに沿った辺a1及び辺a2の長さa及び幅方向Wに沿った辺b1及び辺b2の長さbは共に26.4mmとした。
又、前記一対の第1スリット31aは長さmが7.2mmで、該一対の第1スリット31aの間隔は、それぞれの外側のエッジ間の間隔dを4mmとした。
そして、前記第2スリット31bの幅を0.4mmとすると共に、該第2スリット31bをアンテナ面30の長手方向中心線Cに整列させた。
Here, the analysis result performed using the electromagnetic field simulator regarding one example of the patch antenna 1 according to the present embodiment will be described.
FIG. 5 shows the planar dimensions of the antenna surface 30 used in this analysis.
The antenna surface 30 is formed by AL, and the length a of the side a1 and the side a2 along the longitudinal direction L and the length b of the side b1 and the side b2 along the width direction W are both 26.4 mm. It was.
The pair of first slits 31a has a length m of 7.2 mm, and the distance between the pair of first slits 31a is 4 mm between the outer edges.
The width of the second slit 31b was set to 0.4 mm, and the second slit 31b was aligned with the longitudinal center line C of the antenna surface 30.
前記誘電体20の材質はFR−4(比誘電率εr=4.7)で、送受信素子50のインピーダンスは9.5−j56(Ω)とし、上部が自由空間とされた金属ボックス内に、前記アンテナ面30及び前記送受信素子50を配置させた。 The material of the dielectric 20 is FR-4 (relative permittivity εr = 4.7), the impedance of the transmitting / receiving element 50 is 9.5-j56 (Ω), and the antenna is placed in a metal box whose upper part is free space. The surface 30 and the transmitting / receiving element 50 were disposed.
図6に、前記アンテナ面における電流密度分布を示す。
前記アンテナ面30の長手方向Lに沿って、辺b1から辺b2へ向かって電流の波が生じており、長手方向Lに関する中心線C近傍で電流が最大(即ち、高周波電圧が最小)となっている。
斯かる中心線C近傍が前記低電位部位である。
なお、辺b1及び辺b2において、高周波電圧が最大となるが、その極性は逆である。
FIG. 6 shows a current density distribution on the antenna surface.
A wave of current is generated from the side b1 to the side b2 along the longitudinal direction L of the antenna surface 30, and the current becomes maximum (that is, the high-frequency voltage is minimum) in the vicinity of the center line C with respect to the longitudinal direction L. ing.
The vicinity of the center line C is the low potential portion.
In addition, in the side b1 and the side b2, the high frequency voltage becomes maximum, but the polarity is reversed.
又、図7に、本解析に用いたアンテナ面30及び送受信素子50の放射特性を示す。
図7は、far field と呼ばれるもので、前記アンテナ面30及び送受信素子50によって構成されるRFIDインレットから、上方へ離間された場所における電界強度を角度別にプロットしたものである。
図7中のプロット○は、辺a1及び辺a2に接離する方向に沿った角度別の値であり、プロット□は、辺b1及び辺b2に接離する方向に沿った角度別の値である。
FIG. 7 shows the radiation characteristics of the antenna surface 30 and the transmitting / receiving element 50 used in this analysis.
FIG. 7 is a field called a far field, in which the electric field strength at a location spaced upward from the RFID inlet constituted by the antenna surface 30 and the transmitting / receiving element 50 is plotted by angle.
Plot ◯ in FIG. 7 is a value for each angle along the direction contacting / separating the sides a1 and a2, and a plot □ is a value for each angle along the direction contacting / separating the sides b1 and b2. is there.
図7から明らかなように、本実施の形態に係るパッチアンテナ1は、ほぼ3〜6dBiの利得があり、良好な放射特性が得られることが確認できる。
グラウンド面に対して垂直方向に特に良好な利得が得られると共に、かなり低い打ち上げ角においても十分な利得が得られている。
As is apparent from FIG. 7, the patch antenna 1 according to the present embodiment has a gain of approximately 3 to 6 dBi, and it can be confirmed that good radiation characteristics can be obtained.
A particularly good gain is obtained in a direction perpendicular to the ground surface, and a sufficient gain is obtained even at a considerably low launch angle.
1 パッチアンテナ
10 グラウンド面
20 誘電体
30 アンテナ面
31 開口
31a 一対の第1スリット
31b 第2スリット
41,42 給電点(送受信素子とパッチアンテナとの接続点)
DESCRIPTION OF SYMBOLS 1 Patch antenna 10 Ground surface 20 Dielectric 30 Antenna surface 31 Opening 31a A pair of 1st slit 31b 2nd slits 41 and 42 Feeding point (connection point of a transmission / reception element and a patch antenna)
Claims (7)
前記アンテナ面には、前記誘電体を露出させる開口が設けられており、
前記開口は、前記アンテナ面のうち該開口を介して露出する誘電体によって画される領域が送受信素子に対する整合回路を形成するように構成されていることを特徴とするパッチアンテナ。 A patch antenna having a ground surface and an antenna surface with a dielectric interposed therebetween,
The antenna surface is provided with an opening for exposing the dielectric,
The patch antenna is configured so that a region defined by a dielectric exposed through the opening on the antenna surface forms a matching circuit for a transmission / reception element.
前記第2スリットを挟んだ一方側及び他方側が、前記送受信素子の一対の接続端子にそれぞれ接続されることを特徴とする請求項1又は2に記載のパッチアンテナ。 The opening has a pair of first slits extending in parallel so as to face each other, and a second slit communicating the pair of first slits,
3. The patch antenna according to claim 1, wherein one side and the other side across the second slit are connected to a pair of connection terminals of the transmission / reception element, respectively.
前記アンテナ面には、前記誘電体を露出させる開口であって、互いに対向するように平行に延びる一対の第1スリットと、該一対の第1スリットを連通する第2スリットとを有する開口が形成され、
前記アンテナ面のうち前記開口を介して露出する誘電体によって画される領域は、一端部が前記アンテナ面のうち高周波電圧の低い部位に近接されており、
前記送受信素子は、前記一対の接続端子が前記第2スリットを挟んだ一方側及び他方側において前記アンテナ面に接続されていることを特徴とするRFIDインレット。 An RFID inlet comprising a patch antenna having a ground surface and an antenna surface through which a dielectric is inserted, and a transmitting / receiving element having a pair of connection terminals,
An opening that exposes the dielectric and has a pair of first slits extending in parallel to face each other and a second slit that communicates with the pair of first slits is formed on the antenna surface. And
The region defined by the dielectric exposed through the opening in the antenna surface has one end close to a portion of the antenna surface where the high-frequency voltage is low,
The RFID inlet, wherein the transmitting / receiving element has the pair of connection terminals connected to the antenna surface on one side and the other side across the second slit.
前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置することを特徴とする請求項4又は5に記載のRFIDインレット。 The antenna surface is a rectangle whose length in the length direction parallel to the first slit is L and whose distance in the width direction perpendicular to the first slit is W,
6. The RFID according to claim 4, wherein one end of the region on the antenna surface is located within a range of ± L × 0.1 with respect to L / 2 with respect to the length direction. Inlet.
前記アンテナ面における前記領域は、一端部が、長さ方向に関し、L/2を基準にして±L×0.1の範囲内に位置することを特徴とする請求項4又は5に記載のRFIDインレット。
The antenna surface has a circular or elliptical shape with a distance L in the length direction parallel to the first slit,
6. The RFID according to claim 4, wherein one end of the region on the antenna surface is located within a range of ± L × 0.1 with respect to L / 2 with respect to the length direction. Inlet.
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