JP2006235665A - Command tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a command tester for detecting a failure caused by to a hardware defective obstacle generated in the input/output section of equipment under test such as a storage product in an early stage. <P>SOLUTION: This command tester is provided with a processor 2-1 for control for controlling a channel adapter 3 mounted on a host interface rack, and for managing access with equipment under test connected to a channel adapter, a plurality of back panels BP to which channel adapters 3 which can be controlled by a processor 1-1 for control are connected, a plurality of data managing means 2-2 and 2-3 having comparing means and a host interface mounted rack 2 equipped with a switching means for selectively connecting the data managing means 2-2 and 2-3 to the channel adapter. An exclusive program for the channel adapter is downloaded to the channel adapter 3 by the processor for control at the time of IPL, and control with the equipment under test connected to the channel adaptor is executed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention provides a command tester for evaluating the input / output function of a storage product.

  Patent Document 1 shown as a conventional example in FIG. 6 shows that a computer system uses a pseudo-fault circuit that generates a pseudo-fault signal and generates a pseudo fault in a storage device for evaluation.

  In FIG. 6, the storage device 21 has an interface response function 22 and a data transmission / reception function 23, and also includes an interface pseudo-fault circuit 24 that generates a pseudo-fault signal indicating an abnormal response of the interface, and data such as data mismatch. A pseudo fault generation circuit including a data pseudo fault circuit 25 that generates a pseudo fault signal indicating an abnormality and a hardware pseudo fault circuit 26 that generates a pseudo fault signal indicating a hardware fault is incorporated.

The pseudo-fault generation circuit has an independent communication control circuit 27 separate from the interface, and exchanges a pseudo-fault occurrence instruction and a fake fault occurrence state to the external device via the communication control circuit 27. Therefore, an arbitrary pseudo failure can be generated at an arbitrary timing.
JP 2002-116885 A

  In the above prior art, the evaluation of storage products is performed in the same usage environment as the user usage environment. In other words, since a real host device and OS are used, the protocol for input / output of the storage product is evaluated only for the normal system.

  For this reason, when a fault is found in the input / output function part of a storage product due to a faulty hardware failure such as a bad cable connection between the host device and the storage product by the user from time to time, there is a problem between the host device and the storage product. It was necessary to search for the cause of the failure by obtaining and plugging in the cable and testing it, and it took time and effort to investigate the cause.

  Accordingly, an object of the present invention is to provide a storage product command tester which can detect and correct a malfunction caused by such a hardware failure at an early stage of evaluation of the storage product.

  In order to solve the above problems, in the present invention, a control processor that controls a channel adapter mounted in a host interface rack and manages access to a device under test connected to the channel adapter, and a control processor respectively. A host interface rack having a plurality of back panels to which controllable channel adapters are connected, a plurality of data management means having comparison means, and a switching means for selectively connecting the data management means to the channel adapter A command for downloading to the channel adapter a dedicated program for each channel adapter from the control processor at the time of IPL and enabling control with the device under test connected to the channel adapter. Provide a tester.

  The dedicated interface board connected to the back panel or expansion board is a one-to-one connection. If an abnormality occurs in one board, it can only be used continuously, but in the present invention, one When an abnormality is detected on the board, it is possible to continue use by switching to another channel, so that the maintenance of the board or cable can be performed at an arbitrary time.

  Further, by switching to another channel or restoring to a channel in which an abnormality has been detected, it is possible to continue input / output with the device under test and to check the consistency of the entire process.

  An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration diagram of the present invention, and FIG. 2 shows a schematic block diagram of the present invention. In the figure, 1 is a control personal computer, 2 is a host interface mounting rack, 3 is a channel adapter, and 4 is a storage product as a device under test.

  The control personal computer 1 controls the channel adapter 3 mounted on the host interface mounting rack 2 and manages access to the storage product 4 as the device under test. The control personal computer 1 has a CPU 1-1, a storage unit 1-2, It includes an input / output unit 1-3, an interface control board A, and the like.

  The host interface mounting rack 2 is equipped with a plurality of channel adapters 3 that can be controlled by the control personal computer 1, and also includes OCLINK (optical cable link), BMC (electrical channel), FC (fiber channel), FC-Link. A common back panel BP is provided so that channel adapters of different interfaces such as SCSI (Small Computer System Interface) can be mounted, for example, up to 32 channels. Then, data management units 2-2 and 2-3 having a W / R (read / write) buffer and a compare circuit are provided, and one of the channel adapters can be selectively connected to the data management units 2-2 and 2-3. An additional circuit 2-4 such as a multiplexer is provided.

  The host interface mounting rack 2 further includes a main board 2-1 having a CPU, a memory, an expansion bus, etc., and the additional circuit 2-4 has a DMA (direct memory access) function in addition to the multiplexer. Are provided with slots S0 to S31 so that a channel adapter can be mounted. For example, the expansion bus is provided with an additional data management unit so that the number of switchable channel adapters can be connected in a many-to-many manner.

  The host interface mounting rack 2 further includes a storage unit 2-5, an interface control board B, and the like. In the storage unit 2-5, for example, firmware for creating write data is downloaded from the control personal computer 1 at the start of the command tester, and log information during operation is held.

  The channel adapter 3 is compatible with different interfaces such as OCLINK, BMC, FC, FC-Link, and SCSI, for example, and each channel adapter dedicated program is stored in the CPU memory (not shown) at the time of IPL. Downloaded more, the control with the connected storage product is executed.

  The device under test 4 is evaluated by the command tester of the present invention and is a storage product.

  Of the several types of interfaces in the channel adapter, SCSI will be described as a representative.

  As shown in FIG. 3A, there are 11 types of SCSI BUS, from the Data bus to the Reset bus. Of these, only the Data bus has a multiple bit width, and the others have a 1 bit width. In FIG. 3A, I indicates an initiator, that is, a command tester side (channel adapter side), and T indicates a target, that is, a storage product side. The data is output from the channel adapter side to the storage product side and conversely from the storage product side to the channel adapter side, indicating that the data is in both directions (I ← → T), and the request signal (REQ) is the storage (I ← T) indicates that the output is unidirectional only from the product side to the adapter side. In FIG. 3A, attention (ATN) indicates (I → T).

  As shown in FIG. 3B, there are 10 types of phases from arbitration to bus-free. Arbitration (A) is a use permission signal when a plurality of bus use requests are simultaneously issued, and bus free (BF) indicates a state in which the bus before arbitration can be freely used.

  The details conform to the ANSI (American National Standard Institute) standard.

  The function of the command tester of the present invention will be described.

A. Write Data Creation In the present invention, write data can be generated on the host interface mounting rack 2 side in the following cases.

a. Increment b. Decrement c. LBA embedding Increment and decrement respectively increment and decrement a certain value from the initial value.

  In addition, LBA (logical block address designation) is, for example, designated as a data read destination address by incrementing an address starting from “0” by a certain value.

  In cases other than the above, the data generated on the control personal computer 1 side and transferred to the host interface mounting rack 2 is used. In this way, several types of write data can be created.

  These functions are performed by the CPU of the main board 2-1 by the firmware held in the storage unit 2-5, and the interface control board is provided between the control personal computer 1 and the host interface mounting rack 2 by this function. The usage load of A and B is reduced, the busy rate is lowered, and it can be used for other control.

  In addition, this function makes it possible to run a plurality of simulated jobs assuming a normal host device.

B. Specification of access mode This is executed for the storage product 4 in the host interface mounting rack 2 according to an instruction from the control personal computer 1, and specifies the handling of data for writing to the storage product 4, that is, the access method. . Examples of the access mode include those shown in FIGS. “Write only” shown in FIG. 4 a is simply to write the specified data to the storage product connected to the specified channel adapter.

  “Write / Read (no data compare)” shown in FIG. 4b indicates that the specified data is written to the storage product connected to the specified channel adapter and read out, but not compared. Is. “Write / Read (with data compare)” indicated by c in FIG. 4 reads the specified data after writing it to the storage product, and whether the written data matches the read data. Are compared by the compare circuit of the data management units 2-2 and 2-3.

  Further, “read / write / read (first read = data compare is present, second read = present)” indicated by m in FIG. 4 indicates the following designation. That is, the first read data is created as described in the section for creating write data described in A above, for example, and the data where the data is written is used. Therefore, the comparison is possible, and the second read data indicates a read with respect to the data written immediately before and can be compared.

  In this way, various access modes are designated from the control personal computer 1, and these access modes are executed by the main board 2-1, the data management units 2-2, 2-3, the channel adapter 3, etc. of the host interface mounting rack 2. can do.

C. Write / Read / Compare from Channel Designation The mode designated in the item B is written / read / compare in the channel designated in this item.

  a. The operation is performed from the same channel.

  b. This is done by a combination operation between each channel.

  For example, writing is performed in slot 0 of FIG. 2, read + compare in slot 1, and rewrite in slot 2.

  c. If there is no channel designation, the operation is performed on an inactive random channel, that is, an empty channel.

  This operation is performed by the CPU of the main board 2-1 under the firmware according to an instruction from the control processor 1.

D. Each operation of write / read In order to perform inspection at the time of abnormal operation, it is possible to perform abnormal operation by replacing it with designated data during the operation of each phase as shown in FIG. This is performed by each channel adapter 3 according to an instruction from the control processor 1.

  In the arbitration shown by a in FIG. 5, the bus access request source ID can be raised to an abnormal state by changing the protocol at the time of bus acquisition so that the ID different from the normal one is raised or the ID is not raised. .

  In the selection shown by b of FIG. 5, it can be set as an abnormal condition by changing the connection other party.

  In the reselection indicated by c in FIG. 5, an abnormal state can be set by changing the partner to be reconnected.

  In the message-out indicated by d in FIG. 5, an abnormal state can be obtained by changing data designated to the target.

  In the message-in shown by e in FIG. 5, an abnormal state can be set by changing the data designated from the target and making a different response.

  The command indicated by f in FIG. 5 can be brought into an abnormal state by changing a command parameter such as rewriting a command code or setting an unused bit.

  In (g) to (j) of FIG. 5, the data cannot be replaced and is left as it is.

  In addition to this, immediately after the phase shown in FIG. 5 is switched, a designated wait (wait) is placed in a portion such as during transfer (wait can be specified after a specified byte) or after transfer, and an abnormal operation due to timeout occurs. Is possible. If no weight value is set, the default value can be set. In addition, a reset to the target can be arbitrarily issued, and the number of times can be specified, and an abnormal operation state can be obtained.

E. Recovery Operation after Abnormal Processing If it is determined that the operation in the item C is abnormal, it is possible to continue processing on the next same channel or another channel. Switching to another channel can be specified from the control personal computer 1 or can be switched randomly.

a. In the case of continuing operation on the same channel In the case of continuing operation on the same channel, the same channel cannot be used unless it is restored. In this case, it continues based on the interface protocol after a hard reset or soft reset. (The CPU of the main board 2-1 operates under the firmware in response to an instruction from the control personal computer 1)
For example, (1) when a write command is issued to the LBA 10, a timeout is intentionally generated with a specified wait. (2) Next, a hard reset makes the bus free. (3) Issue a write command to the LBA 10 again. (Issued with channel adapter 3)
These are processed in the same channel.

b. In case of continuous operation in other channels In case of continuous operation in other channels, the abnormal channel shifts to a bus-free state based on the interface protocol after hard reset or soft reset for another operation and is restored. Processing on other channels continues.

  For example, (1) a channel adapter (not shown) connected to the slot S1 intentionally generates a timeout with a designated wait when a write command is issued to the LBA 10, and causes the abnormal termination by the wait command. (2) Next, the channel adapter connected to the slot S1 is shifted to bus-free by a hard reset. (3) A write command is issued again to the LBA 10 by the channel adapter connected to the slot S2 or the empty channel during the processing of the item (2). In this way, processing is performed on another channel.

F. Automatic sense acquisition function When the status is “02” (indicating a check condition) from a connected device such as the storage product 4 connected to the channel adapter 3, the channel adapter 3 determines this, and the channel adapter 3 3 collects error information of the connected device and stores it in the storage unit 2-5 as log information.

  At this time, the channel adapter 3 also collects, as log information, the channel number, the issued command, and, for example, 10 commands issued immediately before.

G. Trace function The channel adapter 3 is capable of recording the issued and received each phase and data with a device such as a connected storage product, trace data of the channel number and date, and the like. However, since the data to be transmitted / received in the data phase is enormous, only the first 16 bytes are used, for example. This function enables failure analysis.

  In the present invention, when a test is performed by a command tester by, for example, specifying an access mode shown in FIG. 4C, a normal response is not returned when an abnormality such as a cable failure exists in the input / output function on the storage product side. Therefore, this is detected by the channel adapter 3, and the multiplexer of the additional circuit 2-4 switches the channel in which this abnormality exists to an empty channel that operates normally, or continues the test, or is instructed by the control personal computer 1 It is possible to continue the test by switching to the channel, or to perform the test again by restoring the channel in which the defect is detected according to the instruction of the control personal computer 1 so that, as in the conventional case, a manual cable is used in the case of an abnormality. The work of inserting and removing is unnecessary, and the test can be performed efficiently.

It is a schematic block diagram of this invention. 1 is a schematic block diagram of the present invention. It is explanatory drawing of the kind of scuffy bus | bath and the kind of each phase. It is an access mode designation | designated explanatory drawing. FIG. 6 is an explanatory diagram of each operation state of write / read. It is explanatory drawing of a prior art example.

Explanation of symbols

1 PC for control 2 Rack with host interface 3 Channel adapter 4 Storage product

Claims (3)

A control processor for controlling the channel adapter mounted in the host interface rack and managing access to the device under test connected to the channel adapter;
A host comprising a plurality of back panels to which channel adapters each controllable by the control processor are connected, a plurality of data management means having comparison means, and a switching means for selectively connecting the data management means to the channel adapter Has a rack with an interface,
A command tester, wherein a dedicated program for each channel adapter is downloaded to the channel adapter from the control processor during IPL so that control with a device under test connected to the channel adapter can be executed. .   The command tester according to claim 1, wherein the device under test is a storage product.   By the above switching means, switching to another channel or restoring to a channel in which an abnormality has been detected makes it possible to continue input / output with the device under test and to check the consistency of the entire process. The command tester according to claim 1.

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