JP2006234711A - Time synchronization system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the synchronization accuracy, without making the performance of other communications deteriorate, in synchronizing the times by timers of a plurality of apparatuses that are interconnected, using a network and have a master-slave relation. <P>SOLUTION: This system comprises a connecting device (master) 1, between nodes and a plurality of processor nodes (slaves) 41-43 connected to the connection device between nodes, and synchronizes copy clocks 411-431, built in respective processor nodes with a master clock 3 of the connection device between nodes. The connection device between nodes comprises a time set command generating means 14 for generating the time set command based on the master clock, a communication data storage means 11 for storing the communication data, a communication data interval calculating means 13 for calculating the interval of the communication data, a time set command inserting means 12 for inserting the output of the time set command generating means into the output of the communication data storage means, and a transmittablity determining means 15 for determining the communication data receivable states of the processor nodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a time synchronization system, and more particularly to a time synchronization system that uses a timer to synchronize time for a plurality of devices that are connected by a network and have a master-slave relationship.

  Patent Document 1 describes an example of a method of performing time synchronization using a timer between a plurality of devices connected in a network in a master-slave relationship. As shown in FIG. 16, this time synchronization method is a system composed of a plurality of processor nodes 960A, 960B, and 960N and an inter-node connection device 950 that connects these processor nodes 960A, 960B, and 960N. A master clock 910 is provided, and each of the plurality of processor nodes 960A, 960B, 960N includes a copy clock 961A, 961B, 961N.

  With the above configuration, the internode connection device 950 transmits a time setting signal to all the processor nodes 960A, 960B, and 960N at regular intervals, and the processor nodes 960A, 960B, and 960N copy the time value of the transmitted time setting signal. The clocks 961A, 961B, and 961N are set to synchronize time.

  Here, conventionally, when the inter-node connection device 950 transmits a time setting signal, the time is set depending on other competing communications, waiting time in the transmission buffer, variation in the distance between the inter-node connection device and the processor node, and the like. Since the time until the setting signal is received differs depending on the individual processor nodes 960A, 960B, and 960N, accurate synchronization cannot be performed. Therefore, in order to solve this problem, the invention described in Patent Document 1 adjusts the time setting data using the difference in delay for each of the processor nodes 960A, 960B, and 960N as a correction value, thereby achieving the arrival time of the time setting signal. Even if they are different, the copy clocks 961A, 961B, and 961N of all the processor nodes 960A, 960B, and 960N can be set at the same time.

Japanese Patent Laid-Open No. 2002-14185

  In the conventional time synchronization method described above, the copy clocks 961A, 961B, and 961N included in the processor nodes 960A, 960B, and 960N are slightly shifted even when time synchronization is performed. In order to prevent this, it is necessary to shorten the interval for transmitting the time setting signal. However, in the above-described prior art, the time setting signal interrupts the communication path without confirming the state of other communication. Therefore, another communication waits during interruption or the time setting signal is input into the transmission buffer. Therefore, later communication is waited until the time setting signal is transmitted. That is, if the transmission interval of the time setting signal is shortened in an environment where communication is frequently occurring with the processor nodes 960A, 960B, and 960N, other high-priority communication is delayed and affects the system. there is a possibility.

  Therefore, the present invention has been made in view of the problems in the conventional time synchronization method described above, and in performing time synchronization by timers of a plurality of devices in a master-slave relationship connected by a network, An object of the present invention is to provide a time synchronization system and the like that can improve the accuracy of time synchronization without degrading the communication performance.

  In order to achieve the above object, the present invention includes an inter-node connection device that operates as a master connected via a network, and a plurality of processor nodes that operate as slaves connected to the inter-node connection device. In the time synchronization system for synchronizing the copy clock built in each of the clocks with the master clock built in the inter-node connection device, the inter-node connection device generates a time setting command based on the master clock Creating means; communication data storing means for storing communication data to the processor node; communication data interval calculating means for calculating an interval of the communication data; and output of the communication data storing means at the time setting command creating means A time setting command insertion means for inserting the output of the communication node, and a communication data reception enabled state of the processor node. Characterized in that it comprises a transmittable determining means for disconnection.

  According to the present invention, the communication data interval calculation means calculates the communication data interval to the processor node, and outputs the communication data storage means for storing the communication data to the processor node based on the master clock. Since the output of the time setting command generation means for generating the setting command is inserted, the accuracy of time synchronization can be improved without degrading the performance even when high priority communication occurs frequently.

  In addition, the present invention includes an inter-node connection device that operates as a master connected via a network, and a plurality of processor nodes that operate as slaves connected to the inter-node connection device, and each of the processor nodes is built in In a time synchronization system that synchronizes a copy clock with a master clock built in the internode connection device, the internode connection device includes a time setting command creating means for generating a time setting command based on the master clock, and Communication data storage means for storing communication data to the processor node, time setting instruction insertion means for inserting the output of the time setting instruction creation means into the output of the communication data storage means, and communication data of the processor node can be received Transmission capability determining means for determining a state, and each of the processor nodes includes the node Characterized in that it comprises a time setting command discarding means to disable incomplete time setting command received from between the connection device.

  According to the present invention, since each of the processor nodes invalidates the incomplete time setting command received from the inter-node connection device by the time setting command discarding means, high priority communication frequently occurs. However, the accuracy of time synchronization can be improved without degrading performance.

  Furthermore, the present invention is an inter-node connection device that is connected to a plurality of processor nodes and synchronizes a copy clock built in each of the plurality of processor nodes with a built-in master clock, based on the master clock. Time setting command generating means for generating a setting command, communication data storing means for storing communication data to the processor node, communication data interval calculating means for calculating an interval of the communication data, and output of the communication data storing means And a time setting command insertion unit for inserting the output of the time setting command generation unit, and a transmission capability determination unit for determining a communication data receivable state of the processor node. As a result, as described above, it is possible to improve the accuracy of time synchronization without degrading the performance even when high priority communication frequently occurs in the network.

  In addition, the present invention is a processor node which is connected to an internode connection device having a built-in master clock and has a copy clock synchronized with the master clock, wherein the incomplete time setting received from the internode connection device Time setting command discarding means for invalidating the command is provided. As a result, as described above, it is possible to improve the accuracy of time synchronization without degrading the performance even when high priority communication frequently occurs in the network.

  As described above, according to the present invention, when performing time synchronization by timers of a plurality of devices connected in a master-slave relationship with a network, the accuracy of time synchronization can be achieved without degrading the performance of other communications. Can be improved.

  FIG. 1 shows a first embodiment of a time synchronization system according to the present invention. This time synchronization system includes a plurality of processor nodes 41, 42, and 43 that perform calculations, and these processor nodes 41 to 43. And an inter-node connection device 1 for connecting the two.

  The internode connection apparatus 1 includes a communication control unit 2, a plurality of communication data transmission units 101, 102, and 103 that receive communication data from the communication control unit 2 and send the communication data to the processor nodes 41 to 43, and a master clock 3. With.

  The processor node 41 includes a reception buffer unit 410 and a copy clock 411, the processor node 42 includes a reception buffer unit 420 and a copy clock 421, and the processor node 43 includes a reception buffer unit 430 and a copy clock 431. With.

  The communication data transmission unit 101 is connected to the processor node 41 on a one-to-one basis, receives data from the communication control unit 2, and stores a communication buffer (communication data storage unit) 11 that stores communication data. Create a time setting command based on the time data sent from the time setting command insertion unit (time setting command insertion means) 12 for inserting a time setting command for time synchronization in the gap between the communication data to be sent and the master clock 3 And a communication data interval calculation unit (communication data interval calculation unit) 13 for calculating a gap between communication data sent from the transmission buffer unit 11 to the time setting command insertion unit 12. And the number of communication data that can be sent based on the number of communication data output from the time setting command insertion unit 12 and the number of return communications for the communication data. Busy control unit for controlling composed of a (transmittable judgment means) 15.

  Next, an operation when a time setting command is issued when communication data is going to be transmitted from the internode connection apparatus 1 to the processor node 41 will be described with reference to FIGS.

  Communication data D1 from the communication control device 2 to the communication data transmission unit 101 is input to the communication data transmission unit 101 through the signal line 1a, received by the transmission buffer unit 11, and stored. The communication data constitutes one block with a plurality of words, has a check code for each block, and checks the block after reception. The transmission buffer unit 11 performs a check for each block, and can transmit to the time setting command insertion unit 12 after the check is completed. This state is the state of the clock 14 in FIG.

  The communication data D1 that can be sent is sent to the processor node 41 via the signal line 1b via the time setting command insertion unit 12 if the processor node 41 can accept the signal from the busy control unit 15. It is done.

  The master clock 3 transmits time data to the time setting command generators 14 of all the communication data transmitters 101 to 103 so that all the processor nodes 41 to 43 can synchronize. . The time setting command creating unit 14 creates the time setting command TC shown in FIG. 3 by adding the delay error adjustment value to the time data from the master clock 3.

  The time setting command TC is composed of two words, and a valid flag indicating that the data is valid for all words, and the first word 0 includes a command field indicating that the communication data is the time setting command TC. The second word 1 is composed of a time received from the master clock 3 and a data field for setting time data obtained by adding delay data to the processor node 41.

  As shown in FIG. 4, the distances L1, L2, and L3 between the internode connection apparatus 1 and the processor nodes 41, 42, and 43 may all be different, and therefore the time setting command TC is set to each processor node 41. The time to reach ~ 43 is also different. Therefore, the difference is reflected in advance in the time data as a delay error adjustment value, and when the processor nodes 41 to 43 set the time data in the copy clocks 411 to 431, the processor nodes 41 to 43 have the same time. To.

  The time setting command creation unit 14 sends a time setting command TC at a predetermined interval. This utilizes, for example, that the low-order bits of time data transmitted from the master clock 3 become a predetermined bit pattern at regular intervals.

  When it is time to issue the time setting command TC, the time setting command insertion unit 12 does not accept the time setting command TC from the time setting command creation unit 14 until the communication data passes through the time setting command insertion unit 12, and communicates. When the last data of the data is sent from the time setting command insertion unit 12, the data is switched to accept the data from the time setting command creation unit 14, and the first half of the time setting command TC is sent at the next timing. The second half of the time setting instruction TC is sent to the processor node 41 at the timing.

  The processor node 41 receives communication data at the reception buffer unit 410. When the time setting command TC is received, the time data of the time setting command TC is set in the copy clock 411, and the synchronization deviation with the other processor nodes 42 and 43 is corrected.

  As shown in FIG. 2, when the communication data D2 is sent from the communication control unit 2 after the communication data D1, the time setting command insertion unit 12 is connected to the time setting command creating unit 14 side after the communication data D1 passes. It does not necessarily switch to. In this case, the communication data interval calculation unit 13 calculates the interval between the communication data D1 and the communication data D2, and the switching is performed only when an interval in which the time setting command TC can be inserted can be secured.

  The communication data interval calculation unit 13 can analyze the contents of the communication data input from the signal line 1a to know the number of words in one block. Further, from the values of the write pointer and the read pointer of the transmission buffer unit 11, The total number of words of communication data existing in the transmission buffer unit 11 is calculated and compared with the total number of words of communication data being input. In the case of this example, when the last word of the communication data D1 comes out from the transmission buffer unit 11, the total number of words of the communication data D2 and the total number of words of communication data existing in the transmission buffer unit 11 And the time setting command insertion unit 12 switches to the signal on the time setting command creating unit 13 side. This state is the state of the clock 9.

  However, when the number of words of the communication data D2 is 6 words as in the example shown in FIG. 5, the interval between the communication data D1 and the communication data D2 is only one cycle as in the clock 15 of FIG. Since it is not empty, the time setting command insertion unit 12 is not switched, but is switched after the communication data D2 passes like the clock 23.

  The busy control unit 15 counts the number of communication data output from the communication data transmission unit 101 to the processor node 41 and the number of receptions transmitted from the processor node 41, and the communication data of the processor node 41 at that time is counted. Calculate the number of receivables. When the receivable number reaches the preset maximum receivable number of communication data of the partner device, a busy signal is sent to the transmission buffer unit 11 and the time setting command insertion unit 12, and the communication data and time setting command TC are transmitted. Stops sending.

  Next, a second embodiment of the time synchronization system according to the present invention will be described with reference to the drawings.

  As shown in FIG. 6, the time synchronization system includes a plurality of processor nodes 51, 52, and 53 that perform calculations, and an inter-node connection device 1 that connects these processor nodes 51 to 53.

  The internode connection apparatus 1 includes a communication control unit 2, a plurality of communication data transmission units 201, 202, and 203 that receive communication data from the communication control unit 2 and send the communication data to the processor nodes 51 to 53, and a master clock 3. With.

  The processor node 51 includes a reception buffer unit 510, a copy clock 511, and a communication data analysis control unit (time setting command discarding unit) 512. The processor node 52 includes a reception buffer unit 520, a copy clock 521, and a communication data analysis control unit 522. The processor node 53 includes a reception buffer unit 530, a copy clock 531, and a communication data analysis control unit 532.

  The communication data transmission unit 201 is connected to the processor node 51 on a one-to-one basis, receives a communication from the communication control unit 2, and stores communication data (communication data storage unit) 21. A time setting command insertion unit (time setting command insertion means) 22 for inserting a time setting command TC for time synchronization in a gap between transmitted communication data and a time setting command TC based on the time data transmitted from the master clock 3 The number of communication data that can be sent based on the number of communication data output from the time setting command generating unit (time setting command generating means) 24 and the number of communication data output from the time setting command insertion unit 22 And a busy control unit (transmission enable determination means) 25 for controlling the transmission.

  Next, a case where a time setting command is issued when communication data is about to be transmitted from the internode connection apparatus 1 to the processor node 51 will be described with reference to FIGS. 6 and 7.

  Communication data D1 from the communication control device 2 to the communication data transmission unit 201 is input to the communication data transmission unit 201 through the signal line 2a, and is received and stored by the transmission buffer unit 21. The communication data constitutes one block with a plurality of words, has a check code for each block, and checks the block after reception. The transmission buffer unit 21 performs a check for each block, and can transmit to the time setting command insertion unit 22 after the check is completed. This is the state of the clock 14 in FIG.

  The communication data D1 that can be sent is sent to the processor node 51 via the signal line 2b via the time setting command insertion unit 22 if the processor node 51 can accept the signal from the busy control unit 25. It is done.

  At this time, if the time setting command creation unit 24 is about to issue the time setting command TC, the time setting command insertion unit 22 causes the time setting command creation unit 24 until the communication data D1 passes through the time setting command insertion unit 22. When the last data of the communication data D1 is transmitted from the time setting command insertion unit 22, the time setting command TC is switched to accept data from the time setting command creating unit 24, and the time is set at the next timing. The first half of the setting command TC is sent, and the second half of the time setting command TC is sent to the processor node 51 at the next timing.

  The processor node 51 receives communication data at the reception buffer unit 510. When the time setting command TC is received, the time data of the time setting command is set in the copy clock 511, and the synchronization deviation with the other processor nodes 52 and 53 is corrected.

  If the communication data D2 is sent from the communication control unit after the communication data D1, and the interval between the communication data D1 output from the transmission buffer unit 21 and the communication data D2 is 0, the time setting command The insertion unit 22 does not switch to the time setting command creation unit 24 side. However, as shown by the clock 16 in FIG. 8, if there is an interval even in one cycle, the time setting instruction insertion unit 22 switches to the time setting instruction creation unit 24 side. In the case of one cycle, the time setting command insertion unit 22 is switched to the transmission buffer unit 21 side with the time setting command TC being incomplete, and the next communication data D2 is sent to the signal line 2b. When receiving the switching signal from the time setting command insertion unit 22 and knowing that the transmission of the time setting command TC has failed, the time setting command creating unit 24 sends the time setting command TC again.

  In the communication data analysis control unit 512, the processor node 51 checks the communication data received by the reception buffer unit 510. In the case of an incomplete time setting command TC, the processor node 51 outputs the command as in the clock 22 of FIG. It is discarded and erroneous data is prevented from being set in the copy clock 511.

  The time setting command creating unit 24 receives the current time from the master clock 3, and creates the time setting command TC shown in FIG. The time setting command TC is composed of two words, each word has a position field indicating the start, middle, and end of communication, and the first word 0 is a command indicating that this communication data is the time setting command TC. The second word 1 is composed of a data field for setting time data obtained by adding the time received from the master clock 3 and the delay data to the processor node 51.

  In addition, the time setting command creation unit 24 receives the switching signal from the time setting command insertion unit 22, and when the switching time to the time setting command creation unit 24 side of the switching signal is shorter than the time setting command sending time, It is considered that the transmission has failed, and the time setting command is transmitted again.

  The busy control unit 25 counts the number of communication data output from the communication data transmission unit 201 to the processor node 51 and the number of receptions transmitted from the processor node 51, and the processor node 51 receives the communication data at that time. Calculate the possible number. When the receivable number reaches the preset maximum communication data receivable number of the counterpart device, a busy signal is transmitted to the transmission buffer unit 21 and the time setting command insertion unit 22 to transmit the communication data and the time setting command. Stop.

  As described above, in the first embodiment, communication data having a larger number of words than communication data transmitted from the communication control unit 2 cannot be inserted, but in the second embodiment, insertion is performed. There is an advantage that there is no limit on the number of words in communication data that can be transmitted.

  Next, an embodiment in which a time setting command TC is issued when communication data D1 and D2 are to be transmitted from the internode connection apparatus 1 shown in FIG. 1 to the processor node 41 will be described with reference to FIGS. This will be described with reference to FIG.

  The communication control unit 2 includes an output register 91 that transmits communication data to the communication data transmission unit 101. The reception register 111, the transmission buffer 112, the write pointer 113, the read pointer 114, and the communication data analysis control unit 115 constitute the transmission buffer unit 11 of FIG. 1 and include a register 132, a register 135, a fixed value input signal line 133, and a selector 134. The pointer calculation unit 138 constitutes the communication data interval calculation unit 13 in FIG. 1, and the selector 121, the register 122, the NOR circuit 123, and the decoder 124 constitute the time setting instruction insertion unit 12 in FIG. The register 143, the adder 146, the decoder 144, the register 145, the register 147, the time setting instruction data 148, and the selector 141 constitute the time setting instruction creating unit 14 in FIG. 1, and include the register 151, the register 152, the addition counter 153, and the addition. Counter 155, arithmetic unit 154, register 1 6, the decoder 157 constitute a busy controller 15 of FIG. 1. Further, the processor node 41 includes a communication data analysis control unit 412, a copy clock 431, a reception register 4101, a reception buffer 4102, and a register 4103 that constitute the reception buffer unit 410 of FIG.

  The communication data transmission unit 101 receives the communication data transmitted from the output register 91 of the communication control unit 2 by the reception register 111 (clocks 2 to 7 in FIG. 11). The communication data entered in the reception register 111 is sent to the transmission buffer 112 and the communication data analysis control unit 115. The communication data analysis control unit 115 performs error analysis and communication data type analysis of the transmitted communication data, and controls the write pointer 113 and the read pointer 114 of the transmission buffer 112. The transmission buffer 112 is a FIFO buffer that performs reading in the order of writing.

  After confirming that the communication data is normal, the communication data analysis control unit 115 sends out a necessary number of strobe signals to the read pointer 113 if the communication data can be transmitted to the processor node 41, and transmits the transmission buffer 112. (Clocks 9 to 14 in FIG. 11). Further, the communication data analysis control unit 115 analyzes the communication data and sends the number of data words to the register 132, sets the register 135 to “1” at the beginning of the communication data, and sets the register 135 at the end of the communication data. Set to “0”.

  When the number of words of communication data sent from the communication data analysis control unit 115 is set, the register 132 holds the current value until the next value is set. The fixed value input signal line 133 inputs the minimum number of words of communication data transmitted from the communication control unit 2 to the selector 134 as a fixed value. In the example of FIG. 11, it is set to 4 words. The selector 134 is switched by the output of the register 135. When the register 135 is “0”, the fixed value input signal line 133 is selected, and when the register 135 is switched from “0” to “1”, the register is registered in the next cycle. Select 132. The pointer calculation unit 138 performs the following calculation using the values of the write pointer 113, the read pointer 114, and the selector 134.

  Selector 134-(write pointer 113-read pointer 114)-number of words of time setting instruction> 0

  The pointer calculation unit 138 outputs “0” to the NOR circuit 123 when the above expression is satisfied, and outputs “1” when the expression is not satisfied. The selector 121 switches between the output of the transmission buffer 112 and the output of the selector 141 according to the output of the NOR circuit 123. When the output of the NOR circuit 123 is “0”, the transmission buffer 112 is selected, and when it is “1”, the selector 141 is selected. The output of the selector 121 is input to the register 122 and sent to the reception register 4101 of the processor node 41. The output of the selector 121 is sent to the decoder 124 at the same time.

  The register 142 receives time data from the master clock 3 and transmits the time data to the adder 146 and the decoder 144. The register 143 stores in advance a delay adjustment value for the processor node 41 for aligning the delay from the inter-node connection device 1 to the processor node 41 and the delay between the inter-node connection device 1 and another processor node. The value is sent to adder 146. The adder 146 adds the time data from the register 142 and the delay adjustment value from the register 143 and transmits the result to the selector 141.

  The decoder 144 decodes a part of the time data from the register 142, and transmits “1” to the register 145 in the case of a specific value. As a result, the register 145 is set to “1” at regular intervals. The register 145 is reset when “1” is set from the decoder 144 and “1” is transmitted from the NOR circuit 123. In the case of simultaneous transmission, the set of “1” from the decoder 144 has priority. In the time setting command data 148, the command field time setting command TC of word 0 in FIG. 3 is set, and the value of the register 145 is inserted into the valid flag portion.

  The register 147 stores the output of the NOR circuit 123, and the output becomes a selection signal of the selector 141. The selector 141 switches between the time setting command data 148 and the output of the adder 146. When the selection signal from the register 147 is “0”, the time setting command data 148 is selected, and when it is “1”, the adder 146 is selected. When the time setting command data 148 is selected, “1” is inserted at the position of the valid flag of word 1 in FIG.

  The decoder 124 decodes the output of the register 122 and sends “1” to the register 156 when the head of communication data is received. When “1” is transmitted from the decoder 124, the register 156 stores the output of the counter 155, and the output is transmitted to the counter 155 and the arithmetic unit 154. The counter 155 adds 1 to the output of the register 156 and transmits it to the register 155. As a result, each time one piece of communication data is sent from the internode connection apparatus to the processor node 41, the value of the register 156 is counted up.

  When receiving communication is transmitted from the processor node 41, the decoder 157 sends “1” to the register 151, and when receiving “1”, the register 151 sends “1” to the register 152. When “1” is transmitted from the register 151, the register 152 stores the output of the counter 153, and the output is sent to the counter 153 and the arithmetic unit 154. The counter 153 adds 1 to the output of the register 152 and transmits it to the register 152. As a result, the value of the register 152 is incremented every time a received communication is returned from the processor node 41. The arithmetic unit 154 subtracts the value of the register 152 from the output value of the register 156, and when the result becomes the number of communication data that the processor node 41 can receive at a time, “1” is analyzed with the NOR circuit 123 and the communication data analysis. The data is sent to the control unit 115.

  The reception register 4101 stores the communication data transmitted from the register 122 of the communication data transmission unit 101. The communication data is sent to the reception buffer 4102, the communication data analysis control unit 412, and the copy clock 431. The communication data analysis control unit 412 analyzes the communication data, notifies the copy clock 431 if it is a time setting command TC, and transmits a control signal to the reception buffer 4102 if it is other communication. In either case, the received communication is returned to the communication data transmitting unit 101. The reception buffer 4102 stores communication data excluding the time setting command TC under the control of the communication data analysis control unit 412, and outputs the communication data to the register 4103 under the control of the analysis control unit 412. The copy clock 431 has a clock function, and sets the value of the time data portion of the time setting command TC in the clock under the control of the communication data analysis control unit 412.

  FIG. 11 shows a case where D1 is 6 words and D2 is 8 words, and a case where the time setting instruction TC can be inserted between D1 and D2 by clocks 15 and 16 is shown. On the other hand, FIG. 12 shows a case where both D1 and D2 are 6 words, and the time setting instruction TC cannot be inserted between D1 and D2 at clock 15, and the time setting instruction at clocks 22 and 23 after D2. The case where TC is inserted is shown.

  Next, an embodiment in which the time setting command TC is issued when the communication data D1 and D2 are to be transmitted from the inter-node connection device 1 shown in FIG. 6 to the processor node 51 will be described with reference to FIGS. This will be described with reference to FIG.

  The communication control unit 2 includes an output register 91 that transmits communication data to the communication data transmission unit 201. The reception register 211, the transmission buffer 212, the write pointer 213, the read pointer 214, and the communication data analysis control unit 512 constitute the transmission buffer unit 21 of FIG. 6, and the selector 221, the register 222, the NOR circuit 223, and the decoder 224 are 6, the register 242, the register 243, the adder 246, the decoder 244, the register 245, the register 247, the time setting instruction data 24a, the selector 241, the register 248, and the AND circuit 249 are configured as shown in FIG. 6, the register 251, the register 252, the addition counter 253, the addition counter 255, the arithmetic unit 254, the register 256, and the decoder 257 constitute the busy control unit 25 in FIG. 6.

  The processor node 51 includes a communication data analysis control unit 512, a copy clock 531, and a reception register 5101, a reception buffer 5102, and a register 5103 that constitute the reception buffer unit 510 of FIG.

  The communication data transmission unit 201 receives the communication data transmitted from the output register 91 of the communication control unit 2 by the reception register 211 (clocks 2 to 7 in FIG. 14). The communication data entered in the reception register 211 is sent to the transmission buffer 212 and the communication data analysis control unit 512. The communication data analysis control unit 512 performs error analysis and communication data type analysis on the transmitted communication data, and controls the write pointer 213 and the read pointer 214 of the transmission buffer 212. The transmission buffer 212 is a FIFO buffer that performs reading in the order of writing.

  After confirming that the communication data is normal, the communication data analysis control unit 512 sends a strobe signal as many times as necessary to the read pointer 213 if the communication data can be transmitted to the processor node 51, and transmits the transmission buffer 212. (Clocks 9 to 14 in FIG. 14).

  The register 242 receives time data from the master clock 3 and transmits the time data to the adder 246 and the decoder 244. The register 243 stores in advance a delay adjustment value for the processor node 51 for aligning the delay from the inter-node connection device 1 to the processor node 51 and the delay between the inter-node connection device 1 and another processor node. The value is sent to adder 246.

  The adder 246 adds the time data from the register 242 and the delay adjustment value from the register 243 and transmits the result to the selector 241. The decoder 244 decodes a part of the time data from the register 242 and transmits “1” to the register 245 in the case of a specific value. As a result, the register 245 is set to “1” at regular intervals. The register 245 is reset when “1” is set from the decoder 244 and “1” is transmitted from the AND circuit 249. In the case of simultaneous transmission, the set of “1” from the decoder 144 has priority.

  The register 247 stores the output of the NOR circuit 223 and transmits it to the register 248, the AND circuit 249, and the selector 241. The AND circuit 249 calculates the logical product of the output of the register 245, the output of the register 248, and the output of the register 247, transmits the result to the register 245, and resets the register 245. This determines whether or not the selector 221 has continuously selected the output of the selector 241 for two cycles and the two-word time setting instruction TC has been sent.

  In the time setting instruction data 24a, the command field time setting instruction TC of word 0 in FIG. 9 is set, and the value of the register 245 is inserted into the bit 0 portion of the position field. The selector 241 switches the output of the time setting command data 24 a and the adder 146. When the selection signal from the register 247 is “0”, the time setting command data 24a is selected, and when it is “1”, the adder 246 is selected. When the time setting command data 24a is selected, “01” is inserted into the position field of word 1 in FIG.

  The decoder 224 decodes the output of the register 222 and sends “1” to the register 256 when the end of the communication data is received. When “1” is transmitted from the decoder 224, the register 256 stores the output of the addition counter 255, and the output is sent to the addition counter 255 and the arithmetic unit 254. The addition counter 255 adds 1 to the output of the register 256 and transmits it to the register 256. Thus, each time one piece of communication data is sent from the internode connection apparatus 1 to the processor node 51, the value of the register 256 is counted up.

  The decoder 257 sends “1” to the register 251 when receiving communication is transmitted from the processor node 51, and sends “1” to the register 252 when receiving “1”. When “1” is input from the register 251, the register 252 stores the output of the counter 253, and the output is sent to the counter 253 and the arithmetic unit 254. The counter 253 adds 1 to the output of the register 252 and transmits it to the register 152. As a result, each time a received communication is returned from the processor node 51, the value of the register 252 is counted up. The arithmetic unit 254 subtracts the value of the register 252 from the output value of the register 256, and when the result becomes the number of communication data that can be received by the processor node 51 at a time, “1” is analyzed with the NOR circuit 223. It transmits to the control part 512.

  The reception register 5101 stores the communication data transmitted from the register 222 of the communication data transmission unit 201. The communication data is sent to the reception buffer 5102, the communication data analysis control unit 512, and the copy clock 531. The communication data analysis control unit 512 analyzes the communication data, and if it is word 0 of the time setting command TC, when word 1 is subsequently transmitted, it notifies the copy clock 531 and instructs to receive word 1. Then, the received communication is returned to the communication data transmitting unit 201. If the communication data transmitted following the word 0 of the time setting command TC is another communication, the word 0 of the time setting command TC is regarded as invalid. If the analysis result of the communication data is other communication data, a control signal is sent to the reception buffer 5102 to be stored in the reception buffer 5102, and the received communication is returned to the communication data transmission unit 201.

  The reception buffer 5102 stores communication data excluding the time setting command TC under the control of the communication data analysis control unit 512, and outputs the communication data to the register 5103 under the control of the analysis control unit 512. The copy clock 531 has a clock function, and sets the value of the time data portion of the time setting command TC in the clock under the control of the communication data analysis control unit 512.

  FIG. 14 shows a case where D1 is 6 words and D2 is 8 words, and a time setting instruction TC can be inserted between D1 and D2 by clocks 15 and 16. FIG. 15 shows a case where both D1 and D2 are 6 words. The time setting instruction TC is inserted between D1 and D2 at clock 15, but D2 is input at the next clock 16. The second half of TC cannot be inserted, and the time setting instruction TC is inserted at clocks 22 and 23 after D2. The first half of the TC between D1 and D2 is considered invalid by the communication data analysis control unit 512 of the processor node 51 and discarded.

It is a block diagram which shows the basic composition of 1st Embodiment of the time synchronization system concerning this invention. 3 is a timing chart for explaining the operation of the internode connection apparatus shown in FIG. 1. It is a command format for demonstrating operation | movement of the internode connection apparatus shown in FIG. It is the schematic which shows the connection state of the internode connection apparatus of the time synchronization system of FIG. 1, and a processor node. 3 is a timing chart for explaining the operation of the internode connection apparatus shown in FIG. 1. It is a block diagram which shows the basic composition of 2nd Embodiment of the time synchronization system concerning this invention. It is a timing chart for demonstrating operation | movement of the internode connection apparatus shown in FIG. It is a timing chart for demonstrating operation | movement of the internode connection apparatus shown in FIG. 7 is an instruction format for explaining the operation of the internode connection apparatus shown in FIG. 6. It is a block diagram which shows the detailed structure of the time synchronization system shown in FIG. It is a timing chart for demonstrating operation | movement of the internode connection apparatus shown in FIG. It is a timing chart for demonstrating operation | movement of the internode connection apparatus shown in FIG. It is a block diagram which shows the detailed structure of the time synchronization system shown in FIG. It is a timing chart for demonstrating operation | movement of the internode connection apparatus shown in FIG. It is a timing chart for demonstrating operation | movement of the internode connection apparatus shown in FIG. It is a block diagram which shows an example of the conventional time synchronization system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Internode connection apparatus 2 Communication control part 3 Master clock 101,102,103 Communication data transmission part 11 Transmission buffer part 12 Time setting command insertion part 13 Communication data interval calculation part 14 Time setting command creation part 15 Busy control part 1a, 1b 1c Signal line 41, 42, 43 Processor node 410, 420, 430 Reception buffer unit 411, 421, 431 Copy clock 201, 202, 203 Communication data transmission unit 21 Transmission buffer unit 22 Time setting command insertion unit 24 Time setting command creation Unit 25 busy control unit 2a, 2b, 2c, 2d signal line 51, 52, 53 processor node 510, 520, 530 reception buffer unit 511, 521, 531 copy clock 512, 522, 532 communication data analysis control unit 91 output register 111 Reception register 112 Transmission buffer 113 Read pointer 114 Read pointer 115 Communication data analysis control unit 132, 135, 122, 145, 147, 151, 152, 156 Register 121, 134, 141 Selector 133 Fixed value input signal line 138 Pointer calculation unit 123 NOR circuit 124, 144 157 Decoder 146 Adder 148 Time setting command data 153, 155 Add counter 154 Calculator 412 Communication data analysis control unit 4101 Reception register 4102 Reception buffer 4103 Register 211 Reception register 212 Transmission buffer 213 Write pointer 214 Read pointers 222, 243, 245 247, 248, 251, 252, 256 Register 221, 241 Selector 223 NOR circuit 224, 244, 257 Decoder 246 Adder 24a Time setting Constant command data 249 AND circuit 253, 255 addition counter 254 arithmetic unit 5101 reception register 5102 reception buffer 5103 register

Claims (4)

An inter-node connection device that operates as a master connected in a network; and a plurality of processor nodes that operate as slaves connected to the inter-node connection device, and each of the processor nodes includes a copy clock included in the node In the time synchronization system that synchronizes with the master clock built in the inter-connection device,
The inter-node connection device calculates a time setting command generating means for generating a time setting command based on the master clock, a communication data storing means for storing communication data to the processor node, and an interval of the communication data A communication data interval calculating means; a time setting instruction inserting means for inserting the output of the time setting instruction creating means into an output of the communication data storing means; and a transmission capability determining means for judging a communication data receivable state of the processor node. A time synchronization system comprising: An inter-node connection device that operates as a master connected in a network; and a plurality of processor nodes that operate as slaves connected to the inter-node connection device, and each of the processor nodes includes a copy clock included in the node In the time synchronization system that synchronizes with the master clock built in the inter-connection device,
The inter-node connection device includes a time setting command generating unit that generates a time setting command based on the master clock, a communication data storing unit that stores communication data to the processor node, and an output of the communication data storing unit. A time setting command insertion unit that inserts an output of the time setting command generation unit; and a transmission capability determination unit that determines a communication data receivable state of the processor node,
Each of the processor nodes comprises time setting command discarding means for invalidating an incomplete time setting command received from the inter-node connection device. An inter-node connection device that is connected to a plurality of processor nodes and synchronizes a copy clock built in each of the plurality of processor nodes with a built-in master clock,
Time setting command creating means for generating a time setting command based on the master clock;
Communication data storage means for storing communication data to the processor node;
Communication data interval calculation means for calculating the communication data interval;
Time setting instruction insertion means for inserting the output of the time setting instruction creation means into the output of the communication data storage means;
An inter-node connection device comprising: a transmission capability determination unit that determines a communication data reception enabled state of the processor node. A processor node which is connected to an inter-node connection device incorporating a master clock and incorporates a copy clock synchronized with the master clock;
A processor node comprising time setting command discarding means for invalidating an incomplete time setting command received from the inter-node connection device.

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