JP2006210824A - Nitride semiconductor light emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a large chip type GaN based light emitting element having a light emitting pattern unlike before, for which etching workability is improved. <P>SOLUTION: A laminated body S is formed on a substrate 1, a plurality of recessed parts h are formed on the laminated body S from an upper surface, and an n-type layer is exposed inside each recess. A p electrode P2 is provided in the remaining region of the upper surface of the laminated body S, and the p electrode is covered with an insulator layer m. The n-type layer exposed inside each recess is provided with an n electrode P1, and n electrodes are connected with each other by a conductor layer P3 connecting the recesses with each other over the insulator layer m, and the large chip type nitride semiconductor light emitting element is attained for which a light emitter is spread in a mesh shape. The laminated body S is composed of a nitride semiconductor and is provided with a laminated structure for which the n-type layer 2 and a p-type layer 4 hold a light emitting layer 3 therebetween for instance, and the n-type layer is positioned on a substrate side. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nitride semiconductor light emitting device formed as a so-called large chip having an outer peripheral shape per device and a light emitting area larger than the original one chip, and in particular, a flip having a back surface of a substrate as a light extraction surface. The present invention relates to a nitride semiconductor light emitting device useful as a chip type.

A nitride semiconductor light-emitting device (hereinafter also referred to as “GaN-based light-emitting device” or simply “light-emitting device”) is a light-emitting device using a nitride semiconductor as a main part of the device structure (such as a light-emitting layer).
FIG. 9 is a diagram schematically showing a typical element structure of a conventional GaN-based light emitting element. On a sapphire substrate 100 which is an insulator, an n-type layer 101 made of a nitride semiconductor and a light emitting layer 102 are formed. The p-type layer 103 is stacked and grown in this order, and the n-type layer and the p-type layer are provided with the n-electrode P10 and the p-electrode P20, respectively.
The surface of the sapphire substrate is provided with a buffer layer and a concavo-convex structure for the purpose of improving the crystal quality and improving the light extraction efficiency, and the nitride semiconductor layer further includes a dedicated contact layer, cladding layer, quantum Although it is subdivided into multiple layers such as a well structure, the details are not shown.

A general formation process of the n-electrode P10 is to partially remove the p-type layer and the light-emitting layer by etching the stacked body (n-type layer 101 / light-emitting layer 102 / p-type layer 103) from the upper surface into a concave shape, In this procedure, the n-type layer is exposed to form an n-electrode forming surface, and an n-electrode P10 is formed on the n-electrode forming surface. The n electrode P10 is in ohmic contact with the n-type layer. In the example of FIG. 9, the light L <b> 10 emitted from the light emitting layer is emitted from the back surface of the substrate 100 to the outside.
The p-electrode P20 is formed by forming a p-electrode in ohmic contact with the p-type layer on almost the entire surface of the remaining p-type layer after forming the n-electrode formation surface.

Today, in order to cover the light emission area or light emission amount of a plurality of elements with one element, the outer shape of one element is increased and the area of the light emitting layer is increased (that is, in the lateral direction perpendicular to the layer thickness direction). Attempts have been made to make large chips.
However, since the GaN-based light emitting device has the above-described device structure, for example, even if the chip of FIG. 9 is simply expanded in the horizontal direction to form a large chip, the current diffusion in the horizontal direction in the n-type layer As a result, light emission in the light-emitting layer becomes non-uniform, and a light emission amount corresponding to the size cannot be obtained.

  Therefore, the p / n structure portion related to light emission (a portion where an n-type layer, a light-emitting layer, and a p-type layer are stacked so as to cause a light-emitting phenomenon; hereinafter referred to as a light-emitting structure portion) is divided, and each divided light-emitting structure is divided. A structure for supplying power to a part has been proposed (for example, Patent Document 1 and Patent Document 2).

Schematically explaining the structure of the light-emitting element disclosed in Patent Document 1, as shown in FIGS. 1 and 2 of the document, a large area substrate that can be a large chip is used as a base, and on this base, A plurality (specifically, four) of convex light emitting structures are provided, and these share one n-electrode. It can be said that such an element structure is a structure in which a plurality of chips shown in FIG.
In such an element structure of a large chip, since a plurality of light emitting structure portions protrude on the base, the layer end face of the light emitting layer is exposed over the entire side surface of each light emitting structure portion. Therefore, a considerable amount of light generated in the light emitting layer leaks out of the element from the layer end face.
Therefore, when such a light emitting device is flip-chip mounted and light is extracted from the back surface of the substrate, there is a problem that the amount of available light extracted from the back surface of the substrate is reduced by the amount of leakage from the side surface of the light emitting structure. is there.

Patent Document 2 discloses a large-chip light-emitting element that solves the problem of Patent Document 1 described above.
The element structure of the large chip disclosed in Patent Document 2 will be schematically described. As shown in FIG. 10A, a large-area substrate 200 is used as a common base, and a convex shape (shown in the figure) is formed on this base. In the example, a large number of hexagonal pyramid-shaped light emitting structure portions 210 are formed, and light L10 (indicated by thick solid line arrows and hidden line arrows) L10 emitted from each light emitting structure portion is below the figure. It faces and is emitted from the back surface of the substrate 200 to the outside.
The aspect of Patent Document 2 is the same as that of Patent Document 1 in that the single light emitting structure portions are gathered together. However, in Patent Document 2, not only the upper surface of each light emitting structure portion but also the side surfaces are covered by the p-electrode. Yes. Although detailed illustration is omitted in FIG. 10A of the present application, in FIG. 13 of Patent Document 2, an insulating film is provided so that the p electrode and the n electrode are not short-circuited, and the p electrode is a large chip. The layered structure covering the entire top surface of the device is shown in detail. By covering the entire surface with the p-electrode, the light leaking from the end face of the light emitting layer is reflected inside the device, the loss of light leakage is improved, and the amount of light when extracting light from the back surface of the substrate is reduced. Will be improved.

  Contrary to the example of Patent Document 2, an aspect in which the n electrode is used as a reflective layer is described in Patent Document 3. In Patent Document 3, the side surface of the light emitting structure of one chip is covered with an n electrode. However, the invention of Patent Document 3 relates to an original small single chip and does not assume a large chip at all.

According to the study by the present inventors, the conventional large chip element structure as disclosed in Patent Documents 1 and 2 is a collection of a plurality of independent small protrusion-like light emitting structure portions. It is like collecting many small chips as described in Reference 3.
In patent document 2, as shown to Fig.10 (a) of this application, the convex light emission structure part is arrange | positioned at the vertex of an equilateral triangle, and is gathered up as a precise | minute arrangement pattern. When the light emitting surface of such a large chip is viewed, the light emission pattern is a pattern in which dotted light sources are dispersed as schematically shown in FIG. In FIG. 10 (b), a white portion without hatching is a portion that emits light (portion where the light emitting structure portion exists), and a dark portion that does not emit light (the light emitting structure portion is deleted), a portion where an n-electrode is provided).

In the structure that emits light as a light emission pattern in which point light sources are dispersed as shown in FIG. 10B, the light emission state becomes unstable for the following reason, and there is a possibility that the light emission may not be performed.
That is, in the element having the structure as shown in FIG. 10, in order to increase the amount of light emission, it is necessary to secure a larger convex light emitting structure, and for this purpose, n electrodes provided between the light emitting structures are provided. It must be thin. As a result, conduction becomes unstable and sufficient current diffusion is hindered, so that the light emission state may become unstable. Also in the manufacturing process, if the n-electrode becomes thin, there is a high possibility of disconnection and the yield is deteriorated, and there is a possibility that the product is disconnected after being manufactured. However, if a sufficiently wide area is ensured for the n-electrode, the convex light emitting structure cannot be increased in size and a large amount of light emission cannot be obtained.
In addition, when wire bonding mounting (mounting in a normal posture) with the light emitting portion on the upper side and the substrate on the lower side using the element having the structure shown in FIG. 10, the heat generated in the light emitting portion is performed on the substrate. The heat dissipation when escaping to the side depends on the thermal conductivity of the substrate. Therefore, when a material having insufficient thermal conductivity such as sapphire is used as the material of the substrate, the entire element is heated by the heat generated in the light emitting section, which may cause a situation in which the light output is reduced. .
Furthermore, since the element having the structure shown in FIG. 10 has discrete light-emitting portions with the p layer on the top surface, flip-chip mounting with the light-emitting portion on the bottom and the back side of the substrate as the take-out surface (inverted upside down) The following problems arise when performing the implementation. The problem is that when bumps are used for bonding, as many bumps as the number of light emitting portions are required, so it takes time to form a large number of bumps. Furthermore, when using an expensive bump material such as Au. The cost is increased due to the formation of a large number, and in the case of using AuSn eutectic solder, there is a possibility of contact with adjacent n electrodes, which makes mounting very difficult.

Further, in the element structure of the conventional large chip as described above, a small protrusion as shown in FIG. 10A is formed from the (n-type layer / light-emitting layer / p-type layer) laminate formed on the entire surface of the substrate. It must be etched in a mesh until a large number of light emitting structures are formed. In such a processing mode, the entire circumference of the side surface of each light emitting structure must be exposed. In particular, in the mode of Patent Document 2, a mesh-like groove must be formed to a depth at which the substrate is exposed. There is a problem that a large amount of energy is required, the etching time is long, and manufacturing efficiency and yield are poor.
In addition, the processing for forming the n-electrode on the exposed end face of the n-type layer needs to be careful not to cause a short circuit with the light emitting layer or the p-type layer, and is difficult to process.
Japanese Patent Laid-Open No. 10-275935 “Semiconductor Light Emitting Element” JP 2004-71644 “Nitride Semiconductor Light Emitting Element” Japanese Patent Application Laid-Open No. 11-340514 “Flip-Chip Optical Semiconductor Device” JP 2002-280611 “Semiconductor Light Emitting Element”

  An object of the present invention is to provide a large chip type GaN-based light emitting device that solves the above problems, has an unprecedented light emitting pattern, has improved etching processability, and has a particularly preferable structure as a flip mounting type device. There is in point to do.

The present invention has the following features.
(1) A laminated body made of a nitride semiconductor is formed on a substrate, and the laminated body includes a first conduction type layer, a light emitting layer, and a second conduction type layer in order from the lower side. A semiconductor light emitting device,
A plurality of recesses are formed on the upper surface of the laminate, the first conductivity type layer is exposed in each recess, the first electrode is connected to the exposed surface of the first conductivity type layer in each recess,
A second electrode is provided in the remaining region of the upper surface of the laminate, and the second electrode is covered with an insulator layer,
A nitride semiconductor light-emitting element in which first electrodes are connected to each other by a conductor layer that communicates with each other in the recesses over the insulator layer.
(2) The nitride semiconductor light-emitting element according to (1), wherein the nitride semiconductor light-emitting element is a flip-chip type element that is mounted with its posture turned upside down so that the stacked body faces the mounting substrate.
(3) The conductor layer connecting the recesses beyond the insulator layer is a first electrode layer in which the first electrode itself extends and extends beyond the insulator layer,
Except for the terminal portion used for connection between the second electrode and the outside, the entire top surface of the laminate including the inner surface of the recess is covered with the first electrode layer, and the portion that should not be in contact with the first electrode layer is The nitride semiconductor light-emitting device according to (1) or (2), which is protected by an insulator layer.
(4) The above-mentioned (1) to (3), wherein the first conductivity type layer is an n-type layer, the first electrode is an n-electrode, the second conductivity-type layer is a p-type layer, and the second electrode is a p-electrode. The nitride semiconductor light emitting device according to any one of the above.
(5) The nitride semiconductor light-emitting element according to (1), wherein the upper surface of the substrate is processed as an uneven surface, and the nitride semiconductor grows as a layer covering the uneven surface to form the bottom layer of the laminate.
(6) The arrangement pattern of the recesses on the top surface of the laminate is an arrangement pattern in which a recess is formed at the apex of each equilateral triangle of a fine mesh pattern having an equilateral triangle as a minimum structural unit. The nitride semiconductor light emitting device described.
(7) The opening shape of the concave portion is a regular hexagon, and the sides that form the regular hexagon and the sides of the regular triangle that is the minimum constituent unit of the fine mesh pattern as the arrangement pattern are orthogonal to each other, The nitride semiconductor light emitting device according to (6), wherein the direction of the regular hexagon of the opening shape of the recess is determined.

The light emitting device of the present invention is formed by disperse discrete recesses in a laminate having a light emitting structure composed of a first conductive type layer, a light emitting layer, and a second conductive type layer. A first electrode formation surface (typically an n electrode formation surface) is formed. Furthermore, the conductor layer which covers the top of a laminated body is provided so that the 1st electrode in each recessed part may mutually communicate. An insulator layer is interposed between the conductor layer and the second conductivity type layer so that there is no short circuit between the conductor layer and the second conductivity type layer or between the conductor layer and the second electrode.
With such a structure provided with a sufficiently wide conductor layer, stable conduction can be obtained. Therefore, since the n electrode can be arranged as the conductor layer over the entire light emitting element, the problem of disconnection caused by the thinning of the n electrode, which has been a problem in the past, can be solved, and current diffusion in the n-type layer is good. Become.

  The light emission pattern of the conventional large chip is a light emission pattern in which dot-like light sources are dispersed as shown in FIG. 10B, whereas in the present invention, as shown in FIG. Since the hatched dark part (first electrode formation surface) is dispersed in the form of dots and the white light emitting part spreads in a mesh pattern, the light emitting structure is larger than the conventional one (that is, the light emitting area is smaller). Increased). In addition, in the element structure of the present invention, the light emitting structure and the conduction path of the n electrode can both be sufficiently large in the element structure without interfering with each other. As a result, a sufficiently large current is supplied to the enlarged light emitting structure, and a high light emission efficiency and a high light emission output that could not be achieved in the past are achieved.

In the present invention, the first electrode forming surfaces are dispersed, whereas the first electrodes are electrically connected to each other, so that the structure is suitable for flip chip mounting. Accordingly, power can be supplied to all the first electrodes with a small amount of bonding, so that the structure can be simplified and the efficiency of the bonding process using Au bumps or the like is improved.
In addition, according to the element of the present invention, since it is possible to mount the light emitting portion almost entirely in contact with the flip chip mounting substrate, it is possible to suppress heat generation during large current injection, which is a problem with large chips. I can do it. By suppressing this heat generation, it is possible to solve the problem that the output is saturated by heat when a large current is input.

In the present invention, the end face of the light emitting layer exposed on the side surface of the light emitting structure in the recess is covered with the conductor layer (especially the n-electrode material itself) via the insulating film, so that light leakage generated in the light emitting layer is prevented. It is suppressed, and the amount of light extracted from the back surface of the substrate located on the upper side during flip chip mounting increases. In particular, when the conductor layer is an n-electrode, Al having a high light reflectance can be used as a material, so that the light extraction efficiency is further improved.
In addition, compared with the conventional large chip type element, particularly the element of Patent Document 2, the element of the present invention can reduce the etching depth for forming the first electrode formation surface, and the shape to be etched. However, since it is not a continuous mesh but a single hole, energy and processing time required for etching can be reduced.

Further, in the conventionally known light emitting element, the light from the light emitting layer spreads in all directions, so that the light reaching the substrate surface is totally reflected due to the refractive index other than the light entering at a predetermined angle, and is opposite to the substrate Or is reflected multiple times by the first conductivity type layer and then attenuated.
On the other hand, by making the surface of the laminate side of the substrate uneven, the light from the light-emitting layer passes through the substrate without being reflected by the substrate surface, increasing the amount of light emitted from the substrate side and flip chip mounting. It becomes suitable for.

  One of the first conductivity type and the second conductivity type in the present invention may be n-type and the remaining other may be p-type. Hereinafter, the light-emitting element of the present invention will be described with the first conductivity type being n-type and the first electrode provided in the first conductivity-type layer being an n-electrode.

FIG. 1 is a cross-sectional view showing an example of the structure of a light emitting device according to the present invention, and only an end face is shown for explanation. As shown in the figure, a laminated body S made of a nitride semiconductor is formed on a substrate 1, and in the laminated body S, in order from the lower side, a first conductivity type layer, a light emitting layer, and a second layer. A conductive layer is included. A plurality of recesses h are formed in the laminate S from the upper surface, and the n-type layer 2 is exposed in each recess. The exposed portion of the n-type layer in the recess is an ohmic contact portion with the n-type electrode. An n-type electrode P1 is provided on each n-type layer exposed in each recess.
On the other hand, a p-type electrode P2 is provided in a region left on the upper surface of the stacked body S, and the p-type electrode forms a mesh shape and spreads on the upper surface of the stacked body as shown in FIG. ing. Further, the p-type electrode P2 is covered and protected by the insulator layer m so as not to short-circuit the following conductor layer provided thereon (the part necessary for bonding is exposed).
The n-type electrodes P1 in each recess are connected to each other by a conductor layer P3 that connects the recesses beyond the insulator layer m. That is, the conductor layer P3 is laminated on the insulator layer m covering the laminated body in FIG.
As shown in FIG. 2B, a large chip that emits light in a mesh shape is obtained by the element structure having the above configuration.

As shown in FIGS. 1 and 2, the light-emitting element includes a crystal substrate 1 and a stacked body S formed thereon, and an n-electrode and a p-electrode are provided on the stacked body, and a light-emitting diode ( Any device may be used as long as it is configured to function as an LED), and there is no limitation on the element structure of incidental details.
The stacked body is made of a nitride semiconductor crystal layer (may include a structure made of a material other than a nitride semiconductor, depending on the purpose), and an n-type layer and a p-type so that light can be generated by current injection. Any layer may be used as long as it has a laminated structure with a light emitting layer interposed therebetween. Examples of the stacked structure in which the n-type layer and the p-type layer sandwich the light emitting layer as described above include a single quantum well (SQW) structure, a multiple quantum well (MQW) structure, and a structure in which an SQW structure is further stacked. These include various quantum well structures and DH structures.

The nitride semiconductor referred to in the present invention is a group III nitride determined by the formula Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). It is a compound semiconductor.
By selecting the composition ratios a and b in the above formula, any binary to quaternary mixed crystal such as GaN, AlGaN, InGaN, and AlInGaN can be obtained.
Part of the Group 3 element can be replaced with boron (B), thallium (Tl), or the like, and part of N can be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth ( Bi) and the like can be substituted.
Examples of impurities for imparting n-type conductivity to the nitride semiconductor include silicon (Si), germanium (Ge), carbon (C), selenium (Se), and tellurium (Te).

The substrate may be any substrate on which a nitride semiconductor crystal layer can be grown. Examples of the material include sapphire (C plane, A plane, R plane), SiC (6H, 4H, 3C), GaN, AlN, Si, Examples include spinel, ZnO, GaAs, and NGO.
Among these substrates, the sapphire substrate is insulative, and both the n-type electrode and the p-type electrode must be provided in the laminate, so that the advantage of the present invention is most remarkable.

Examples of methods for growing a nitride semiconductor crystal layer (GaN-based crystal layer) on a wafer substrate include HVPE, MOVPE, and MBE.
Techniques, structures, techniques, and the like necessary for growing a high-quality GaN-based crystal layer on the wafer substrate may be used as appropriate. As such, for example, a technique of interposing a buffer layer (particularly, a GaN-based low-temperature growth buffer layer) between the crystal substrate and the GaN-based crystal layer, providing a SiO ₂ mask pattern on the substrate surface, or the substrate surface itself And a technique for forming a GaN-based crystal layer by lateral growth or facet growth, thereby reducing the dislocation density in the crystal.

A LEPS method (Lateral Epitaxy on a Patterned Substrate) is known as a technique for reducing dislocation density by performing uneven processing on a substrate surface itself and growing a GaN-based crystal layer so as to cover the unevenness.
The LEPS method is a method of growing a GaN-based crystal including substrate surface treatment (buffer layer formation, nitridation treatment, etc.) after completing uneven processing on the main surface of the substrate, and is made of SiO ₂ or the like. A selective growth mask is not used. From these points, the LEPS method can most simplify the manufacturing process and minimize contamination and alteration of the GaN-based crystal among the dislocation density reduction methods that intentionally generate the lateral growth of the crystal. Is the method.

Among the LEPS methods, a method (facet LEPS method) in which independent crystal units are generated on the concave bottom surface and the convex top surface of the concave / convex surface of the substrate, and the concave / convex surface is embedded by faceting them, This is an excellent crystal growth method in which the dislocation density (density of threading transition) on the surface of the crystal layer is uniformly reduced.
By applying a facet LEPS method to grow a high-quality crystal layer, the light emitting efficiency in the active layer is improved, the breakdown voltage characteristics of the pn junction is improved, and the conductivity of the contact layer is improved for reducing the operating voltage of the device. A favorable effect such as a reduction in contact resistance between the contact layer and the electrode can be expected.
The facet LEPS method is described in detail in Patent Document 4 described above. Further, the manner in which independent crystal units are generated on the uneven surface of the substrate and are combined with each other to form a layer is schematically shown in FIG.

In the facet LEPS method, a combination of unevenness specifications and growth conditions is important. The concavo-convex surface is a main surface on which the GaN-based crystal can be c-axis oriented (a plate surface whose c-axis is perpendicular to the main surface when the GaN-based crystal is grown on the main surface). It is formed by applying uneven processing.
On this main surface, using growth conditions (relatively low temperature, relatively high hydrogen gas concentration, relatively high pressure) in which the growth rate in the c-axis direction is high and the growth rate in the direction perpendicular to the c-axis is low. GaN-based crystals are grown. Accordingly, facets oriented obliquely with respect to the main surface, such as {1-101} facets and {11-22} facets, on the concave bottom surface and convex top surface of the substrate uneven surface in the course of crystal growth. Independent crystal units having side wall surfaces (hereinafter referred to as “oblique facets”) are generated. This is facet growth.

As described above, in facet growth, a large number of fine crystals having oblique facets as side wall surfaces are formed in the initial stage of the growth. In the process in which the small crystals are repeatedly united and become larger, the propagation direction of the dislocations is bent, and the dislocations in the opposite direction form loops and disappear, thereby reducing the dislocation density.
Also, when shifting from facet growth to flattening, lateral growth occurs from the side wall surface of the crystal generated on the bottom surface of the concave portion and the top surface of the convex portion, and the propagation direction of the dislocation is bent. Density is reduced.
In order to maximize the latter effect, it is preferable that the crystal generated in the facet growth process has a shape that maximizes the area of the oblique facet that becomes the side wall surface. In the case of a crystal growing from a polygonal concave or convex portion, the shape is a pyramid with the polygon as the bottom, and in the case of a crystal growing from a striped concave or convex portion, It is a roof shape with a triangular cross section extending in the longitudinal direction of the stripe.

When making the unevenness | corrugation of a board | substrate into a striped pattern, both the groove width and the convex ridge width are 1 micrometer-10 micrometers, Especially 2 micrometers-6 micrometers are preferable. When the band width is 1 μm or more, the resist mask can be exposed with an inexpensive contact exposure apparatus when patterning the etching mask. When using an exposure apparatus such as a stepper capable of higher-accuracy exposure, a narrower band width may be used.
As for the uneven step of the substrate, the uneven interface sufficiently exhibits the effect of light scattering so that the crystal unit can grow from the bottom surface of the concave portion and can merge with the crystal unit grown from the top surface of the convex portion. Thus, it is preferable to set it as 0.1 micrometer-5 micrometers, especially 0.5 micrometer-2 micrometers. As a result, it becomes easy to grow the concavo-convex shape with high accuracy, and the light scattering effect can be obtained most efficiently.
These values may be applied as the height of the polygon and the interval between adjacent sides of the polygon when the unevenness of the substrate is a polygon.

  If the crystal growth is continued even after independent crystal units are generated on the concave bottom surface and the convex top surface of the concave-convex substrate by facet growth, each crystal unit gradually expands in the lateral direction. Eventually, when adjacent crystal units come into contact with each other, faster lateral growth occurs, and the space between the side wall surfaces (diagonal facets) of the adjacent crystal units gradually fills, flattening the surface.

  In order to start the flattening process early, the growth conditions are changed when the independent crystal units are formed on the concave bottom surface and the convex top surface of the concavo-convex substrate. , Lower atmospheric hydrogen gas concentration, lower pressure). When such growth conditions are switched, the substrate surface is completely covered with the GaN-based crystal in a short time, and the subsequent filling between the side wall surfaces of adjacent crystal units also proceeds in a short time, thereby flattening the surface. Is achieved faster.

The method for growing the GaN-based crystal on the concavo-convex substrate is not particularly limited. In addition to the MOVPE method, a conventionally known method such as a hydride vapor phase epitaxy (HVPE) method or a molecular beam deposition (MBE) method is appropriately used. can do.
From the viewpoint of manufacturing efficiency, it is preferable that the growth of the GaN-based semiconductor layer stacked on the base substrate is performed consistently in one growth furnace by the MOVPE method.

In the facet LEPS method, the uneven surface of the substrate formed to reduce the dislocation density and the uneven surface between the embedded GaN-based crystal layer scatters the light from the light emitting layer and extracts more light to the outside. (Improves light extraction efficiency). In particular, when the light-emitting element is a flip chip mounting type, more light can enter the substrate and be extracted from the back surface of the substrate to the outside due to light scattering at the uneven interface.
Accordingly, an aspect in which the facet LEPS method is applied by performing uneven processing on the substrate surface and the light emitting element is a flip chip mounting type is the most preferable aspect for increasing the light output of the light emitting element.

As an aspect of the n-type layer exposure, as shown in FIG. 3A, the n-type layer 2 is exposed on the bottom surface of the recess h formed on the top surface of the laminate, or as shown in FIG. The substrate 1 is exposed on the bottom surface of the recess, and the n-type layer 2 is exposed as the inner wall surface.
In the former mode, the contact area with the n electrode formed on the n-type layer can be widened, and the contact resistance between the n electrode and the n layer can be reduced. Moreover, since the time required for exposure can be shortened, it is a preferable mode of exposure.
In general, in order to form the recess h in the mode shown in FIG. 3B, the depth to the bottom surface of the recess h in the mode shown in FIG. It is necessary to dig deeper by etching or the like about 7D to 14D further from the bottom surface. Therefore, the structure shown in FIG. 3A has an advantage that the productivity is better.

The cross-sectional shape of the recess formed on the top surface of the laminate is not limited, but a rectangular wave shape in which the opening shape (shape on the top surface of the laminate) and the bottom surface shape are substantially equal, or an inverted trapezoidal shape in which the bottom surface shape is smaller than the opening shape, etc. Can be mentioned.
If the cross-sectional shape of the concave portion on the upper surface of the laminate is an inverted trapezoidal shape, as shown in FIG. 3A, the inner wall surface of the concave portion (= the side surface of the laminate) becomes a slope, and Is preferably reflected on the inclined surface and directed toward the back surface of the substrate. When the inner wall surface of the recess is a slope, the slope angle θ of the slope is preferably 15 degrees or more and less than 90 degrees, preferably 15 degrees or more and 60 degrees or less, and most preferably 45 degrees.
Providing such an inclination can be achieved by forming the cross-sectional shape of the etching mask used in the etching process for exposing the end face of the stacked body so that the mask thickness becomes thinner as it approaches the edge of the mask.

  Hereinafter, it is assumed that the n-type layer is exposed at the bottom surface of the concave portion on the top surface of the laminate, and the bottom surface is referred to as an “n-type electrode forming surface”. The configuration of the present invention will be described assuming that the shape and the bottom shape are equal.

It is sufficient if there are a plurality of recesses on the upper surface of the laminate, and the arrangement pattern on the laminate (arrangement pattern of the recess openings on the upper surface of the laminate) is not limited, but the light emitting area is increased as a large chip, and Examples of preferable arrangement patterns for obtaining stronger light emission include the following.
(A) A pattern in which a plurality of recess openings are all included in the upper surface region without being in contact with the outer peripheral line of the upper surface region of the laminate. For example, two rectangular recess openings are provided in FIG. 4 (a), four rectangular recess openings are provided in FIG. 4 (b), and U-shaped recess openings are engaged with each other in FIG. 4 (c). Yes.
(B) A pattern in which a plurality of recess openings are in contact with the original outer peripheral line (the outer peripheral line before forming the concave part) of the upper surface region of the laminate. In this pattern, recesses are also opened on the outer peripheral side surface of the laminate. For example, in FIG. 5A, two rectangular recess openings are provided, and the remaining upper surface region of the stacked body is drawn in an S shape. In FIG. 5B, the upper surface region of the stacked body is formed at four corners. A recessed opening is provided, and the remaining upper surface area of the stacked body draws a cross, and in FIGS. 5C and 5D, a part of the outer periphery of the upper surface area of the stacked body is in contact with most of the remaining area. In FIG. 5E, the recess openings are provided so as to form a stripe shape.
(C) A pattern combining the above (a) and (b). That is, a pattern formed by a recess opening that is included in the upper surface region of the laminate and does not contact the outer periphery, and a recess opening that contacts the outer periphery. For example, in FIG. 6 (a), recess openings are formed in the entire periphery and center of the outer peripheral edge of the upper surface region of the laminate, and in FIG. 6 (b), on the three sides of the outer peripheral edge of the upper surface region of the laminate. A recess is formed, and a recess opening is formed in the upper surface region so as to be biased toward the remaining one side. Moreover, in FIG.6 (c), the recessed part opening is formed in the four corners and center of the upper surface area | region of a laminated body.
(D) A pattern in which concave portions are formed concentrically. For example, in FIG. 6D, an annular recess opening is formed in the entire periphery and center of the outer peripheral edge of the upper surface region of the laminate, and in FIG. 6E, an annular recess opening is formed in the upper surface region of the laminate. In addition, a single recess is formed at the center.
(E) A pattern obtained by arbitrarily combining the patterns (a) to (d) above.

In FIGS. 4 to 5, the opening shape of the concave portion on the top surface of the laminate is illustrated as a rectangle, but instead, a circle, an ellipse, a triangle, a quadrangle, a pentagon, a hexagon, other polygons, an indeterminate shape, etc. It is good also as various dot-like shape (shape whose vertical-horizontal dimension ratio is about 0.5-2).
Further, the pattern drawn by the concave portions is a stripe shape, a bent line shape such as an L-shape or a U-shape, an annular shape, a shape branched into one or more (including a comb shape), a radial shape (T-shape, Y-shape, (Including a cross shape), a net shape (lattice shape), an amid shape, and other arbitrary patterns.
Each of the patterns such as the stripe shape and the bent line shape may be constituted by a straight line and / or a curved line.

Among the arrangement pattern of the recesses on the top surface of the laminate, as shown in Fig. 2 (a), draw a fine mesh pattern with a regular triangle (one-dot chain line) as the minimum structural unit, and form a recess at the apex of each regular triangle. The arrangement pattern is preferable in that the n-type electrode forming surface can be efficiently arranged on the entire top surface of the laminate.
Among these arrangement patterns, as shown in FIG. 7A, the opening shape of the recess is a regular hexagon, and the side W1 of the regular hexagon and the equilateral triangle (one-dot chain line) which is the minimum constitutional unit as the arrangement pattern. In the arrangement mode in which the directions of the regular hexagons are determined so that the sides W2 are orthogonal to each other, the adjacent regular hexagons have the same distance between the vertices and between the sides, so that the current diffusion is This is a preferred embodiment in that it is uniformly stabilized as a whole. On the other hand, as shown in FIG. 7B, an arrangement mode in which the orientation of the regular hexagon is determined so that the vertex W3 of the regular hexagon is on the side W2 of the regular triangle (dashed line) is the present invention. In this aspect, adjacent regular hexagonal vertices are close to each other, but the sides are separated from each other by the distance between the vertices, which may cause local current diffusion.

  When the n-type layer is exposed at the bottom surface in the concave portion on the top surface of the stacked body, the n electrode provided on the bottom surface preferably extends as large as possible in the bottom surface. The distance from the outer peripheral line is preferably 15 μm or less, more preferably 10 μm or less, and particularly preferably 5 μm or less.

The element is characterized in that n electrodes are connected to each other by a conductor layer that connects the insides of the recesses, and at least two n electrodes need only be connected to each other. The more connected, the better because the number of bonding points can be reduced. Most preferred is an embodiment in which the n electrodes in all the recesses are connected to each other.
When there are a large number of independent n electrodes, for example, in the case of wire bonding, since it is necessary to connect a wire to each n electrode, the structure becomes complicated, resulting in disadvantages in terms of manufacturing cost and yield. Become. In addition, when the electrode on the chip side and the electrode on the side of the mounting substrate such as a lead frame or submount are bonded with a conductive bonding material (solder, silver paste, etc.), alignment with each n electrode is also possible. The accuracy required for this is increased, and there are similar problems.

  The thickness of the n-electrode may be a thickness that provides a metallic luster and has sufficient reflectivity for light going out of the layer, and for that purpose it is preferably 30 nm or more. Increasing the thickness of the n electrode to 500 nm or more is preferable because the heat dissipation effect is increased.

The shape of the laminate left after the recess on the top surface of the laminate is formed differs depending on the shape and arrangement pattern of the recess, but when the laminate is divided by the recess, it is divided in the case of wire bonding. A wire must be connected to the p-electrode for each stacked body, resulting in a disadvantage in terms of manufacturing cost and yield.
In addition, each p-electrode (or p-bonding) is also used when the chip-side electrode and the electrode on the mount base such as a lead frame or submount are joined with a conductive bonding material (solder, silver paste, etc.). Electrode) and the lead electrode on the side of the mounting base material are required to be highly accurate, which is disadvantageous in terms of manufacturing cost and yield.
Accordingly, the number of independent laminates is preferably limited to 4 or less, more preferably 3 or less, and even more preferably 2 or less, and most preferably, as shown in FIG. This is an aspect in which the electrodes are connected to one with a mesh shape without being divided.

When element separation is performed by dicing, scribing, laser scribing, laser fusing, or the like, if the laminate is broken, the light emitting region tends to be damaged and the light emission characteristics tend to deteriorate.
Therefore, it is preferable to remove at least the depth that reaches the light emitting layer by etching before element isolation before element separation, and this etching process is efficient if it is also used as a recess formation process.
When the strip-like region including the dividing line is removed, the end face of the laminate (including the end face of the light emitting layer) is exposed, but this is covered with a transparent insulating film, and the n electrode is further covered by the n electrode. Is preferably extended.

When n electrodes are connected to each other by a conductor layer that connects the concave portions on the upper surface of the multilayer body, as shown in FIG. 8, insulation is provided between the p electrode P2 and the conductor layer P3 (= n electrode P1). What is necessary is just to prevent both short circuit by interposing the body layer m.
Further, a portion that should not be in contact with the conductor layer P3 (for example, a light emitting layer exposed on the inner wall surface of the recess, a p-type layer, etc.) may be protected by the insulator layer m as shown in FIG.
Thus, in order to protect only the intended portion with the insulator layer m, the entire upper surface of the laminate S is covered with the insulator layer (transparent insulating film) m, leaving only the intended portion, and the other portions. May be removed by etching or the like.
As shown in FIG. 8, a terminal portion (a bump-like conductor portion for bonding) P21 used for connecting the p-electrode to the outside is formed by an insulator layer m so that it can be connected to the outside. It is not covered and exposed in a state of being insulated from the conductor layer P3.
Thus, in order to locally expose only the terminal portion P21 and its periphery, for example, a photoresist is formed only in a region that should not be covered by the conductor layer P3, and a conductor layer P3 is deposited over the entire other region. And the like, and then the photoresist is lifted off.

Although there is no limitation to the material of the insulating layer, preferably, it is mentioned as a transparent insulating film such as a near-ultraviolet ~ SiO 2 having high light reflectivity in the visible short wavelength _region, SiN _x is preferable. The reason why transparency is preferable is that light generated in the light emitting layer can be extracted without absorbing it.
In the case where a transparent insulating film is formed immediately above the p-electrode and n-electrode, it is preferable to form a Ni thin film on the surface of the p-electrode and n-electrode, since the adhesion with the transparent insulating film is improved. .

The outer peripheral shape of the light-emitting element is not particularly limited, but a rectangular shape is preferable in consideration of the dividing step. The size of the light-emitting element is also not limited. For example, when the outer peripheral shape is a square, a preferable length of one side is 0.5 mm to 5 mm, more preferably 0.5 mm to 3 mm, and still more preferably 0.5 mm to 2 mm. It is. Increasing the size of the large chip increases the absolute light amount, and decreasing it increases the number of light emitting elements obtained from a single wafer. The dimensions of the large chip may be determined in consideration of such factors.
The above range is merely an example of the size of a large chip, and may be smaller than the above range due to the downsizing of individual elements, or a requirement for a surface emitting board having a large light emitting area. Depending on the size, it may be the same size as the wafer.

  For the n-electrode, a material capable of forming ohmic contact with the n-type nitride semiconductor is used at least in a region in contact with the n-type layer. From the viewpoint of light extraction efficiency from the substrate side, an embodiment in which the n electrode is formed on the entire semiconductor layer (excluding the p electrode bonding portion) is preferable. Further, the entire contact surface with the n-type layer may be made of the ohmic material, but may be partial. As an example of the latter, a layer made of an ohmic Ti-Al alloy is formed in a lattice shape having openings on the n-electrode forming surface, and a non-ohmic Ag layer having higher reflectivity is laminated thereon. Alternatively, ohmic Al is formed in a film thickness (10 nm or less) such that an area made of Al forms an island shape, and a high Ag layer is stacked thereon.

Al as the n-electrode material forms an ohmic contact with the n-type layer and has high light reflectivity in the near ultraviolet to visible short wavelength region. Therefore, the n electrode may be formed of an Al single layer.
As the n-electrode material, an Al alloy having high heat resistance while having high light reflectivity, such as an Al—Nd alloy, may be used instead of pure Al. Also in the case of Ag, an Ag—Cu alloy, an Ag—Bi alloy, or the like is preferably used.

An oxide film is easily formed on the surface of the n electrode made of Al or Al alloy. Therefore, although the chemical stability is high, on the other hand, the bonding property with the metal material is not so good at the time of wire bonding or when bonding to the electrode with a metal material such as solder.
Therefore, it is preferable to provide an Au layer as a surface layer at least in a portion to be bonded. In that case, between the layer made of Al or Al alloy and the Au layer, Al and Au are mutually diffused and alloyed by solder bonding and other processes exposed to high temperature (Al ohmic property and Au acid resistance). It is preferable to provide a barrier layer made of a metal having a melting point higher than that of Au.

When Al or an Al alloy is used as the material for the n-electrode, the luminous efficiency can be improved because it is more reflective than the ohmic p-electrode material such as Ni or Pd.
Therefore, rather than reflecting light emitted from the laminated body by the p electrode itself, the p electrode itself is a light-transmitting film, or an opening electrode having an opening (window) through which light can be transmitted. It may be preferable to cover the top with a highly reflective n-electrode and reflect it with the n-electrode.

  When wire bonding is performed, it is preferable to provide a bonding electrode (pad electrode) on the p electrode in order to reduce damage to the p electrode and the light emitting element structure below the p electrode when bonded to the wire. Alternatively, a bonding electrode electrically connected to the p electrode may be separately provided outside the light emitting region.

  The conductor layer that connects the insides of the recesses beyond the laminated body may be a good conductor dedicated for connection or a layer in which the n-electrode itself is extended. As described above, a preferable metal material (Al or the like) is selected for the n-electrode for making ohmic contact with the GaN-based crystal layer, and on the other hand, the conductor layer that connects the recesses beyond the laminate can be formed as much as possible. A good conductor is preferred. Moreover, it is preferable in terms of manufacturing efficiency if both are formed at the same time in one process using the same material. Considering these points, and further considering mounting with eutectic solder and Au bumps, [Al (lowermost layer) / Ti (middle layer) / Au (surface layer)], [Al (lowermost layer) / Pd (middle layer) ) / Au (surface layer)], [Al (lowermost layer) / TiW (middle layer) / Au (surface layer)] and the like.

Although the procedure for manufacturing the light emitting element is not limited, examples of preferable steps include the following.
(I) A laminate is formed on the substrate to form a recess (n-electrode forming surface). Next, a lower layer of the n-electrode is formed and ohmic contact is made with the n-type layer. Next, a predetermined portion is covered with an insulator layer, an upper layer of the n electrode is formed, and the n electrodes in each recess are connected to each other.
(Ii) A laminate is formed on the substrate to form a recess (n-electrode forming surface). Next, a predetermined part is covered with an insulator layer, and an n-electrode (single layer or multilayer) is formed.
In (i) and (ii) above, the stage at which the p-electrode is formed is arbitrary, but when the n-electrode extends over the p-electrode, the p-electrode is formed before forming the transparent insulating film. Then, it is efficient to form the transparent insulating film so as to cover the end face and the upper face of the p-electrode.

  As described above, the light-emitting element according to the present invention can be formed into a light-emitting pattern that spreads in a mesh shape that has not been heretofore, and the recesses in which the n-electrodes are to be formed are dispersed in a dot-like manner. Sex has been improved.

It is sectional drawing which shows typically the element structure of the light emitting element by this invention. 1 is a partial cross-sectional perspective view schematically showing an element structure and a light emission pattern of a light emitting element according to the present invention. For the sake of explanation, electrodes and insulator layers are omitted. It is a figure which illustrates roughly the aspect of exposure of the n-type layer in the recessed part of the light emitting element by this invention. It is a figure which illustrates schematically the desirable arrangement pattern of the crevice to the upper surface of a layered product in the present invention. It is a figure which illustrates schematically the desirable arrangement pattern of the crevice to the upper surface of a layered product in the present invention. It is a figure which illustrates schematically the desirable arrangement pattern of the crevice to the upper surface of a layered product in the present invention. It is a figure which illustrates schematically the desirable opening shape and arrangement pattern of the crevice to the layered product upper surface in the present invention. In this invention, it is sectional drawing explaining the local exposure of the p electrode at the time of covering the upper surface of a laminated body with an insulator layer and the conductor layer on it. It is the schematic diagram which showed the element structure of a conventionally well-known GaN-type light emitting element. It is a figure which shows roughly the element structure of the large chip | tip disclosed by patent document 2, and its light emission pattern.

Explanation of symbols

1 Substrate 2 First Conductive Layer 3 Light-Emitting Layer 4 Second Conductive Layer P1 First Electrode P2 Second Electrode m Insulator Layer h Recess

Claims (7)

A nitride semiconductor light emitting device in which a laminate made of a nitride semiconductor is formed on a substrate, and the laminate includes a first conduction type layer, a light emitting layer, and a second conduction type layer in that order from the bottom. Because
A plurality of recesses are formed on the upper surface of the laminate, the first conductivity type layer is exposed in each recess, the first electrode is connected to the exposed surface of the first conductivity type layer in each recess,
A second electrode is provided in the remaining region of the upper surface of the laminate, and the second electrode is covered with an insulator layer,
A nitride semiconductor light-emitting element in which first electrodes are connected to each other by a conductor layer that communicates with each other in the recesses over the insulator layer.   The nitride semiconductor light-emitting device according to claim 1, wherein the nitride semiconductor light-emitting device is a flip-chip device that is mounted upside down so that the stacked body faces the mounting substrate. The conductor layer that connects the insides of the recesses beyond the insulator layer is a first electrode layer in which the first electrode itself extends and extends beyond the insulator layer,
Except for the terminal portion used for connection between the second electrode and the outside, the entire top surface of the laminate including the inner surface of the recess is covered with the first electrode layer, and the portion that should not be in contact with the first electrode layer is The nitride semiconductor light emitting device according to claim 1, wherein the nitride semiconductor light emitting device is protected by an insulator layer.   The nitriding according to claim 1, wherein the first conductivity type layer is an n-type layer, the first electrode is an n-electrode, the second conductivity-type layer is a p-type layer, and the second electrode is a p-electrode. Semiconductor light emitting device.   The nitride semiconductor light-emitting element according to claim 1, wherein the upper surface of the substrate is processed as an uneven surface, and the nitride semiconductor grows as a layer covering the uneven surface to become the lowermost layer of the laminate.   2. The nitride according to claim 1, wherein the arrangement pattern of the recesses on the upper surface of the laminate is an arrangement pattern in which a recess is formed at the apex of each equilateral triangle of a fine mesh pattern having an equilateral triangle as a minimum structural unit. Semiconductor light emitting device.   The opening of the recess is such that the shape of the opening of the recess is a regular hexagon, and the sides that form the regular hexagon and the sides of the equilateral triangle that is the minimum constituent unit of the fine mesh pattern as the arrangement pattern are orthogonal to each other. The nitride semiconductor light emitting device according to claim 6, wherein the direction of the regular hexagonal shape is determined.

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