JP2006203736A - Image sensor and its image reading method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image sensor which secures the same reading time and achieves a perfect nondestructive read in spite of specific shape, direction or the like of an image area without depending on the reading direction of the specific image area. <P>SOLUTION: The image sensor in which a plurality of pixels having a light receiving element are arranged in a plain surface is provided with the same number of A/D converters as a plurality of pixels to A/D-convert a pixel signal output from the plural pixels in a pixel-by-pixel mode, and the same number of memories as the plural pixels to store the digital pixel signal converted by the A/D converter each pixel. The image sensor reads the digital pixel signal in a pixel-by-pixel mode, to designate a coordinate disposed in a plain surface voluntarily and to be stored in the memory. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image sensor and an image reading method thereof, and more particularly, to an image sensor capable of random access on a pixel basis and an image reading method thereof.

  2. Description of the Related Art Today, imaging devices and cameras using an image sensor are spreading their application fields in various forms regardless of consumer or industrial use.

  Solid-state image sensors include a CCD image sensor using a CCD as a solid-state image sensor used in the image sensor and a CMOS image sensor using a CMOS.

  CCD image sensors are configured to sequentially read out the charge stored in a light receiving element such as a photodiode like a bucket relay, and are widely used in digital cameras and the like today from the viewpoint of low noise and high image quality. It is used.

  On the other hand, the CMOS image sensor generates a lot of noise compared to the CCD image sensor at the beginning, and is considered to be slightly inferior to the CCD image sensor in terms of image quality. For this reason, in the general application field, the spread has been delayed as compared with the CCD image sensor.

  However, with the progress of noise reduction technology for CMOS image sensors, some of the image quality equivalent to or surpassing that of CCD image sensors has appeared. For this reason, various advantages other than the image quality of the CMOS image sensor have attracted attention.

  The first advantage is that the CMOS image sensor consumes less power than the CCD image sensor. This is advantageous when applied to a portable device using a battery.

  The second advantage is that the process technology related to the manufacture of the CMOS image sensor is common to the process technology of a device with a large demand such as a CMOS memory and is a highly versatile technology. For this reason, it is possible to share development and design and share manufacturing equipment, and cost reduction can be expected.

  A third advantage is that a specific partial pixel region or a specific single pixel can be randomly accessed in all pixel regions. In the case of a CCD image sensor, since the charge accumulated in the light receiving element is sequentially read out like a bucket relay, it is theoretically difficult to randomly access a specific partial pixel region or a specific pixel alone. On the other hand, the CMOS image sensor is a method in which the X coordinate and Y coordinate of the two-dimensional array are designated independently, and the received light amount of a single pixel corresponding to the designated coordinates is read. For this reason, it is possible in principle to read out a specific partial pixel region or a specific single pixel out of all the pixel regions.

  In application fields such as digital cameras for consumer use, the size of the display screen is standardized in advance, and this is a method of generating images by sequentially reading out the same pixel area, so that each pixel is randomly accessed. Is rarely needed.

  On the other hand, in an industrial imaging device or the like, a random access function for pixels is often required to achieve, for example, ultra-high speed and high resolution, or for special image processing.

  For example, Patent Document 1 discloses a technique for achieving both high spatial resolution and high-speed real-time characteristics in an imaging camera device that displays image feature amounts, and among these, a CMOS image that can be randomly accessed for each frame of an image. A sensor is used (see paragraph [0021] of Patent Document 1).

Japanese Patent Application Laid-Open No. 2004-228561 has a technology in which each pixel of an image sensor is provided with a memory circuit corresponding to one-to-one, and reading of pixel data of the image sensor is controlled based on binary data stored in the memory circuit. It is disclosed. For example, when the data in the memory circuit is “1”, the pixel data is read out. When the data is “0”, the pixel data is not read out so that the readout time can be shortened as a whole. In addition, binary data (“1” or “0”) stored in the memory circuit is written in advance on an arbitrary two-dimensional surface, whereby pixel data corresponding to “1” can be randomly accessed and read out. It is possible.
JP 2003-319262 A JP-A-11-275468

  By the way, as described above, the CMOS image sensor is a device capable of random access in principle, but the update time for updating the column in the X direction (horizontal direction) and the update for updating the row in the Y direction (vertical direction). It is generally known that it differs greatly from time.

  For this reason, a predetermined partial pixel area (for example, a rectangular partial pixel area having a total of 1024 elements) by a random access function from among all pixel areas (for example, a square area having about 1 million pixels of 1024 elements × 1024 elements). Image data of a horizontally long rectangular area (X direction: 64 elements, Y direction: 16 elements) and a vertically long rectangular area (X direction: 16 elements, Y direction: 64 elements). In the case of the image data of (), even if the number of pixels is the same, there is a large difference in readout time.

  The reason for this will be described with reference to FIG. FIG. 8 schematically shows the configuration of a conventional CMOS image sensor 4 (N rows and M columns).

  Each pixel of the CMOS image sensor 4 includes a light receiving element 41 that converts light into an electric charge (pixel signal), a switching transistor 42 for resetting the electric charge accumulated in the light receiving element 41, and a pixel signal generated in the light receiving element 41. An amplifying transistor 43 to be amplified and a cell switch 44 for selecting the amplified pixel signal are provided.

  When reading out a pixel signal of a specific pixel of the CMOS image sensor 4, for example, the pixel Pn, m, first, a predetermined voltage is applied to the row selection signal Sr, n designating the Y coordinate. As a result, all the cell switches 44 of the pixels Pn, m (m = 1 to M) in the nth row are turned on, and each pixel signal is output to the column readout line Lm (m = 1 to M).

  Next, a predetermined voltage is applied to the column selection signal Sc, m that specifies the X coordinate. As a result, only the m-th column switch 46 is turned on, and the pixel signal of the specific single pixel Pn, m is output to the output line Lout.

  When reading out pixel signals of a predetermined partial area of the CMOS image sensor 4, a predetermined voltage is sequentially applied to the column selection signal and the row selection signal so that the pixel signal of the partial area having a predetermined shape is continuously obtained. Can be read out.

  For example, when reading pixel signals of rectangular partial regions from the n1st row to the n2th row as the Y coordinate and the m1st column to the m2th column as the X coordinate, a state in which a voltage is applied to the row selection signals Sr, n1 Thus, the voltage is applied by sequentially switching from the column selection signals Sc, m1 to the column selection signals Sc, m2. As a result, the pixel signal of the n1st row is read in the row direction from the m1st column to the m2th column. When the reading of the pixel signals in the n1st row is completed, the pixel signals in the (n1 + 1) th row direction are read out. Similarly, pixel signals in a predetermined partial region can be read out by sequentially reading out pixel signals up to the n2nd row.

  Incidentally, the column readout line Lm (m = 1 to M) and the output line Lout provided in the CMOS image sensor 4 have a certain transmission resistance and transmission capacity. For this reason, when signals are transmitted through these transmission lines, it is necessary to consider the delay time due to the resistance component and the capacitance component.

  In particular, the column readout line Lm (m = 1 to M) is directly connected to each pixel via the cell switch 44, and the drive current for driving these transmission lines is small, so that the pixel signal is accurately transmitted. Therefore, it is necessary to set the switching time of the cell switch 44 with sufficient consideration for the delay time. Therefore, the update time (access speed) for switching the cell switch 44 using the row selection signal and switching the pixel in the column direction (Y direction) must be set relatively long.

  For example, in the conventional example of the CMOS image sensor 4 having 1024 × 1024 pixels, the update time (access speed) in the Y direction is about 400 nsec.

  On the other hand, as shown in FIG. 8, the CMOS image sensor 4 has a configuration in which a high-speed driving amplifier 45 is provided together with the column switch 46 between the column readout line Lm (m = 1 to M) and the output line Lout. ing. Therefore, it is possible to secure a sufficient drive current for driving the output line Lout by the high-speed drive amplifier 45, and the switching time of the column switch 46 can be set short. As a result, the update time (access speed) for switching the column switch 46 using the column selection signal and switching the pixels in the row direction (X direction) can be set short.

  For example, in the conventional example of the CMOS image sensor 4 having the number of pixels of 1024 × 1024, the update time (access speed) in the X direction is about 20 ns.

  As a result, as shown in FIG. 9A, pixel signals of a horizontally long rectangular partial region (X direction: 64 elements, Y direction: 16 elements, number of pixels 1024) from a 1024 × 1024 CMOS image sensor 4, for example. The readout time for scanning in the X direction is obtained by multiplying the total value of the readout time in the X direction (about 20 nx 64) and the update time in the Y direction (about 400 ns) per row by the number of rows (16). Value, that is, about 26.9 μs.

  On the other hand, the pixel signal of the vertically long rectangular partial region (X direction: 16 elements, Y direction: 64 elements, pixel number 1024) illustrated in FIG. 9B is scanned in the X direction from the same CMOS image sensor 4. In the case of reading, the read time in the X direction per row (about 20 nx 16) and the update time in the Y direction (about 400 ns) multiplied by the number of rows (64), that is, about 46.1 μs.

  Even when reading out pixel signals of the same vertically long rectangular partial area (X direction: 16 elements, Y direction: 64 elements, number of pixels 1024), scanning is performed in the Y direction as shown in FIG. 9C. When reading data, the reading time varies greatly. The readout time for scanning in the Y direction is obtained by multiplying the total value of the readout time in the Y direction (about 400 ns × 64) and the update time in the X direction (about 20 ns) per column by the number of columns (16). Value, that is, about 409.9 μs.

  As described above, in the conventional CMOS image sensor, even if the number of pixels is the same, there is a great difference in the readout time depending on the shape or orientation of the partial pixel region to be read out or the reading scanning direction.

  As a result, as in the imaging camera device disclosed in Patent Literature 1, a system that extracts the size and rotation angle of a specific partial pixel region from the entire pixel region while changing it for each frame (see FIG. 4 of Patent Literature 1). .)), The readout time of image data differs from frame to frame, which is a major limitation in system timing design and results in a loss of system performance (high-speed real-time performance).

  Although the technique disclosed in Patent Document 2 can reduce the time required to designate coordinates, it does not equalize the difference between the update times in the X direction and the Y direction described above.

  In the imaging camera device disclosed in Patent Document 1, the same pixel may be accessed a plurality of times in the same frame. In this case, the nondestructive readability of the CMOS image sensor is required. In a conventional CMOS image sensor, the peripheral circuit of a light receiving element such as a photodiode is composed of an analog circuit, so that the electric charge accumulated in the light receiving element gradually changes with time to realize complete nondestructiveness. It is difficult.

  The present invention has been made in view of the above circumstances, and does not depend on the reading direction of a specific pixel region, and if the number of pixels is the same, the same reading time can be set regardless of the shape or direction of the specific pixel region. It is an object of the present invention to provide an image sensor and an image reading method thereof that can be ensured and that enable complete nondestructive reading.

  In order to solve the above problems, an image sensor according to the present invention is a pixel output from a plurality of pixels in an image sensor in which a plurality of pixels having light receiving elements are arranged in a planar shape as described in claim 1. The same number of A / D converters as the plurality of pixels for A / D converting the signal for each pixel, and the same number of memories as the plurality of pixels for storing the digital pixel signals converted by the A / D converter for each pixel. The digital pixel signal for each pixel stored in the memory can be read out by arbitrarily designating the coordinates of the planar arrangement.

  In order to solve the above problems, an image sensor according to the present invention includes a predetermined number of pixels in an image sensor in which a plurality of pixels having light receiving elements are arranged in a planar shape. A number of A / D converters and A / D converters that divide pixel signals that are sequentially output from a plurality of pixels in the group into A / D converters that sequentially A / D convert each group. A digital pixel signal for each pixel that is stored in the memory by arbitrarily designating the coordinates of the planar arrangement, and having the same number of memories as the number of the groups for dividing and storing the converted digital pixel signal for each group It is characterized in that the signal can be read out.

  Moreover, in order to solve the said subject, the image reading method of the image sensor which concerns on this invention is the image reading method of the image sensor by which the several pixel which has a light receiving element was arranged in planar shape, as described in Claim 11 The pixel signals output from a plurality of pixels are A / D-converted in parallel for each pixel, and the A / D-converted digital pixel signals are stored in the memory in parallel for each pixel, and the coordinates of the planar array Can be arbitrarily specified, and a digital pixel signal for each pixel stored in the memory can be read out.

  According to another aspect of the present invention, there is provided a method for reading an image from an image sensor, wherein a plurality of pixels having light receiving elements are divided into a predetermined number of groups and arranged in a planar shape. In the image reading method of the image sensor, pixel signals are sequentially output from a plurality of pixels in the group, and the pixel signals sequentially output from the group are A / D converted in parallel for each group, and A / D converted. The digital pixel signals are divided and stored in parallel in memory for each group, and the digital pixel signals for each pixel stored in the memory can be read by arbitrarily designating the coordinates of a planar arrangement. To do.

  According to the image sensor and the image reading method thereof according to the present invention, the same reading time can be ensured regardless of the shape and direction of a specific pixel area as long as the number of pixels is the same, regardless of the reading direction of the pixel area. And allows complete non-destructive readout.

  Embodiments of an image sensor and an image reading method thereof according to the present invention will be described with reference to the accompanying drawings.

(1) First Embodiment FIG. 1 is a diagram showing a configuration example in a first embodiment of an image sensor 1 according to the present invention.

  The image sensor 1 includes pixel units P arranged in M rows in the X direction and N rows in the Y direction, and a total of MN pixel units P (P (n, m), n = 1 to N, m = 1 to M).

  In FIG. 1, of the MN pixel units P, the pixel unit P (n, m) in the nth row and the mth column and the pixel unit P (n, m + 1) in the nth row and the m + 1th column among the MN pixel units P. , Only four pixel units P of the pixel unit P (n + 1, m) in the (n + 1) th row and the mth column and the pixel unit P (n + 1, m + 1) in the (n + 1) th row and the m + 1th column are illustrated. ing.

  Each pixel unit P includes a pixel 11 that converts light into a pixel signal, an A / D converter 12 that converts a pixel signal of an analog signal output from the pixel 11 into a digital signal, and a pixel signal converted into a digital signal. And a memory 13 for storing.

  The A / D converter 12 and the memory 13 have a one-to-one correspondence with the pixels 11, and the entire image sensor 1 is configured to include the same number of MN as the pixels 11.

  Further, the A / D converter 12 and the memory 13 are physically disposed adjacent to the pixel 11.

  The pixel 11 is composed of a photodiode or the like, and receives a light receiving element 14 that converts light into an electrical signal, and a switching transistor 15 for resetting the charge accumulated in the light receiving element 14 for each frame time (image update cycle), for example. And an amplifying transistor 16 that amplifies the electrical signal of the light receiving element 14 and outputs the signal as an analog pixel signal.

  The output of the memory 13 of each pixel unit P is connected to a column bus Bm (m = 1 to M) passing through the same column, and each column bus Bm (m = 1 to M) is output via the column switch 17. Connected to bus Bout. The pixel signal of the image sensor 1 is taken out through the output bus Bout.

  On the other hand, the image sensor 1 includes a control unit 10 that generates a control signal for each pixel unit P. In the control signal generated by the control unit 10, a pixel reset signal for resetting the light receiving element 14, a writing signal for A / D converting the pixel signal to be stored in the memory 13, and coordinates are designated and stored in the memory 13. A row readout signal and a column readout signal for reading out the read pixel signal are included.

  Among these control signals, the pixel reset signal and the write signal are connected by distributing a common signal from the control unit 10 to all the pixel units P. In each pixel unit P, the pixel reset signal is used for switching. The gate of the transistor 15 and the write signal are connected to the A / D converter 12 and the memory 13.

  On the other hand, the row readout signal is connected to the memory 13 of the pixel unit P in the corresponding row as an independent row readout signal Rr, n (n = 1 to N) for each row.

  The column readout signal is connected to the column switch 17 of the corresponding column as an independent column readout signal Rc, m (m = 1 to M) for each column.

  The operation of the image sensor 1 configured as described above will be described.

  FIG. 2 shows a timing chart of the image sensor 1. The pixel reset signal is periodically generated by the control unit 10 every frame time Tf. This pixel reset signal is distributed in common to all the pixel units P, and the charges accumulated in the light receiving elements 14 in each pixel unit P are reset all at once. The image is updated every frame time Tf by the pixel reset signal.

  After being reset by the pixel reset signal, a new pixel signal is accumulated (exposed) in the light receiving element 14 in each pixel unit P. After a predetermined exposure time Te has elapsed, a writing signal is distributed from the control unit 10 to all the pixel units P in common. The A / D converter 12 in each pixel unit P converts the analog amount pixel signal output from the pixel 11 into a digital amount based on the write signal.

  Further, the memory 13 in each pixel unit P stores the pixel signal converted into the digital quantity based on the writing signal. As a result, the pixel signal is simultaneously stored in the memory 13 for each pixel unit P based on the write signal.

  Next, the control unit 10 uses the row readout signal and the column readout signal to specify the row and column of the pixel unit P, that is, the coordinates, and reads out the pixel signal of the pixel unit P at the corresponding coordinates. For example, when the pixel signal of the pixel unit P (n, m) is read out, the row readout signal Rr, n and the column readout signal Rc, m are turned on, whereby the pixel of the pixel unit P (n, m) is turned on. The signal is output to the output bus Bout via the column bus Bm.

  When the pixel signal of the pixel unit P (n + 1, m) is subsequently read out, the row readout signal Rr, n + 1 and the column readout signal Rc, m are turned on so that the pixel unit P (n + 1, m) is turned on. The pixel signal of m) is output to the output bus Bout via the column bus Bm.

  In this way, during the readout time Tr, the pixel signal of any pixel unit P in the image sensor 1 can be sequentially read out by sequentially updating the row readout signal and the column readout signal.

  The memory 13 can be configured in various forms, but is preferably configured with SRAM (Static Random Access Memory). This is because, for example, SRAM can be written and read faster than DRAM, and the access time is uniform between the X coordinate and the Y coordinate, and it does not depend on the reading order when reading a plurality of pixel signals. This is because it is possible to always read with a constant reading time if the number of pixels is the same.

  In the conventional image sensor, as shown in FIG. 8, the pixel signal is output in the form of an analog signal via the column readout line Lm and the output line Lout. For this reason, in order to maintain the waveform of the analog signal, it is necessary to set the read time in consideration of the delay time of the transmission line and the drive capability of the transmission source, and there is a certain limit to shortening the read time.

  Furthermore, generally, the ability to drive a pixel signal from each pixel in the column direction (Y direction) via the column readout line Lm is low, and it is provided at the end of the column readout line Lm in the row direction (X direction). The driving capability is high due to the effect of the high-speed driving amplifier 45. For this reason, the update time for updating the pixels in the Y direction becomes long, and there is a large difference in the update time from when updating in the X direction. Even if the number of pixels is the same, the shape and orientation of the pixel area to be read out Alternatively, the readout time differs greatly depending on the readout direction.

  On the other hand, according to the image sensor 1 according to the first embodiment, the pixel signal is converted into a digital signal for each pixel unit P, and further stored in the memory 13 for each pixel unit P. The digital signal stored in the memory 13 is read out via the column bus Bm and the output bus Bout.

  Therefore, it is not necessary to consider the maintenance of the waveform of the analog signal as in the conventional image sensor, and it becomes possible to transfer the digital signals of “0” and “1” at high speed. Further, if an SRAM is used as the memory 13, the update time in the X direction and the update time in the Y direction can be set to be the same. A constant readout time can be realized.

  In other words, the image sensor 1 according to the first embodiment can perform completely random access in the same manner as a general SRAM with respect to reading out pixel signals.

  Furthermore, according to the image sensor 1 according to the first embodiment, complete nondestructive readout can be realized. In the conventional image sensor 4, since the peripheral circuit of the light receiving element 14 is formed of an analog circuit, for example, when accessing the same pixel a plurality of times within the same frame time Tf, the complete identity for each access is It could not be ensured, and some fluctuations had to be allowed.

  On the other hand, according to the image sensor 1 according to the first embodiment, after the pixel signal is once stored in the memory 13, the same pixel signal can be read out any number of times unless the pixel signal is rewritten. It is possible to realize complete nondestructive reading.

  FIG. 3 shows a timing chart when accessing the pixel unit P at a completely random position using the image sensor 1 according to the first embodiment.

  According to the image sensor 1 according to the first embodiment, even when the coordinates of the pixel unit P are the same as the Y coordinates and the X coordinates are continuously updated as in PA, PB, and PC, Even if the X coordinate and Y coordinate change discretely and randomly as in the case of PC to PD or PE to PF, the pixel signal is synchronized with the period of the read clock signal while maintaining a constant processing delay Td. Are read out, and complete random accessibility can be realized.

  FIG. 4 shows a situation in which pixel signals of a rectangular partial pixel region (m × n) are read from all pixel regions (M × N) while rotating the direction for each frame.

  In special image cameras for industrial use or the like, there is a case where an image sensor that enables ultra-high-speed shooting while maintaining high resolution may be required. In such a case, for example, the total number of pixels is set to a high resolution of 1024 × 1024, and all pixels are updated at an extremely high speed of about 1 ms (1000 update times per second). However, it is not easy even with future technology.

  Therefore, when shooting at a normal speed, for example, when shooting at a frame time of 33 ms (update cycle of about 30 times per second), the total number of pixels (1024 × 1024) is updated, and when shooting at a very high speed, partial pixels A method is conceivable in which only pixels in a region (for example, 128 × 256) are read and updated at an extremely high speed.

  At this time, in an industrial camera or the like, there is a demand to always capture an image of an object that is rotated, moved, enlarged, or reduced (hereinafter referred to as rotation or the like) with a certain direction and size.

  The technique disclosed in Patent Document 1 responds to such a demand. The feature amount of an object to be rotated is extracted, and only a partial pixel region including the object is fixed at a certain position and orientation by tracking based on a feedback technique. , It is possible to read out while converting the size. That is, instead of performing transformation such as rotation on the object after reading out the pixel signal of the partial pixel region having a certain position, orientation, and size, the coordinates of the readout of the pixel signal itself are inversely affine transformed beforehand. By reading the pixel signal of the partial pixel area using the calculated coordinates, an image that has been subjected to conversion such as rotation is obtained at the time of reading. For this reason, the image processing time is shortened as a whole, and a great effect is expected for ultra high-speed shooting.

  In the technique disclosed in Patent Document 1, it is necessary to read out partial pixel regions having different shapes and orientations for each frame time as shown in FIG. 4 (FIG. 4 shows an example in which only the orientation changes). . At this time, if the readout time of the pixel signal differs for each frame time depending on the shape and orientation of the partial pixel region, it becomes difficult to perform image processing on the output of the image sensor at an appropriate processing timing. In addition, if the readout time of the pixel signal differs for each frame time, the system timing must be constructed assuming that the readout time will be the longest in the end, and the power of the extra high-speed camera cannot be demonstrated. It will be.

  According to the image sensor 1 according to the first embodiment, even when the shape, orientation, or readout direction of the partial pixel region is different, it is possible to always read out the pixel signal with the same readout time as long as the number of pixels does not change. Therefore, the image sensor 1 suitable for the technique disclosed in Patent Document 1 can be provided.

  The pixel 11 shown in FIG. 1 can be formed using CMOS (Complementary Metal Oxide Semiconductor), but an A / D converter 12, a memory 13, a column switch 17, a logic circuit configuring the control unit 10, and the like are also included. Similarly, it can be formed using CMOS. For this reason, the entire image sensor 1 can be formed on a single CMOS chip, and a small, highly integrated and low power consumption image sensor 1 can be realized at low cost.

  In addition, process technology using CMOS is widely spread as various logic circuits and memory circuits, and since existing process technology can be used without developing new special process technology, development risk is low and low. Contributes to cost reduction.

  The image sensor 1 shown in FIG. 1 includes the control unit 10, but the control unit 10 may be separated and provided outside the image sensor 1 from the viewpoint of mounting efficiency.

(2) Second Embodiment FIG. 5 shows a configuration example in the second embodiment of the image sensor 2 according to the present invention.

  The main difference between the image sensor 2 according to the second embodiment and the image sensor 1 according to the first embodiment is that the image sensor 1 according to the first embodiment has an A / D converter for each pixel unit P. 12 and the memory 13 are provided. In the image sensor 2 according to the second embodiment, the pixel units P are grouped for each column, and the A / D converter 22 and the memory 23 are provided for each group. It is the point which is set as the structure to provide.

  Grouping may be performed line by line. In any grouping, the basic configuration and operation are not different. In this description, an embodiment in which each column is grouped will be described.

  The image sensor 1 according to the first embodiment has a configuration in which an A / D converter 12 and a memory 23 are disposed adjacent to a pixel 11. For this reason, in order to maintain the light receiving area of the pixel 11 as in the conventional CMOS image sensor, a highly integrated CMOS process is required. However, recent advances in CMOS micro-process technology are remarkable and are sufficiently realizable in the near future.

  On the other hand, when the current CMOS process is used, if the A / D converter 12 and the memory 13 are disposed adjacent to the pixel 11, the light receiving area of the pixel 11 may have to be reduced. There is. As a result, the amount of light received by the pixel 11 is reduced. Further, if the light receiving area of the pixel 11 is maintained, the area of the CMOS chip (area of the pixel array region 2a) must be increased. In this case, it is necessary to increase the size of the optical system such as a lens system. It becomes.

  In the image sensor 2 according to the second embodiment, the pixel 21, the A / D converter 22, and the memory 23 are physically separated and arranged. As a result, even if the current CMOS process technology is used, the image sensor 2 can be realized without reducing the light receiving area of the pixel 21 or increasing the area of the pixel array region 2a.

  The configuration and operation of the image sensor 2 according to the second embodiment will be described focusing on differences from the image sensor 1 according to the first embodiment.

  In the pixel 21 according to the second embodiment, a charge transfer switch 27 and a charge holding capacitor 28 are provided between the light receiving element 24 and the gate of the amplifying transistor 26. A capacitor reset switch 28 a is connected to the charge holding capacitor 28.

  The output of the amplifying transistor 26 is connected to the column readout line Lm (m = 1 to M) via the cell switch 29.

  Each column readout line Lm (m = 1 to M) is connected to the A / D converter 22 at one end of the pixel array region 2a. Each A / D converter 22 is provided for each column. For example, the A / D converters 22 are arranged in the A / D converter area 2b on the outer periphery of the pixel array area 2a.

  Similarly to the A / D converter 22, the memory 23 is provided for each column, and the output of the A / D converter 22 is connected to the memory 23. For example, each memory 23 is arranged in a memory area 2c adjacent to the A / D converter area 2b.

  The control unit 20 provided in the image sensor 2 generates various control signals. Among these control signals, the pixel reset signal and the pixel transfer signal are signals common to all the pixel units P (P (n, m), n = 1 to N, m = 1 to M) from the control unit 20. In each pixel unit P, the pixel reset signal is connected to the gate of the switch transistor 25 and the pixel transfer signal is connected to the charge transfer switch 27 in each pixel unit P.

  On the other hand, the row selection signal is connected to the cell switch 29 of the pixel unit P in the corresponding row as an independent row selection signal Rn (n = 1 to N) for each row.

  The write signal is distributed and connected to the A / D converter 22 and the memory 23 provided for each column.

  In addition, an SRAM read address signal and an SRAM control signal are connected to each memory 23 from the control unit 20, and an output of each memory 23 is further connected to an output bus Bout.

  The operation of the image sensor 2 configured as described above will be described.

  FIG. 6 shows a timing chart of the image sensor 2.

  Similar to the image sensor 1 according to the first embodiment, the pixel reset signal is periodically generated by the control unit 20 at every frame time Tf, and the charges accumulated in the light receiving elements 24 in each pixel unit P are simultaneously transmitted. Reset to. The image is updated every frame time Tf by the pixel reset signal.

  After being reset by the pixel reset signal, a new pixel signal is accumulated (exposed) in the light receiving element 24 in each pixel unit P. Immediately before the predetermined exposure time Te elapses, a capacitor reset signal is distributed from the control unit 20 to all the pixel units P in common, and the capacitor reset switch 28a is turned on to reset the charge holding capacitor 28. Is done. As a result, the pixel information of the previous frame stored in the charge holding capacitor 28 is erased. Thereafter, the pixel transfer signal is distributed from the control unit 20 to all the pixel units P in common. The charge transfer switch 27 is turned on by the pixel transfer signal, and the pixel signals of a new frame are transferred all at once to the charge holding capacitor 28.

  Thereafter, a row selection signal is sequentially output from the first row to the Nth row from the control unit 20. As a result, the pixel signals accumulated in the charge holding capacitors 28 are sequentially output to the column readout lines Lm (m = 1 to M) from the first row to the Nth row.

  On the other hand, the control unit 20 outputs a write signal to the A / D converter 22 and the memory 23 in synchronization with the row selection signal, and is output from the column readout line Lm (m = 1 to M). The signals are sequentially A / D converted and stored in the memory 23.

  When the row selection signal selects the Nth row, the pixel signals of all the rows in the corresponding column are digitized and stored in the memory 23. Since the memory 23 is provided for each column, all the pixel signals of the image sensor 2 are grouped for each column and stored in the memory 23. Since writing to the memory 23 is performed in parallel for each column, writing in a short time is possible.

  Subsequently, an SRAM read address signal and an SRAM control signal for designating an address (coordinates) are output from the control unit 20 to each memory 23, and a pixel signal at the designated address is output to the outside via the output bus Bout. The

  In the memory 23, all pixel signals are grouped and stored for each column, but it is not necessary to read out all the pixel signals at the time of reading.

  Further, by configuring the memory 23 with SRAM, it is possible to make the read update time in the X direction and the Y direction uniform.

  Therefore, regarding the readout of the pixel signal, complete random accessibility illustrated in FIG. 3 can be realized in the same manner as the image sensor 1 according to the first embodiment. In the case of reading out the partial pixel area, as illustrated in FIG. 4, as long as the number of pixels is the same, the partial pixel area always has a constant readout time regardless of the shape, orientation, or readout direction of the partial pixel area. It becomes possible to read out the pixel signal of the pixel region.

  Further, all the components of the image sensor 2, that is, the control unit 20, the pixel unit P, the A / D converter 22, and the memory 23 are general-purpose CMOS as in the image sensor 1 according to the first embodiment. It can be formed on a single CMOS chip using process technology, and the same effects as the first embodiment, such as small size and high integration, low power consumption, and low cost, can be obtained.

  Note that the controller 20 may be provided outside the image sensor 2 as in the first embodiment.

  According to the image sensor 2 according to the second embodiment, since the A / D converter 22 and the memory 23 are provided adjacent to the outside of the pixel array region 2a, in addition to the effects of the first embodiment. Even if the current CMOS process technology is used, the light receiving area of each pixel unit P is not reduced and the pixel array area is not enlarged. Further, when the CMOS process miniaturization technology advances, it is possible to achieve further higher resolution (increase in the number of pixels) while maintaining the same pixel array area.

(3) Third Embodiment FIG. 7 shows a configuration example of a third embodiment of the image sensor 3 according to the present invention.

  Although the image sensor 3 according to the third embodiment and the image sensor 2 according to the second embodiment have different physical arrangements of the A / D converter 22 and the memory 23, the basic configuration and There is no difference in operation.

  The image sensor 3 according to the third embodiment includes an A / D converter 22 and a memory 23 that are responsible for the odd-numbered pixel units P, and an A / D converter 22 and a memory 23 that are responsible for the even-numbered pixel units P. Are arranged in different regions.

  In the example shown in FIG. 7, the A / D converter 22 and the memory 23 in charge of odd columns are arranged in the A / D converter region 3b and the memory region 3c on one end side of the pixel array region 3a, respectively. The A / D converter 22 and the memory 23 in charge are arranged in the A / D converter area 3d and the memory area 3e on the other end side of the pixel array area 3a, respectively.

  Thus, by arranging the A / D converter 22 and the memory 23 in charge of the odd-numbered columns and the even-numbered columns separately in two, the mountable area of the A / D converter 22 and the memory 23 in units of columns can be afforded. Can be secured. This is particularly effective when the number of bits for A / D conversion is large.

  The addressing method for reading out the pixel signal from the memory 23 is not particularly limited. For example, the address of the memory 23 can be specified using a row address, a block address, and a chip select (CS) signal.

  In the example shown in FIG. 7, the pixel array on the surface of 1024 × 1024 elements is divided into groups of 1024 columns, and 16 columns are formed as one block, and a total of 64 blocks are configured. The memory 23 (SRAM # 1 to # 16) in charge of odd columns or even columns in each block stores 1024 rows of pixel signals. If the number of bits for A / D conversion is 10 bits, each memory 23 (SRAM # 1 to # 16) stores data of 1024 × 10 bits.

  The memory 23 (SRAM # 1 to # 16) in the block can be selected using a chip select signal (CS1 to CS16).

  With the address configuration as described above, by performing addressing from the control unit 30 using a row address, a block address, and a chip select signal, it is possible to output a pixel unit pixel signal of the designated address to the output bus Bout. it can.

  The above addressing method can also be applied to the image sensor 2 according to the second embodiment.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, the constituent elements over different embodiments may be appropriately combined.

The figure which shows the structural example in 1st Embodiment of the image sensor which concerns on this invention. 3 is a timing chart showing an operation example of the first embodiment of the image sensor according to the present invention. The 1st figure explaining operation | movement of 1st Embodiment of the image sensor which concerns on this invention. FIG. 3 is a second diagram illustrating the operation of the first embodiment of the image sensor according to the present invention. The figure which shows the structural example in 2nd Embodiment of the image sensor which concerns on this invention. The timing chart which shows the operation example of 2nd Embodiment of the image sensor which concerns on this invention. The figure which shows the structural example in 3rd Embodiment of the image sensor which concerns on this invention. The figure which shows the structural example of the conventional CMOS image sensor. The figure explaining the read time of the conventional CMOS image sensor.

Explanation of symbols

1, 2, 3 Image sensor 1a, 2a, 3a Pixel array region 2b, 3b, 3d A / D converter region 2c, 3c, 3e Memory region 4 Conventional CMOS image sensor 10, 20, 30 Controller 11, 21 Pixel 12, 22 A / D converter 13, 23 Memory 14, 24 Light receiving element 15, 25 Switch transistor 16, 26 Amplifying transistor Bm (m = 1 to M) Column bus Bout Output bus Lm (m = 1 to M) Column readout line P (n, m) (n = 1 to N, m = 1 to M) Pixel unit

Claims (12)

In an image sensor in which a plurality of pixels having light receiving elements are arranged in a plane,
The same number of A / D converters as the plurality of pixels for A / D converting the pixel signals output from the plurality of pixels for each pixel;
A plurality of pixels that store the digital pixel signals converted by the A / D converter for each pixel, and the same number of memories.
An image sensor configured to be able to read digital pixel signals for each pixel stored in the memory by arbitrarily designating coordinates of the planar arrangement. The image sensor according to claim 1, wherein the memory is an SRAM (Static Random Access Memory). The image sensor according to claim 1, wherein the A / D converter and the memory are provided adjacent to the pixel for each pixel. The image sensor according to claim 1, wherein the pixel, the A / D converter, and the memory are formed on a single chip by a complementary metal oxide semiconductor (CMOS). In an image sensor in which a plurality of pixels having light receiving elements are arranged in a plane,
A number of A / D converters that divide the plurality of pixels into a predetermined number of groups and sequentially A / D convert pixel signals sequentially output from the plurality of pixels in the group for each group. When,
A digital pixel signal converted by the A / D converter is divided into the groups and stored in the same number of memories.
An image sensor configured to be able to read digital pixel signals for each pixel stored in the memory by arbitrarily designating coordinates of the planar arrangement. The plurality of pixels are arranged in a plane in a row in the X direction and a column in the Y direction,
6. The image sensor according to claim 5, wherein the group is grouped for each column in the Y direction or for each row in the X direction. The image sensor according to claim 5, wherein the memory is configured by an SRAM (Static Random Access Memory). The image sensor according to claim 5, wherein the A / D converter and the memory are provided adjacent to a planar region in which the pixels are arranged. The image sensor according to claim 5, wherein the pixel, the A / D converter, and the memory are formed on a single chip by a complementary metal oxide semiconductor (CMOS). The group for each column or row is classified into a first group for each odd-numbered column or row and a second group for each even-numbered column or row, and corresponds to the first group. And the A / D converter and the memory corresponding to the second group are arranged in opposing areas outside the planar area where the pixels are arranged. The image sensor according to claim 6. In an image reading method of an image sensor in which a plurality of pixels having a light receiving element are arranged in a planar shape,
A / D conversion is performed on the pixel signals output from the plurality of pixels in parallel for each pixel,
The A / D converted digital pixel signal is stored in a memory in parallel for each pixel,
An image reading method characterized in that a digital pixel signal for each pixel stored in the memory can be read by arbitrarily designating coordinates of the planar arrangement. In the image reading method of the image sensor in which a plurality of pixels having light receiving elements are divided into a predetermined number of groups and arranged in a plane,
Sequentially outputting pixel signals from a plurality of pixels in the group;
A / D conversion is performed in parallel for each group of pixel signals sequentially output from the group,
The A / D converted digital pixel signal is divided and stored in a memory in parallel for each group,
An image reading method characterized in that a digital pixel signal for each pixel stored in the memory can be read by arbitrarily designating coordinates of the planar arrangement.

Images