JP2006202265A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer that, even when at least one of a plurality of tasks subjected to time division concurrent processing is described as a particular task, can execute a conditional control flow in the particular task. <P>SOLUTION: Even if the execution of a conditional judgment instruction described in an L task finds it unnecessary to execute instructions described after the instruction, a CPU 32 apparently executes the execution-unnecessary instructions to cause the value of a program counter 23 to be incremented in the execution of the L task in the same manner as if it is necessary to execute the instructions, but prohibits the execution results of the instructions from being reflected to the CPU 32 itself or a peripheral circuit 38 or 39. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention can execute a plurality of tasks in a time-sharing manner in parallel, and at least one of them is a specific task in which a fixed loop program is written so that the instruction address increment is constant. It relates to the microcomputer which becomes.

Patent Document 1 discloses a microcomputer having the configuration shown in FIG. This microcomputer has a CPU 11, a program memory 12 constituted by a ROM, a data memory 13 constituted by a RAM, an I / O block 14 (input / output pins), and a CPU switching signal (clock signal) described later. A timing generator (not shown) for generating data, a data bus 15 for transmitting and receiving data, an address bus 16 for transmitting and receiving address signals, and control buses 17 and 18 for transmitting and receiving read signals and write signals, respectively, are provided.
The CPU 11 includes, for example, two address registers 19 and 20 and two operation registers 21 and 22 for pipelining two types of tasks (L task and A task) in a time-sharing manner. , 20 and the arithmetic registers 21 and 22 are alternately switched by a CPU switching signal, and apparently function to switch the two CPUs alternately.

In this case, one address register 19 and operation register 21 are registers for CPU0 (for L task), and the other address register 20 and operation register 22 are registers for CPU1 (for A task). The value of the program counter 23 (address of the next instruction to be fetched) is updated according to the switching of the address registers 19 and 20, and the CPU 0 (for L task) and CPU 1 (for A task) are updated from the program counter 23. Address signals are alternately output to the program memory 12.
In the CPU 11, an error detection circuit 24 that determines the type of task to which the instruction read from the program memory 12 belongs and detects the error, and decodes (decodes) the instruction that has passed through the error detection circuit 24. An instruction decoder / instruction sequencer 25 is provided. Depending on the contents of the instruction decoded by the instruction decoder / instruction sequencer 25, the arithmetic unit 26 (ALU) performs an operation using the operation registers 21 and 22, and a read signal or write A signal is output to the control buses 17 and 18.

  On the other hand, in the program memory 12, a program area 27 for CPU0 (for L task), a program area 28 for CPU1 (for A task), and a table immediate data area 29 are provided. In this case, the L task stored in the program area 27 for the CPU 0 is composed of a fixed looped program in which branch instructions that may lead to program runaway are prohibited. As a result, when the L task program is executed, execution is started from address 0, instructions are executed in order of address 1, address 2, address 3, and so on. Overflows and returns to address 0. Thereafter, the execution of instructions in the order of the addresses is repeated. All the instructions of the L task are fixed to one word.

The L task is suitable for performing sequence control processing, and the program includes a routine for monitoring runaway of the A task and a routine for backup sequence for establishing system fail-safety. Furthermore, this L task also has a function as a timer by a fixed loop operation. For example, when an increment instruction or a decrement instruction is executed and the count value reaches a predetermined set value, an interrupt is generated in the processing of the A task. This makes it possible to perform fixed-time processing equivalent to timer interrupts.
On the other hand, for the A task, branch instructions prohibited by the L task are also permitted, and are suitable for, for example, complex analysis processing and numerical processing. As for the A task, as in the L task, all instructions are fixed to a one-word instruction. In the A task and the L task, both an operation code and an operand (address) are allocated in one word.

  Next, a pipeline control system employed by the microcomputer having the above configuration will be described with reference to FIG. This pipeline is configured as, for example, a three-stage pipeline including instruction fetch, instruction decode, and instruction execution stages, and is designed so that all instructions can be processed without delay in the three-stage pipeline. Each stage is executed in one cycle, and one instruction is executed in three cycles, but apparently one instruction is processed in one cycle by processing three instructions in parallel by a three-stage pipeline. Is equivalent to running

The time for one cycle (each stage) is defined by a CPU switching signal (clock signal). This CPU switching signal has the same low-level time TLo and high-level time THi, and CPU0 (L task) instruction fetch is performed during the low level period, and CPU1 (A task) instruction fetch is performed during the high level period. By doing this, both the CPU0 (L task) and CPU1 (A task) programs are pipelined in parallel at a time division ratio of 1: 1.
Further, when the CPU 1 fetches the branch instruction included in the program of the A task, the branch destination is fetched at the instruction decode stage in order to fetch the instruction at the branch destination address at the instruction fetch stage next to the A task including the branch instruction. It is configured to set the address. FIG. 6 shows the processing timing when the instruction at address (Y + 1) of CPU 1 is a branch instruction (JMP) to address YY during pipeline processing.

The CPU 11 has a plurality of address registers 19 and 20 for sequentially setting different instruction addresses in the program counter 23, and a plurality of instructions for sequentially setting the instructions decoded by the instruction decoder / instruction sequencer 25 in the arithmetic unit 26. Computation registers 21 and 22 are provided, and a plurality of programs 27 and 28 stored in the program memory 12 can be pipelined by sequentially switching the plurality of address registers 19 and 20 and the plurality of computation registers 21 and 22 It is configured.
JP-A-6-250857

In the microcomputer of Patent Document 1, as described above, execution of a branch instruction is prohibited in the L task (that is, description of the branch instruction in the program is prohibited). Therefore, the value of the program counter 23 is always “1”. (In this case, it is set regardless of the number of bytes of one instruction), and the timer function using the runaway monitoring process on the A task side or the counter value of the program counter 23 is provided. It can be realized.
However, on the L task side, the restriction that the branch instruction is prohibited is added, so that the branch process cannot be executed. For example, whether or not to execute the predetermined arithmetic process is selected according to the result of the predetermined condition determination. There is a problem that such a conditional control flow cannot be realized.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a conditional control flow in a specific task even when at least one of a plurality of tasks that are processed in time-division parallel processing is described as the specific task. It is to provide a microcomputer that can execute the above.

According to the microcomputer of claim 1, even if the CPU executes the condition determination instruction described in the specific task, the instruction described after the instruction becomes unnecessary. Since the instruction that does not need to be executed is executed, the value of the program counter when the specific task is executed is increased in the same way as when the instruction is required, and the processing time is the same as when the instruction is executed. To do. However, since it is prohibited to reflect the execution result of the instruction on the CPU or the peripheral circuit, the state is substantially the same as when the instruction is not executed.
Therefore, the increment value of the instruction address is constant and the execution time of the instruction is the same regardless of the determination result of the condition determination instruction. Therefore, even in a specific task, conditional branching is performed while maintaining isochronism of processing time. Processing becomes possible, and programs can be described in more various ways.

  According to the microcomputer of claim 2, when the instruction that does not need to be executed is a load instruction, the CPU prohibits writing the data read by executing the load instruction to the internal register. The execution result of the instruction is not reflected on the CPU, and substantially the same state as when the load instruction is not executed can be maintained.

  According to the microcomputer of claim 3, when the instruction that does not need to be executed is a load instruction, the CPU executes the load instruction and writes the read data to the internal register. Data is converted into the data value of the internal register and overwritten on the internal register. Therefore, similarly to the second aspect, the execution result of the load instruction is not reflected on the CPU, and the same state as when the load instruction is not executed can be maintained.

  According to the microcomputer of claim 4, when the instruction that does not need to be executed is an arithmetic instruction, the CPU prohibits writing the data resulting from the execution of the arithmetic instruction to the internal register. The execution result is not reflected on the CPU, and substantially the same state as when the operation instruction is not executed can be maintained.

  According to the microcomputer of claim 5, when the instruction that does not need to be executed is an arithmetic instruction, the CPU writes the data that is the result of executing the arithmetic instruction to the internal register. Data is converted into the data value of the internal register and overwritten on the internal register. Therefore, similarly to the fourth aspect, the execution result of the arithmetic instruction is not reflected on the CPU, and the same state as when the arithmetic instruction is not executed can be maintained.

  According to another aspect of the microcomputer of the present invention, when the instruction that does not need to be executed is a store instruction, the CPU converts the operand address of the store instruction into a dummy address that does not actually have a data write target. Output. Since the external circuit of the CPU returns an acknowledge signal in response to the access by the dummy address, a bus error does not occur and the execution result of the store instruction is not reflected in the external circuit. Therefore, the same state as when the store instruction is not executed can be maintained.

  According to the microcomputer of the seventh aspect, when converting the operand address of the store instruction into a dummy address, the CPU converts all the lower bits of the operand address into “1” by a predetermined number of bits. That is, in the address area assigned to the peripheral circuit to which the operand address is to be written, the beginning of the area to the predetermined part is to be written, and the rest is assigned to the part responding to the dummy address. Then, access to the address area is secured by maintaining the upper bits of the operand address as it is, and if all the remaining lower bits are converted to “1”, the CPU is arranged at the tail side of the address area. The dummy address area to be accessed can be accessed.

  According to the microcomputer of claim 8, when the CPU converts the operand address of the store instruction into a dummy address, the CPU adds a predetermined address value to the operand address. The dummy address area arranged on the rear side of the address area can be accessed.

  An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a functional block diagram showing the configuration of the CPU 32 in the microcomputer 31 of the present invention. The basic configuration of the CPU 32 is the same as that of the CPU 11 shown in FIG. 5, but in FIG. 1, only the portion related to the gist of the present invention is extracted and shown for convenience of illustration. A new component in the CPU 32 is that a skip determination circuit 33 is mainly provided. In this embodiment, the CPU 32 accesses a 2-byte instruction, and the increment value of the program counter 23 is “2”.

The skip discriminating circuit 33 includes an instruction address output from the program counter 23, a CPU switching signal, a branch instruction signal and a load / store signal output from an instruction decoder / instruction sequencer (hereinafter simply referred to as an instruction decoder) 25. And is given. The instruction decoder 25 outputs a branch instruction signal when the decoded instruction is a branch instruction (including a conditional branch instruction) and the branch determination is established and the condition determination result signal from the arithmetic unit 26 becomes active. It is configured. This signal has an active (high) period as many as the number of branches (steps) specified by the branch instruction.
The instruction decoder 25 changes the load / store signal to a low level when the decoded instruction is a load instruction or an operation instruction, and changes the load / store signal to a high level when the decoded instruction is a store instruction. (For other instructions, the signal level is maintained).

  The result of the instruction decoder 25 decoding the instruction fetched via the instruction register 34 when the CPU switching signal is at the low level and indicates that the CPU 0 is in the L task (specific task) processing period. When a branch instruction signal is output when is a branch instruction and branch determination is established, the signal is recognized as a skip signal. In this case, the skip determination circuit 33 writes the program counter 23 and the (general purpose) register 35 for a predetermined period when the instruction to be executed when the branch execution condition is not satisfied is a load instruction or an operation instruction. The prohibition signal is output.

Further, when the skip determination circuit 33 recognizes the skip signal and the instruction to be executed when the branch execution condition is not satisfied is a store instruction, the skip determination circuit 33 similarly applies to the program counter 23 and the register 35. And a dummy address switching signal to the address bus / load store unit 36. When a dummy address switching signal is given, the address bus / load store unit 36 converts all the lower-order bits of the operand address of the store instruction stored in the address bus / load / store unit 36 to “1” by a predetermined number of bits. It is supposed to be. For example, when the address is 16 bits and the access address of the peripheral circuit 38 shown in FIG. 2 is “0x4xxx”, the address is “0x4FFF” which is the end of the address area of the peripheral circuit 38. Is converted to
The register 35 is configured so that data obtained from the peripheral circuit via the load store unit 36 as a result of execution of the load instruction is not stored during the period when the write inhibit signal is active. Similarly, storage of data obtained as a result of the arithmetic unit 26 executing the arithmetic instruction is prohibited.

  FIG. 2 is a functional block diagram schematically showing the overall configuration of the microcomputer 31. The CPU 32 includes a ROM 36 and a RAM 37 as the data memory 13 and peripheral circuits 38 and 39 (peripherals 1 and 2) as the I / O block 14 via the address bus 15 and the data bus 16, and a bus state controller (BSC, external Circuit, peripheral circuit) 40. When the CPU 32 accesses the peripheral circuits 38 and 39 having a low access speed, the BSC 40 performs cycle adjustment such as inserting a wait cycle and returns an acknowledge signal to the CPU 32.

In the peripheral circuits 38 and 39, the address areas assigned to the peripheral circuits 38 and 39 end up in areas such as internal registers where data is written, and dummy address areas where data is not actually written. It is set in addition to the part. The BSC 40 is configured to return an acknowledge signal even when the CPU 32 accesses the dummy address area.
If the BSC 40 inserts a wait cycle when the CPU 32 accesses the peripheral circuits 38 and 39, the instruction execution stage in the pipeline processing of the CPU 32 is delayed. However, since such information can be grasped in advance when the program is written, when the CPU 32 performs an access that causes a delay in execution during the L task, the increment value of the program counter 23 has a weight for the delay. The calculation process is performed so that

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 3A shows an example of the flow of processing when the microcomputer 31 in this embodiment executes the L task. In the present embodiment, processing equivalent to a conditional branch instruction can be realized even in an L task.
For example, FIG. 3B shows the flow of processing of a conventional L task, execution of branch instructions is prohibited, and processing steps (1) to (5) are executed sequentially, and the program counter 23 When it overflows, the program counter 23 returns to the initial address “0”, and a fixed loop is formed so that the processing steps (1) to (5) are repeatedly executed. Since these are examples of a large number of instructions executed by the CPU, the number of processing steps does not match the increment of the instruction address.

On the other hand, in the L task of this embodiment, a “determination” step is inserted between the processing step (1) and the processing step (2) instead of the processing step (5). When the result of the condition determination is true (T), the processing steps (2) and (3) are executed. When the result of the condition determination is false (F), the processing steps (2) and (3) are executed. Execution is skipped (A, B) and processing step (4) is executed.
However, in the L task, it is necessary to guarantee that the increment value of the program counter 23 is constant and that the processing time is isochronous. That is, they should not vary depending on the result of the “determination” step. Therefore, in the present embodiment, skip processes A and B, which replace process steps (2) and (3), are executed as shown in FIG.

  FIG. 4 shows a timing chart when processing is executed in accordance with the flowchart of FIG. 3A. FIG. 4A shows a case where the result of the determination step is “true”, and FIG. This corresponds to the case where the result of the step is “false”. Processing step (2) is a load instruction for the peripheral circuit 38 or 39, and processing step (3) is a store instruction for the peripheral circuit 38 or 39. For read access and write access executed by the CPU 32 in response to these instructions, for example, two wait cycles are inserted by the BSC 40, and three cycles are required to execute the processing steps (2) and (3). It is like that.

As shown in FIG. 4B, in the case of skip A, the CPU 32 fetches, decodes, and executes the load instruction of the process (2) as in the case of (a). However, at the stage where the load instruction is decoded, a write inhibit signal is output from the skip discriminating circuit 33 to the register 35 (high active). As a result, the read cycle is executed, and the data read via the address bus / load store unit 36 is not written to the register 35. Therefore, the execution result of the read cycle is not reflected in the CPU 32, and is substantially equivalent to a state in which the load instruction is not executed.
When the instruction in the process (2) is an arithmetic instruction, it is processed in the same manner as in the case of the load instruction, and the CPU 32 executes the arithmetic instruction in the arithmetic unit 26, but the execution result is written in the register 35. Absent.

  In the case of skip B, the CPU 32 fetches, decodes, and executes the store instruction of the process (3) as in the case of (a). However, when the store instruction is decoded, the CPU 32 also stores the address in the address bus / load store unit 36. A write inhibit signal is output from the skip discriminating circuit 33. As a result, the address output to the address bus 15 when the write cycle is executed is converted into the dummy address area of the peripheral circuit 38 or 39. Accordingly, no data is written to the peripheral circuit 38 or 39, which is substantially equivalent to a state in which the store instruction is not executed.

As described above, according to the present embodiment, the CPU 32 apparently executes the condition determination instruction described in the L task, even if it is not necessary to execute the instruction described after the instruction. The unnecessary instruction is executed. Accordingly, the value of the program counter 23 when the L task is executed increases in the same manner as when the instruction is required, and the same time as when the instruction is executed elapses. Since the reflection to itself or the peripheral circuit 38 or 39 is prohibited, the state is substantially the same as when the instruction is not executed.
Therefore, the same result as that obtained when the branch instruction is executed is obtained. Since the increment value of the instruction address is constant and the execution time of the instruction is the same regardless of the determination result of the condition determination instruction, conditional branching is performed while maintaining isochronism of processing time even in the L task. Processing becomes possible, and programs can be described in more various ways.

In addition, when the instruction that does not need to be executed is a load instruction, the CPU 32 prohibits writing the data read by executing the load instruction into the internal register 35, so that the execution result of the load instruction is reflected in the CPU 32. In other words, the same state as when the load instruction is not executed can be maintained. The same applies to a case where an instruction that does not need to be executed is an arithmetic instruction.
In addition, when the instruction that does not need to be executed is a store instruction, the CPU 32 converts the operand address of the store instruction into a dummy address that does not actually have a data write target, and outputs the dummy address. Therefore, no bus error occurs and the execution result of the store instruction is not reflected in the peripheral circuits 38 and 39. Therefore, the same state as when the store instruction is not executed can be maintained.

  Further, when converting the operand address of the store instruction into a dummy address, the CPU 32 converts all the lower bits of the operand address to “1” by a predetermined number of bits, and therefore maintains the upper bits of the operand address as they are. As a result, access to the address area of the peripheral circuit 38 or 39 can be ensured, and a dummy address area arranged on the tail side of the address area can be accessed.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
When the CPU 32 converts the operand address into a dummy address, a predetermined address value may be added to the operand address. The dummy address need not be set for each access target, and one common area may be set.
The BSC 40 may be provided as necessary.
The number of tasks processed in parallel by the CPU may be “3” or more.
The increment value of the instruction address in the specific task may be “1” or “4”.

The branch instruction signal is not limited to the one output by the instruction decoder 25, but may be generated and output by the arithmetic unit 26 or the skip determination circuit 33.
In the above embodiment, when the load instruction or the operation instruction is executed during the period in which the write prohibition signal is active, the execution result data is prohibited from being stored in the register 35, but instead of prohibiting the storage, Data obtained as an instruction execution result may be converted into a data value stored in the register 35 at that time and overwritten. Even in such a configuration, since the execution result of the instruction is not reflected on the CPU 32, the same state as when the load instruction and the operation instruction are not executed can be maintained.
There may be two or more types of instruction lengths, for example, 1 word length and 2 word length.

1 is a functional block diagram showing a configuration of a CPU in a microcomputer according to an embodiment of the present invention. Functional block diagram schematically showing the overall configuration of the microcomputer (A) is a flowchart showing processing when the microcomputer according to this embodiment executes an L task, and (b) is a flowchart showing a flow of processing of a conventional L task. FIGS. 3A and 3B are timing charts when processing is executed in accordance with the flowchart of FIG. 3A, where FIG. 3A is “true” as a result of the determination step, and FIG. 3B is “false” as a result of the determination step. Figure showing the case Functional block diagram showing the configuration of a conventional microcomputer Timing chart showing pipeline processing when the instruction at address (Y + 1) of CPU 1 is a branch instruction (JMP) to address YY

Explanation of symbols

  In the drawing, 23 is a program counter, 31 is a microcomputer, 32 is a CPU, 33 is a skip discrimination circuit, 35 is a register, 38 and 39 are peripheral circuits, and 40 is a BSC (external circuit, peripheral circuit).

Claims (8)

A plurality of tasks can be executed in a time-sharing manner, and at least one of them is a specific task in which a fixed loop program is described so that the instruction address increment is constant. ,
If the CPU executes the condition determination instruction described in the specific task and the execution of the instruction described after the instruction becomes unnecessary, the execution result of the instruction is reflected in the CPU or its peripheral circuit. A microcomputer characterized in that it is prohibited from being allowed to occur.   2. The microcomputer according to claim 1, wherein when the instruction that does not require execution is a load instruction, the CPU prohibits writing of data read by executing the load instruction to an internal register.   When the instruction that does not require execution is a load instruction, the CPU sets the data to the data value of the internal register when the read data is written to the internal register by executing the load instruction. 2. The microcomputer according to claim 1, wherein the microcomputer is converted and overwritten on the internal register.   4. The CPU according to claim 1, wherein, when an instruction that does not require execution is an arithmetic instruction, the CPU prohibits writing of data, which is a result of executing the arithmetic instruction, to an internal register. 5. A microcomputer according to 1.   When the instruction that does not need to be executed is an arithmetic instruction, the CPU writes the data that is the result of executing the arithmetic instruction to the internal register as the data value of the internal register. 4. The microcomputer according to claim 1, wherein the microcomputer is converted and overwritten on the internal register. When the instruction that does not need to be executed is a store instruction, the CPU converts the operand address of the store instruction into a dummy address that does not actually have a data write target, and outputs the dummy address.
6. The microcomputer according to claim 1, wherein an external circuit of the CPU is configured to return an acknowledge signal in response to access by the dummy address.   7. The CPU according to claim 6, wherein when the operand address of the store instruction is converted into the dummy address, the lower-order bits of the operand address are all converted to "1" by a predetermined number of bits. Microcomputer. 7. The microcomputer according to claim 6, wherein when the operand address of the store instruction is converted into the dummy address, the CPU adds a predetermined address value to the operand address.

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